US20060062026A1

US20060062026A1 - High efficiency power conversion circuits

Info

Publication number: US20060062026A1
Application number: US10/944,588
Authority: US
Inventors: Ernest Wittenbreder
Original assignee: Technical Witts Inc
Current assignee: Technical Witts Inc
Priority date: 2004-09-18
Filing date: 2004-09-18
Publication date: 2006-03-23
Also published as: US7589571B1; US7439717B1

Abstract

A composite high voltage schottky rectifier is revealed that provides a forward voltage slightly larger than a low voltage schottky rectifier combined with a high voltage breakdown capability. The composite rectifier can be formed from the combination of a low voltage schottky rectifier, a high voltage mosfet, and a few small passive components. A quarter bridge primary switching network similar in some ways to a half bridge primary switching network is revealed. The quarter bridge network consists of four switches with voltage stress equal to half the line voltage and the network applies one quarter of the line voltage to a primary magnetic circuit element network thereby reducing the number of primary winding turns required to one quarter by comparison to a common full bridge network. A synchronously switched buck post regulator is revealed for multi-output forward converters. The synchronously switched buck post regulator accomplishes precise independent load regulation for each output and reduced magnetics volume by using a coupled inductor with a common core for all outputs plus a second smaller inductor for each output except the highest voltage output. An improved capacitor coupled floating gate drive circuit is revealed that provides an effective drive mechanism for a floating or high side switch without the use of level shifting circuits or magnetic coupling. The capacitor coupled floating gate drive circuit is an improvement over prior art capacitor coupled floating gate drive circuits in that the new circuit uses a positive current feedback mechanism to reject slowly changing voltage variations that cause unintentional switch state changes in prior art capacitor coupled floating gate drive circuits.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The subject invention generally pertains to electronic power conversion circuits, and more specifically to high frequency, switched mode electronic power converters. Some of the subject matter of this application was first revealed in patent application Ser. No. 10/137,908. Some of the subject matter of this application was first revealed in Disclosure Document Number 527396.
2. Description of Related Art
In modern commercial power electronic circuits passive rectifiers are generally composed of silicon. For low voltage applications schottky barrier rectifier types dominate and in higher voltage applications ultra-fast junction rectifiers dominate. There are some new material technologies that are just beginning to emerge, but, in general, these are not cost competitive with silicon devices and have not gained wide acceptance in high volume commercial power supplies. Junction rectifiers are available for low voltage applications but are not commonly used because schottky barrier types offer much lower forward voltage and do not have the charge storage effects of junction rectifiers which can result in large switching losses during the turn on transition of the main switch. Schottky barrier rectifiers are superior to junction rectifiers in every way except that they have higher parasitic capacitance than a junction rectifier. The higher parasitic capacitance is not of so much importance that it significantly offsets the other advantages of schottky rectifiers. It would be desirable to have available schottky barrier rectifiers that can operate at high voltage. There are a few schottky barrier devices that can operate up to 200 volts reverse voltage, but the forward voltage of schottky rectifiers with higher voltage ratings is higher than the forward voltage of a low voltage schottky rectifier, so that the forward voltage advantage diminishes as the voltage rating increases. It would be desirable to have available a schottky rectifier that has a high voltage rating with the forward voltage of a low voltage schottky rectifier. FIG. 13 illustrates a composite high voltage power mosfet used in a zero voltage switching (ZVS) power converter according to the prior art. The composite power mosfet of FIG. 13 includes a low voltage schottky rectifier, D 1 , in series with the main power mosfet, M 1 , and a high voltage ultra-fast junction rectifier in anti-parallel to the power mosfet. The composite structure of FIG. 13 is common because the body diode of M 1 is slow to turn off, having a relatively large reverse recovery time compared to an ultra-fast junction rectifier. The diodes D 1 and D 2 are used to prevent the turn on of the intrinsic body diode of M 1 . D 1 blocks body diode conduction and D 2 provides a path for reverse currents that otherwise might flow in the body diode. One of the problems of the FIG. 13 circuit is that the on voltage of the composite power mosfet can never be less than the forward voltage of the schottky rectifier D 1 . What is needed is a high voltage schottky diode that can substitute for the junction rectifier D 2 and obviate the schottky diode D 1.
For low voltage point of load (POL) power converters planar magnetics devices have gained wide-spread popularity. This development has allowed POL converters to achieve higher power densities than previously attainable due to the lower profile of planar magnetics and the fact that the magnetic circuit elements are typically the tallest components in the circuit and thereby drive the maximum converter height. In off line power converters the magnetic circuit elements generally also drive the skyline dimension, but planar magnetics have not gained any significant commercial acceptance in off line power supplies because off line power supplies generally require a larger step down ratio and more primary turns are required to accommodate the higher voltages. More primary turns imply more winding layers which add to the cost of the magnetic circuit elements. Half bridge circuits such as the circuit illustrated in FIG. 7 provide some relief in that the primary winding voltage in the half bridge is one half of the line voltage. What is needed is a primary circuit structure that reduces the primary winding voltage to one quarter or one eighth of the line voltage or lower.
Many electronic circuits require power at more than one voltage, so power supply manufacturers offer power supplies with multiple regulated outputs. This was often an application for magnetic amplifiers, but magnetic amplifiers have become less popular as switching frequencies have risen and silicon semiconductor prices have fallen. One common way of providing additional regulated outputs in current use is illustrated in FIG. 16. Operational wave forms for the FIG. 16 circuit are illustrated in FIG. 17. In FIG. 16 a second regulated output is provided by a synchronously switched buck post regulator, which is a sort of semiconductor magnetic amplifier. In the FIG. 16 circuit an output choke L 1 is provided for the main output and a second output choke L 2 is provided for the second output. In general the first output voltage is fed back to control the primary switch and the second output is regulated with a local feedback loop which controls the delay in the turn on time of MS2A with respect to the turn on time of MS1A. This is leading edge modulation which is similar to that used in a magnetic amplifier. In most of these power converters there is a maximum power level which is the sum of the powers of the two outputs, but either of the two outputs can be operated at or near the maximum power level. This requires two output chokes each of which must be sized for the converter's maximum power level. An alternate method is illustrated in FIG. 18. The FIG. 18 circuit uses a coupled output choke to obviate two separate magnetic circuit elements sized for maximum power. In the coupled inductor the single core must be sized for maximum power and the window area must be sized to accommodate two windings each of which must be capable of accommodating the maximum output power. This is an improvement which results in a smaller and cheaper output choke, compared to the FIG. 16 circuit. The disadvantage of the FIG. 18 circuit is that the second output is not independently regulated and two secondary windings are required on the main transformer. What is needed is a circuit that achieves the performance of the FIG. 16 circuit but with lower total output choke volume.
FIG. 23 illustrates a ZVS coupled inductor buck converter employing a simple floating drive circuit based on capacitor coupling to an inverting driver integrated circuit (IC), UAUX. This floating drive circuit works well where the input source voltage is invariant, but the circuit can change state if there are voltage variations of the input source during the time that the switch MAUX is turned on causing erratic operation, power losses, and, in some cases, component failure. What is needed is a similar simple floating drive circuit that is tolerant of voltage variations of the input source.

OBJECTS AND ADVANTAGES

An object of the subject invention is to reveal a composite high voltage schottky rectifier that combines the low forward voltage properties of the schottky rectifier with the high voltage handling capability of a junction rectifier.
Another object of the subject invention is to reveal primary switching networks that reduce winding voltage stresses and semiconductor component stresses by comparison to a half bridge switching network.
Another object of the subject invention is to reveal a technique for achieving multiple independently regulated output voltages with reduced total magnetics volume.
Another object of the subject invention is to reveal a simple capacitor coupled gate drive circuit that is tolerant of voltage variations at the source terminal of the high side switch during the on time of the high side switch.
Further objects and advantages of my invention will become apparent from a consideration of the drawings and ensuing description.
These and other objects of the invention are provided by novel circuit techniques that combine a schottky barrier rectifier with a high voltage power mosfet to achieve a composite schottky rectifier with a lower forward voltage than can be achieved with a junction rectifier and a higher breakdown voltage than can be achieved with a schottky diode. Also revealed are primary switching circuits that provide significantly reduced voltage stresses to both power semiconductors and magnetic windings so that planar magnetic circuit elements become more practical. Also revealed are new circuit structures for achieving independently regulated outputs in a multi-output power supply with reduced magnetics volume. Also revealed is a simple capacitor coupled floating drive circuit that is tolerant of voltage variations at the terminals of the high side switch.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by reference to the drawings.
FIG. 1(a) illustrates a composite high voltage schottky rectifier according to the subject invention.
FIG. 1(b) illustrates a composite high voltage schottky rectifier with a capacitor connected in parallel to the schottky diode to reduce the maximum voltage applied to the schottky diode according to the subject invention.
FIG. 1(c) illustrates a composite high voltage schottky rectifier with a capacitor connected in parallel to the power mosfet in order to increase the source voltage of the power mosfet in the off state of the power mosfet according to the subject invention.
FIG. 1(d) illustrates a composite high voltage schottky rectifier with the important intrinsic parasitic circuit capacitances revealed according to the subject invention.
FIG. 2(a) illustrates a voltage wave form of the drain to anode voltage of the composite high voltage schottky rectifier according to the subject invention.
FIG. 2(b) illustrates a voltage wave form of the gate to anode voltage of the composite high voltage schottky rectifier according to the subject invention.
FIG. 2(c) illustrates a voltage wave form of the cathode to anode voltage of the composite high voltage schottky rectifier according to the subject invention.
FIG. 2(d) illustrates a voltage wave form of the gate to source voltage of the composite high voltage schottky rectifier according to the subject invention.
FIG. 3(a) illustrates a plot of the intrinsic drain source capacitor current versus source voltage of the composite high voltage schottky rectifier according to the subject invention.
FIG. 3(b) illustrates a plot of intrinsic drain source capacitor voltage versus source voltage of the composite high voltage schottky rectifier according to the subject invention.
FIG. 4(a) illustrates a composite high voltage schottky rectifier with the gate voltage source provided by a capacitor charged from the source of the power mosfet according to the subject invention.
FIG. 4(b) illustrates the FIG. 4(a) circuit with a capacitor added to reduce the maximum reverse voltage of the schottky diode according to the subject invention.
FIG. 5(a) illustrates a composite high voltage schottky rectifier with the gate voltage source provided by a capacitor charged from the drain of the power mosfet via a diode resistor network according to the subject invention.
FIG. 5(b) illustrates a composite high voltage schottky rectifier with the gate voltage source provided by a capacitor charged from the drain of the power mosfet via a resistor according to the subject invention.
FIG. 6 illustrates the power circuit of a boost converter incorporating the high voltage composite schottky rectifier according to the subject invention.
FIG. 7 illustrates a half bridge forward converter according to the prior art.
FIG. 8 illustrates a quarter bridge primary switching network according to the subject invention.
FIG. 9(a) illustrates the timing wave forms for the S 1A and S 1B switches of FIG. 8 according to the subject invention.
FIG. 9(b) illustrates the timing wave forms for the S 2A and S 2B switches of FIG. 8 according to the subject invention.
FIG. 9(c) illustrates the voltage wave form for the difference voltage between nodes A and B of FIG. 8 according to the subject invention.
FIG. 9(d) illustrates the node C voltage wave form of FIG. 8 according to the subject invention.
FIG. 9(e) illustrates the node D voltage wave form of FIG. 8 according to the subject invention.
FIG. 9(f) illustrates the node B voltage wave form of FIG. 8 according to the subject invention.
FIG. 9(g) illustrates the node A voltage wave form of FIG. 8 according to the subject invention.
FIG. 10 illustrates the quarter bridge primary switching network of the subject invention applied to a dc transformer circuit.
FIG. 11(a) illustrates an eighth bridge primary switching network according to the subject invention.
FIG. 11(b) illustrates an alternate eighth bridge primary switching network according to the subject invention.
FIG. 11(c) illustrates another alternate eighth bridge primary switching network according to the subject invention.
FIG. 12 illustrates the eighth bridge switching network of the subject invention applied in a forward converter.
FIG. 13 illustrates a composite power mosfet for use in a ZVS application according to the prior art.
FIG. 14 illustrates a composite power mosfet incorporating the composite high voltage schottky rectifier of the subject invention for use in a ZVS application.
FIG. 15 illustrates a dc transformer circuit incorporating the quarter bridge primary switching network and the composite high voltage schottky rectifier of the subject invention.
FIG. 16 illustrates a forward converter with two independently regulated outputs according to the prior art.
FIG. 17(a) illustrates the timing wave form for the MPRI and MS1A switches of FIG. 16.
FIG. 17(b) illustrates the timing wave form for the MS1B switch of FIG. 16.
FIG. 17(c) illustrates the timing wave form for the MS2A switch of FIG. 16.
FIG. 17(d) illustrates the timing wave form for the MS2B switch of FIG. 16.
FIG. 17(e) illustrates the current wave form for the L 1 inductor of FIG. 16.
FIG. 17(f) illustrates the current wave form for the L 2 inductor of FIG. 16.
FIG. 18 illustrates a forward converter with two outputs utilizing a single coupled output choke according to the prior art.
FIG. 19 illustrates a forward converter with two independently regulated outputs using a coupled output choke according to the subject invention.
FIG. 20(a) illustrates the timing wave form for the MPRI and MS1A switches of FIG. 19 according to the subject invention.
FIG. 20(b) illustrates the timing wave form for the MS1B switch of FIG. 19 according to the subject invention.
FIG. 20(c) illustrates the timing wave form for the MS2A switch of FIG. 19 according to the subject invention.
FIG. 20(d) illustrates the timing wave form for the MS2B switch of FIG. 19 according to the subject invention.
FIG. 20(e) illustrates the current wave form for the L 1A inductor of FIG. 19 according to the subject invention.
FIG. 20(f) illustrates the current wave form for the L 2 and L 1B inductors of FIG. 19 according to the subject invention.
FIG. 21 illustrates a forward converter with two independently regulated outputs using a coupled output choke with low magnetic coupling according to the subject invention.
FIG. 22 illustrates a current doubler rectifier forward converter with a quarter bridge primary network and two independently regulated outputs using coupled output chokes according to the subject invention.
FIG. 23 illustrates a ZVS coupled inductor buck converter with a capacitor coupled floating drive circuit according to the prior art.
FIG. 24 illustrates a ZVS active clamp flyback converter employing a capacitor coupled floating drive circuit according to the subject invention.
FIG. 25(a) illustrates a timing wave form for the main switch of the FIG. 24 circuit according to the subject invention.
FIG. 25(b) illustrates a timing wave form for the auxiliary switch of the FIG. 24 circuit according to the subject invention.
FIG. 25(c) illustrates a voltage wave form for the reset capacitor of the FIG. 24 circuit according to the subject invention.
FIG. 25(d) illustrates a voltage wave form of the floating drive coupling capacitor of the FIG. 24 circuit according to the subject invention.
FIG. 25(e) illustrates a current wave form of the floating drive coupling capacitor of the FIG. 24 circuit according to the subject invention.
FIG. 26 illustrates a variation of the capacitor coupled floating drive circuit of FIG. 24 according to the subject invention.
FIG. 27 illustrates a second variation of the capacitor coupled floating drive circuit of FIG. 24 according to the subject invention.
FIG. 28 illustrates a dc transformer circuit employing the quarter bridge primary network of the subject invention together with three of the capacitor coupled floating drive circuits of the subject invention used to drive the three high side switches of the quarter bridge circuit.

SUMMARY

The subject invention uses a circuit that combines a low voltage schottky diode with a high voltage power mosfet and a capacitor to achieve a composite high voltage schottky rectifier with low forward voltage and high reverse breakdown voltage. The subject invention also uses a four switch network with two pairs of capacitors to achieve a primary switching network with switch voltage stress equal to half the line voltage and primary winding voltage stress equal to one quarter the line voltage. The concept can be extended to achieve a primary switching network with winding voltage stress equal to one eighth of the line voltage. These networks make more practical the use of planar magnetics for off line power supply applications. The subject invention also reveals an improved capacitor coupled floating drive circuit that can be used to drive the three high side switches of the four switch network. The subject invention also reveals a circuit that can achieve multiple independently regulated outputs in a forward converter with lower overall magnetic circuit volume and cost.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1(a) illustrates a composite high voltage schottky rectifier circuit with its three essential components, a low voltage schottky diode, a dc gate voltage source, and a high voltage power mosfet. FIG. 1(d) illustrates the same circuit with its intrinsic parasitic capacitances. The intrinsic parasitic capacitances of consequence include the schottky diode capacitance, CCA, the gate source capacitance of the power mosfet, CGS, and the drain source capacitance of the power mosfet, CDS. Each of these intrinsic parasitic capacitances are voltage dependent, being larger in capacitance with lower applied voltage and smaller in capacitance at higher applied voltage. The power mosfet also has a drain gate parasitic capacitance which is not illustrated because its effects are insignificant and inconsequential. In a conducting state the schottky diode is forward biased and a voltage equal to the gate voltage source plus the forward voltage of the schottky diode is applied between the gate and source terminals of the power mosfet so that the power mosfet is fully enhanced and the channel of the power mosfet has a low resistance that contributes only a minor amount to the forward voltage of the composite high voltage schottky rectifier.
During an off transition the voltage at the node A in FIG. 1(a) is reduced with respect to the voltage at the node D in FIG. 1(a). As the node A voltage begins to fall the schottky diode becomes reverse biased and the power mosfet remains in an on state until the voltage at the node B rises with respect to the node A voltage to a point at which the gate to source voltage of the power mosfet is at its threshold voltage. As the node B voltage continues to rise the channel resistance of the power mosfet becomes large and the voltage across the drain to source terminals of the power mosfet rises. As the voltage across the composite rectifier continues to rise currents flow in the intrinsic capacitors illustrated in FIG. 1(d). The capacitor currents cause the drain to source capacitance and the schottky diode capacitance to charge and the gate to source capacitance to discharge. A voltage wave form for the node D voltage with respect to the node A voltage is illustrated in FIG. 2(a). Corresponding wave forms for node C and node B with respect to node A are illustrated in FIG. 2(b) and FIG. 2(c), respectively. The gate to source voltage wave form for the power mosfet is illustrated in FIG. 2(d). Note that the gate to source voltage (FIG. 2(d)) indicates that the power mosfet is turned on and off while the voltage at the gate of the mosfet with respect to the anode of the composite schottky rectifier (FIG. 2(b)) does not change.
FIG. 3(a) illustrates the drain to source capacitor current as a function of the node B voltage, referring to FIG. 1(a), for a typical power mosfet. FIG. 3(b) illustrates the drain to source capacitor voltage of the power mosfet as a function of the node B voltage. One can see from FIG. 3(a) that there is no current in the drain to source capacitor until the power mosfet reaches its threshold region where the channel current, which, in a likely application, will be the power converter's load current (or some multiple or fraction of the load current), transfers to the drain to source capacitance and to the drain to gate capacitance. The shape of the curve in FIG. 1(a) above the threshold region depends on the relative size of the drain to source and drain to gate capacitances and can vary considerably from one part type and manufacturer to another. The upward sloping curve of FIG. 3(b) is indicative of the fact that the drain to source capacitance typically falls as the drain to source voltage rises.
Each of the intrinsic parasitic capacitances, illustrated in FIG. 1(d), are non-linear, decreasing in capacitance as the voltage across the composite rectifier increases, however, the order of the capacitance decrease is much larger for the drain to source capacitance and the schottky diode capacitance compared to the decrease in the gate to source capacitance. The non-linear behavior of the intrinsic capacitances is not entirely consistent from one part type to another and also varies by manufacturer. Some high voltage mosfets may not be suitable for use in a composite schottky rectifier. Some power mosfets made by Fairchild have relatively large drain to source capacitance and the drain to source capacitance remains larger than the gate to source capacitance up to about 100 volts but continues to fall rapidly relative to the gate to source capacitance above the 100 volt range. More typically one finds the drain to source capacitance smaller than the gate to source capacitance over the entire voltage range or over the entire voltage range above a few volts and most typically one finds that the ratio of drain to source capacitance to gate to source capacitance continues to fall over the entire voltage range with a ratio in the range of 1:10 at about 50 volts. One of the more popular high voltage mosfets at the time of this writing is the CoolMOS series from Infineon. A typical ratio of drain to source capacitance to gate to source capacitance for drain to source voltage above 50 volts is 1:40 for the CoolMOS components so that the node B voltage will rise about 1 volt for every 40 volts of rise of the drain to source voltage for the range of voltages from 50 volts up to the breakdown voltage rating of the part. If the gate to source voltage is 10 volts during the on state and zero volts during the off state when the composite schottky rectifier voltage is 60 volts and the drain to source voltage is 50 volts, then for a six hundred volt CoolMOS power mosfet component the minimum gate to source voltage will be about −14 volts when the composite schottky rectifier voltage is 624 volts, neglecting the effects of the schottky diode capacitance, which will serve to reduce the negative gate voltage stress of the power mosfet.
By connecting a capacitor to the node B as illustrated in FIG. 1(b) or FIG. 1(c) one can alter the node B voltage and effect the gate to source voltage stress of the power mosfet. The capacitor connection illustrated in FIG. 1(b) serves to reduce the negative gate voltage stress of the power mosfet. If the ratio of gate to source capacitance to drain to source capacitance is very large then at relatively small rectifier reverse voltages the gate to source voltage may not fall much below the threshold voltage so that there may be more leakage current through the mosfet than desired. This situation is very unlikely with the power mosfets available at the time of this writing, but a capacitor placed as illustrated in FIG. 1(c) provides a simple remedy that causes the node B voltage to rise above the voltage it would have in the off state without the added capacitor thereby placing the gate to source voltage of the power mosfet further into the off region and reducing reverse currents in the power mosfet.
A practical implementation of the composite high voltage schottky rectifier is illustrated in FIG. 4(a). In the FIG. 4(a) circuit the gate drive dc voltage source is provided by a capacitor, C 1 , connected between the gate of the power mosfet M 1 and the anode of the schottky diode D 1 . The minimum capacitance of C 1 should be in the range of two orders of magnitude (100×) larger than the gate to source capacitance of the power mosfet M 1 , so that the voltage of C 1 will be substantially invariant over a switching cycle. C 1 is charged to a voltage sufficient to fully enhance the power mosfet by currents that flow through the resistor R 1 and the forward biased zener diode Z 1 . The C 1 voltage is clamped to its desired voltage by the zener diode Z 1 and the rectifier diode D 2 . FIG. 4(b) illustrates the FIG. 4(a) with an added capacitor that may be necessary to limit the gate negative voltage stress of the power mosfet.
FIG. 5(a) illustrates a second practical implementation of the composite high voltage schottky rectifier similar to the FIG. 4(a) circuit wherein the gate drive source capacitor C 1 is charged through a resistor R 1 and a rectifier diode D 2 in the drain circuit. Since the average drain to source voltage will be larger than the voltage needed to fully enhance the gate of the power mosfet in almost all applications the rectifier diode D 2 is not necessary and can be eliminated in most cases, as illustrated in FIG. 5(b).
FIG. 6 illustrates the composite high voltage schottky rectifier of the subject invention applied in a boost converter. The composite high voltage schottky rectifier provides an efficiency advantage by accomplishing lower forward voltage for lower conduction losses and by accomplishing reduced switching losses by elimination of reverse recovery effects, by comparison to an ultra-fast junction rectifier.
FIG. 7 illustrates a half bridge forward converter. In the half bridge converter the two equal value capacitors C 1 and C 2 divide the line voltage so that one half of the line voltage is applied to each of the two capacitors. Mosfets M 1 and M 2 alternate in a symmetrical way so that M 1 is on then both switches are off then M 2 is on then both switches are off so that, when one of the switches is on, only one half of the line voltage is applied to the primary winding of the transformer. One feature that is unique to the half bridge is that the voltage stress of the primary winding is one half of the line voltage. With reduced voltage stress for the primary winding only half the number of primary turns are required for a given core. This offers an advantage to converters that would use planar magnetics since windings with large numbers of turns are difficult and/or expensive to accomplish using planar magnetics. Large numbers of turns either require large numbers of layers which requires a high expense and reduces the window utilization factor, since for each additional copper layer an insulating layer must be added, thereby reducing the space available for copper, or a larger number of turns per layer is required which results in a lower window utilization factor, since for each turn on a printed circuit board layer an additional trace-to-trace clearance space must be added which reduces the space available for copper and the window utilization factor. It would be a great advantage to be able to use planar magnetics in off line power supply applications since planar magnetics offer a much lower vertical profile by comparison to conventional wound magnetics and by placing the windings on a printed circuit board the parasitic components are less variable and leakage inductance can be made to be much smaller by using a high degree of interleaving. FIG. 8 illustrates a quarter bridge primary switching network which reduces the voltage stress on the primary winding network to one quarter of the line voltage and simultaneously reduces the voltage stress applied to each of the primary switches to one half of the line voltage. As in the half bridge converter the switches are operated symmetrically so that the division of voltage between the capacitors C 1 and C 2 is maintained at one half of the line voltage for each capacitor. It is assumed that the capacitance of C 1 is equal to the capacitance of C 2 . In the quarter bridge switching network the switch S 1A is operated in full synchronization with switch S 1B, as illustrated in FIG. 9(a), and switch S 2A is fully synchronized with switch S 2B, as illustrated in FIG. 9(b). The maximum duty cycle for any switch is 50% and the duty cycle may be modulated in some cases in order to accomplish regulation. All of the switches are operated with the same duty cycle. During a first on state switches S 1A and S 1B are on so that the series combination of C 3 and C 4 is applied across the capacitor C 1 . It is assumed that the capacitance of C 3 is equal to the capacitance of C 4 . The voltage applied to the series combination of C 3 and C 4 divides equally between C 3 and C 4 so that the applied voltage to C 3 is one quarter of the line voltage and the applied voltage to C 4 is one quarter of the line voltage. During the first on state the voltage at the node A, illustrated in FIG. 9(g), at the left side of the primary winding network is equal to one half of the line voltage with respect to ground and the voltage at the node B, illustrated in FIG. 9(f), at the right side of the primary winding network is higher by the voltage of the capacitor C 4 since the switch S 1B is on. The voltage at the node B, illustrated in FIG. 9(f), is three quarters of the line voltage with respect to ground since the voltage of the capacitor C 4 is one quarter of the line voltage. Therefore the voltage applied to the primary winding network during the first on state is the voltage difference between the node B voltage and the node A voltage, which is illustrated in FIG. 9(c), or three quarters of the line voltage minus one half of the line voltage, or one quarter of the line voltage. During the first on state capacitors C 2 and C 3 are charging and capacitors C 1 and C 4 are discharging. During a first off state all four switches are off and the voltage applied to the primary winding network is zero. During the first off state the node D voltage, illustrated in FIG. 9(e), is at one quarter of the line voltage, the node A voltage and the node B voltage are at one half of the line voltage, and the node C voltage, illustrated in FIG. 9(d), is at three quarters of the line voltage, all with respect to ground. During a second on state, the duration of which is identical to the first on state, the switches S 2A and S 2B are on, applying the capacitor C 2 voltage across the series combination of capacitor C 3 and capacitor C 4 . The voltage at node A remains at one half of the line voltage but the voltage at node B drops to one quarter of the line voltage since the negative terminal of capacitor C 4 is connected to ground through S 2B. Therefore the voltage applied to the primary winding network during the second on state is the voltage difference between the node B voltage and the node A voltage, or one quarter of the line voltage minus one half of the line voltage, or minus one quarter of the line voltage. During the second on state capacitors C 1 and C 4 are charging and capacitors C 2 and C 3 are discharging. During a second off state, the duration of which is identical to the first off state, the node voltages are exactly the same as they were during the first off state. After the second off state the operating cycle is complete and a new operating cycle begins. No aspect of the operation of the circuit requires or depends on the matching of capacitor values. If the capacitance values are unequal in either capacitor leg the charge flow will be altered so that the larger capacitor handles proportionately more of the charge flow and the smaller capacitor handles proportionately less of the charge flow. There is no advantage to purposely choosing different value capacitors. Each capacitor should be sufficiently large so that its voltage is substantially invariant during a full switching cycle. One benefit of the subject invention is that the switch voltage stress is equal to one half of the line voltage.
FIG. 10 illustrates the subject invention applied to a full bridge transformer operated as a dc transformer. For the FIG. 10 circuit the output voltage will be one quarter of the line voltage multiplied by the secondary to primary turns ratio. In the FIG. 10 circuit the switches are accomplished with power mosfets operated at 50% duty cycle. In a practical application the duty cycle will be slightly less than 50% to allow for some dead time to accomplish zero voltage switching.
FIG. 11(a) illustrates an eighth bridge primary switching network which adds a second leg of four switches and a third leg of two capacitors to the quarter bridge primary switching network in order to accomplish a circuit that applies one eighth of the line voltage to the primary winding network. The switches in the added second leg of four switches experience only one quarter of the line voltage as a voltage stress and the capacitors in the added third capacitor leg experience only one eighth of the line voltage as a voltage stress. Alternate arrangements of the eighth bridge primary switching network that accomplish identical results are illustrated in FIG. 11(b) and FIG. 11(c). In FIG. 11(a), FIG. 11(b), and FIG. 11(c) switches S 1A, S 1B, S 1C, and S 1D are operated in full synchronization with a maximum duty cycle of 50% and switches S 2A, S 2B, S 2C, and S 2D are also operated in full synchronization with a maximum duty cycle of 50%.
FIG. 12 illustrates the circuit of FIG. 11(b) implemented with power mosfets in a forward converter with push pull secondary windings, as one example.
In off line zero voltage switching applications it is common to see the switch arrangement of FIG. 13 where a schottky diode is placed in series with the high voltage power mosfet to block body diode currents and an ultra-fast high voltage junction rectifier is placed in anti-parallel with the power mosfet to provide a path for reverse currents that would otherwise flow in the body diode. The FIG. 13 circuit is used to avoid the body diode conduction because the reverse recovery time of the body diode of high voltage power mosfets can be long, in some cases it may be longer than the on time of the power mosfet, particularly in transient conditions where the body diode can remain conducting after the gate has been driven below its threshold voltage. In a full bridge, half bridge, or quarter bridge circuit the failure of a power mosfet to turn off due to body diode reverse recovery can lead to a catastrophic failure in the absence of a circuit such as the FIG. 13 circuit that eliminates the body diode conduction. An alternate method would be to use a high voltage schottky diode whose forward voltage is lower than the forward voltage of the body diode. Unfortunately high voltage schottky diodes with low forward voltages due not exist at the time of this writing. A practical alternate method utilizes the composite high voltage schottky rectifier of the subject invention, as illustrated in FIG. 14. In FIG. 14 the composite high voltage schottky rectifier provides an alternate path for current that would otherwise flow in the body diode of the power mosfet M 1 . In order for the circuit of FIG. 14 to be effective the forward voltage of the composite high voltage schottky rectifier must be less than the forward voltage of the body diode for the maximum reverse current. The forward voltage for the composite high voltage schottky rectifier consists of the forward voltage of the schottky diode D 1 plus the drain source voltage of the power mosfet M 2 , when M 2 is in its on state. FIG. 15 illustrates the quarter bridge primary network incorporating composite high voltage schottky rectifiers in order to eliminate body diode conduction in the switches of the quarter bridge circuit. The application is a dc transformer circuit which can be made to be a zero voltage switching circuit.
FIG. 16 illustrates a single-ended forward converter with two outputs that can be independently regulated. The first output relies on modulation of the primary switch to achieve its regulation. The second output relies upon a second local control loop (not shown) to accomplish its regulation. The second output is a synchronously switched buck converter which is also referred to as a semiconductor magnetic amplifier since the switch control is similar to that of a magnetic amplifier. The main switch, MS2A, of the second output's buck converter is turned off in synchronization with the first output in each switching cycle and turned on after the switch MS1A during each switching cycle. Wave forms of the switch timing and output choke currents are illustrated in FIGS. 17(a) through 17(f). In commercial multi-output power supplies the designer's goal is to provide two independently regulated outputs, each of which can handle the converter's full output power rating in order to accommodate the broadest range of customers. In the FIG. 16 circuit each of the two output chokes must be sized to accommodate the full output load. FIG. 18 illustrates another prior art example that has been used for multi-output power supplies. In the FIG. 18 circuit there is a single output choke that accommodates both outputs, but the two outputs cannot be independently regulated in the FIG. 18 circuit. Different voltage levels can be set by adjusting the turns ratios for the two outputs. The turns ratio for the secondary windings should match the turns ratio for the coupled inductor windings in order for the output currents to be non-pulsating. The FIG. 18 circuit has the advantage of smaller magnetics over the FIG. 17 circuit, since the two outputs share a common magnetic core, but the two outputs are not independently regulated. The common magnetic core of the two outputs of the FIG. 18 circuit need only be large enough to handle the full power of the power supply.
FIG. 19 illustrates a two output power supply with independently regulated outputs that uses a common magnetic core for the two outputs, thereby saving the space of another large core sized to handle the full output power, plus a second much smaller core, L 2 , with a much smaller inductance that adds the ability to independently regulate the second output in a synchronously switched buck converter. In the FIG. 19 circuit the first output is controlled by controlling the duty cycle of the primary switch MPRI. The switch MS1A is operated in full synchronization with MPRI and the switch MS1B is operated in anti-synchronization to MPRI. A wave form illustrating the switch timing for MPRI and MS1A is illustrated in FIG. 20(a). A wave form illustrating the timing for the MS1B switch is illustrated in FIG. 20(b). The output voltage for the first output is determined by the duty cycle of MPRI and the turns ratio of the transformer T. For the second output the switch MS2A is turned off in synchronization with MPRI, but MS2A is turned on after MPRI so that there is a delay between the time MPRI is turned on and the time at which MS2A is turned on, as illustrated in FIG. 20(c). Switch MS2B turns on in synchronization with switch MS1B when MPRI is turned off, but MS2B turns off after MS1B is turned off due to the delay in the turn on of MS2A. MS2B operates in anti-synchronization to MS2A, as illustrated in FIG. 20(d). Because MS2A is delayed with respect to MPRI and MS1A the duty cycle for the second output will be less than the duty cycle for the first output and the voltage at the second output will be less than the voltage at the first output. The inductor L 2 forces the output current for the second output to be non-pulsating since an infinite voltage would be required to create a step change in current in L 2 . The current in L 1A is also non-pulsating, since there is no mechanism in the circuit to instantly interrupt current flow in either L 1A or L 1B. Current in L 1A is provided through MS1A and the transformer secondary winding when MPRI is on or through MS1B when MPRI is off, although L 1A could still be pulsating despite this fact, but only if the current in L 1B is interrupted. L 2 forces the current in L 1B to be continuous. The currents in L 1A and L 1B will both be continuous, but they will not, in general, be simple triangular wave forms. A current wave form for L 1A is illustrated in FIG. 20(e) and a corresponding wave form for L 1B current is illustrated in FIG. 20(f). The current in L 1B must be equal to the current in L 2 , since the two windings are in series. The slope of the current in L 2 will depend on the value of L 2 and the voltage applied to L 2 . During the course of one switching cycle there are three different values of applied voltage for L 2 . When MPRI is off MS1B and MS2B are on and the voltage at the node A is zero. While MPRI is off the dotted terminal of L 2 is at ground and the undotted terminal of L 2 is at a voltage V₁, where $V_{1} = V_{OUT2} - \frac{N_{2}}{N_{1}} * V_{OUT1}, V_{OUT2}$
is the output voltage of the second output, V_OUT1is the output voltage of the first output, N₂is the number of turns of L 1B, and N₁is the number of turns of L 1A. Depending on the turns ratio, $\frac{N_{2}}{N_{1}},$
the current slope of L 2 during the time that MPRI is off can be positive, negative, or zero. In the example illustrated the current slope of L 2 is near zero during the off time of MPRI, as illustrated in FIG. 20(f). When MPRI turns on, MS1A also turns on, and the voltage at the node A becomes positive, such that $V_{A} = \frac{N_{SEC}}{N_{PRI}} * V_{INPUT},$
where V_INPUTis the voltage of the input source, N_PRIis the number of primary turns of transformer T, and N_SECis the number of secondary turns of transformer T. While MS1A is on and MS2B remains on, the voltage at the undotted terminal of L 2 is V₂, where $V_{2} = V_{OUT2} + \frac{N_{2}}{N_{1}} * (V_{A} - V_{OUT1}),$
so that the undotted terminal of L 2 is higher in voltage than the dotted terminal of L 2 and the current in L 2 must be decreasing. In the example illustrated the rate of decreasing current is relatively large for this example while MPRI is on and MS2A is off, as illustrated in FIG. 20(f). When MS2B turns off and MS2A turns on, while MPRI and MS1A remain on, the voltage at the dotted terminal of L 2 is V_Aand the voltage at the undotted terminal of L 2 is V₂and the voltage applied to L 2 is V₃, where V₃=V_A−V₂. During the on time of MS2A, the current slope in L 2 can be positive, negative, or zero depending on the turns ratio, $\frac{N_{2}}{N_{1}},$
and the values of V_A, V_OUT1, and V_OUT2. In the example illustrated the current slope in L 2 is positive, as illustrated in FIG. 20(f). In a practical application the current slope of L 2 during the on time of MS2A will, in general, be positive. Since L 2 is connected in series with L 1B the current in L 1B will always be equal to the current in L 2 . The current slope in L 1A will depend on the voltage applied to L 1A and on the current slope of L 1B and L 2 . The relationship between the voltage applied to L 1A and its current slope is $\begin{matrix} \begin{matrix} V_{L1A} = L_{1 A} * \frac{ⅆ I_{L1A}}{ⅆ t} + M_{12} * \frac{ⅆ I_{L1B}}{ⅆ t} \\ = L_{1 A} * \frac{ⅆ I_{L1A}}{ⅆ t} + M_{12} * \frac{ⅆ I_{L2}}{ⅆ t}, \end{matrix} & (1) \end{matrix}$
where V_L1Ais the L 1A applied voltage, I_L1Ais the current in L 1A, I_L1Bis the L 1B current, M₁₂is the L 1A L 1B mutual inductance, and I_L2is the L 2 current. From equation (1) we can solve for the L 1A current slope so that $\begin{matrix} \frac{ⅆ I_{L1A}}{ⅆ t} = \frac{V_{L1A}}{L} - \frac{M_{12}}{L_{1 A}} * \frac{ⅆ I_{L2}}{ⅆ t} . & (2) \end{matrix}$
From equation (2) we see how the L 1A current slope depends on both the voltage applied to the L 1A winding and the current slope in the L 1B winding. The turns ratio, $\frac{N_{2}}{N_{1}},$
should be set to provide a minimum average applied voltage for L 2 in order to minimize the current slopes and output ripple currents, which serves to minimize the size of L 2 . The primary benefit of the subject invention is a reduction in total magnetics volume combined with independent regulation of both outputs. The reduction of magnetics volume is accomplished by using a common core for the L 1A and L 1B windings so that only one large core capable of handling the full output power is required. A second smaller inductor, L 2 , is required to provide independent regulation for both outputs.
FIG. 21 illustrates the subject invention with series inductances l 1A and l 1B, which represent the leakage inductances or uncoupled inductances in each winding of L 1 . In general, it is preferable to loosely couple the windings in a coupled inductor forward converter application, thereby increasing the leakage inductances, since the main advantage of using the common core for both outputs is a size and cost reduction, not a performance improvement. The effect of the leakage inductance here is to improve the overall ripple performance. The relatively large leakage inductances, in comparison to a tightly coupled L 1 , provide additional current smoothing without an additional magnetic circuit element.
FIG. 22 illustrates a multi-output current doubler rectifier forward converter with a quarter bridge primary switching network and independently regulated outputs according to the subject invention. In the FIG. 22 circuit planar magnetics become more practical because of the reduction of primary winding voltage stress. In the current doubler configuration two chokes are required for each output. In the FIG. 22 circuit two independently regulated outputs are achieved using two large chokes and two small chokes.
FIG. 23 illustrates a ZVS coupled inductor buck converter employing a simple capacitor coupled floating drive circuit for driving the high side power mosfet switch, MAUX. The floating drive circuit is powered by a floating bootstrap capacitor, CBOOT, that is charged through DBOOT during the on time of the main switch, MMAIN. When the PWM drive signal for the main switch MMAIN goes low the main switch turns off and the same PWM drive signal that turns off the main switch is transmitted via CAUX to the input of the inverting gate driver IC, UAUX, forcing the output of the inverting gate driver IC, UAUX, to go high, turning on the auxiliary switch, MAUX. During this transition the source voltage of the auxiliary switch MAUX is rising quickly, which forces the input to UAUX low relative to the floating ground reference terminal of UAUX, due to the coupling capacitor CAUX which, absent any change in the PWM drive signal, tries to hold the input terminal of UAUX fixed with respect to primary circuit ground. The input signal to UAUX is held low during the switching transition as a result of the voltage rise of the source of MAUX during the switching transition after UAUX initially changes state as a result of the drive signal provided to turn off the main switch. The clamp diodes at the input to UAUX prevent the input voltage to UAUX from exceeding the supply voltage rails of UAUX and the resistor RAUX limits the current in the clamp diodes to a current less than their maximum current rating during the switching transitions.
When the PWM drive signal to the main switch goes high, this same PWM gate drive signal is transmitted to the input of UAUX by CAUX, which results in the output of UAUX going low which turns off MAUX at the same instant that MMAIN is turned on. During the subsequent switching transition the source voltage of UAUX falls rapidly, which forces the input to UAUX high, relative to the floating ground reference terminal of UAUX, due to the coupling capacitor, CAUX, which, absent any changes in the PWM drive signal, tries to hold the input to UAUX fixed with respect to the primary circuit ground. A high input signal to UAUX results from the voltage fall of the source of MAUX during the switching transition after UAUX initially changes state as a result of the drive signal provided to turn on the main switch. The capacitor coupled floating drive circuit of FIG. 23 works well when the source voltage of MAUX does not change during the on time of MAUX. A drop in voltage at the source of MAUX during the on time of MAUX can turn off MAUX, which would be an undesirable result.
FIG. 24 is a ZVS active clamp flyback converter employing an improved capacitor coupled floating drive circuit, which adds a non-inverting buffer UAUX2 and a resistor RFB to the capacitor coupled floating drive circuit of FIG. 23. The improved capacitor coupled floating drive circuit is powered by a bootstrap capacitor CBOOT which is charged through a bootstrap diode DBOOT during the on time of the main switch MMAIN. Although it may not be necessary, it is preferred that the input to UAUX2 be a Schmitt trigger input. A Schmitt trigger input is an input with a variable threshold voltage incorporating hysteresis, so that, when the input is high, the threshold voltage for a change of state is lower than the threshold voltage for a change of state when the input is low. The use of a Schmitt trigger input is typically without cost since these are readily available and no more expensive than standard input logic integrated circuits. FIG. 25(a) illustrates the switch timing of the main switch MMAIN in FIG. 24 and FIG. 25(b) illustrates the switch timing for the auxiliary switch MAUX of FIG. 24. A turn off transition of the main switch MMAIN begins when the PWM drive signal changes from a high state to a low state. The same PWM drive signal for the main switch MMAIN is transmitted to the input of UAUX2 through CAUX and RAUX, which causes the output of UAUX2 to go low and the output of UAUX1 to go high, which turns on the auxiliary switch MAUX. When the auxiliary switch MAUX is turned on, current at first flows into the capacitor, CRESET, through MAUX. After the switch MAUX is turned on, the current in CRESET drops until the current reaches zero and reverses direction and increases to a current equal in magnitude, but opposite in direction, to the CRESET current at the beginning of the on time of MAUX. As a result of the current in CRESET, the voltage of CRESET changes, as illustrated in FIG. 25(c). As a result of the changing voltage in CRESET the voltage at the source terminal of MAUX, during the on time of MAUX, also changes with the CRESET voltage. There is a corresponding change in CAUX voltage during the on time of MAUX, as illustrated in FIG. 25(d), which creates a corresponding current in CAUX, as illustrated in FIG. 25(e). The current in CAUX also flows in RAUX and RFB. Some of the CAUX current flows in RAUX and DCLAMP2 , as the CRESET and CAUX voltages rise during the on time of MAUX. During this time some of the current also flows in RFB, but there is no change of state of UAUX2 during this time period because both the input and output of UAUX2 remain in the low state. The current in CAUX forces the input of UAUX2 lower, thereby forward biasing DCLAMP2 . Eventually the current in MAUX and CRESET reaches zero and reverses, at which time the current flowing in CAUX also reverses and significant current no longer flows in RAUX, since the input impedance of UAUX2 is very high and current in RAUX reverse biases DCLAMP2 . For a typical integrated circuit buffer the input resistance is in the range of teraohms (10¹²ohms) so that the current in RAUX is zero, for all practical purposes, after the current in CRESET reverses direction. The CAUX current will flow in RFB and the UAUX2 input voltage will rise due to the IR drop of RFB after the current in CRESET reverses direction. For a typical active clamp flyback converter the voltage change of the reset capacitor is larger, usually much larger, than the logic supply voltage, so that, without RFB, the voltage change of CRESET and CAUX, when the switch MAUX is on and the voltage of CRESET and CAUX are decreasing, is more than sufficient to cause UAUX2 to change state, which would result in the unintentional turn off of MAUX. With RFB in place the current in CAUX creates a rise in UAUX2 input voltage, but the rise in UAUX2 input voltage will be insufficient to cause a change of state in UAUX2 , unless the value of RFB is too large. UAUX2 will change state if the UAUX2 input voltage reaches a threshold voltage, V_Threshold. For a Schmitt input buffer with +5 volt logic supply voltage a typical minimum threshold voltage, V_Threshold, is about 2.5 volts. The current in CAUX, I_CAUX, depends on the rate of voltage change of $C_{AUX}, \frac{ⅆ V_{CAUX}}{ⅆ t},$
and is given by $I_{CAUX} = C_{AUX} * \frac{ⅆ V_{CAUX}}{ⅆ t}, where C_{AUX}$
is the capacitance value of CAUX. The rate of voltage change of CAUX, $\frac{ⅆ V_{CAUX}}{ⅆ t},$
is related to the rate of voltage change of CRESET, $\frac{ⅆ V_{CRESET}}{ⅆ t} \cdot \frac{ⅆ V_{CAUX}}{ⅆ t} \leq \frac{ⅆ V_{CRESET}}{ⅆ t}$
and the equality applies when R_FB=0, so that, in general $\frac{ⅆ V_{CAUX}}{ⅆ t} < \frac{ⅆ V_{CRESET}}{ⅆ t} .$
The current in CRESET is given by $I_{CRESET} = C_{RESET} * \frac{ⅆ V_{CRESET}}{ⅆ t},$
where I_CRESETis the current in CRESET and C_RESETis the capacitance value of CRESET. The maximum rate of change of voltage for CRESET and CAUX will occur at maximum load and minimum line voltage and results in the maximum peak current, I_PEAK, in MMAIN and Lzvs, which can be determined from circuit component values, the maximum load, and the minimum line voltage. A maximum value for $\frac{ⅆ V_{CRESET}}{ⅆ t} and \frac{ⅆ V_{CAUX}}{ⅆ t}$
can be determined based on I_PEAKand is given by $\frac{ⅆ V_{CAUX}}{ⅆ t} < \frac{ⅆ V_{CRESET}}{ⅆ t} \leq \frac{I_{PEAK}}{C_{RESET}} .$
If the voltage drop in RFB is always less than the UAUX2 input threshold voltage, V_Threshold, then unintentional state changes of UAUX2 can be prevented. The voltage of RFB is given by $V_{RFB} = I_{CAUX} * R_{FB} = R_{FB} * C_{AUX} \frac{ⅆ V_{CAUX}}{ⅆ t} \leq R_{FB} * C_{AUX} * \frac{ⅆ V_{CRESET}}{ⅆ t} \leq \frac{R_{FB} * C_{AUX} * I_{PEAK}}{C_{RESET}},$
where V_RFBis the voltage of RFB and R_FBis the resistance value of RFB. If R_FBwere equal to zero then there could be no changes of state to UAUX2 , but this is undesirable since it is desired to change the state of MAUX, which requires that UAUX2 also change state. R_FBneeds to be sufficiently small to reject UAUX2 changes of state due to CRESET voltage drops during the on time of MAUX, but sufficiently large to enable intentional state changes of UAUX2 when the PWM drive source changes state. During the on time of MAUX, in order to avoid unintentional turn off of MAUX, we must have V_RFB<V _Thresholdwhich can be achieved if R_FB $R_{FB} < \frac{V_{Threshold} * C_{RESET}}{I_{PEAK} * C_{AUX}} .$
As a numerical example, for a 150 watt off line active clamp flyback converter under development at the time of this writing, V_Threshold=2.5 volts, I_PEAK=3 amperes, C_AUX=5 picofarads, and C_RESET=220 nanofarads, so that R_FBmust be less than 36 kiloohms. In the circuit under development R_FBmust be larger than 3 kiloohms in order to provide a change of voltage greater than the threshold voltage at the UAUX2 input in response to a change of state of the PWM drive source. In the current example a R_FBvalue near the geometric mean of the minimum and maximum acceptable values can be chosen and reliable operation can be expected with ample margins. If the range of acceptable values of R_FBis too narrow or non-existent then the situation can be most easily remedied by increasing C_RESET. Alternate remedies are increasing V_Thresholdand reducing I_PEAK, but both of the alternate remedies involve other consequences to the circuit operation and cost that may be unacceptable or much more difficult to achieve. Decreasing C_AUXincreases both the minimum acceptable value of R_FBand increases the maximum acceptable value of R_FB, so that decreasing C_AUXhas no benefit to the problem of insufficient range of acceptable R_FBvalues.
A turn on transition of the main switch MMAIN begins when the PWM drive signal changes from a low state to a high state. The PWM drive signal is transmitted to the UAUX2 input via CAUX, which forces the output of UAUX2 to a high state and forces the output of UAUX1 to a low state, thereby turning off MAUX. During the turn on transition of MMAIN the source voltage of MAUX falls rapidly, which has the result of forcing the input of UAUX2 high, discharging CAUX through RAUX and DCLAMP3 , and reinforcing the change initiated by the change in state of the PWM drive signal. During the on time of MMAIN, the source voltage of MAUX is held at the primary ground potential or zero volts for the duration of the on time of MMAIN. During the on time of MMAIN, there is no change in the MAUX source voltage and no mechanism in play to cause an unintentional change of state in MAUX.
FIG. 26 illustrates an alternate arrangement of the capacitor coupled floating drive circuit of the subject invention wherein two inverting gates are used to provide the positive current feedback via RFB and a non-inverting gate driver IC is used in place of the inverting gate driver IC of FIG. 24. Another alternate arrangement is illustrated in FIG. 27. In the FIG. 27 arrangement two inverters are used with an inverting gate driver IC to achieve the same results achieved in the FIG. 24 and FIG. 26 circuits, except that the propagation delay of the FIG. 27 circuit will be larger since there are three gates connected in series in FIG. 27 versus two in series for FIGS. 24 and 26.
FIG. 28 illustrates the use of the capacitor coupled floating drive circuit in a quarter bridge dc transformer circuit, according to the subject invention. The capacitor coupled floating drive circuit revealed in FIG. 24 is applied to the three high side switches in the quarter bridge primary switching network. The drive signal for the single low side switch M 2B is used to provide the input for the M 1A and M 1B switches. An inverted low side drive source must be added, as shown, to provide the input drive signal for the M 2A high side switch. The use of the capacitor coupled floating drive circuits of the subject invention in the quarter bridge primary switching network provides an inexpensive and reliable gate drive solution that is insensitive to voltage variations resulting from the charging and discharging of the circuits capacitors.

CONCLUSION, RAMIFICATIONS, AND SCOPE OF INVENTION

Thus the reader will see that a simple circuit comprising a schottky rectifier, a high voltage mosfet, and a dc source of voltage can provide a composite high voltage schottky rectifier with the low conduction losses of a schottky rectifier and the high voltage stress capabilities of a high voltage mosfet, thereby combining the benefits of both circuit elements in a single simple circuit structure. The reader will also see that the dc source of voltage can be implemented in a number of simple ways with the simplest dc source of voltage comprising a zener diode, a resistor, and a capacitor. The reader will also see that a quarter bridge primary switching network can be formed from four capacitors and four switches to provide a primary switching network that applies one quarter of the line voltage to a primary winding network and half of the line voltage to the switches. The same techniques used to achieve the quarter bridge switching network can be extended to achieve a one eighth bridge network. The reader will also see that a multi-output power supply using a secondary side synchronously switched post buck regulator can be improved by combining the output chokes onto a single core capable of handling the converter's full power and adding a small choke for the second output to provide fully independent regulation of the outputs. The reader will also see that an improved capacitor coupled floating drive circuit can be formed by providing a novel positive current feedback mechanism that results in the rejection of slowly varying currents that could otherwise cause an unintentional change in state of a switch.
While my above description contains many specificities, these should not be construed as limitations on the scope of the invention, but rather, as exemplifications or preferred embodiments thereof. Many other variations are possible. For example, a one sixteenth bridge primary switching network and higher order bridge primary switching networks are possible by extending the techniques revealed in this application, power converters with more than two independently regulated outputs using a single large output coupled inductor plus much smaller chokes for the second and successive outputs are possible using the techniques revealed here, a composite high voltage schottky rectifier utilizing a P channel mosfet or IGBT instead of the N channel mosfet are also possible, and many other digital networks that provide a similar positive current feedback mechanism for a capacitor coupled floating drive circuit are possible. Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their legal equivalents.

Claims

1. A composite high voltage schottky rectifier having an anode terminal and a cathode terminal comprising,

a schottky diode having an anode terminal connected to said anode terminal of said composite high voltage schottky diode and having a cathode terminal,

a high voltage N channel power mosfet having a source terminal connected to said cathode terminal of said schottky diode, a drain terminal connected to said cathode terminal of said composite high voltage schottky diode, and a gate terminal,

a source of dc potential having a positive terminal connected to said gate terminal of said high voltage N channel power mosfet and having a negative terminal connected to said anode terminal of said schottky diode,

whereby said composite high voltage schottky diode accomplishes both high reverse voltage greater than, but substantially equal to, the breakdown voltage of said high voltage N channel power mosfet and a forward voltage drop substantially less than a junction rectifier thereby achieving higher efficiency than a high voltage junction rectifier.

2. The composite high voltage schottky rectifier of claim 1 further comprising,

a capacitor having a terminal connected to said cathode terminal of said schottky diode.

3. The composite high voltage schottky rectifier of claim 1 integrated onto a single die.

4. A secondary side buck post regulator for a second output of a multi-output forward converter comprising,

a first coupled inductor having a first winding and a second winding with an undotted terminal of said first winding connected to a first output of said multi-output forward converter and with said second winding connected in series with said second output of said multi-output forward converter,

a second inductor connected in series with said second winding of said first coupled inductor,

first switch means having a drain terminal connected to a dotted terminal of said first winding of said first coupled inductor,

second switch means, operable substantially in anti-synchronization to said first switch means, having a source terminal connected to an output terminal, which is common to said first output and to said second output of said multi-output forward converter and having a drain terminal connected to a source terminal of said first switch means and connected to a series winding network comprising said second inductor and said second winding of said first coupled inductor,

whereby said secondary side buck post regulator provides a second precisely regulated output with reduced magnetics volume and cost.

5. A capacitor coupled floating gate drive circuit comprising,

an alternating source of voltage having two operating voltage states separated by a substantially fixed dc voltage difference and having at least a first terminal and a second terminal with said first terminal of said alternating source of voltage connected to a first reference voltage having a substantially fixed dc voltage difference to one of said operating voltage states of said alternating source of voltage.

a capacitor having two terminals with said first terminal of said capacitor coupled to said second terminal of said alternating source of voltage,

a digital logic and drive circuit having at least a first input terminal, a first output terminal, a second output terminal coupleable to a gate terminal of a mosfet, a first supply voltage terminal, and a reference terminal coupleable to a source terminal of said mosfet, wherein the voltage signal appearing at said first output terminal is substantially in synchronization with the voltage applied at said first input terminal and the voltage signal appearing at said second output terminal is substantially in anti-synchronization to the voltage applied at said first input terminal,

a first clamp diode having an anode terminal and a cathode terminal with said anode terminal of said first clamp diode connected to said first input terminal of said digital logic and drive circuit and said cathode terminal of said first clamp diode connected to said first supply voltage terminal of said digital logic and drive circuit,

a second clamp diode having an anode terminal and a cathode terminal with said cathode terminal of said second clamp diode connected to said first input terminal of said digital logic and drive circuit and said anode terminal of said second clamp diode connected to said reference terminal of said digital logic and drive circuit,

a first resistor having two terminals with said first terminal of said first resistor coupled to said second terminal of said capacitor and with said second terminal of said first resistor coupled to said first input terminal of said digital logic and drive circuit,

a second resistor having two terminals with said first terminal of said second resistor coupled to said first output of said digital logic and drive circuit and said second terminal of said second resistor coupled to said second terminal of said capacitor,

whereby said first resistor provides current limiting to protect said first and second clamp diodes from over current associated with quickly varying applied voltage changes to said capacitor, said second resistor provides positive current feedback for rejecting capacitor currents associated with slowly varying applied voltage changes to said capacitor, and said digital logic and drive circuit provides an output signal at said second output terminal, which is substantially in anti-synchronization to said alternating source of voltage applied at said first terminal of said capacitor, for enhancing said gate of said mosfet.

6. The capacitor coupled floating gate drive circuit of claim 5 wherein said first input of said digital logic and drive circuit is a Schmitt trigger input.

7. The capacitor coupled floating gate drive circuit of claim 5 wherein said clamp diodes are integrated into said digital logic and drive circuit.

8. A quarter bridge switching network comprising,

an input coupleable to a source of dc power having a positive terminal and a negative terminal,

an output coupleable to a winding network having first and second terminals,

a first capacitor leg comprising,

a first capacitor having first and second terminals with said first terminal of said first capacitor connected to said positive terminal of said input,

a second capacitor having a first terminal and a second terminal with said first terminal of said second capacitor connected to said second terminal of said first capacitor and with said second terminal of said second capacitor connected to said negative terminal of said input,

a first switch leg comprising,

first switch means having first and second terminals with said first terminal of said first switch means connected to said positive terminal of said input,

second switch means having first and second terminals with said first terminal of said second switch means connected to said second terminal of said first switch means and with said second terminal of said second switch means connected to said second terminal of said first capacitor,

third switch means having first and second terminals, operable substantially in synchronization with said first switch means, with said first terminal of said third switch means connected to said second terminal of said second switch means,

fourth switch means having first and second terminals, operable substantially in synchronization with said second switch means, with said first terminal of said fourth switch means connected to said second terminal of said third switch means and with said second terminal of said fourth switch means connected to said negative terminal of said input,

a second capacitor leg comprising,

a third capacitor having first and second terminals with said first terminal of said third capacitor connected to said second terminal of said first switch means,

a fourth capacitor having first and second terminals with said first terminal of said fourth capacitor connected to said second terminal of said third capacitor and with said second terminal of said fourth capacitor connected to said second terminal of said third switch means,

whereby an ac voltage of peak value substantially equal to one quarter of the voltage of said source of dc power connected at said input is created between said second terminal of said first capacitor and said second terminal of said third capacitor.

9. The quarter bridge switching network of claim 8 wherein said first terminal of said output is connected to said second terminal of said first capacitor and said second terminal of said output is connected to said second terminal of said third capacitor.

10. The quarter bridge switching network of claim 8 further comprising four composite high voltage schottky rectifiers of claim 1, with one composite high voltage schottky rectifier in parallel with each of said four switch means, whereby said composite high voltage schottky rectifier eliminates body diode conduction in each of said four switch means.

11. The quarter bridge switching network of claim 8 applied to a forward converter having multiple outputs with one of said multiple outputs employing said secondary side post regulator of claim 4.

12. The quarter bridge switching network of claim 8 further comprising three of said capacitor coupled floating gate drive circuits of claim 5 for driving said first, second, and third switch means.

13. An eighth bridge switching network comprising the quarter bridge switching network of claim 8 and further comprising,

a second switch leg comprising,

fifth switch means having first and second terminals, operable substantially in synchronization with said first switch means, with said first terminal of said fifth switch means connected to said second terminal of said first switch means,

sixth switch means having first and second terminals, operable substantially in synchronization with said second switch means, with said first terminal of said sixth switch means connected to said second terminal of said fifth switch means and with said second terminal of said sixth switch means connected to said second terminal of said third capacitor,

seventh switch means having first and second terminals, operable substantially in synchronization with said first switch means, with said first terminal of said seventh switch means connected to said second terminal of said sixth switch means,

eighth switch means having first and second terminals, operable substantially in synchronization with said second switch means, with said first terminal of said eighth switch means connected to said second terminal of said seventh switch means and with said second terminal of said eighth switch means connected to said second terminal of said fourth capacitor,

a third capacitor leg comprising,

a fifth capacitor having first and second terminals with said first terminal of said fifth capacitor connected to said second terminal of said fifth switch means,

a sixth capacitor having first and second terminals with said first terminal of said sixth capacitor connected to said second terminal of said fifth capacitor and with said second terminal of said sixth capacitor connected to said second terminal of said seventh switch means,

whereby an ac voltage of peak value substantially equal to one eighth of the voltage of said source of dc power connected at said input is applied to said winding network connected at said output by action of said switch means.

14. The eighth bridge switching network of claim 13 wherein said first terminal of said output is connected to said second terminal of said third capacitor and said second terminal of said output is connected to said second terminal of said fifth capacitor.

15. An eighth bridge switching network comprising the quarter bridge switching network of claim 8 and further comprising,

a second switch leg comprising,

fifth switch means having first and second terminals, operable substantially in synchronization with said second switch means, with said first terminal of said fifth switch means connected to said second terminal of said first switch means,

sixth switch means having first and second terminals, operable substantially in synchronization with said first switch means, with said first terminal of said sixth switch means connected to said second terminal of said fifth switch means and with said second terminal of said sixth switch means connected to said second terminal of said third capacitor,

seventh switch means having first and second terminals, operable substantially in synchronization with said second switch means, with said first terminal of said seventh switch means connected to said second terminal of said sixth switch means,

eighth switch means having first and second terminals, operable substantially in synchronization with said first switch means, with said first terminal of said eighth switch means connected to said second terminal of said seventh switch means and with said second terminal of said eighth switch means connected to said second terminal of said fourth capacitor,

a third capacitor leg comprising,

16. The eighth bridge switching network of claim 15 wherein said first terminal of said output is connected to said second terminal of said third capacitor and said second terminal of said output is connected to said second terminal of said fifth capacitor.

17. The eighth bridge switching network of claim 15 wherein said first terminal of said output is connected to said second terminal of said first capacitor and said second terminal of said output is connected to said second terminal of said fifth capacitor.