KR0176883B1 - Complex number multiplier - Google Patents

Abstract

The complex multiplier of the present invention includes first to fourth registers to which multipliers (X _R , X _I ) and multiplicand (Y _R , Y _I ) are input, and multipliers that multiply the multipliers and multiplicands by real and real numbers, First to fourth code detectors for detecting the sign of data multiplied by each multiplier, and fifth to fourth code detectors for latching the multiplication result of each multiplier, First and second adders and subtracters for performing addition or subtraction in accordance with the mode control signal of the control unit, respectively, with the eighth register, the latch results of the fifth and sixth registers, and the seventh and eighth register latch results, A first ± 1 processing unit connected to the first adder-subtractor and receiving the detection results of the first and second code detectors and performing +1 if the addition is performed and -1 if the addition is subtracted according to the mode control signal of the controller; Connected to the second adder and subtracter, and outputs detection results of the third and fourth code detectors A second shift register for shifting the digit according to the ± 1 processed digits, and an output of each shifter are input to the first and second shifters. And a first and a second output selection unit for selecting and outputting a signal processed by ± 1 according to the control signal of the control unit and a signal not output by the selection unit. In the conventional arithmetic operation, an error occurring in the finite word length is prevented There is an effect that precise calculation can be performed.

Description

Complex multiplier

FIG. 1 is a circuit diagram of a complex multiplier according to a conventional technique; FIG.

FIG. 2 is an input / output timing diagram of FIG.

FIG. 3 is a detailed diagram of the multiplier of FIG. 1;

FIG. 4 is a circuit diagram of a complex multiplier according to the present invention. FIG.

FIG. 5 is a detailed circuit diagram of a fourth-degree sign detecting unit. FIG.

FIG. 6 is a detailed circuit diagram of the processing unit of the fourth phase ± 1; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

31 to 34, 39 to 42: Registers 35 to 38:

43, 44: adder / subtracter 45, 46: ± 1 processor

47, 48: SHIFTER 49, 50:

51 to 54: Sign detecting section 55:

Field of the Invention [0002] The present invention relates to a multiplier, and more particularly to a complex multiplier for processing errors occurring in arithmetic operations.

The first turn of that illustrates a complex number multiplier according to a prior art, data (X _R, X _I, Y _R, Y _I) is input, a latch (latch) registers (14) and, the respective registers that Multipliers 5 to 8 for multiplying X _R and Y _R , X _R and Y _I , X _I and Y _R , X _I and Y _I in the output, and registers 9 to 9 for latching the respective multiplication results (13, 14) for performing addition or subtraction on the basis of the control signal of the control section (20) by taking the latch results of the registers (9, 10) and the latch results of the registers (11, 12) (15,16) connected to the adder / subtracter (13,14) for shifting the digits according to the calculation result according to the control signal of the controller (20), and a shifter (15,16) And output selection units 17 and 18 for outputting the final output in accordance with the control signal of the control unit 20. [

The multipliers 5 to 8 selectively output the outputs of the multiplier 21, the comparator 22, the multiplier 21 and the comparator 22 as shown in FIG. 3 The comparator 22 approximates (-1) x (-1) to compensate for the disadvantage of the finite-world length.

In other words, When the two inputs of Since it can not be multiplied and it can not be expressed because it exceeds 1 bit in the finite word length (S 'is more than 1 bit)

This is expressed as a decimal number, for example, ( ₁₀ , 000) ₁₀ (0,999,999) ₁₀ .

The operation of the complex multiplier will now be described with reference to FIG.

The data input is a complex number data and real (X _R) and imaginary (X _I), and the real number (Y _R) and imaginary (Y _I), where X _R, X _I, Y _R, Y _I is a 2 (N = 4, 5, 6, ...) bits.

The multiplier 5 multiplies X _R and Y _R and the multiplier 6 multiplies X (X) and Y _R (X) as described above, and outputs the input data to the registers 1 to 4 at the clock edge of FIG. the _R and Y _I, a multiplier (7) causes the X _I and Y _R, multiplier 8, respectively and stores the result then multiplied by the X _I and Y _I for each register (9-12).

The result of the multiplication of X _R and Y _R and X _R and Y _{I in} the multiplier is input to the adder-subtracter 13 through the registers 9 and 10 and is added or subtracted in accordance with the mode control signal R of the controller 20 And the result of the multiplication of X _I and Y _R and X _I and Y _I is input to the adder-subtracter 14 through the registers 11 and 12 and inputted to the mode control signal I of the controller 20 So that addition or subtraction is performed.

Here, the mode control signals R and I are different control signals, and when the overflow occurs during the acceleration / deceleration, the control unit 20 transmits an 'H' signal to ignore the result of the overflow .

The shifters 15 and 16 perform digit shift on the result of the adder / subtracter 13 and 14 according to a control signal of the controller 20, store the final result in the register, (H) * PI (H) * PR (L) * PI (H) by using output selection units 17 and 18 to reduce the data output pin to 32 (L), PR (H) * PI (L), and PR (L) * PI (H).

However, in the conventional complex multiplier, a finite word length is approximated to a similar value in order to compensate for the disadvantage. However, this method has a problem that a precise value can not be obtained.

Therefore, an object of the present invention is to provide a complex multiplier capable of correct calculation even when a finite word length is exceeded.

In order to achieve the above object, a complex multiplier according to the present invention comprises first to fourth registers receiving multipliers (X _R , X _I ) and multiplicands (Y _R , Y _I ), and multipliers First to fourth multipliers for multiplying real and imaginary numbers, imaginary and imaginary numbers, first to fourth code detectors for detecting signs of data to be multiplied by the respective multipliers, and multipliers for multiplying the multiplication results of the multipliers First to eighth registers for latching and latching results of the fifth and sixth registers, and seventh and eighth register latch results, respectively, and performing addition or subtraction in accordance with a mode control signal of the control unit, And a second adder / subtracter, connected to the first adder / subtracter, for inputting the detection results of the first and second code detectors and performing +1 if the addition is performed and -1 if the subtraction is performed according to the mode control signal of the controller 1 & circ & 1 processing unit, and a second adder / subtracter connected to the third adder and the fourth adder, A second ± 1 processor for performing the same operation as that of the first adder with the detection result of the detector being input; first and second shifters for performing digit shift according to the ± 1 processed values; And a first and a second output selection unit for selecting and outputting the signal processed by ± 1 according to the control signal of the control unit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention.

A complex multiplier of the present invention, in the conventional complex multiplier code detector and the ± 1 processing section that further connected, FIG. 4 a register, the data X _R, X _I, Y _R, Y _I input, respectively, as shown in Multipliers 35 to 38 for multiplying X _R and Y _R , X _R and Y _I , X _I and Y _R , and X _I and Y _I in the outputs of the registers, A code detector 51-54 for detecting a sign of data multiplied by a multiplier and sending the result to the ± 1 processors 44 and 45, registers 39-42 for latching the results of multiplication, Adder / subtractors 43 and 44 for performing addition or subtraction in accordance with the mode control signal of the control unit 55 with the latch results of 39 and 40 and the latch results of the registers 41 and 43 as inputs, 44, and receives the detection results of the code detection units 51, 52 as input, and outputs the mode control signal of the control unit 55 as 1 processing unit 45 for performing +1 operations for addition and subtraction of -1 for smoothing, and ± 1 processing unit 45 for performing the same operation as the ± 1 processing unit 45 by taking the detection results of the sign detecting units 53 and 54 as input, 1 processing unit 46 and shifters 47 and 48 for shifting the digits according to the respective ± 1 processed results and the outputs of the shifters 47 and 48 are inputted and the control of the control unit 55 And output selection units 49 and 50 for final output according to the signals.

As shown in FIG. 5, the sign detecting unit includes a first NOR gate for receiving (n / 2) lower bits and a second NOR gate for receiving the remaining upper bits including the inverted 1 bit, (58) configured to receive an output of the multiplier and a multiplier processor, and a multiplier (58) configured to buffer the output of the multiplier 6, the ± 1 processing unit includes a gyre gate 61 to which the outputs (DET1, DET2) of the code detection unit are inputted, and a buffer 59 for inputting the output of the gygate as input A register 62 for selecting a processing result of ± 1 if an overflow does not occur, a +/- selector 63 for selecting + or - by decoding the mode control signal of the controller, , - And a multiplexer 65 for selecting and outputting the original data and ± 1 processed data according to the output result of the register 62, And the overall operation is as follows.

First, data input is two vectors (X, T) of a real value (X _R, Y _R) and an imaginary value and (X _I, Y _I), the X _R, X _I, Y _R, Y _I is the number of bits 2 " complementary sign having 2n (n = 4, 5, 6, ...) bits and the data is latched in each register 31 to 34 at the edge of the clock signal, The multiplier 35 multiplies X _R and Y _R , the multiplier 36 multiplies X _R and Y _I , the multiplier 37 multiplies X _I and Y _R , the multiplier 38 multiplies X _I and Y _I and stores the result in the registers 39 to 42, respectively, at the next clock edge.

The values stored in the registers 39 and 40 are added or subtracted by the adder / subtracter 43 in accordance with the mode control signal of the controller 55. The values stored in the registers 41 and 42 are also input to the controller The adder / subtracter 44 performs addition or subtraction in accordance with the mode control signal of the adder / subtracter 55.

At this time, an overflow signal generated in the addition or subtraction is sent to the ± 1 processing units 45 and 46 and the control unit 55, and the control unit 55 controls the overflow value to be ignored.

The result of the adder-subtractor 43 is passed to the ± 1 processor 45 and the result of the adder-subtractor 44 is passed to the ± 1 processor 46 to process ± 1.

(-1) when the data to be multiplied by the multiplier 35 is -1 x -1 (-1: when the input data is a negative value, hereinafter referred to as -1) 1 processing unit 45 and transmits the detection signal of the sign detecting unit 52 to the ± 1 processing unit 45 in the same manner.

For example, if the input data bit is 10 bits, the code detection unit outputs a sign detection signal as H (H) if a [9: 0] = 1000000000 and b [9: 0] = 1000000000. Otherwise, L) signal.

If the output of the sign detecting unit is a high signal indicating (-1) x (-1), the control unit 55 of the control unit 55 decodes the mode control signal to +1, And sends it to the shifter 47. If the detection signal is low, it is not necessary to perform ± 1, and the result of the adder-subtractor 43 is sent to the shifter 47 as it is.

More specifically, if the sign detection signal is high, the high select signal is input to the data terminal of the register and is sent to the multiplexer so that the overflow does not occur. / -Selector decodes the mode control signal of the control unit to add or subtract, and generates the Mo [3: 0] signal so that the sign detection signal is + 1 or + in the + 1 processor.

For example, when the current mode control signal indicates (A-B), -1 is performed if DET2 (B) is high, and +1 when DET1 (A) is high.

Then, the ± 1 processor controlled in this way is operated according to the Mo [3: 0] signal and then inputted to the I1 terminal of the multiplexer, and the input signal not performing the operation of ± 1 is input to the Io terminal, If the result of the detection section is high, select the I1 terminal value that is ± 1, and if low, select the Io terminal value that is not ± 1 and output it.

The results of the two ± 1 processing units 45 and 46 are shifted to the left or the right according to the shift control signal of the control unit 55 in the shifters 47 and 48 Both of which are sent to the output selection units 49 and 50.

In the output selection unit (49,50) to reduce the number of data output pins in half, the P _R (H) P, and _I (H) according to the selection signal (Osel) of the controller (55), P _R (L ) And P _I (L), P _R (H) and P _R (L), and P _I (H) and P _I (L)

As described above, according to the present invention, it is possible to precisely calculate arithmetic operations by preventing errors occurring in finite word lengths.

Claims (3)

A multiplier (X _R, X _I) and the multiplicand for the first through the fourth register and the multiplier and multiplicand error of the (Y _R, Y _I) as an input and the real number, real and imaginary, for multiplication for the imaginary part and the imaginary First to fourth multipliers, first to fourth code detectors for detecting the sign of data multiplied by each of the multipliers, fifth to eighth registers for latching the multiplication result of each multiplier, First and second adder / subtracters for adding or subtracting a result of the latch of the sixth register and a result of the seventh and eighth latches, respectively, in accordance with the mode control signal of the controller; A first ± 1 processor for inputting detection results of the first and second code detectors and performing +1 for addition and -1 for subtraction in accordance with the mode control signal of the controller, And outputs the detection results of the third and fourth code detection sections as inputs and outputs the same as the first adder A first and a second shifters for shifting the digits in accordance with the ± 1 processed results of the calculations, and a second shifter for shifting the outputs of the shifters according to control signals of the control unit. And a first and a second output selector for selecting and outputting the processed signal and the non-processed signal, respectively. The apparatus of claim 1, wherein the first to fourth code detection units include a first NOR gate having (n / 2) lower bits as inputs, a second NOR gate having an inverted upper bit as an input, A multiplier processing unit; A multiplier processor configured to be the same as the multiplier processor; An AND gate for receiving an output of the multiplier and an output of the multiplier processor; and a buffer for buffering and outputting the output of the AND gate. 2. The apparatus of claim 1, wherein the first and second 占 processes comprise an orgate receiving an output of the sign detecting unit and an output of the orgate as an input, A +/- selector for selecting + or - to decode the mode control signal of the controller, a +/- 1 processor for processing +/- 1 on data actually input according to the result of the + and - selection, And a multiplexer for selecting and outputting the input original data and ± 1 processed data according to an output result of the register.