JPH0540605A - Floating point multiplier - Google Patents

Abstract

PURPOSE:To attain the multiplication of the fixed points and also the non- normalized floating points without deteriorating the multiplying speed of the normalized floating points just by adding a small quantity of hardware to a constitution where a normalized floating point multiplier is used as a basic device. CONSTITUTION:The fixed points or the mantissas (of the non-normalized floating points) which are held by the registers 1 and 2 are shifted to the left by the left shifters 5 and 6 by zero numbers P1 and P2 continuous to the highest places detected by the priority encoders 3 and 4 and then multiplied by e multiplier circuit 7 which multiplies the mantissas of the normalized floating points. Both numbers P1 and P2 are added together by an adder 8, and the shift extent of a right shifter 9 is obtained. Then the shifter 9 shifts the multiplication result of the circuit 7 to the right by the number shown by the addition result of the adder 8. Thus, the multiplication results are obtained for the fixed points (or the mantissas of non-normalized floating points) held by the registers 1 end 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point multiplication apparatus suitable for multiplication of fixed-point numbers as well as multiplication of normalized floating-point numbers, and further multiplication of non-normalized floating-point numbers.

[0002]

2. Description of the Related Art Conventionally, in a multiplication device of a computer that handles fixed-point numbers in addition to normalized floating-point numbers, a dedicated multiplication device for realizing multiplication of normalized floating-point numbers and multiplication of fixed-point numbers are realized. It was common to have a dedicated multiplier separately.

Further, in addition to the above-mentioned normalized floating point number and fixed point number, when a denormalized floating point number is also handled, a dedicated multiplication device for realizing multiplication of the denormalized floating point number is further provided. I was prepared.

On the other hand, in order to reduce the amount of hardware, a multiplication device for fixed-point numbers, that is, a complex structure capable of performing multiplication on the assumption that there are consecutive zeros in the upper part of the multiplicand and the divisor. Based on (sharing) the multiplication device of (1), a method of realizing the multiplication of a fixed-point number, the multiplication of a normalized floating-point number, and the multiplication of a non-normalized floating-point number was also known.

[0005]

As described above, conventionally, in order to realize the multiplication of a fixed-point number (further, a denormalized floating-point number) in addition to the multiplication of a normalized floating-point number, a normalized floating-point number is used. It has been common to separately provide a multiplication device dedicated to multiplication of a decimal point number and a multiplication device dedicated to multiplication of a fixed point number (and further a multiplication device dedicated to denormalized floating point numbers). However, such a configuration has a drawback that the scale of the device becomes enormous. Further, in order to suppress the scale of the apparatus having such a configuration, a multiplication device having a lower function may be combined to realize the calculation, but there is a problem that the calculation speed is lowered.

On the other hand, in the method of suppressing the enormous scale of the apparatus by realizing the multiplication of the normalized floating point number (further, the denormalized floating point number) based on the fixed point multiplication device. However, since the multiplication is performed on the assumption that there are consecutive zeros in the multiplicand and the higher order of the multiplier, there is a problem that the speed of floating-point arithmetic is reduced.

The present invention has been made in view of the above circumstances, and an object thereof is to increase the normalization floating point multiplication speed by adding a small amount of hardware to the structure based on the normalization floating point number multiplication device. It is an object of the present invention to provide a floating-point multiplication device that can perform multiplication of fixed-point numbers and further denormalization floating-point numbers without degrading.

[0008]

SUMMARY OF THE INVENTION The present invention provides a multiplication circuit for multiplying the mantissa part of a normalized floating point number, and a fixed point number (or denormalized floating point number) input for multiplication. Zero detection circuit that detects the number of consecutive zeros on the most significant side of (the mantissa part of), and the number of zeros detected by this zero detection circuit as the input fixed-point number (or the mantissa of the denormalized floating-point number). Part) to the left shift circuit, and the fixed-point number (or mantissa part of the denormalized floating-point number) of the multiplicand detected by the zero detection circuit, and the fixed-point number (or The result of addition of the adder for adding the number of zeros of the mantissa part of the denormalized floating point number) and the multiplication circuit for the above multiplicand and multiplier after left shift by the above left shift circuit Indicates It is characterized in that a right shift circuit for right shifting.

[0009]

In the above structure, in the case of multiplication of a fixed-point number (or the mantissa part of a denormalized floating-point number), the operand data (multiplicand and multiplier) of the consecutive zeros is the highest. The number is shifted to the left by the left shift circuit and input to the multiplication circuit for multiplication of the mantissa part of the normalized floating point number. Therefore, the fixed point number (or the mantissa part of the denormalized floating point number) using the multiplication circuit is used. ) Multiplication can be performed without reducing the speed.

The multiplication result of this multiplication circuit is right-shifted by the right shift circuit by the number indicated by the addition result of the adder, and corrected to the multiplication result of the correct fixed-point number (or the mantissa part of the denormalized floating-point number). To be done.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the essential structure of a floating point multiplication device according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 holds a mantissa part of a normalized floating point number which is a multiplicand of multiplication, a mantissa part of a denormalized floating point number which is a multiplicand of multiplication, or a fixed point number which is a multiplicand of multiplication. Register (input register), 2 is a mantissa part of a normalized floating-point number that is a multiplier for multiplication, a mantissa part of a denormalized floating-point number that is a multiplier for multiplication,
Alternatively, it is a register (input register) for holding a fixed-point number that is a multiplier of multiplication.

Reference numeral 3 denotes a zero detection circuit for inputting the data held in the register 1 and outputting the number (digit number) P1 of "0" (zero) which is continuous on the most significant side of the data.
For example, the priority encoder (4) inputs the data held in the register (2), and outputs the number (digit number) P2 of consecutive "0" s on the most significant side of the data (priority encoder (zero detection circuit)). ).

Reference numeral 5 is a left shifter for shifting the data held in the register 1 to the left by the number P1 of zeros detected by the priority encoder 3, and 6 is detected by the priority encoder 4 for the data held in the register 2. It is a left shifter that shifts left by the number P2 of zeros.

Reference numeral 7 is a multiplication circuit, and its multiplicand side input A
Is connected to the output of the left shifter 5, and the multiplier side input B is connected to the output of the left shifter 6. This multiplication circuit 7
Is a well-known circuit for executing the multiplication of the mantissa part of the normalized floating point number, and conventionally, the output of the register 1 is connected to the multiplicand side input A and the multiplier 2 side input B is connected to the register 2 The output of is connected and used.

Reference numeral 8 denotes an adder for adding the numbers P1 and P2 of zeros detected by the priority encoders 3 and 4, and 9 denotes the multiplication result (output) of the multiplication circuit 7 by the number indicated by the addition result of the adder 8. A right shifter that shifts to the right.

Next, the operation of the configuration of FIG. 1 will be described. First, the configuration of FIG. 1 is obtained by adding a small amount of hardware to a well-known IEEE floating-point format normalized data multiplication device. That is, in the configuration of FIG.
And the multiplication circuit 7 is a component of the device for multiplying the normalized data in the IEEE floating point format, and by adding the priority encoders 3 and 4, the left shifters 5 and 6, the adder 8 and the right shifter 9, As described above, in addition to the multiplication of the mantissa part of the normalized floating point number, the multiplication of the mantissa part of the denormalized floating point number and the multiplication of the fixed point number are possible.

The register 1 holds the mantissa part of the normalized floating point, which is the multiplicand in the case of multiplication of the normalized floating point number, and holds it in the case of multiplication of the denormalized floating point number. The denormalized floating-point number that is the multiplicand is input and held, and when the fixed-point number is multiplied, the fixed-point number that is the multiplicand is input and held.

Similarly, the register 2 holds the mantissa part of the normalized floating point, which is a multiplier when multiplying the normalized floating point number, and holds it when multiplying the denormalized floating point number. The denormalized floating-point number that is a multiplier is input and held, and the fixed-point number that is a multiplier is input and held if the fixed-point number is multiplied.

The priority encoders 3 and 4 detect the binary digit numbers P1 and P2 of "0" which are consecutive to the most significant (MSB) of the output data of the registers 1 and 2, and the same P1 and P2 are detected. Is output. Where registers 1 and 2
If the stored data (multiplicand, multiplier) of is the mantissa part of the normalized floating point number, the MSB is "1", so P1,
The values of P2 are all "0".

The left shifters 5 and 6 shift the output data of the registers 1 and 2 to the left by the number of binary digits (bit number) indicated by P1 and P2 output from the priority encoders 3 and 4, and the MSB is set to "1". Output the data. Therefore, when the output data of the registers 1 and 2 is the normalized floating point number, the left shift is not performed, and the outputs of the left shifters 5 and 6 match the output data of the registers 1 and 2.

The output of the left shifter 5 is supplied to the multiplicand side input A of the multiplication circuit 7, and the output of the left shifter 6 is supplied to the multiplier side input B of the multiplication circuit 7. The multiplication circuit 7 inputs the outputs of the left shifters 5 and 6 supplied to the inputs A and B, that is, the output data of the registers 1 and 2 are the priority encoders 3 and 3, respectively.
4 is shifted left according to the outputs P1 and P2, and its MSB
Is input, and the data is multiplied as the mantissa part of the normalized floating point number.

The outputs P1 and P2 of the priority encoders 3 and 4 are supplied to the left input L and the right input R of the adder 8. The adder 8 adds P1 and P2 supplied to the left input L and the right input R, that is, the left shift number of the input data, and outputs the right shift number (P1 + P2) to the output data (multiplication result) from the multiplication circuit 7. calculate.

The right shifter 9 shifts the output data (multiplication result) of the multiplication circuit 7 to the right by the number of binary digits indicated by the addition result (P1 + P2) of the adder 8, and the mantissa part of the normalized floating point number, Outputs the mantissa part of a denormalized floating point number or the multiplication result of a fixed point number.

By the above operation, it is possible to perform the multiplication of the normalized floating point number, the denormalization floating point number and the fixed point number. More detailed reasons why such multiplication is possible will be described for (1) multiplication of normalized floating-point numbers and (2) multiplication of denormalized floating-point numbers or multiplication of fixed-point numbers. ..

(1) Case of Multiplication of Normalized Floating Point Number First, when the mantissa part of the normalized floating point number is input and held in the registers 1 and 2, its MSB is "1".
The values of the outputs P1 and P2 of the priority encoders 3 and 4 are both "0", and therefore the output of the adder 8 is also "0". In this case, the left shifters 5 and 6 and the right shifter 9 do not perform the shift operation, and the normal mantissa part of the normalized floating-point number is multiplied.

(2) In the case of denormalized floating-point number multiplication or fixed-point number multiplication When the mantissa part or fixed-point number of a denormalized floating-point number is input and held in registers 1 and 2, priority is given. The encoders 3 and 4 output the numbers P1 and P2 of "0" which are continuous on the MSB side. The output data of the registers 1 and 2, that is, the mantissa part of the input denormalized floating point number or the fixed point number is left-shifted by the left shifters 5 and 6 according to the outputs P1 and P2 of the priority encoders 3 and 4. ..

Here, assuming that the mantissa part or fixed-point number of the denormalized floating point number input is N1 and N2, the value after shifting by the left shifters 5 and 6 (left shifter 5 and left shifter 5).
6), the outputs of the priority encoders 3 and 4 are P1 and P2, respectively, and are thus N1 × 2 ^P1 N2 × 2 ^P2 .

This value (the output N1 × of the left shifters 5 and 6)
2 ^P1 , N2 × 2 ^P2 ) is input to the multiplicand side input A and the multiplier side input B of the multiplication circuit 7, the output of the multiplication circuit 7 is N1 × N2 × 2 ^{P1 + P2} Is obtained.

Since the adder 8 calculates P1 + P2, if the output of the multiplication circuit 7 is right-shifted by the value P1 + P2, N1 × N2 is obtained as a result. By the above procedure, the multiplication of the mantissa part of the normalized floating point number, the multiplication of the mantissa part of the denormalized floating point number, and the multiplication of the fixed point number can be realized.

In the above embodiment, the description has been made assuming that a small amount of hardware is added to the device for multiplying the normalized data in the IEEE floating point format, but the present invention is not limited to multiplication of the normalized data in other floating point format. The same applies to the device.

[0032]

As described in detail above, according to the present invention,
Zero detection circuit (first and second zero detection circuits) that detects the number of zeros that are consecutive on the most significant side of the fixed-point number (or the mantissa part of the denormalized floating-point number) input as the multiplicand or multiplier
Detected, and the input fixed-point number (or the mantissa part of the input denormalized floating-point number) is left-shifted by the left shift circuit (first and second left shift circuits) by that number, and the mantissa of the normalized floating-point number is detected. By supplying to the multiplication circuit for partial multiplication,
Performing multiplication of fixed-point numbers (or mantissas of denormalized floating-point numbers) as if they were multiplication circuits for normalized floating-point numbers, as if they were multiplications of mantissas of normalized floating-point numbers. In addition, the output of the multiplication circuit is shifted to the right by the right shift circuit by the sum of the left shift amounts on the multiplicand side and the multiplier side calculated by the adder. It is possible to obtain the correct multiplication result for the mantissa part of the decimal point number.

That is, according to the present invention, a small amount of hardware such as a zero detection circuit, a left shift circuit, a right shift circuit and an adder is added to the structure based on the normalized floating point number multiplication device. It is possible to carry out multiplication of fixed-point numbers and further multiplication of non-normalized floating-point numbers without lowering the normalization floating-point multiplication speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a floating point multiplication device according to an embodiment of the present invention.

[Explanation of symbols]

1, 2 ... Register, 3, 4 ... Priority encoder (zero detection circuit), 5, 6 ... Left shifter (left shift circuit), 7 ... Multiplication circuit, 8 ... Adder, 9 ... Right shifter (right shift circuit).

Claims (2)

[Claims] 1. A floating-point multiplication device having a multiplication circuit for performing multiplication of a mantissa part of a normalized floating-point number, wherein the number of zeros consecutive on the most significant side of a fixed-point number which is a multiplicand is A first zero detection circuit for detecting, a second zero detection circuit for detecting the number of consecutive zeros on the most significant side of a fixed-point number that is a multiplier, and a first zero detection circuit for detecting the number. And a first left shift circuit for left-shifting the multiplicand by the number of zeros and supplying it to the multiplication circuit, and a left-shift for the multiplier by the number of zeros detected by the second zero detection circuit. Second supply to the multiplication circuit
Left shift circuit, an adder for adding the number of zeros detected by the first and second zero detection circuits, and the multiplicand and multiplier after left shift by the first and second left shift circuits. A right shift circuit for right-shifting the multiplication result of the target multiplication circuit by the number indicated by the addition result of the adder; and, in addition to the multiplication of the normalized floating point number, the multiplication of the fixed point number is also possible. A floating-point multiplication device characterized in that 2. A floating-point multiplication apparatus having a multiplication circuit for multiplying a mantissa part of a normalized floating-point number, wherein a mantissa part of a denormalized floating-point number to be a multiplicand, or a fixed-point number maximum The first zero detection circuit that detects the number of consecutive zeros on the upper side, and the mantissa part of the denormalized floating-point number that is a multiplier, or the number of consecutive zeros on the most significant side of the fixed-point number. A second zero detection circuit for detecting the above, a first left shift circuit for left-shifting the multiplicand by the number of zeros detected by the first zero detection circuit, and supplying the left-shifted multiplicand to the multiplication circuit; The second multiplier is left-shifted by the number of zeros detected by the zero detection circuit and is supplied to the multiplication circuit.
Left shift circuit, an adder for adding the number of zeros detected by the first and second zero detection circuits, and the multiplicand and multiplier after left shift by the first and second left shift circuits. A right shift circuit for right-shifting the multiplication result of the target multiplication circuit by the number indicated by the addition result of the adder; and, in addition to the multiplication of the normalized floating point number, the multiplication of the denormalized floating point number And a floating point multiplication device characterized by being capable of multiplying a fixed point number.