JPS62165222A - Power factor regulator - Google Patents

Abstract

PURPOSE:To regulate a power factor stepwise to improve the accuracy by providing a control means which controls the gate of a semiconductor switch in accordance with the detection signal of a detecting circuit to adjust the magnitude and the phase of the current, which is supplied from a main circuit to a system, in such direction that the power factor is one. CONSTITUTION:The lead/delay polarity of the power factor and the magnitude of a reactive power are detected as a signal L/D and a signal vD respectively by a detecting circuit 9 in accordance with a system voltage (v) and a current (i) in the state of feeding from a power source to a load 2. The current supplied from the main circuit to the system is set in the delay/lead direction by the signal L/D, and the magnitude of the current is set by the signal vD. A DC current ID flowing to a DC reactor 5 is set as the output of a control circuit 14. The control factor and the phase of a PWM waveform are adjusted on a basis of these set values, and a power factor regulated output is obtained in the main circuit by the control of thyristors 4U-4Y, and power factor one is obtained when viewing the load 2 and a power factor regulating circuit, that is, reactive power zero is obtained. Thus, the power factor is regulated continuously with a simplified device and this device is superior in accuracy.

Description

[Detailed description of the invention] Human and industrial applications The present invention relates to a power factor adjustment 4FE system for a power system.

B0 Summary of the Invention The present invention has the following features in a power factor adjustment device that is connected in parallel to a load with a poor power factor, by adjusting the phase and magnitude of the current supplied to the grid from a main circuit having a semiconductor switch and a DC reactor. This allows for highly accurate power factor adjustment without making it complicated or expensive.

C1 Conventional technology In order to compensate for reactive power caused by loads with poor power factors such as induced lightning, motors, rectifiers, etc., as shown in Fig. 2, power is supplied from an AC power source 1 to a load 2. A power factor adjustment device 3 is connected in parallel. This power factor adjustment device i13 includes switches 31+32 such as Sai1 Nostar.
1 noa actor 33 capacitor 34 inserted in series,
The control circuit 35 detects the system power factor and controls opening and closing of the switches 31 and 32. Capacitor 34 which becomes a power factor adjustment element. Reactor 33 Toma each switch 31+32
FFI and FFI switches are provided in parallel, and the switches are opened and closed selectively or in combination depending on the production power factor.

D1 Problems to be Solved by the Invention In conventional power factor fA adjusting devices, the more highly accurate adjustment is attempted, the more circuit stages of power factor adjusting elements and switches are required, making the device configuration complicated and expensive. There was a problem. Further, even if the number of circuit stages is increased, the power factor check is performed in stages, which limits the ability to measure the power factor.

E.Means and Functions for Solving Problems for 1 The present invention has been made in view of the above-mentioned problems.The present invention has been made in view of the above problems. The current in the main circuit and the system that supplies power from the source to the load,
II! Pressure test l1ll: Power factor, reactive '■, which detects the lagging and leading polarity of the power factor and the magnitude of reactive power from the 1x sign.
a force detection circuit; and a control means for controlling the gate of the semiconductor switch based on the detection signal of the detection circuit, and adjusting the current supplied from the main circuit to the grid in a direction in which the magnitude of the current is 9 phases and the taka rate is 1; The power factor of the system is controlled to be 1 by continuously and steplessly adjusting the control rate and phase of the semiconductor switch of the circuit based on the advance and magnitude of the system power factor.

F. Example FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Bridge configuration GTO thyristor 4U, 4y,
4X.

The DC reactor 5 is connected to the DC side of the 4Y, and the AC side is connected in parallel to the load 2 to form the main circuit of the current type power factor adjustment device. These thyristors 4U to 4Y are PWs described later.
Gate control by M control is performed to send and receive power factor adjustment current, and a filter 6 is provided on the AC side to remove high frequency components associated with PWM control.

The control circuit is composed of 7-17. The superposition detection circuit 7 and the 'e pressure detection circuit 8 detect the system load currents l and * and the pressure 'V, respectively. The power factor, reactive force, and force detection circuit 9 calculates the polarity L/D of the delay and lead of the power factor due to the load 2 from the main voltage V of the detection current 19 of the detection circuit 7.8, and the magnitude of the reactive power VD.
Detect. The phase shifters 10 and 11 obtain waveforms of a voltage VL that is 90 degrees ahead of the pressure V and a heavy pressure VD that is delayed 9011 degrees for detection by the detection circuit 8. The changeover switch 12 selects the phase shifter 1 according to the power factor and reactive power detection circuit 90 power factor detection signal L/D.
0 and 11 (voltage waveforms VL and Vl) are switched to four outputs of the PWM control fundamental wave signal v1. Multiplier 13
T multiplies the fundamental wave signal v1 by the reactive power magnitude signal vD from the detection circuit 9 to adjust the amplitude of the signal v1.

The DC current dividing circuit 14 uses the DC reactor 50 current detection signal as a feedback signal, and obtains a current control signal for the DC reactor 5 in response to the reactive power signal VD from the detection circuit 9. Comparator 15C adds DC current control signal Pc to the output of multiplier 13,
By comparing the levels of this oW signal and the triangular wave signal of the triangular wave (carrier wave) generator 16, a PWM waveform can be obtained. The gate circuit 17 receives the PWM waveform from the comparator 15? 1 power amplification and distribution thyristor 4U, 4y.

Each gate signal of 4X and 4y is obtained as a PWM waveform.

With the current-type power factor adjustment device having such a configuration, the power factor can be reduced to 1 by controlling the thyristors 4U to 4Y of the main circuit in PWM according to the direction of delay and advance of the power factor and its magnitude.
Adjust to. To explain this operation in detail, when power is being supplied from source 1 to load 2, the system 'tdc it, voltage V,
Detection circuit 9 lags the power factor from airflow i.

The leading polarity is detected as a signal L/D, and the magnitude of reactive current and force is detected as VD, and the W flow supplied from the main circuit to the grid is set to the lagging direction and the leading direction by No. 18 L/D, and the signal is The magnitude of the current is set by VD. Also,
A current T DC current in the DC reactor 5 is set as the output of the control circuit 14. PWM based on these settings
The control rate and phase of the waveform are r:, Y, @;, and the power factor adjustment output is obtained in the main circuit by controlling the thyristors 4U to 4Y, and the power factor when looking at the power factor adjustment circuit is output from the power source 1 at a negative angle of 2°. 1 unit, that is, zero reactive power is obtained.

Therefore, control of delayed or advanced reactive power is performed steplessly and continuously according to the control rate of the main circuit, and the thyristor 4U
~ 4Y, responsive lO just by adjusting the control (wealth) rate
i precision.

Note that although a single-phase circuit is shown in the embodiment, it goes without saying that this can be applied to a three-phase circuit in a similar configuration.

Further, the design may be changed as appropriate, such as replacing the GTO thyristors 4U to 4Yt in the main circuit with other semiconductor switches. For example, a control means that obtains a sine wave output is used instead of PWM control for power factor adjustment.

G1 Effects of the Invention As described above, according to the present invention, a main circuit having a semiconductor switch and a DC reactor is connected in parallel to a load, and the power factor is adjusted by controlling the main circuit output current from the detection of the system power factor. As a result, compared to a conventional configuration using a switch and a power factor adjustment element, the device can be simplified, stepless and continuous power factor adjustment can be performed, and the accuracy is also improved.

[Brief explanation of drawings]

Fig. 1 is a T circuit diagram showing an embodiment of the present invention, and Fig. 2 is a diagram of a conventional power factor adjustment device. 4y...
GTO thyristor, 5... DC reactor, 7...
・'a Outflow/outflow circuit 8...IN pressure detection circuit, 9...
Power factor, reactive power detection circuit, 10, 11...phase shifter,
14... DC army 1st flow control circuit, 15... Comparator, 1
6... Triangular wave generator, I7... Gate circuit.

Claims (1)

[Claims] A main circuit for current-type power factor adjustment that has a semiconductor switch and a DC reactor and is connected in parallel to the load, and detects the lagging, leading polarity, and invalidity of the power factor from the current and voltage detection signals of the system that supplies power from the power supply to the load. A power factor/reactive power detection circuit for detecting the magnitude of electric power, and a gate control of the semiconductor switch based on the detection signal of this detection circuit, and a power factor of 1 for the magnitude and phase of the current supplied from the main circuit to the grid. What is claimed is: 1. A power factor adjustment device comprising: a control means for adjusting in a direction in which the power factor is adjusted;