JPS5914044A - Processor for input of data - Google Patents

Processor for input of data

Info

Publication number
JPS5914044A
JPS5914044A JP12285282A JP12285282A JPS5914044A JP S5914044 A JPS5914044 A JP S5914044A JP 12285282 A JP12285282 A JP 12285282A JP 12285282 A JP12285282 A JP 12285282A JP S5914044 A JPS5914044 A JP S5914044A
Authority
JP
Japan
Prior art keywords
input
data
cpu
converted
selector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12285282A
Other languages
Japanese (ja)
Inventor
Fushiaki Haruhara
春原 節昭
Shinichi Taya
田谷 信一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chino Corp
Original Assignee
Chino Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chino Works Ltd filed Critical Chino Works Ltd
Priority to JP12285282A priority Critical patent/JPS5914044A/en
Publication of JPS5914044A publication Critical patent/JPS5914044A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter

Abstract

PURPOSE:To attain a large amount of data processing in a fixed processing time, by executing simultaneously AD conversion in parallel with the data processing, and when there are many processing, increasing the processing speed. CONSTITUTION:A selector 5 closes the 1st channel switches S1 of respective input switches 21-2n by instruction from a central processing unit (CPU) 4 to enter input signals of the respective 1st channels. After completing said input, AD converters 31-3n are immediately actuated by an output from a start circuit 6 and respective input signals are simultaneously converted into digital signals. After completing the AD conversion, an end signal is transmitted to the CPU 4 through an address bus A.B and the converted data are collected by the CPU 4 through a data bus D.B. Subsequently, the selector 5 is actuated again, the 2nd channel switches S2 of respective input switches 21-2n are closed, so that the input signals of the 2nd channels are inputted and A/D converted simultaneously and the converted data are collected by the CPU 4.

Description

【発明の詳細な説明】 (1)発明の分野 この発明は、多数のアナログ信号データを取り込むデー
タ入力処理装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a data input processing device that takes in a large number of analog signal data.

(2)従来技術 多数の温度等のプロセス量を取り込み、デジタ理装置が
知られている。そして、入力信号に乗ってくる交流ノイ
ズの影響を軽減するため、積分形(1) A−D変換器等を用いてアナログ入力信号をディジタル
信号に変換している。
(2) Prior Art Digital processing equipment is known that incorporates a large number of process variables such as temperature. In order to reduce the influence of alternating current noise on the input signal, the analog input signal is converted into a digital signal using an integral type (1) AD converter or the like.

しかしながら、特に積分形のA−D変換器は。However, especially integral type A/D converters.

積分時間を多く必要とするため、同時に多数のデータを
高速にディジタル変換することは困難であった0 (3)発明の目的 この発明の目的は、高速に多数のデータを取り込むこと
ができるデータ入力処理装置を提供することである。
Since a large amount of integration time is required, it is difficult to simultaneously convert a large amount of data into digital data at high speed.0 (3) Purpose of the Invention The object of the present invention is to provide a data input system that can input a large amount of data at high speed. The purpose of the present invention is to provide a processing device.

(4)発明の実施例 第1図は、この発明の一実施例を示す構成説明図である
(4) Embodiment of the Invention FIG. 1 is an explanatory diagram showing an embodiment of the invention.

図において、11.・・・、1nは、それぞれnチャン
ネルの複数のアナログ入力信号が供給される入力入力切
換器、31.・・・、3nは各入力切換器21.・・・
In the figure, 11. . . , 1n are input input switchers each supplied with a plurality of n-channel analog input signals; 31. . . , 3n indicates each input switch 21. ...
.

2nにより取り出された入力信号を順次ディジタル信号
に変換する例えば積分形のA−D変換器。
For example, an integral type A-D converter that sequentially converts input signals extracted by 2n into digital signals.

4は、各A−D変換器31.・・・、3nの変換データ
をデータ・バスD−Bを通じて収集するとともにアドレ
ス・バスA−4+を通じて入力切換器21.・・・。
4 is each A-D converter 31. . . , 3n conversion data are collected through the data bus DB, and are also sent to the input switch 21 . . . , 3n through the address bus A-4+. ....

2nの制御を行うセレクタ5.A−D変換器31゜・・
・、3nのスタート制御を行うスタート回路6の制御を
行うマイクロコンビーータのような中央処理装置である
Selector 5.2n controls the selector 5.2n. A-D converter 31°...
. , 3n is a central processing unit such as a microconbeater that controls the start circuit 6 that performs start control.

動作は次の通りである。The operation is as follows.

中央処理装置4の命令によりセレクタ5は各入力切換器
21.・・・、2nの各第1チヤンネルのスイッチS1
を閉とし、各第1チヤンネルの入力信号が取り込まれる
。取り込みが終了すると直ちにスタート回路6によりA
−D変換器31.・・・、3rlが動作し。
In response to instructions from the central processing unit 4, the selector 5 selects each input switch 21. ..., 2n each first channel switch S1
is closed, and the input signal of each first channel is taken in. Immediately after the capture is completed, the start circuit 6
-D converter 31. ..., 3rl is working.

各入力信号は同時にディジタル信号に変換される。Each input signal is simultaneously converted to a digital signal.

中央処理装置4により変換ケータはデータ・バスD−B
を通じて収集される。
The data bus D-B is converted by the central processing unit 4.
collected through.

次に再びセレクタ5が作動し、各入力切換器21、・・
・、2nの第2チヤンネルのスイッチS2を閉とし、各
第2チヤンネルの入力信号が取り込まれ。
Next, the selector 5 operates again, and each input switch 21,...
, 2n's second channel switch S2 is closed, and the input signal of each second channel is taken in.

同時にA−D変換され、中央処理装置4に収集される。At the same time, the signals are A-D converted and collected in the central processing unit 4.

以下同様の動作がくり返されて、入力データは取り込ま
れ、必要な用途に使用される。
The same operation is repeated thereafter, and the input data is captured and used for necessary purposes.

(5)発明の要約 以上述べたように、この発明は、中央処理装置。(5) Summary of the invention As described above, the present invention relates to a central processing unit.

セレクタ、スタート回路により複数の入力信号を同時に
複数のA−D変換器でディジタル信号に変換し取り込む
ようにしたデータ入力処理装置である。
This is a data input processing device in which a plurality of input signals are simultaneously converted into digital signals by a plurality of A-D converters and taken in by a selector and a start circuit.

(6)発明の効果 A−D変換が同時に並行して行なわれるので。(6) Effect of invention Because A-D conversion is done in parallel at the same time.

処理点数が多い場合、処理速度が大幅に向上し。When the number of processing points is large, processing speed is significantly improved.

一定の処理時間で多量のデータ処理が可能となる。A large amount of data can be processed in a fixed processing time.

又、セレクタ、スタート回路は単一ですみ、それだけ装
置構成が簡素、安価のものとなり、信頼性も高い。
In addition, only a single selector and start circuit are required, which makes the device configuration simpler and cheaper, and has high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この発明の一実施例を示す構成説明図である
。 11〜1n・・・入力端子、21〜2n・・・入力切換
器。 31〜3n・・・A−D変換器、4・・・中央処理装置
、5・・・セレクタ、6・・・スタート回路特許出願人
 株式会社 千野製作所 (5)
FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention. 11-1n...input terminal, 21-2n...input switch. 31-3n...A-D converter, 4...Central processing unit, 5...Selector, 6...Start circuit Patent applicant Chino Seisakusho Co., Ltd. (5)

Claims (1)

【特許請求の範囲】[Claims] 1、 それぞれ複数の入力信号を切換選択する複数の入
力切換器と、各入力切換器により取り出された入力信号
を順次ディジタル信号に変換する複数のA−D変換器と
、各A−D変換器の出力を収集するとともに前記入力切
換器、A−D変換器の制御を行う中央処理装置とを備え
たことを特徴とするデータ入力処理装置。
1. A plurality of input switchers that each switch and select a plurality of input signals, a plurality of A-D converters that sequentially convert the input signals taken out by each input switch into digital signals, and each A-D converter. A data input processing device comprising a central processing unit that collects the output of the input switch and controls the input switch and the A-D converter.
JP12285282A 1982-07-16 1982-07-16 Processor for input of data Pending JPS5914044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12285282A JPS5914044A (en) 1982-07-16 1982-07-16 Processor for input of data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12285282A JPS5914044A (en) 1982-07-16 1982-07-16 Processor for input of data

Publications (1)

Publication Number Publication Date
JPS5914044A true JPS5914044A (en) 1984-01-24

Family

ID=14846231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12285282A Pending JPS5914044A (en) 1982-07-16 1982-07-16 Processor for input of data

Country Status (1)

Country Link
JP (1) JPS5914044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0327477A (en) * 1990-05-09 1991-02-05 Canon Inc Body information processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0327477A (en) * 1990-05-09 1991-02-05 Canon Inc Body information processing method

Similar Documents

Publication Publication Date Title
JPS5914044A (en) Processor for input of data
KR850007175A (en) PCM code decoder
JP2500755B2 (en) Redundant system switching method
JPS61161885A (en) Video signal sending circuit
JPS58188990A (en) Control system of key telephone system
KR200148662Y1 (en) High speed image processor
JP2858190B2 (en) Parallel processing system
KR970002072B1 (en) A/d convertor input device using time division type
JPH08182029A (en) Inter-system connection method
JPH11282466A (en) Signal processor and signal processing method
JPS5970247U (en) Time division selection processing device for multiple analog inputs
JPS6025932B2 (en) TDM/FDM conversion method
JPS59177641A (en) Input taking-in device
JPS5862927A (en) Analog input device
JPS6013591B2 (en) Multi-point scanning method
JPH09246928A (en) Multiplexer
JPH0832451A (en) Simultaneous sampling method for input data
JPS61245229A (en) Input device
JPH086617A (en) Controller
JPH0246981B2 (en) DEIJITARUSHINGOSHORISOCHI
JPS6143090A (en) Transmitting circuit of video signal
JPH0654319U (en) Matrix switcher with digital time division processing
JPS6369342A (en) Time division multiplexing circuit
JPH02121540A (en) Synchronous multiple converting device
JPH0769727B2 (en) Multi-point analog input processor