JPS61161885A - Video signal sending circuit - Google Patents

Video signal sending circuit

Info

Publication number
JPS61161885A
JPS61161885A JP311285A JP311285A JPS61161885A JP S61161885 A JPS61161885 A JP S61161885A JP 311285 A JP311285 A JP 311285A JP 311285 A JP311285 A JP 311285A JP S61161885 A JPS61161885 A JP S61161885A
Authority
JP
Japan
Prior art keywords
circuit
signal
selection
video
cameras
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP311285A
Other languages
Japanese (ja)
Inventor
Hideto Fujiwara
秀人 藤原
Fumihiko Isogai
磯貝 文彦
Takeshi Fukuhara
福原 毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP311285A priority Critical patent/JPS61161885A/en
Publication of JPS61161885A publication Critical patent/JPS61161885A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To use commonly an A/D converting circuit and to make the whole of the device low-priced and small by selecting plural analog video signals inputted from plural cameras and connecting the selected signal to one unit of video signal sending circuit. CONSTITUTION:A synchronizing signal of a compound video signal is separated from plural cameras 1 by a synchronizing separating circuit which is not shown in the figure, and plural analog video signals are supplied to a selecting circuit 6. By the indication from a control circuit 8, one of the above-mentioned plural analog video signals is selected, sent to an A/D converter 3 and converted to a digital signal. The selected digital signal is sent through a sending circuit 4 to a video bus 5. The selecting signal from the control circuit 8 is also sent through the sending circuit 4 to the video bus 5. Thus, plural cameras can be used by one video signal sending circuit, and the low-priced and small device can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ロボット等の視覚システムに用いられる画
像処理装置の映像信号処理、送出を行なう映像信号送出
回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal transmission circuit for processing and transmitting video signals of an image processing device used in a visual system of a robot or the like.

〔従来の技術〕[Conventional technology]

従来、この種の装置として第2図に示すものがあった0
図において、1は白黒の映像を入力するカメラ、2は同
期分離回路、3はA/D変換回路、4は送出回路、5は
ビデオバスである。
Conventionally, there was a device of this type as shown in Figure 2.
In the figure, 1 is a camera that inputs black and white video, 2 is a synchronization separation circuit, 3 is an A/D conversion circuit, 4 is a sending circuit, and 5 is a video bus.

次に動作について説明する。同期分離回路2ではカメラ
1から送られる白黒の複合映像信号が入力され、これよ
り同期信号及びクロック信号5YNCを分離して送出回
路4へ送るとともに、該同期分離後のアナログ映像信号
をA/D変換回路3へ送出する。A/D変換回路3では
上記アナログ映像信号をデジタル変換しデジタル映像信
号と。
Next, the operation will be explained. The synchronization separation circuit 2 receives the black and white composite video signal sent from the camera 1, separates the synchronization signal and clock signal 5YNC, sends it to the output circuit 4, and sends the analog video signal after the synchronization separation to the A/D. It is sent to the conversion circuit 3. The A/D conversion circuit 3 digitally converts the analog video signal into a digital video signal.

A/D変換のクロック信号を送出回路4へ送出する。送
出回路4はドライブ用ICにより構成され、A/D変換
回路3並びに同期分離回路2がらの入力信号を外部ビデ
オバス5に出力する。
A clock signal for A/D conversion is sent to the sending circuit 4. The sending circuit 4 is constituted by a drive IC, and outputs input signals from the A/D conversion circuit 3 and the synchronization separation circuit 2 to the external video bus 5.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の映像信号送出回路は以上のように構成されている
ので、入力部であるカメラを1個しか使えず、複数のカ
メラを使おうとするとカメラの台数骨だけ上記従来装置
を必要としていた。このため装置規模が太き(なり高価
になる等の問題点があった。
Since the conventional video signal sending circuit is configured as described above, only one camera, which is an input section, can be used, and if a plurality of cameras are to be used, the above-mentioned conventional device is required for each camera. For this reason, there were problems such as the equipment being large (and expensive).

この発明は上記のような問題点を解消するためになされ
たもので、1台の装置で複数のカメラを使用できるもの
を安価かつ小型に構成できる映像信号送出回路を得るこ
とを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a video signal sending circuit that can be constructed inexpensively and compactly so that a plurality of cameras can be used in one device.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る映像信号送出回路は、複数のカメラから
入力される複数のアナログ映像信号を選択する選択回路
と、該選択回路の選択手順を決める選択信号を出力する
制御回路とを設けたものである。
A video signal transmission circuit according to the present invention includes a selection circuit that selects a plurality of analog video signals input from a plurality of cameras, and a control circuit that outputs a selection signal that determines the selection procedure of the selection circuit. be.

〔作用〕 この発明においては、選択回路が制御回路からの制御信
号に応じて複数のカメラのアナログ映像信号の中から1
つのアナログ映像信号を選択するから、A/D変換回路
等を共通に使用できる。
[Operation] In the present invention, the selection circuit selects one of the analog video signals of the plurality of cameras according to the control signal from the control circuit.
Since two analog video signals are selected, A/D conversion circuits and the like can be used in common.

〔実施例〕〔Example〕

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例による映像信号送出回路を示
し、図において、1は入力部である複数のカメラ、6は
後述する制御回路8からの選択信号30.Sl、32.
・・・により複数のカメラ1からのアナログ映像信号を
切換選択する選択回路、3は上記選択回路6からのアナ
ログ映像信号出力をA/D変換するA/D変換回路、4
はA/D変換回路3からのデジタル映像信号を直列にビ
デオバス5に送出する送出回路、7は複数のカメラ1及
び後述する制御回路8に同期信号及びクロック信号5Y
NCを与える同期発生回路、8は上記選択回路6に選択
信号SO,Sl、S2.・・・を与えるとともに上記送
出回路4に上記同期発生回路7からの同期信号及びクロ
7り信号5YNCを送出する制御回路であり、この制御
回路8はそれを制御する上位のコントローラであるホス
トシステム(ホストI /F)へ接続されている。
FIG. 1 shows a video signal sending circuit according to an embodiment of the present invention. In the figure, reference numeral 1 indicates a plurality of cameras as input units, reference numeral 6 indicates selection signals 30. Sl, 32.
..., a selection circuit that switches and selects analog video signals from a plurality of cameras 1; 3, an A/D conversion circuit that A/D converts the analog video signal output from the selection circuit 6; 4;
7 is a sending circuit that serially sends the digital video signal from the A/D conversion circuit 3 to the video bus 5, and 7 is a sending circuit that sends a synchronization signal and a clock signal 5Y to the plurality of cameras 1 and a control circuit 8 to be described later.
A synchronization generating circuit 8 provides selection signals SO, Sl, S2 . ... and sends out the synchronization signal from the synchronization generating circuit 7 and the clock signal 5YNC to the sending circuit 4, and this control circuit 8 is a host system that is a higher-level controller that controls it. (Host I/F).

次に動作について説明する。A/D変換回路3と送出回
路4は従来のものと同じ動作をする。そして同期発生回
路7は入力部である複数のカメラ1を同期動作させるた
めの同期信号及びクロック信号5YNCを複数のカメラ
1に与えるとともに制御回路8へ上記同期信号及びクロ
ック信号5YNCを送る。そして上位のホストシステム
に接続されている制御回路8には複数の映像信号を直列
に送出する順序がホストシステムからの指示により所望
の組合せ手順で記憶されており、1画面毎にその切換選
択信号So、31.S2.・・・を選択回路6へ送る。
Next, the operation will be explained. The A/D conversion circuit 3 and the sending circuit 4 operate in the same way as conventional circuits. The synchronization generating circuit 7 provides a synchronization signal and a clock signal 5YNC to the plurality of cameras 1, which are input units, for synchronously operating the plurality of cameras 1, and also sends the synchronization signal and the clock signal 5YNC to the control circuit 8. The control circuit 8 connected to the upper host system stores the order in which the plurality of video signals are sent in series in a desired combination procedure according to instructions from the host system, and the switching selection signal is stored for each screen. So, 31. S2. ... is sent to the selection circuit 6.

ここで選択用の信号としては、カメラの台数をNとする
とjog2 (N)ビット必要である。ここで、接続さ
れている複数のカメラすべての映像信号を出力する必要
はなく、例えばそのうちの2台の映像信号を1画面ずつ
交互に出力したり、あるいは1台を常に選択するように
してもよい。
Here, as the selection signal, jog2 (N) bits are required, assuming that the number of cameras is N. Here, it is not necessary to output the video signals of all the connected cameras; for example, it is possible to output the video signals of two of them alternately, one screen at a time, or to always select one camera. good.

このような回路を備えた本実施例回路において、カメラ
1は同期発生回路7からの同期信号及びクロック信号5
YNCによってすべてのカメラから白黒の複合映像信号
が同期して出力される。
In the circuit of this embodiment including such a circuit, the camera 1 receives the synchronization signal and clock signal 5 from the synchronization generation circuit 7.
Black and white composite video signals are synchronously output from all cameras by YNC.

上記同期信号及びクロック信号5YNCは制御回路8に
も入力され、画像の切換信号のタイミング用として使用
される他、送出回路4を経て、ビデオバス5へ送出され
る。一方、複数のカメラ1からの複合映像信号はそれぞ
れ図示しない同期分離回路によって同期信号及びクロッ
ク信号が分離され、該分離後の複数のアナログ映像信号
の1つが前記制御回路8からの指示により選択回路6で
選択されてこれがA/D変換回路3へ送られ、該A/D
変換回路3でデジタル信号に変換され、該信号は送出回
路4を経てビデオバス5へ送出される。
The synchronization signal and clock signal 5YNC are also input to the control circuit 8, used for timing the image switching signal, and are also sent to the video bus 5 via the sending circuit 4. On the other hand, the composite video signals from the plurality of cameras 1 are each separated into a synchronization signal and a clock signal by a synchronization separation circuit (not shown), and one of the plurality of separated analog video signals is sent to a selection circuit according to an instruction from the control circuit 8. 6 is selected and sent to the A/D conversion circuit 3, where the A/D
The conversion circuit 3 converts the signal into a digital signal, and the signal is sent to the video bus 5 via the sending circuit 4.

さらに制御回路8からの選択信号SO,S1.S2、・
・・も送出回路4を経てビデオバス5へ送出される。
Furthermore, selection signals SO, S1 . S2,・
... are also sent to the video bus 5 via the sending circuit 4.

このように本実施例の構成によれば、複数のアナログ映
像信号を切換えてこれを順次デジタル変換するようにし
たので、1台の映像信号送出回路で複数のカメラを使用
でき、安価かつ小型の装置とすることができる。
As described above, according to the configuration of this embodiment, multiple analog video signals are switched and sequentially converted into digital signals, so multiple cameras can be used with one video signal transmission circuit, which is inexpensive and compact. It can be a device.

なお、上記実施例では送出信号の切換を1画面単位で行
なうものについて説明したが、1水平走査時間のN倍、
又は1画面単位のN倍で行なうものであってもよい。
In the above embodiment, the transmission signal is switched in units of one screen.
Alternatively, it may be performed N times in units of one screen.

また上記実施例では白黒用のものの場合について説明し
たが、選択回路とA/D変換回路との間にカラー分離回
路と選択回路とを設けることにより、カラー用の映像信
号送出回路とすることができる。
Furthermore, although the above embodiment describes the case of a monochrome video signal transmission circuit, by providing a color separation circuit and a selection circuit between the selection circuit and the A/D conversion circuit, it is possible to create a color video signal transmission circuit. can.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る映像信号送出回路によれ
ば、複数のカメラからのアナログ映像信号を選択するこ
とにより、1台の映像信号送出回路に複数のカメラを接
続できるように構成したので、装置が安価にでき、また
小型のものが得られる効果がある。
As described above, the video signal transmission circuit according to the present invention is configured so that a plurality of cameras can be connected to one video signal transmission circuit by selecting analog video signals from a plurality of cameras. This has the advantage that the device can be made inexpensive and compact.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による映像信号送出回路を
示すブロック図、第2図は従来の映像信号送出回路を示
すブロック図である。 図において、1は入力部のカメラ、2は同期分離回路、
3はA/D変換回路、4は送出回路、5はビデオバス、
6は選択回路、7は同期発生回路、8は制御回路である
。 なお図中、同一符号は同−又は相当部分を示す。
FIG. 1 is a block diagram showing a video signal sending circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional video signal sending circuit. In the figure, 1 is the camera of the input section, 2 is the synchronous separation circuit,
3 is an A/D conversion circuit, 4 is a sending circuit, 5 is a video bus,
6 is a selection circuit, 7 is a synchronization generation circuit, and 8 is a control circuit. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)複数のカメラからのアナログ映像信号を入力とし
この複数のアナログ映像信号のうちの1つを後述する選
択信号に応じて選択する選択回路と、上記複数のカメラ
に対して同期信号及びクロック信号を与える同期発生回
路と、上記選択回路からのアナログ映像出力信号をA/
D変換するA/D変換回路と、上記同期信号及びクロッ
ク信号を入力とし上記選択回路の選択手順を決める選択
信号と上記同期信号及びクロック信号を出力する制御回
路とを備え、上記A/D変換回路からのデジタル映像出
力信号、上記制御回路からの選択信号及び同期信号とク
ロック信号を外部ビデオバスに出力することを特徴とす
る映像信号送出回路。
(1) A selection circuit that receives analog video signals from a plurality of cameras and selects one of the plurality of analog video signals according to a selection signal described later, and a synchronization signal and clock for the plurality of cameras. The analog video output signal from the synchronization generation circuit that provides the signal and the selection circuit described above is
The A/D conversion circuit includes an A/D conversion circuit that performs D conversion, and a control circuit that receives the synchronization signal and the clock signal as input and outputs the selection signal that determines the selection procedure of the selection circuit and the synchronization signal and the clock signal. A video signal sending circuit characterized in that it outputs a digital video output signal from the circuit, a selection signal, a synchronization signal, and a clock signal from the control circuit to an external video bus.
JP311285A 1985-01-10 1985-01-10 Video signal sending circuit Pending JPS61161885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP311285A JPS61161885A (en) 1985-01-10 1985-01-10 Video signal sending circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP311285A JPS61161885A (en) 1985-01-10 1985-01-10 Video signal sending circuit

Publications (1)

Publication Number Publication Date
JPS61161885A true JPS61161885A (en) 1986-07-22

Family

ID=11548264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP311285A Pending JPS61161885A (en) 1985-01-10 1985-01-10 Video signal sending circuit

Country Status (1)

Country Link
JP (1) JPS61161885A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217381A (en) * 1986-03-19 1987-09-24 Toshiba Eng Co Ltd External form inspection device
JPS63110875A (en) * 1986-10-28 1988-05-16 Agency Of Ind Science & Technol Input system for plural camera information
JPH01115282A (en) * 1987-10-29 1989-05-08 Canon Inc Synchronizing signal processor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217381A (en) * 1986-03-19 1987-09-24 Toshiba Eng Co Ltd External form inspection device
JPH0546590B2 (en) * 1986-03-19 1993-07-14 Toshiba Engineering Co
JPS63110875A (en) * 1986-10-28 1988-05-16 Agency Of Ind Science & Technol Input system for plural camera information
JPH01115282A (en) * 1987-10-29 1989-05-08 Canon Inc Synchronizing signal processor

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