JPH11327701A - Microcomputer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable control of a regulator without a CPU running away even at the time of the regulator operation or stop and without making connection terminals a user can use fewer. SOLUTION: A regulator 1 lowers a voltage applied to a power source terminal and supplies it with an internal circuit, and a control signal switches operation or stop. A counter 2 stops when a reset signal to be inputted is inactive and starts counting operation when the signal is active by a signal from a clock terminal. A pulse width decision circuit 31 outputs an operation control signal as a result of this counter 2 deciding an active level width of a specific bit signal and a reset signal counted to the regulator 1 and controls operation or stop. The length of the active level width of the reset signal to be inputted to a reset signal input terminal controls switching of operation or stop of the regulator 1 which lowers the voltage applied to an external power source terminal and supplies it with the internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device having a constant voltage output circuit (referred to as a regulator as appropriate) for reducing a voltage applied to an external power supply terminal and supplying the reduced voltage to an internal circuit. The present invention relates to a microcomputer device that switches the operation or stop of a regulator depending on the length of an active level width of a reset signal input to a reset input terminal.

[0002]

2. Description of the Related Art In recent years, electronic devices using microcomputer devices have been developed to have more functions and to save power. In addition, due to miniaturization of electronic devices, malfunctions in other components and devices due to noise radiated by the electronic components have become a problem. Therefore, the microcomputer device is required to have a high-speed CPU process, low power consumption, and low noise for suppressing radiation noise during operation. In order to reduce the power consumption and reduce noise, a microcomputer device having a regulator mounted therein is known. This regulator makes the internal power supply voltage lower than the external power supply voltage. As a result, the operating voltage of the microcomputer device is reduced, the current consumption is reduced, and since the amplitude value of the internal signal is reduced, the radiation noise can be reduced.

On the other hand, for high-speed data processing in a CPU, the operating voltage cannot be reduced, and the voltage cannot be reduced by a regulator. In order to solve this conflicting contradiction, if low power consumption or low noise is prioritized by electronic equipment at present, the mounted regulator is operated and high-speed data processing by CPU is prioritized. Stops the operation of the mounted regulator.

Conventionally, as an example of setting the operation or stop of such a regulator, a configuration provided with a control register and a configuration provided with an external terminal for exclusive use disclosed in Japanese Patent Application Laid-Open No. 5-108193 are known. Have been.

The example shown in FIG. 4 is a configuration example in which a control register is provided, and a frequency divider circuit 41 generates a system clock signal obtained by dividing a clock signal input to a clock signal input terminal by an operation control signal. And supplies it to the CPU 42. The CPU 42 outputs a write control signal to the register 43. The write control signal from the register 43 is output to the frequency dividing circuit 41 and the regulator 44. The regulator 44 operates when priority is given to lower power consumption or lower noise. Conversely, when priority is given to high-speed data processing by the CPU 42, the operation of the regulator 44 is stopped.

In such a configuration in which the operation or the stop is switched by using such a control register, the CPU may run away. This is because the regulator output voltage is usually set to the lowest voltage at which the CPU and other peripheral circuits operate. That is, in order to reduce power consumption and noise, the internal power supply voltage is reduced as much as possible. For example, when the operation or stop of the regulator is switched by the CPU operation, the output voltage of the regulator becomes unstable in a transitional state in which the state changes from the stop state to the operation state.

[0007]

As described above, in the above-described conventional example, the output voltage may become unstable when switching the operation or stop of the regulator. Therefore, if the output voltage of the regulator is set to the minimum operating voltage of the CPU and peripheral circuits, the regulator voltage may fall below the minimum voltage. In this case, the CPU may run away. In order to avoid this runaway, it is necessary to set the regulator setting voltage to be slightly higher than the minimum operating voltage of the CPU and peripheral circuits, and to design with a margin.

In a configuration in which a dedicated terminal is provided to switch the operation or stop of the regulator, the problem of the transient voltage drop as described above can be avoided, but the number of connection terminals usable by the user is reduced. However, it becomes extremely difficult to use the microcomputer as a multi-functional microcomputer.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and switching between operation and stop of a constant voltage output circuit for reducing a voltage applied to an external power supply terminal and supplying the same to an internal circuit is performed by a reset input terminal. Can be controlled by the length of the active level width of the reset signal input to the
Low current consumption and low noise can be achieved, and C
It is an object of the present invention to provide a microcomputer device that eliminates the possibility of a PU runaway and controls the operation of a constant voltage output circuit without reducing the number of terminals that can be used by a user.

[0010]

In order to solve the above-mentioned problems, in a microcomputer device of the present invention, a voltage applied to a power supply terminal is stepped down and supplied to an internal circuit, and operation or stop is performed by a control signal. Constant voltage output means for switching, a counting means for stopping when an input reset signal is inactive, and starting a count operation with a clock signal from a clock terminal when active, and a predetermined bit signal counted by the counting means and resetting And a pulse width determining means for outputting an operation control signal as a result of determining the active level width of the signal to the constant voltage output means to control operation or stop.

In the present invention, the counting means is provided so as to secure a stabilization time of the oscillation circuit during the input of the reset signal.
The oscillation stabilization time elapsing due to the generation of the overflow signal is shared with an oscillation stabilization counter shown in a peripheral circuit including the central processing unit.

Further, the present invention is characterized in that the predetermined bit number signal counted by the counting means is at least two bits, and the noise of the input reset signal is removed and output to the pulse width determining means. It is characterized by further comprising means.

In the present invention, the pulse width judging means is set by a falling edge detecting circuit for outputting a latch initialization signal which detects a falling of a reset signal, a rising edge of the most significant bit from the counting means, and A latch circuit that is reset by a latch initialization signal from the falling edge detection circuit and outputs a timer OVF signal; and a timer OVF signal from the one latch circuit and an arbitrary bit other than the most significant bit from the counting means. The other latch circuit that outputs to the constant voltage output means an operation control signal that is set at the rising edge of the AND operation with the bit and that is reset by the latch initialization signal from the falling edge detection circuit; Timer O from latch circuit
An AND circuit for outputting a logical product signal of the VF signal and an arbitrary bit other than the most significant bit from the counting means to the other latch circuit.

Further, according to the present invention, the operation control signal as a result of the determination of the active level width of the reset signal activates the constant voltage output means, and the active level width of the reset signal is highest. It is characterized in that the value is smaller than the sum of the bit set time and an arbitrary bit set time other than the most significant bit set time.

According to the present invention, the operation control signal resulting from the determination of the active level width of the reset signal activates the constant voltage output means, and the active level width of the reset signal is the highest. The value is larger than the sum of the bit set time and any bit set time other than the highest bit.

In the microcomputer device of the present invention, the operation or stop of the constant voltage output circuit is switched by the active level width of the reset signal input to the reset signal input terminal.
The execution or the stop of the constant voltage output circuit can be switched without setting data in the operation control register for the constant voltage output circuit by executing the PU instruction.

At the switching timing, when the CPU or other peripheral circuits are not operating, that is, when the reset signal is being input, the output voltage of the constant voltage output circuit drops momentarily in the transitional state of switching. However, there is no possibility that the CPU will run away.

Further, the output voltage of the constant voltage output circuit is used by a CPU.
In addition, since the voltage can be set to the minimum voltage at which the peripheral circuits can operate, lower current consumption and lower noise can be achieved as compared with a conventional microcomputer device.

Further, it is not necessary to provide an operation control terminal for the constant voltage output circuit, and the external terminal can be effectively used as a terminal for setting other functions.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a microcomputer device of the present invention.

This microcomputer device has a clock input terminal T1 to which a clock signal from a clock generator or the like is input, a reset signal input terminal T2 to which a reset signal is input, and an external power supply terminal T3 to which an external power supply voltage is applied. And Further, the operation control signal 27
, A counter (counting means) 2 capable of controlling a count start or a stop clear by an internal reset signal 22, and a noise removal of a reset signal 21 from a reset signal input terminal T2. And a noise removing circuit 7 for outputting the internal reset signal 22. A pulse width determination circuit 31 for inputting an m-bit signal 29 as the most significant bit and an n-bit signal 28 as an arbitrary bit other than the most significant bit in the counting by the counter 2 and detecting the active level width of the reset signal 21 have.

The pulse width determination circuit 31 shown in FIG. 1 has a pulse-shaped latch initialization signal 23 which detects the falling edge (trailing edge) of the internal reset signal 22 output from the noise removal circuit 7.
Falling edge detection circuit 8 that outputs
And a latch circuit 3 which is set (high level) at the rising edge of the m-bit signal 29 and reset (low level) by the latch initialization signal 23 and outputs a timer OVF signal of this processing output. .

Further, the pulse width determination circuit 31 is set (high level) at the rise of the AND operation of the timer OVF signal 26 and the n-bit signal 28 from the latch circuit 3 and reset by the latch initialization signal 23 ( The operation control signal 27 generated by being (low level)
And an AND circuit 5 that outputs a logical product signal of the timer OVF signal 26 and the n-bit signal 28 from the latch circuit 3 to the latch circuit 4.

The microcomputer device is usually C
Units such as a PU and peripheral circuits are built in, but the configuration and description of these units will be omitted.

Hereinafter, the operation of this embodiment will be described.

First, the operation of each unit in FIG. 1 will be described.

The regulator 1 operates or stops in response to the operation control signal 27 output from the pulse width determination circuit 31. The external power supply voltage 20 applied to the external power supply terminal T3 during operation is input to the regulator 1, and the reduced internal power supply voltage 30 is reduced by the CPU and peripheral circuits (not shown).
Apply to When the regulator 1 is stopped, the internal power supply voltage 30 that does not decrease the external power supply voltage 20 is supplied.

The counter 2 is controlled to start or stop counting by an internal reset signal 22 output from the noise elimination circuit 7. At the start of the count, the count is incremented by the clock signal 24 input to the clock input terminal T1, and when the stop is cleared, the counter 2 is initialized and the count is stopped. The counter 2 outputs the counted m-bit signal 29 of the most significant bit information to the pulse width determination circuit 31. Also, an n-bit signal 28 of arbitrary bit (1 bit) information other than the most significant bit of the counter 2
Is output to the pulse width determination circuit 31.

The noise elimination circuit 7 receives a reset signal 21 input to the reset signal input terminal T2, and converts the internal reset signal 22 after noise elimination into the counter 2, the pulse width determination circuit 31, the CPU and Output to a peripheral circuit (not shown).

The pulse width determination circuit 31 receives an m-bit signal 29 and an n-bit signal 28 from the counter 2,
The internal reset signal 22 is input from the noise removal circuit 7. The timer OVF signal 26 and the operation control signal 27 are generated from the m-bit signal 29, the n-bit signal 28 and the internal reset signal 22, the timer OVF signal 26 is output from the latch circuit 3, and the operation is performed from the latch circuit 4. The control signal 27 is output to the regulator 1.

This timer OVF signal 26 is output to a CPU and peripheral circuits (not shown), and an operation control signal 27
Is output to the regulator 1.

Next, the overall operation will be described.

The reset signal 21 input to the reset signal input terminal T2 becomes active, and the noise removal circuit 7
When the internal reset signal 22 from which the noise has been removed goes low, the counter 2 starts operating. Next, the reset signal 21 becomes inactive and the internal reset signal 2
When 2 goes high, the counting operation of the counter 2 stops. The pulse width determination circuit 31 determines the active level width of the reset signal 21 from the count information of the counter 2 and outputs an operation control signal 27 based on the result. The regulator 1 switches between operation and stop by the operation control signal 27. That is, the operation of the regulator 1 is controlled by the active level width of the reset signal 21.

In the pulse width determination circuit 31, the internal reset signal 22 is input to the falling edge detection circuit 8.
When the edge detection circuit 8 detects the falling edge (trailing edge) of the internal reset signal 22, it outputs a pulse-like latch initialization signal 23 to the latch circuits 3 and 4. Latch circuit 3 is m
It is set (high level) at the rise of the bit signal 29 and is reset (low level) by the latch initialization signal 23. This processing output becomes the timer OVF signal.
The latch circuit 4 is set (high level) by the rising of the AND circuit 5 by the AND operation of the timer OVF signal 26 and the n-bit signal 28, and is reset (low level) by the latch initialization signal 23. This output becomes the operation control signal 27.

Therefore, when controlling the operation or stop of the regulator 1, it is not necessary to provide a dedicated control terminal. Further, it is unnecessary for a CPU (not shown) (a central processing unit in the microcomputer device) to set a value in a regulator operation control register by executing an instruction as described in the conventional example.

Hereinafter, the main part of the above operation will be described in detail.

FIG. 2 is a timing chart of the operation state of the regulator 1.

Since the operation or stop of the regulator 1 is performed by the active level width of the reset signal 21, the operation after the reset signal 21 becomes active (low level) will be described.

When the reset signal 21 becomes active (low level), the internal reset signal 22 becomes active (low level) after a delay in the noise removing circuit 7. When the internal reset signal 22 becomes active (low level), the counter 2 starts counting up by the clock signal 24, and the falling edge detection circuit 8 of the pulse width determination circuit 31 outputs the pulse-like latch initialization signal 2
3 is output.

When the latch initialization signal 23 is output, the latch circuit 3 and the latch circuit 4 clear the output (low level), so that the timer OVF signal 26 and the operation control signal 27 become low level. Thereafter, the counter 2 counts up and the n-bit signal 28 becomes high level.

At the time of this processing, the m-bit signal 29
Is low level, the output of the AND circuit 5 is also low level, and the output of the latch circuit 4 is not set. Further, when the counter 2 continues counting and the m-bit signal 29 goes high, the latch circuit 3 is set and the timer O
VF26 becomes high level. Thereby, the AND circuit 5
Becomes high level.

At the timing when the latch circuit 3 is set, the n-bit signal 28 is at a low level. When the count is further increased, the n-bit signal 28 goes high again, and the output of the AND circuit 5 goes high, so that the latch circuit 4 is set.

As a result, the operation control signal 27 becomes high level, and the regulator 1 enters the operating state. in this way,
After the timer OVF signal 26 goes high, the internal reset signal 2 is kept until the n-bit signal 28 goes high.
When 2 is at the low level, the regulator 1 enters the operating state.

FIG. 3 is a timing chart when the regulator 1 is stopped.

After the low level is input to the reset signal 21, the counter 2 counts up, and the m-bit signal 29
Is the same as the operation of the regulator 1 until the timer OVF signal 26 is set.
The description is omitted.

N after the timer OVF signal 26 is set
Before the bit signal 28 goes high, the internal reset signal 22 changes to the inactive level (high level). In this case, the operation control signal 27 remains at the low level, and the regulator 1 is stopped.

As described above, the operation or stop of the regulator 1 is controlled by the length of the active level width of the reset signal 21 input to the reset signal input terminal T2. Here, the active level width of the reset signal 21 satisfies the condition of “m bit signal 29 set time + n bit signal 28 set time <active level width” when the regulator 1 is operated.

When the regulator 1 is stopped, the condition of “active level width <m bit signal 29 set time + n bit signal 28 set time” is satisfied.

Specifically, the counter 2 is composed of 8 bits,
n bits are allocated to 6 bits, and the clock signal 2
In the case where the input frequency of 4 is 1 MHz, the regulator 1
The active level width of the reset signal 21 for making the operation state is obtained by Equation 1. In this case, the active level width is 160 μs or more. m-bit signal 29 set time = 1 μs × 128 count n-bit signal 28 set time = 1 μs × 32 count

[0051]

(1 μs × 128) + (1 μs × 32) = 160 μs The counter 2 in the above embodiment is a counter for simply generating the operation control signal 27 for controlling the operation or stop of the regulator 1. However, this counter can be replaced by an oscillation stabilizing counter built in a conventional microcomputer device. This oscillation stabilization counter is a counter for securing the stabilization time of the oscillation circuit during the input of the reset signal, and is a well-known method for notifying the CPU and other peripheral circuits of the elapse of the oscillation stabilization time by generating an overflow signal of the counter. Circuit.

When the oscillation stabilizing counter is also used as the counter 2 of this embodiment, the active level width of the reset signal 21 for designating the operation or stop of the regulator 1 is as follows. It is necessary to always input the active level of the reset signal 21 for the oscillation stabilization time or longer. When the regulator 1 is set in the operating state, “the set time of the m-bit signal 29 + the set time of the n-bit signal 28 <
When the regulator 1 is stopped, the condition is “m bit signal 29 set time <active level width <m bit signal 29 set time + n bit signal 28 set time”.

In the above example, when the operation of the regulator 1 is designated, an active level width of 160 μs or more is input. When the regulator 1 is stopped, an active level width of 128 μs or more and less than 160 μs is input. The difference between the two active level widths can be changed by the bit position of the n-bit signal 28, and when the absolute value of the active level width is changed, the number of bits of the counter 2 can be increased or decreased. Arbitrary design is possible according to the standard of the signal output unit (not shown).

[0054]

As described above, according to the present invention, the operation or stop of the constant voltage output circuit is switched according to the active level width of the reset signal input to the reset signal input terminal. As a result, the current consumption and the noise can be reduced without lowering the output voltage even when the regulator is operating or stopped, and the runaway of the CPU is eliminated, and the number of connection terminals usable by the user is reduced. The operation of the constant voltage output circuit can be controlled without the need.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a microcomputer device of the present invention.

FIG. 2 is a timing chart of an operation state of a regulator in the embodiment.

FIG. 3 is a timing chart in a stop state of a regulator in the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional microcomputer device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Regulator 2 Counter 3, 4 Latch circuit 5 AND circuit 7 Noise removal circuit 8 Edge detection circuit 20 External power supply voltage 21 Reset signal 22 Internal reset signal 26 Timer OVF signal 27 Operation control signal 31 Pulse width judgment circuit

Claims (7)

[Claims] 1. A constant voltage output means for stepping down a voltage applied to a power supply terminal and supplying the same to an internal circuit and switching between operation and stop by a control signal, and stopping when an input reset signal is inactive,
A counting means for starting a counting operation with a clock signal from a clock terminal when active; and a constant voltage output of an operation control signal as a result of determining a predetermined bit number signal counted by the counting means and an active level width of a reset signal. And a pulse width determining means for controlling operation or stop by outputting to the means. 2. The microcomputer device according to claim 1, wherein the counting means controls the elapse of the oscillation stabilization time by the generation of an overflow signal so as to secure the stabilization time of the oscillation circuit during the input of the reset signal. A microcomputer device which is also used as an oscillation stabilization counter shown in a peripheral circuit including the device. 3. The microcomputer device according to claim 1, wherein the predetermined bit number signal counted by said counting means is at least two bits. 4. The microcomputer device according to claim 1, further comprising a noise removing unit that removes noise from the input reset signal and outputs the noise to a pulse width determining unit. 5. A falling edge detecting circuit for outputting a latch initialization signal which detects a falling edge of a reset signal, said pulse width determining means being set by rising of a most significant bit from counting means, and One latch circuit which is reset by a latch initialization signal from the falling edge detection circuit and outputs a timer OVF signal; and a timer OVF signal from the one latch circuit and an arbitrary bit other than the most significant bit from the counting means. The other latch circuit for outputting to the constant voltage output means an operation control signal which is set at the rising edge of the AND operation and is reset by the latch initialization signal from the falling edge detection circuit; From the timer OVF signal from the counter and any bit other than the most significant bit from the counting means, Serial other microcomputer device according to claim 1, wherein an AND circuit for outputting to the latch circuit, characterized in that it comprises for. 6. An operation control signal obtained as a result of determining an active level width of the reset signal activates the constant voltage output means, and the active level width of the reset signal is set to the most significant bit set. 2. The microcomputer device according to claim 1, wherein the value is smaller than the sum of the time and an arbitrary bit set time other than the most significant bit. 7. An operation control signal as a result of determining an active level width of the reset signal activates the constant voltage output means, and the active level width of the reset signal is set to the most significant bit set. 2. The microcomputer device according to claim 1, wherein the value is larger than the sum of the time and an arbitrary bit set time other than the highest order.