JP2009303434A - Motor controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor controller that eliminates the need for a standby terminal. <P>SOLUTION: The motor controller with a motor driving circuit for controlling the rotation of a motor in compliance with the pulse width of a PWM signal further includes a standby circuit which enables a standby signal which sets the motor driving circuit to a standby state when the pulse width of the PWM signal becomes a predetermined value or below and disables the standby signal when the pulse width of the PWM signal exceeds the predetermined value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a motor control device including a motor drive circuit that controls the rotation of a motor according to the pulse width of a PWM signal, and in particular, a standby signal for controlling the motor drive circuit to a standby state based on the PWM signal. The present invention relates to a generated motor control device.

Many motor control devices including a motor drive circuit that controls the number of rotations of a motor in accordance with the pulse width of a PWM signal have been proposed in, for example, Patent Document 1 and others. In such a motor control apparatus, when the motor drive circuit is controlled to a standby state by a standby signal, for example, as shown in FIG. In addition to inputting a signal, a standby signal is input from the standby terminal 5, and when the standby signal is enabled, the motor 1 is stopped regardless of the PWM signal.
JP 2005-160255 A

  However, the special provision of the standby terminal 5 for external input as described above increases the number of terminals to the motor drive circuit 2 constituted by a semiconductor circuit or the like, which increases the chip size and increases the cost. There is a problem that leads to In other words, when there are no free pins so far, it is necessary to select a package with a large number of pins, and there is a disadvantage that the cost increases due to the increase in size of the package.

  An object of the present invention is to provide a motor control device that eliminates the need for a standby terminal and solves the above-described problems by generating a standby signal based on a PWM signal.

In order to achieve the above object, a motor control device according to a first aspect of the present invention is a motor control device including a motor drive circuit that controls rotation of a motor in accordance with a pulse width of a PWM signal. A standby circuit that enables a standby signal that sets the motor drive circuit to a standby state when a width is less than or equal to a predetermined value, and that disables the standby signal when a pulse width of the PWM signal exceeds a predetermined value; It is further provided with the feature.
According to a second aspect of the present invention, in the motor control device according to the first aspect, the standby circuit counts a pulse width of the PWM signal by a clock generation circuit that generates a clock and a clock generated by the clock generation circuit. And a counter circuit that enables the standby signal when the count result is less than or equal to a predetermined count value and disables the standby signal when the count value exceeds the predetermined count value.
According to a third aspect of the present invention, in the motor control device according to the second aspect, the clock generation circuit can change a frequency of a clock generated therein.
According to a fourth aspect of the present invention, in the motor control device according to the second aspect, the counter circuit includes a first D-type flip-flop in which the PWM signal is input to a D terminal and the clock is input to a CLK terminal; The D terminal is connected to the Q terminal of the first D-type flip-flop, the CLK terminal is connected to the second D-type flip-flop, and the D terminal is connected to the Q terminal of the second D-type flip-flop. A third D-type flip-flop in which the clock is input to the CLK terminal; an AND circuit having an input side connected to the Q terminal of the first D-type flip-flop and the Q terminal of the second D-type flip-flop; A fourth D-type flip-flop circuit having an output of the AND circuit connected to the D terminal and a Q terminal of the third D-type flip-flop connected to the CLK terminal. , Wherein the standby signal from the Q terminal of the D-type flip-flop of the fourth outputs.

  According to the present invention, when the pulse width of the PWM signal becomes a predetermined value or less, the standby signal for setting the motor drive circuit to the standby state is enabled, and when the pulse width of the PWM signal exceeds the predetermined value, the standby signal is Since the standby circuit for disabling is provided, it is not necessary to specially provide a standby terminal, and an increase in package size and cost can be avoided.

  FIG. 1 is a block diagram showing the configuration of a motor control apparatus according to an embodiment of the present invention. Reference numeral 1 denotes a motor, 2 a motor drive circuit, and 3 a PWM terminal, which are the same as those shown in FIG. In this embodiment, a standby circuit 4 having an input side connected to the PWM terminal 3 and an output side connected to the motor drive circuit 2 is provided for such a motor control device.

  The standby circuit 4 includes a clock generation circuit 41 and a counter circuit 42 as shown in FIG. That is, the pulse width of the PWM signal input from the PWM terminal 3 is counted by the counter circuit 42 by the clock generated by the clock generation circuit 41, and the standby signal STBY is set to enable / disable according to the count value of the counter circuit 42. To do.

  FIG. 3 is a block diagram showing the configuration of the counter circuit 42. The D-type flip-flops DFF1 to DFF3 in which the clock CLK is input to the clock terminal and the Q terminal in the previous stage is connected to the D terminal, and the D-type flip-flop are shown. An AND circuit AND1 that calculates the logical product of the Q terminals of DFF1 and DFF2, and a D-type flip-flop DFF4 in which the D terminal of DFF3 is connected to the clock terminal and the output of AND1 is connected to the D input.

  Hereinafter, the operation of the counter circuit 42 will be described with reference to the timing chart of FIG. When the PWM signal is input to the D terminal of the first stage DFF1, the PWM signal is at the H level at the rising edge at the time t1 of CLK, so that the output signal T1 at the Q terminal of the DFF1 is at the H level. At this time, the output signal T2 at the Q terminal of DFF2 does not transition from the L level. The same applies to DFF3 and DFF4.

  Next, when CLK rises at time t2, since the signal T1 at the D terminal of the DFF2 is at the H level, the signal T2 at the DFF2Q terminal transitions to the H level. As a result, the signals T1 and T2 both become H level, so that the output signal T4 of the AND circuit AND1 changes from L level to H level and is input to the D terminal of the DFF4.

  Next, when CLK rises at time t3, since the signal T2 at the D terminal of the DFF3 is at the H level, the signal T3 at the DFF3Q terminal transitions to the H level. Since the CLK terminal of DFF4 also rises at the same time, the standby signal STBY at the Q terminal of DFF4 transitions from the L level to the H level. As a result, the standby is disabled, and the motor drive circuit 2 drives the motor in accordance with the PWM signal.

  Thereafter, even when the time t4, t5 and the CLK signal rise, the above state is repeated and the signal T3 maintains the H level, so that the Q terminal of the DFF 4 maintains the H level. That is, the standby disable state continues.

  Next, when the pulse width of the PWM signal becomes small and the PWM signal becomes L level immediately before time t8, the signal T1 changes from H level to L level, so that the T4 signal becomes L level, and the Q terminal of the DFF4 Standby signal STBY attains L level. Thereby, the standby is enabled, and the motor drive circuit 2 stops the motor drive.

  Thereafter, since the signal T4 does not transit to the H level even after the time t9, the standby enabled state is maintained.

  As described above, in this embodiment, if the pulse width of the PWM signal is equal to or more than three clocks CLK, the standby signal STBY output from the Q terminal of the DFF 4 becomes H level and is set to a disabled state. When the pulse width of the PWM signal is reduced to two or less of the clock CLK, the standby signal STBY becomes L level and the standby is set to the enabled state. That is, whether the standby signal STBY is enabled or disabled is determined by the pulse width of the PWM signal and the cycle (frequency) of the clock CLK.

  Therefore, if the frequency of the clock generated by the clock generation circuit 41 can be controlled using a PLL circuit or the like, the pulse width of the PWM signal at which the standby signal is switched can be easily changed. Since the clock generation circuit 41 is used when generating the PWM signal, it can be shared.

It is a block diagram of the motor control apparatus of the Example of this invention. FIG. 2 is a block diagram of the motor control device showing the standby circuit of the motor control device of FIG. 1 in more detail. FIG. 3 is a block diagram of a motor control device that embodies a counter circuit of the motor control device of FIG. 2. 4 is a time chart of the operation of the counter circuit of FIG. 3. It is a block diagram of the conventional motor control apparatus.

Explanation of symbols

  1: motor drive circuit, 2: motor, 3: PWM terminal, 4: standby circuit, 41: clock generation circuit, 42: counter circuit, 5: standby terminal.

Claims (4)

In a motor control device provided with a motor drive circuit that controls the rotation of the motor according to the pulse width of the PWM signal,
When the pulse width of the PWM signal falls below a predetermined value, the standby signal for setting the motor drive circuit to a standby state is enabled, and when the pulse width of the PWM signal exceeds a predetermined value, the standby signal is disabled. A motor control device further comprising a standby circuit.   The standby circuit counts a pulse width of the PWM signal by a clock generation circuit that generates a clock, and a clock generated by the clock generation circuit, and enables the standby signal when the count result is equal to or less than a predetermined count value, The motor control device according to claim 1, further comprising: a counter circuit that disables the standby signal when a predetermined count value is exceeded.   The motor control apparatus according to claim 2, wherein the clock generation circuit is capable of changing a frequency of a clock generated therein. The counter circuit is
The PWM signal is input to the D terminal and the clock is input to the CLK terminal, and the Q terminal of the first D flip-flop is connected to the D terminal, and the clock is input to the CLK terminal. A second D-type flip-flop that connects the Q terminal of the second D-type flip-flop to the D terminal and the clock is input to the CLK terminal; and the first D-type flip-flop An AND circuit whose input side is connected to the Q terminal of the flip-flop and the Q terminal of the second D-type flip-flop, the output of the AND circuit is connected to the D terminal, and the third D-type flip-flop of the third D-type flip-flop is connected to the CLK terminal. A fourth D-type flip-flop circuit connected to the Q terminal;
3. The motor control device according to claim 2, wherein the standby signal is output from a Q terminal of the fourth D-type flip-flop.

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