JPH08298781A - Bridge-type inverter device - Google Patents

Abstract

PURPOSE: To reduce the switching loss of the switch of an inverter device. CONSTITUTION: A switch circuit 5a of an inverter device is constituted of first and second main switches TR1 and TR2, first and second auxiliary switches S1 and S2, first to fourth reactors L1-L4, first to fourth capacitors C1-C4, and first to eighth diodes D1-D8. First and second main switches TR1 and TR2 are subjected to ZVS operation. When the first and second auxiliary switches S1 and S2 are turned on and off, the switches are subjected to ZCS and ZVS operations, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bridge type, half bridge type or multi-phase inverter device.

[0002]

2. Description of the Related Art When a switch of a bridge type inverter for converting direct current into alternating current is turned on and off, switching loss occurs. To solve this kind of problem, the partial resonance is used to switch the switch to ZCS (Zero Current Switching) or ZVS.
It has been proposed to reduce switching loss, surge voltage, and noise by (zero voltage switching). However, there is a demand for an inverter device that can surely and easily achieve reduction of the loss of not only the main switch but also the partial resonance switch. Further, it is required to simplify the structure of the partial resonance circuit.

Therefore, an object of the present invention is to provide a bridge type inverter device which can meet the above demands.

[0004]

The invention according to claim 1 for achieving the above object will be described with reference to the reference numerals of the drawings showing an embodiment. One of the invention is provided between one end and the other end of a DC power supply. Alternatively, a plurality of switch circuits are connected, and the switch circuit connects the load with a current in a first direction and an opposite second current.
In a bridge type, half bridge type, or multi-phase bridge type inverter device configured to flow a current in the direction of, at least one of the switch circuits is connected between one end and the other end of the DC power supply 1. A main conversion circuit comprising a series circuit of first and second main switches TR1 and TR2, wherein the interconnection middle point of the first and second main switches TR1 and TR2 is connected to a load; And the first main switch TR1 and the second main switch TR1 connected in anti-parallel
And a series circuit of the second diodes D1 and D2, the first auxiliary switch S1 and the first reactor L1,
The first auxiliary switch S1 is connected to the first reactor L.
The first auxiliary switch S1 and the first reactor L1 are arranged closer to one end side of the power source 1 than the one, and the one end of the power source 1 and the first and second main switches TR1 and T1.
A first auxiliary circuit connected between the interconnection midpoint of R2, a second auxiliary switch S2 and a second reactor L.
2 is a series circuit with the second auxiliary switch S2
Is arranged on the other end side of the power source 1 with respect to the second reactor L2, and the second reactor L2 and the second auxiliary switch S2 are connected to the first and second main switches TR.
1, a second auxiliary circuit connected between the interconnection middle point of TR2 and the other end of the power source 1, and one end of which is the first auxiliary circuit.
And a first capacitor C1 connected to the interconnection middle point of the second reactors L1 and L2 and a second capacitor C1 whose one end is connected to the interconnection middle point of the first and second reactors L1 and L2. Capacitor C2 and the first capacitor C
A third diode D3 connected between the other end of 1 and the terminal of the first reactor L1 on the side of the first auxiliary switch S1; and the second auxiliary switch S2 of the second reactor L2. A fourth diode D4 connected between the side terminal and the other end of the second capacitor C2, the first capacitor C1, the second reactor L2, and the second auxiliary switch S2. A fifth diode D5 connected in parallel to the circuit connected in series,
The first auxiliary switch S1 and the first reactor L
A sixth diode D6 connected in parallel to a circuit in which 1 and the second capacitor C2 are connected in series.
A third reactor L3 connected between the first capacitor C1 and the third diode D3, and a third reactor L3 connected between the second capacitor C2 and the fourth diode D4. 4 reactor L4, a seventh diode D7 connected in series with the third reactor L3 between the first capacitor C1 and the third diode D3, and the second capacitor C2. Between the fourth diode D4 and the fourth reactor L4
An eighth diode D8 connected in series with one end thereof, one end of which is connected to one end of the power source 1 and the other end of which is connected between the third diode D3 and the seventh diode D7. A third capacitor C3, a fourth capacitor C4 having one end connected to the other end of the power supply 1 and the other end connected between the fourth diode D4 and the eighth diode D8; The first and second main switches TR1 and TR2 are generated to generate first and second main control pulses for alternately turning on the first and second main switches TR1 and TR2 at a constant cycle with a dead time, and the first auxiliary switch. At least the first auxiliary control pulse for controlling the ON of S1
Second auxiliary control pulse which is generated so as to include a part of the period from the trailing edge of the main control pulse to the leading edge of the first main control pulse, and which is used to turn on the second auxiliary switch S2. To include at least a part of the period from the trailing edge of the first main control pulse to the leading edge of the second main control pulse and to have a predetermined time gap with the first auxiliary control pulse. The present invention relates to an inverter device including a switch control circuit that occurs in As described in claim 2, the first and second auxiliary resonance capacitors Ca and Cb can be connected in parallel to the first and second main switches TR1 and TR2. Further, as described in claim 3, 4 or 5, first and second auxiliary diodes Da and Db can be provided.
Further, as described in claims 6 and 7, the third and fourth capacitors C3 and C4 or the first and second auxiliary switches S
Clamping diodes De and Df can be connected in parallel with 1 and S2. In addition, as described in claim 8, diodes Dg and Df for preventing discharge of parasitic capacitance of the first and second auxiliary switches S1 and S2 can be connected in series with the first and second reactors L1 and L2. it can. Also, as shown in claim 9, instead of the first and second reactors L1 and L2 in claim 1, one reactor La is provided to connect the first and second main switches TR1 and TR2 to a middle point and a second interconnection point. It can be connected between the interconnection middle points of the first and second auxiliary switches S1, S2. In addition, claim 10
The first and second auxiliary resonance capacitors Ca and Cb can be added to the circuit of claim 9. Further, as shown in claims 11, 12, and 13, auxiliary diodes Da and Db can be added. In addition, claim 1
As shown in FIG. 4, third and fourth capacitors C3, C4
Clamping diodes De and Df can be connected in parallel with. In addition, as described in claim 15, diodes Dg and Dh for preventing discharge of the parasitic capacitance of the first and second auxiliary switches S1 and S2 are provided in the first and second auxiliary switches S1 and S2.
1 and S2 can be connected in series. Further, it is desirable to provide first and second auxiliary charging diodes D21 and D22 as shown in claims 16 and 17. Further, as shown in claims 18 and 19, the first and second switching loss reducing capacitors Cx1 and Cx2 and the first and second capacitors are used for the inverter devices of claims 1 to 8 and claims 9 to 17. , And the third and fourth switching loss reducing diodes Dx1, Dx2, Dx3, Dx4 can be added.

[0005]

According to the invention of each claim, the first
And turn-on and turn-on of the second main switches TR1 and TR2, and the first and second auxiliary switches S1 and
When S2 is turned off, ZVS is set, so that switching loss, surge voltage, and noise can be reduced. Further, the partial resonance operation can be obtained with a single power source having no midpoint potential, and the power source configuration is simplified. Further, according to the inventions of claims 2 and 10, energy can be supplied to the resonance circuit by the first and second auxiliary resonance capacitors Ca and Cb, and a stable resonance operation can be obtained. According to claims 3 to 8 and 11 to 15, the voltage can be limited by the added diode. According to Claims 16 and 17, the first and second capacitors C1
, C2 can be fully charged. According to the invention of claim 18, the first and second reactors L1
, L2 through the first and second diodes Dx1 and Dx2.
Since the switching loss reducing capacitors Cx1 and Cx2 are connected in parallel, the first and second auxiliary switches S1 and
Immediately before the turn-off of S2, the first and second reactors L1
, L2, the flow rate of the currents I1 and I2 flowing to the third and fourth capacitors C3 and C4 decreases. That is, part of the current of the first and second reactors L1 and L2 is the first
And the first and second capacitors Cx1 for reducing switching loss when the second auxiliary switches S1 and S2 are turned off.
Commute to Cx2. As a result, the rising speeds of the voltages Vc3 and Vc4 of the third and fourth capacitors C3 and C4 at the time of turning off the first and second auxiliary switches S1 and S2 become slow,
The rise of the voltage of the first and second auxiliary switches S1 and S2 is also delayed. Even if the first and second auxiliary switches S1 and S2 are turned off, the storage function (carrier accumulation function)
Due to this, the currents Is1 and Is2 do not become zero immediately but continue to flow for a while. The current flowing due to this storage action becomes a switching loss. The switching losses of the first and second auxiliary switches S1 and S2 are the product of the current flowing through them and this voltage. Therefore, as described above,
When the voltages of the first and second auxiliary switches S1 and S2 drop during turning off, the switching loss here also drops.
Also in the invention of claim 19, since the first and second switching loss reducing capacitors Cx1 and Cx2 are provided for the same purpose as the invention of claim 18, the same effect as in claim 18 can be obtained. .

[0006]

[First Embodiment] Next, a bridge type inverter device according to a first embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, this inverter device is configured to convert a DC voltage of a DC power supply 1 into an AC by a bridge type inverter circuit and supply the AC to a load 2. The DC power supply 1 is composed of a rectifier circuit or a battery, and the load 2 is composed of, for example, an output transformer 3 connected to the load connection terminals 2a and 2b and a load circuit 4 connected to the output transformer 3.

The inverter circuit is composed of a combination of first and second switch circuits 5a and 5b having a half bridge structure. The first switch circuit 5a is a first and second main switch TR1 for forming a first arm of the bridge circuit.
, TR2 and the first and second diodes D1, D2, in addition to the first and second auxiliary switches S1, S2 and the first, second, third to achieve ZVS or ZCS.
And the fourth capacitors C1, C2, C3, C4 and the first, second, third and fourth reactors L1, L2, L3.
, L4, the third, fourth, fifth, sixth, seventh and eighth diodes D3, D4, D5, D6, D7, D8, and the first and second resistors R1 as capacitor charging means, R
2 and. The second switch circuit 5b includes third and fourth main switches TR3 and TR4 to form a second arm of the bridge circuit, and a ninth and tenth diode D.
9 and D10, in order to achieve ZVS and ZCS, third and fourth auxiliary switches S3 and S4 and fifth and
Sixth, seventh and eighth capacitors C5, C6, C7, C
8 and the fifth, sixth, seventh and eighth reactors L5, L
6, L7, L8 and the 11th to 16th diodes D11 to
And D16.

First and second for forming a main conversion circuit
The series circuit of the main switches TR1 and TR2 is connected between one end and the other end of the power source 1, and the first and second main switches T1 and TR2 are connected.
The interconnection middle point of R1 and TR2 is connected to the first load connection terminal 2a as an output terminal. The first and second diodes D1 and D2 are connected to the first and second main switches TR1.
, TR2 are connected in anti-parallel. The series circuit of the third and fourth main switches TR3 and TR4 is also connected between one end and the other end of the power source 1, and the third and fourth main switches TR3 and TR3 are connected.
, TR4 are connected to the second load connection terminal 2b at the interconnection middle point. Ninth and tenth diodes D9, D
The numeral 10 is connected in anti-parallel to the third and fourth main switches TR3 and TR4. The first to fourth main switches TR1
~ TR4 is an insulated gate type (MOS type) field effect transistor whose source is connected to the substrate,
The diodes incorporated therein may be the first, second, ninth and tenth diodes D1, D2, D9, D10.

A first circuit comprising a series circuit of a first auxiliary switch S1 and a first reactor L1 between one end of the power source 1 and the interconnection middle point of the first and second main switches TR1 and TR2. Auxiliary circuit is connected. A second auxiliary circuit composed of a series circuit of a second reactor L2 and a second auxiliary switch S2 between the interconnection middle point of the first and second main switches TR1 and TR2 and the other end of the power source 1. Are connected. First and second capacitors C having the same capacitance as each other
One ends of 1 and C2 are the first and second reactors L1 and L2.
Are connected to the interconnection middle points. The other end of the first capacitor C1 is connected to the terminal on the first auxiliary switch S1 side of the first reactor L1 via the third reactor L3, the seventh diode D7 and the third diode D3, and The other end of the capacitor C2 of the fourth reactor L
It is connected to the second auxiliary switch S2 side terminal of the second reactor L2 through the fourth, eighth diode D8 and fourth diode D4. The fifth diode D5 is the second
Is connected between the terminal (emitter) on the power source 1 side of the auxiliary switch S2 and the other end (upper end) of the first capacitor C1. That is, the fifth diode D5 is connected to the first capacitor C1, the second reactor L2 and the second auxiliary switch S2.
And are connected in parallel to the series connection circuit. Sixth
The diode D6 is connected between the other end (lower end) of the second capacitor C2 and the power supply 1 side terminal (collector) of the first auxiliary switch S1. That is, the sixth diode D6 is connected to the first auxiliary switch S1 and the first reactor L.
It is connected in parallel to the series connection circuit of 1 and the second capacitor C2. The charging resistors R1 and R2 are connected in parallel to the fifth and sixth diodes D5 and D6.
One end of the third capacitor C3 has a first auxiliary switch S1.
Of the third diode D3, D7 and the other end of the diode D3, D7. One end of the fourth capacitor C4 is connected to the interconnection middle point of the fourth and eighth diodes D4 and D8, and the other end is connected to the second
Is connected to the emitter of the auxiliary switch S2. The capacitances of the third and fourth capacitors C3 and C4 are the first
The capacitances of the second capacitors C1 and C2 may be the same as or different from each other. In this embodiment, C3,
The capacity of C4 is smaller than that of C1 and C2. Also,
Reactor L3 and L4 have inductance values L1 and L2
May be the same as or different from. In this embodiment, L3 and L4 are smaller than L1 and L2.

The second switch circuit 5b is substantially the same circuit as the first switch circuit 5a, and includes the third and fourth switches.
One end of the power supply 1 and the third and fourth main switches TR3 to achieve ZVS of the main switches TR3 and TR4 of
A third auxiliary switch S3 between the middle point of the interconnection of TR4
And a fifth auxiliary circuit L5 connected in series to a third auxiliary circuit. Third and fourth main switch T
A fourth auxiliary circuit, which is a series circuit of a sixth reactor L6 and a fourth auxiliary switch S4, is connected between the interconnection middle point of R3 and TR4 and the other end of the power source 1. Fifth
And one ends of the sixth capacitors C5 and C6 are the fifth and sixth ends, respectively.
It is connected to the midpoint of the interconnection of reactors L5 and L6. The other end of the fifth capacitor C5 has a seventh reactor L
7th and 15th diode D15 and 11th diode D11
Via the third auxiliary switch S of the fifth reactor L5
It is connected to the terminal on the 3 side, and the other end of the sixth capacitor C6 is connected to the eighth reactor L8, the sixteenth diode D16 and the first
It is connected to the terminal of the sixth reactor L6 on the side of the fourth auxiliary switch S4 via the second diode D12. First
The third diode D13 is the lower terminal (emitter) of the fourth auxiliary switch S4 and the other end (upper end) of the fifth capacitor C5.
Is connected between and. That is, the thirteenth diode D
Reference numeral 13 is connected in parallel to the series connection circuit of the fifth capacitor C5, the sixth reactor L6 and the fourth auxiliary switch S4. The fourteenth diode D14 is connected between the other end (lower end) of the sixth capacitor C6 and the upper terminal (collector) of the third auxiliary switch S3. That is,
The fourteenth diode D14 is connected in parallel to the series connection circuit of the third auxiliary switch S3, the fifth reactor L5 and the sixth capacitor C6. Charging resistor R3
, R4 are connected in parallel to the fifteenth and sixteenth diodes D15, D16. One end of the seventh capacitor C7 is connected to the collector of the third auxiliary switch S3, and the other end thereof is connected to the interconnection middle point of the eleventh and thirteenth diodes D11, D13. Also, the eighth capacitor C8
Is connected to the midpoint of the interconnection between the twelfth and sixteenth diodes D12 and D16, and the other end is connected to the emitter of the fourth auxiliary switch S4.

In FIG. 1, some of the connecting lines between them are omitted for convenience of illustration, but the switches TR1 to TR4 are not shown.
, S1 to S4 control terminals (bases) are connected to the control circuit 6. As shown in principle in FIG. 2, the control circuit 6 includes first, second, third and fourth main control pulse generation circuits 7, 8, 9, 10 and first to fourth auxiliary control pulse generation circuits. It has circuits 11, 12, 13, and 14, an oscillator 15, and a phase control circuit 16. The first and second main control pulse generation circuits 7 and 8 are controlled by the oscillator 15 to generate a signal shown in FIG.
The first and second main control pulses shown in (B) are generated at a constant cycle, and the first and second main switches TR1 and T1 are generated.
Supply to the base of R2. The third and fourth main control pulse generation circuits 9 and 10 are controlled by the oscillator 15 and the phase control circuit 16 to generate the third and fourth main control pulses shown in FIGS. 3C and 3D, This is the third and fourth main switch T
Supply to the base of R3 and TR4. The first and second main control pulses and the third and fourth main control pulses are the same except that they have a phase difference between them. 3 (A), (B)
The first and second main control pulses of are alternately generated with a time gap (dead time) Ta between them, as shown in FIG.
The third and fourth main control pulses in (D) also occur alternately with a time gap Ta. In this time gap Ta, the auxiliary switches S1, S2, S3 and S4 are turned on while the capacitors C1, C2, C5 and C6 are charged, and almost all the electric charges of C1, C2, C5 and C6 are generated by the resonance operation. The time required for release is set. That is, Ta
Is 0 to 90 degrees of the waveform of the resonance current of C1 L2 or C2 L1.
It is set to a degree or more.

The first auxiliary control pulse generation circuit 11 has a second
Of the second main control pulse of FIG. 3 (B) as shown in FIG. 3 (E).
A pulse from t7 to t9 after a certain time from 6 is generated. The width of the first auxiliary control pulse supplied to the first auxiliary switch S1 has a dead time with respect to the second auxiliary control pulse, and at least from the trailing edge of the second main control pulse to the first control. It is determined to include a portion during the leading edge of the pulse. The second auxiliary control pulse generating circuit 12 is connected to the first main control pulse generating circuit 7, and as shown in FIG. 3 (F), from the trailing edge time t0 of the first main control pulse of FIG. 3 (A). A pulse of t1 to t4 is generated after a fixed time.
The width of the second auxiliary control pulse supplied to the second auxiliary switch S2 has a dead time between it and the first auxiliary control pulse, and at least the trailing edge time t0 of the first main control pulse.
To a portion of the second main control pulse during the leading edge time t2. The third and fourth auxiliary control pulse generation circuits 13 and 14 are connected to the fourth and third main control pulse generation circuits 10 and 9 as shown in FIG.
The third and fourth auxiliary control pulses are formed such that a relationship similar to that of the first and second main control pulses is obtained between the fourth and third main control pulses. To be done.

[0013]

[Operation] The basic operation of the inverter circuit of FIG. 1 is the same as that of a known inverter. That is, while the main switches TR1 and TR4 shown in FIGS. 1 and 4 are turned on at the same time, the current in the first direction is generated in the circuit composed of the power source 1, the first main switch TR1, the load 2 and the fourth main switch TR4. Flow to load 2, second
Also, while the third main switches TR2 and TR3 are simultaneously turned on, a current in the second direction flows through the load 2 in the circuit composed of the power source 1, the third main switch TR3, the load 2 and the second main switch TR2. .

Next, the first to fourth main switches TR1 to T
The operation of R4 during the turn-on and turn-off periods will be described. However, the operation during the turn-off period of the first main switch TR1 and the turn-on of the second main switch TR2 shown at t0 to t2 and the turn-off and the first turn of the second main switch TR2 shown at t6 to t8 in FIG. Main switch TR1
During the turn-on period of the third main switch TR3
3 and the operation of the fourth main switch TR4 during the turn-off period and the operation of the fourth main switch TR4 during the turn-off period and the third main switch TR3 during the turn-off period are substantially the same. The operation in the period t0 to t5 will be described in detail with reference to FIG. 4, and the description of the operation in the other periods will be omitted.

[0015]

[Capacitor charging operation] In this embodiment, for example, the first,
Fourth, sixth and seventh capacitors C1, C4, C6, C
It is necessary to precharge 7 in the direction shown in FIG.
In order to perform this charging, the first and fourth main switches TR1
, Turn on TR4. As a result, a charging current flows in the circuit of the first main switch TR1, the first capacitor C1 and the first resistor R1, and the first capacitor C1 is charged to the power supply voltage V. In addition, the first main switch TR1 and the second
In the circuit of the reactor L2, the fourth diode D4 and the fourth capacitor C4, the fourth capacitor C4 is charged to the polarity shown in FIG. Further, a current also flows through the circuit of the fourth resistor R4, the sixth capacitor C6 and the fourth main switch TR4, and the sixth capacitor C6 is charged. The seventh capacitor C7 is also charged by the same circuit as C4. Of course, conversely to the above, the second, third, fifth and eighth capacitors C2, C3, C5, C8 can also be precharged. After the inverter operation by the first to fourth main switches TR1 to TR4 is started, the loss in resonance is replenished via the main switches TR1 to TR4.

[0016]

[Turn-off and turn-on operation] FIG. 4 shows the states of the respective parts of FIG. 1 in the section t0 to t5 of FIG. The first main switch TR1 is turned off at the time point t0 when the first capacitor C1 is almost charged to the power supply voltage V, and the second main switch TR1 is turned off at a time point t1 after the second time.
When the auxiliary switch S2 of is turned on, the energy of the first capacitor C1 is released in the resonance circuit composed of the first capacitor C1, the second reactor L2, the second auxiliary switch S2 and the fifth diode D5. , The voltage Vc1 of the first capacitor C1 decreases in the waveform of the sine wave in the 90 to 180 degree section as shown in FIG. 4 (D). At this time, since the fifth diode D5 is on, the second main switch TR
The voltage Vc1 of the first capacitor C1 is applied to both ends of the voltage V2, and the voltage Vtr2 of the second main switch TR2 decreases toward zero from t1 to t2 as shown in FIG. 4 (I). . Further, the voltage Vtr1 of the first main switch TR1 becomes a value obtained by subtracting the voltage Vtr2 of the second main switch TR2 from the power supply voltage V, and rises slowly as shown in FIG. 4 (H). When the second auxiliary switch S2 is turned on at time t1, the fourth capacitor C4, the eighth diode D8, the fourth reactor L4, the second capacitor C2 and the second capacitor C4 serve as a discharge circuit for the fourth capacitor C4. Reactor L2
And a second auxiliary switch S2 are formed, and the resonance current of this loop also flows. The resonance frequency of the resonance circuit of the fourth capacitor C4 is the first capacitor C4.
Since it is somewhat lower than the resonance frequency of the resonance circuit of 1,
The voltage Vc4 of the capacitor C4 becomes zero at t3 slightly after t2 as shown in FIG. 4 (G). Also, the second capacitor C2 is charged as shown in FIG. The current I2 of the second reactor L2 flows as a sine wave from 0 to 90 degrees from the time t1 as shown in FIG. 4 (F). When the current I2 of the second reactor L2 reaches almost the peak value of the sine wave at time t2, the second reactor L2
The voltage of 2 becomes 0V, the voltage Vc1 of the first capacitor C1 also becomes zero, the reverse bias of the second diode D2 is released, and the current I2 due to the release of the stored energy of the second reactor L2 becomes The current is commutated to the diode D2 and flows as a circulating current through the closed circuit of the second reactor L2, the second auxiliary switch S2 and the second diode D2. The charging of the second capacitor C2 continues until after t2, and ends when the voltage Vc2 becomes the power supply voltage V at t3. Applying an on-control signal to the second main switch TR2 at or near the time t2 at which the second diode D2 switches to forward bias, a ZVS of the second main switch TR2 is achieved. Second main switch TR
The preferred range at the on-start of 2 is t2 to t4.
The fourth capacitor C4 is discharged and the second capacitor C2 is charged while the second diode D2 or the second main switch TR2 is on. However, when the voltage Vc2 of the second capacitor C2 becomes higher than the power supply voltage V, the sixth diode D6 is turned on, and the energy of the second and fourth reactors L2 and L4 is fed back to the power supply 1 or the load 2. . The voltage Vc4 of the fourth capacitor C4 becomes zero t
If the second auxiliary switch S2 is left on after the time point 3 also, the circulating current continues to flow in the closed circuit of the second reactor L2, the second auxiliary switch S2 and the second diode D2, and power loss occurs. Occurs. Therefore, the second auxiliary switch S2 is turned off at t4 after t3. At this time t4, the voltage Vc4 of the fourth capacitor C4 and FIG.
Since the voltage Vs2 of the second auxiliary switch S2 shown in (2) is zero, the second auxiliary switch S2 becomes ZVS. When the second auxiliary switch S2 is turned off at t4, the current flowing there is changed to the second reactor L2 and the fourth diode D.
4 and the fourth capacitor C4 and the second diode D2 or the closed circuit of the second main switch TR2 are commutated, the fourth capacitor C4 is charged, and this voltage Vc4 is sinusoidal as shown in FIG. 4 (G). It becomes higher in the waveform in the 0 to 90 degree section of the wave and becomes the power supply voltage V. With the above operation, the voltage Vc1 of the first capacitor C1 is zero at time t5, the voltages Vc2 and Vc4 of the second and fourth capacitors C2 and C4 are charged to the power supply voltage V, and the voltage of the third capacitor C3 is charged. Is maintained at the power supply voltage V, the conditions for turning off the second main switch TR2 at t6 and turning on the first main switch TR1 at t8 in FIG. 3 are satisfied.

When the second main switch TR2 is turned off, immediately after this, the first auxiliary switch S1 is turned on,
A resonance circuit of the second capacitor C2, the sixth diode D6, the first auxiliary switch S1 and the first reactor L1 is formed, and a current corresponding to the interval t1 to t2 in FIG. 4 flows in this circuit. In addition, the discharge of the third capacitor C3 causes the third capacitor C3, the first auxiliary switch S1 and the first auxiliary switch S1 to
Is generated in the closed circuit of the reactor L1, the first capacitor C1 and the seventh diode D7. When the current of the first reactor L1 reaches its peak, this voltage becomes zero and the first
Diode D1 of the first diode becomes forward biased, and the first reactor L1, the first diode D1, and the first auxiliary switch S
The circuit of 1 is formed. The voltage changes of the first, second and third capacitors C1, C2, C3 when the second main switch TR2 is turned off and the first main switch TR1 is turned on are shown in FIGS. 4 (E), (D), ( The same as in G), the ZVS of the first and second main switches TR1, TR2 and the first auxiliary switch S1 is achieved. A similar operation occurs in the second switch circuit 5b, and the same effect can be obtained.

In FIG. 4, the load 2 is explained as no load.
Is regarded as a resistance, a current corresponding to the voltage applied to the load 2 is applied to the first to fourth main switches TR1 to TR4.
Flowing through. At this time, even if the storage currents of the main switches TR1 to TR4 flow, the voltages of the first to fourth main switches TR1 to TR4 do not rise suddenly at the turn-off time, so that the power loss is small.

This embodiment has the following effects. (1) ZVS (zero current switch) when the main switches TR1 to TR4 are turned on and off and the auxiliary switches S1 to S4 are turned off, and ZVS (zero current switch) when the auxiliary switches S1 to S4 are turned on. Therefore, switching loss, surge voltage, and noise can be reduced. (2) Since the snubber circuit has substantially no loss, efficiency improvement is achieved. (3) PWM control with a constant frequency is possible, and voltage control can be easily performed. (4) Partial resonance operation can be obtained with a single power source having no midpoint potential, and the configuration is simplified. (5) Reactor L through diode D1 or D2
Since there is a period in which the circulating current of 1 or L2 flows, the degree of freedom at the time of turn-on becomes high.

[0020]

Second Embodiment Next, a bridge type inverter device according to a second embodiment of the present invention will be described with reference to FIG.
However, in FIG. 5 and FIGS. 6 to 9, which will be described later, and FIGS. 11 to 20, and 22, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The inverter circuit of FIG. 5 has four auxiliary resonance capacitors Ca in addition to the inverter circuit of FIG.
, Cb, Cc and Cd are added. The first and second auxiliary resonance capacitors Ca and Cb are the first and second capacitors, respectively.
Are connected in parallel to the main switches TR1 and TR2.
The capacitors Cc and Cd are connected in parallel to the third and fourth main switches TR3 and TR4. The configuration of the circuit of FIG. 5 is the same as that of FIG. 1 except for the above.

The main switches TR1 to TR4 and the auxiliary switches S1 to S4 of FIG. 5 are driven as shown in FIG. 3 similarly to those of FIG. Therefore, the basic operation of the inverter of the circuit of FIG. 5 is the same as that of FIG. By the way, in the circuit of FIG. 1, if the voltage of the first, second, fifth and sixth capacitors C1, C2, C5, C6 is insufficient to reach the power supply voltage V, ZVS cannot be achieved well. The first, second, fifth and sixth capacitors C1, C2, C5
, C6 is fully charged to the power supply voltage V,
Ldi / dt depends on the wiring inductance of the switch circuit
Voltage is generated between the switches and does not become ZVS.
The first and second auxiliary resonance capacitors Ca to Cd of FIG.
Is provided to solve the above problems.

The first capacitor C1 and the fourth capacitor C4 and the second auxiliary resonance capacitor Cb are charged to the power source voltage V, and the first main switch TR1 is turned off while the capacitor Ca is at zero volt, and thereafter the first capacitor TR1 is turned off. When the second auxiliary switch S2 is turned on, the resonance current due to the discharge of the first capacitor C1 and the resonance current due to the discharge of the fourth capacitor C4 flow as in the circuit of FIG. At the same time, the second auxiliary resonance capacitor Cb and the second reactor L
Resonance also occurs in the circuit composed of 2 and the second auxiliary switch S2. As a result, the voltage of the second auxiliary resonance capacitor Cb or the same voltage Vc1 of the first capacitor C1 as this is applied to both ends of the second main switch TR2, and the second main switch TR2 is applied. The voltage Vtr2 of the device decreases toward zero. Further, the voltage Vtr1 of the first main switch TR1 becomes a value obtained by subtracting the voltage Vtr2 of the second main switch TR2 from the power supply voltage V, and rises slowly. Figure 5
In this circuit, since energy is supplied from the second auxiliary resonance capacitor Cb to the second reactor L2, the energy shortage of the resonance circuit is compensated. This function and effect can be obtained based on the first auxiliary resonance capacitor Ca when the second main switch TR2 is turned off and the first main switch TR1 is turned on. Since the first and second auxiliary resonance capacitors Ca and Cb are directly connected between the terminals of the power source 1, they are reliably charged to the power source voltage V. Therefore,
After starting the inverter, the resistors R1 to R4 can be disconnected from the circuit. In the circuit of FIG. 5, the capacitor Ca
The operation other than the auxiliary resonance of .about.Cd is the same as that of the circuit of FIG.

[0023]

[Third Embodiment] In the inverter device of the third embodiment shown in FIG. 6, the first to fourth auxiliary diodes Da to D are added to the circuit of FIG.
The configuration is exactly the same as that of FIG. 1 except that d is added. The first auxiliary diode Da is connected between the interconnection middle point of the first reactor L1 and the third diode D3 and the other end (ground) of the power source 1, and the second auxiliary diode Db is connected to the second auxiliary diode Db. It is connected between the middle point of the interconnection of the reactor L2 and the fourth diode D4 and one end of the power supply 1. Third and fourth auxiliary diodes Dc, Dd
Is also connected in the same manner as Da and Db.

The diodes Da and Db are composed of the third and fourth capacitors C3 and C4, and the first and second reactors L1 and L1.
This is a feedback diode for preventing the energy of L2 from being charged higher than the power supply voltage V. That is, if the third and fourth capacitors C3, C4 are going to be higher than the power supply voltage V, the first and second auxiliary diodes Da,
When Db is turned on, the first and second reactors L1 and L
The energy of 2 is returned to the power supply 1. In FIG. 6, the other parts operate in the same way as in FIG.

Incidentally, the first and second auxiliary diodes Da
, Db can be changed as shown by the broken line in FIG. That is, in FIG. 6, the cathode of the first auxiliary diode Da is connected to the cathode of the seventh diode D7 and the anode of the second auxiliary diode Db is connected to the anode of the eighth diode D8, as in FIG. 12 described later. It is modified so as to be connected, or the cathode of the first auxiliary diode Da is connected to the anode of the seventh diode D7 and the anode of the second auxiliary diode D6 is connected to the eighth diode as shown in FIG. It can be modified to connect to the cathode of D8. Even if you change the connection like this,
And the second auxiliary diodes Da and Db are connected in series to the first and second reactors L1 and L2 to form the surplus energy discharging circuit.

[0026]

[Fourth Embodiment] An inverter device according to a fourth embodiment shown in FIG. 7 is obtained by adding first and second clamping diodes De and Df to the circuit of FIG. The first clamping diode De is connected to the third and seventh capacitors C3 and C.
The second clamp diode Df connected in parallel to 7
Is connected to the fourth and eighth capacitors C4 and C8.

First and second clamping diodes De
, Df, the third and fourth capacitors C3, C4 are discharged when a circulating current flows through the diodes D1, D2 of the first switch circuit 5a, and even if this voltage becomes zero, the reactor becomes The energy of L3 and L4 remains and the third and fourth capacitors C3 and C4 may be charged in the opposite direction. However, when the clamping diodes De and Df are provided as shown in FIG. 7, the energy of the reactors L3 and L4 is fed back to the power source and the voltages of C3 and C4 are clamped to zero.

The clamping diodes De and Df are connected to the first and second auxiliary switches S as shown by the dotted line in FIG.
1 and S2 can be connected in anti-parallel. In this case, the third and fourth capacitors C3 and C4 are connected to the third
And the clamping diodes De and Df are connected in parallel via the fourth diodes D3 and D4.

[0029]

[Fifth Embodiment] An inverter device according to a fifth embodiment of FIG. 8 is a diode Dg for preventing discharge of parasitic capacitance between the collector and emitter of the first and second auxiliary switches S1 and S2.
It has Dh. The first parasitic capacitance discharge prevention diode Dg is connected in series to the first reactor L1 and
The parasitic capacitance discharge prevention diode Dh is connected in series with the second reactor L2. The second switch circuit 5b is also provided with similar diodes Dg and Dh.

Since the parasitic capacitances of the first and second auxiliary switches S1 and S2 are connected in parallel with the third and fourth capacitors C3 and C4, the third and fourth capacitors C
3 and C4 are charged at the same time. The third and fourth capacitors C3 and C4 are prevented from being discharged by the third and fourth diodes D3 and D4, but the parasitic capacitances of the first and second auxiliary switches S1 and S2 are different from those of the first and second auxiliary switches S1 and S2. Main switch T
R1, TR2 or diodes D1, D2 and first and second
Attempts to discharge through the reactors L1 and L2. However, in the circuit of FIG. 8, this discharge is caused by the diodes Dg and Dh.
Block with. This can reduce the loss due to the discharge of the parasitic capacitance.

The discharge prevention diodes Dg and Dh can be connected in series to the first and second auxiliary switches S1 and S2. In FIG. 8, the first feedback diode Da shown in FIG. 6 is connected between the anode of the discharge prevention diode Dg and the other end (ground) of the power source 1 to prevent the second discharge prevention. Diode Dh cathode and power supply 1
The second feedback diode Db shown in FIG. 6 can be connected to one end (upper end) of the.

[0032]

[Sixth Embodiment] Next, referring to FIG. 9 and FIG.
The inverter device of the embodiment will be described. In the inverter device of FIG. 9, the first and second reactors L1 and L2 of FIG.
One reactor La is provided instead of. Reactor La is the first and second main switches TR1 and TR2.
Interconnection middle point and first and second auxiliary switches S1, S
Connected between two interconnection midpoints. Further, the interconnection middle point of the first and second capacitors C1 and C2 is connected to the interconnection middle point of the first and second main switches TR1 and TR2. First and second auxiliary switches S1 and S2
Are connected in series with each other without a reactor. 9 is the same as that of FIG. 1 except for the above. In FIG. 9, La, L3, and L4 are the first, second, and third reactors in claim 9. The second switch circuit 5b shown by a block is formed in the same manner as the first switch circuit 5a.

The first and second main switches TR1 of FIG.
TR2 and the first and second auxiliary switches S1 and S2 are driven according to FIG. 3 like those of FIG. The initial charging of the capacitors C1, C3 and C4 is performed in the same manner as in the first embodiment. FIG. 10 shows the waveform of each part in the same section as in FIG. First, third and fourth capacitors C1, C3, C
4 is charged to the power supply voltage V, the first main switch TR1 is turned on and the second main switch TR2 is turned off, and then the first main switch TR1 is turned off at t0 in FIG.
Immediately after that, when the second auxiliary switch S2 is turned on at t1, the energy of the first capacitor C1 is C1, La,
It discharges in the resonance circuit composed of S2 and D5. The energy of the fourth capacitor C4 is C4, D8, L4, C2.
, La and S2 are discharged in the resonance circuit. In short, in the circuit of FIG. 9, instead of the second reactor L2 of FIG. 1, the first and fourth capacitors C1 and C1 are passed through the common reactor La.
A discharge circuit is formed by the resonance of C4. This allows
The voltages Vc1, Vc2 and Vc4 of the first, second and fourth capacitors C, C2 and C4 change in the same manner as in FIG. 4 as shown in FIGS. 10 (D), (E) and (G). Also, the voltages Vtr1 and Vtr2 of the second main switches TR1 and TR2 are also shown in FIG.
As shown in (H) and (I), it changes similarly to FIG. 4, and the current I1 of the reactor La also changes as shown in FIG. 10 (F). The direction of the electric current of the reactor La is opposite to that shown in FIG. 10F when the first auxiliary switch S1 is turned on.
When the current I1 of the reactor La reaches its peak, the voltage of the reactor La becomes zero, and the second diode D2 is turned on at the time t2. As a result, a circulating circuit of the reactor La, the second auxiliary switch S2 and the second diode D2 is formed. Although a current flows through the common reactor La in FIG. 9 in place of the second reactor L2 in FIG. 1, other operations are basically the same as those in the circuit of FIG. Main switches TR1 and TR2
, ZVS of the first and second auxiliary switches S1 and S2 is achieved, and the same effect as the first embodiment can be obtained.

[0034]

[Seventh Embodiment] The circuit of FIG. 11 is obtained by adding the first and second auxiliary resonance capacitors Ca and Cb to the circuit of FIG. The first and second auxiliary resonance capacitors C of FIG.
a and Cb are connected in parallel to the first and second main switches TR1 and TR2, and act as a source of resonance energy as in the circuit of FIG.

[0035]

Eighth Embodiment The circuit shown in FIG. 12 is obtained by adding the first and second auxiliary diodes Da and Db to the circuit shown in FIG. One end of the first auxiliary diode Da is connected to the other end (ground) of the power supply 1, and the other end is the seventh diode D7.
And a third capacitor C3. Second
Of the auxiliary diode Db is connected between the fourth capacitor C4 and the eighth diode D8, and the other end is connected to the power source 1
Is connected to one end. The first and second auxiliary diodes Da and Db of FIG. 12 have the same operation and effect as those of the third embodiment shown in FIG.

[0036]

[Ninth Embodiment] FIG. 13 shows an inverter device in which the connection points of the first and second auxiliary diodes Da and Db of FIG. 12 are changed. In FIG. 13, the cathode of the first auxiliary diode Da is connected to the anode of the seventh diode D7, and the anode of the second auxiliary diode Db is connected to the cathode of the eighth diode D8. Even with this connection, the same effects as those of the third and eighth embodiments can be obtained.

[0037]

[Tenth Embodiment] The circuit shown in FIG. 14 is the same as the circuit shown in FIG.
And second auxiliary diodes Da and Db are added. The first and second auxiliary diodes Da and Db are the first
And the second auxiliary switches S1 and S2 are connected in anti-parallel. The first and second auxiliary diodes Da and D of FIG.
b is the reactor La as in the third, eighth and ninth embodiments.
Has a function of returning the surplus energy to the power source and also has a clamping function like the diodes De and Df in FIG.

[0038]

[Eleventh Embodiment] The circuit of FIG. 15 is obtained by adding the first and second clamping diodes De and Df to the circuit of FIG. In FIG. 15, the first and second clamping diodes De and Df are connected in parallel to the third and fourth capacitors C3 and C4 as in FIG. This FIG.
The circuit has the same effect as that of FIG.

[0039]

[Twelfth Embodiment] The circuit shown in FIG. 16 is the same as the circuit shown in FIG. 9 for preventing the discharge of the parasitic capacitance between the collector and emitter of the first and second auxiliary switches S1 and S2. The diode Dg and Dh are added. The first and second discharge preventing diodes Dg, Dh are connected in series to the series circuit of the first and second auxiliary switches S1, S2, and the first and second auxiliary switches S1, S2.
And the common reactor La. FIG.
The circuit of 6 has the same effect as the circuit of FIG.

[0040]

[Thirteenth Embodiment] A half-bridge type inverter device according to a thirteenth embodiment of FIG. 17 will be described below. The inverter device of FIG. 17 is provided with first and second conversion capacitors C11 and C12 instead of the second switch circuit 5b of the inverter device of FIG. Capacitors C11, C12
The series circuit of is connected between one end and the other end of the power supply 1, and the load 2 is connected to the interconnection midpoint. Since the switch circuit 5a of this half-bridge device is the same as that in FIG. 9, it is possible to obtain the same effects as those in FIG. In addition,
A half bridge circuit similar to that of FIG. 17 can be configured by using the switch circuit 5a of FIGS. 1, 5 to 8, and 11 to 16 to obtain similar effects.

[0041]

[Fourteenth Embodiment] The inverter device of the fourteenth embodiment shown in FIG. 18 is obtained by adding the first and second auxiliary charging diodes D21 and D22 to the inverter device of FIG. Are configured the same as in FIG. First auxiliary charging diode D
21 is connected between the upper end (the other end) of the first capacitor C1 and the terminal of the first reactor L1 on the first auxiliary switch S1 side, and the second auxiliary charging diode D22 is the second auxiliary charging diode D22. The second auxiliary switch S2 side terminal of the reactor L2 and the second
Is connected to the lower end (the other end) of the capacitor C2.

The first and second auxiliary charging diodes D21 and D22 contribute to the charging of the first and second capacitors C1 and C2. That is, after the second auxiliary switch S2 is turned off, a closed circuit of the second reactor L2, the second auxiliary charging diode D22 and the second capacitor C2 is formed.
The second capacitor C2 is charged with the energy of the second reactor L2. Further, after the first auxiliary switch S1 is turned off, a circuit of L1-C1-D21 is formed, and the energy of the first reactor L1 charges the first capacitor C1. In the circuit of FIG. 1, the first and second capacitors C1 and C2 are the first and second auxiliary switches S1 and
The third and fourth capacitors C3 and C4 are provided during the on period of S2.
It is charged based on the electric charge of, but may not be fully charged. However, in the circuit of FIG. 18, diodes D21 and D
Charging through 22 eliminates this kind of problem.
After the second and first capacitors C2 and C1 are charged to desired values, current flows through the circuit of L2-D22-D6-1-D2 and the circuit of L1-D1-1-D5-D21.

[0043]

Fifteenth Embodiment A fifteenth embodiment shown in FIG. 19 is obtained by adding the first and second auxiliary charging diodes D21 and D22 to the circuit shown in FIG. 9 as in the case of FIG. As a result, the same effect as that of the circuit of FIG. 18 can be obtained. That is, the La-D22-C2 circuit charges the second capacitor C2, and the La-C1-D21 circuit charges the first capacitor C1. It should be noted that after the second and first capacitors C2 and C1 are charged to a desired value, La-D
22-D6-1-D2 circuit, La-D1-1-D5-D
The current of the reactor La flows in the circuit of 21.

[0044]

Sixteenth Embodiment The inverter device shown in FIG. 20 is different from the inverter device shown in FIG. 1 in that it has first to fourth switching loss reducing capacitors Cx1 to Cx4 and first to eighth switching loss reducing diodes Dx1. .About.Dx8 are added, and the other components are the same as those in FIG. The first switching loss reducing capacitor Cx1 and the first switching loss reducing diode Dx1 are connected in series with each other, and the series circuit is connected in parallel with the first reactor L1. The second switching loss reducing capacitor Cx2 and the second switching loss reducing diode Dx2 are connected in series with each other, and this series circuit is connected to the second reactor L2.
Are connected in parallel. The anode of the third switching loss reducing diode Dx3 is the second auxiliary switch S2.
Is connected to the lower end, that is, the emitter, and the cathode is connected to the upper end of the first switching loss reducing capacitor Cx1. Therefore, the third switching loss reducing diode Dx3 is connected to the first switching loss reducing capacitor Cx1, the second reactor L2, and the second auxiliary switch S2.
And are connected in parallel to the circuits connected in series with each other. Fourth switching loss reduction diode Dx4
Is connected to the lower end of the second switching loss reducing capacitor Cx2, and its cathode is connected to the upper end of the first auxiliary switch S1 or collector. Therefore, the fourth switching loss reduction diode Dx4
Is connected in parallel to a circuit in which the second switching loss reducing capacitor Cx2, the first reactor L1 and the first auxiliary switch S1 are connected in series.
Since the second switch circuit 5b has the same configuration as the first switch circuit 5a, the series circuit of the capacitor Cx3 and the diode Dx5 is connected in parallel with the reactor L5, and the circuit of the capacitor Cx4 and the diode Dx6 is connected in parallel with the reactor L6. The diode Dx7 is connected in parallel to the circuit in which the capacitor Cx3, the reactor L6, and the auxiliary switch S4 are connected in series, and the diode Dx8 is connected to the capacitor Cx4, the reactor L5, and the auxiliary switch S3 in series. Connected in parallel to the connected circuit.

The basic operation of the inverter device of FIG. 20 is the same as that of the inverter device of FIG. FIG. 21 shows FIG.
The state of each part of 0 is shown similarly to FIG. 21 (A)-
(J) shows the state of the same part as (A)-(J) of FIG. 21 (K) and (L) are voltages Vcx1 and Vcx of the first and second switching loss reducing capacitors Cx1 and Cx2, respectively.
Indicates 2. When the second auxiliary switch S2 is turned on at t1 in FIG. 21, the charges accumulated in the first switching loss reducing capacitor Cx1 are transferred to the capacitor Cx1, the second reactor L2, the second auxiliary switch S2 and the third auxiliary switch S2.
Is discharged by the resonance circuit of the switching loss reducing diode Dx3, and the voltage Vcx1 of the capacitor Cx1 becomes zero at t2. Note that, also in FIG. 20, the second auxiliary switch S
At the time of turn-on of 2, C1-L2-S2-
A resonant circuit of D5 is also formed. After that, when the second auxiliary switch S2 is turned off at t4, L2-D4-C4-D
The circuit of 2 is formed in the same manner as the device of FIG.
-Dx2-Cx2 closed circuit is formed and capacitors C4, C
The voltages Vc4 and Vcx2 of x2 gradually increase toward the power supply voltage V as shown in FIGS. When the second switching loss reducing capacitor Cx2 of FIG. 20 is not provided as in the circuit of FIG. 1, all of the current I2 of the second reactor L2 is commutated to the fourth capacitor C4, and FIG.
The voltage Vc4 of the fourth capacitor C4 rises rapidly and the voltage of the second auxiliary switch S2 also rises as shown by the dotted line in the section t4 to t5 of (G). On the other hand, FIG.
In the above device, a part of the current of the second reactor L2 is commutated to the second switching loss reducing capacitor Cx2, so that the rising speed of the voltage Vc4 of the fourth capacitor C4 is as shown in FIG.
It decreases as shown by the solid line from t4 to t5 of 1 (G). By the way, the second auxiliary switch S2 is a transistor, which has a function of accumulating carriers, and even if the second auxiliary switch S2 is turned off at t4 in FIG. 21, a current Is2 is generated in the section from t4 to t5 in FIG. The current continues to flow, causing power loss in the second auxiliary switch S2. The power loss in this second auxiliary switch S2 is the product of the current Is2 flowing through it and the voltage here, ie the voltage Vc4 of the fourth capacitor C4. t4 to t5
At, since the voltage Vc4 of the fourth capacitor C4 and the voltage of the second auxiliary switch S2 become low, the switching loss also becomes small. When the first, third and fourth auxiliary switches S1, S3 and S4 are turned off, the same operational effect as when the second auxiliary switch S2 is turned off can be obtained. Further, the capacitors Cx1 to Cx4 and the diodes Dx1 to Dx8 shown in FIG. 20 can be added to the inverter devices shown in FIGS.

[0046]

[Seventeenth Embodiment] The inverter device shown in FIG. 22 is the same as the inverter device shown in FIG. 9 except that the first and second switching loss reducing capacitors Cx1 and Cx2 and the first, second, third and fourth switching losses. Reduction diodes Dx1, Dx2, D
The configuration is the same as that of FIG. 9 except that x3 and Dx4 are added. A first series circuit of a first switching loss reducing capacitor Cx1 and a first switching loss reducing diode Dx1 and a second series of a second switching loss reducing capacitor Cx2 and a second switching loss reducing diode Dx2 Are connected in parallel to the common reactor La. However, the first and second switching loss reduction diodes Dx1 and Dx2 are connected in opposite polarities. The third switching loss reducing diode Dx3 is connected between the emitter of the second auxiliary switch S2 and one terminal of the first switching loss reducing capacitor Cx1. After all, the diode Dx3 is connected in parallel to the series circuit of the first switching loss reducing capacitor Cx1 and the common reactor La and the second auxiliary switch S2. The fourth switching loss reducing diode Dx4 is connected between one end of the second switching loss reducing capacitor Cx2 and the collector of the first auxiliary switch S1. After all, the diode Dx4 is connected to the first auxiliary switch S1 and the common reactor La and the second auxiliary switch S1.
Is connected in parallel to the series circuit of the switching loss reducing capacitor Cx2.

The basic operation of the inverter device of FIG. 22 is the same as that of the inverter device of FIG. FIG. 23 shows FIG.
The state of each part of 1 is shown similarly to FIG. FIG. 23 (A)
(J) shows the state of the same part as (A)-(J) of FIG. 23 (K) and (L) are voltages Vcx1 and Vc of the first and second switching loss reducing capacitors Cx1 and Cx2, respectively.
Indicates cx2. When the second auxiliary switch S2 is turned on at t1 in FIG. 23, the charge accumulated in the first switching loss reducing capacitor Cx1 is transferred to this capacitor Cx1.
And common reactor La, second auxiliary switch S2 and third
Is discharged by the resonance circuit of the switching loss reducing diode Dx3, and the voltage Vcx1 of the capacitor Cx1 becomes zero at t2. Note that, also in FIG. 22, the second auxiliary switch S
At the time of turn-on of 2, C1-La-S2-
A resonant circuit of D5 is also formed. After that, when the second auxiliary switch S2 is turned off at t4, La-D4-C4-D
The second circuit is formed in the same manner as the device of FIG.
-Dx2-Cx2 closed circuit is formed and capacitors C4, C
The voltages Vc4 and Vcx2 of x2 gradually increase toward the power supply voltage V as shown in FIGS. 23 (G) and 23 (L). When the second switching loss reducing capacitor Cx2 of FIG. 22 is not provided as in the circuit of FIG. 9, all of the current I2 of the common reactor La is commutated to the fourth capacitor C4, and FIG.
The voltage Vc4 of the fourth capacitor C4 rises rapidly and the voltage of the second auxiliary switch S2 also rises as shown by the dotted line in the section t4 to t5 of (G). On the other hand, FIG.
In the device described above, a part of the current of the common reactor L2 is commutated to the second switching loss reducing capacitor Cx2,
The rising speed of the voltage Vc4 of the fourth capacitor C4 is shown in FIG.
It decreases as shown by the solid line from t4 to t5 in (G). By the way, the second auxiliary switch S2 is a transistor,
Even if it has a carrier accumulating action and is turned off at t4 in FIG. 23, the current Is2 continues to flow as shown by the dotted line in the section from t4 to t5 in FIG. Occurs. The power loss in this second auxiliary switch S2 is the product of the current Is2 flowing there and the voltage here, ie the voltage Vc4 of the fourth capacitor C4. In the period from t4 to t5, the voltage Vc4 of the fourth capacitor C4 and the voltage of the second auxiliary switch S2 become low, so that the switching loss also becomes small. When the first auxiliary switch S1 is turned off, the same operational effect as when the second auxiliary switch S2 is turned off can be obtained. Further, the capacitors Cx1 and Cx2 and the diodes Dx1 to Dx4 of FIG. 22 can be added to the inverter devices of FIGS. 11 to 17 and 19.

[0048]

[Eighteenth Embodiment] The inverter device shown in FIG. 24 is a switching loss reducing diode Dx1, Dx2, Dx5, D.
The structure is the same as that of FIG. 20 except that the connection portion of x6 is changed. In FIG. 24, the cathodes of the first and fifth switching loss reducing diodes Dx1 and Dx5 are connected to the nodes of the third and eleventh diodes D3 and D11.
Second and sixth switching loss reducing diodes Dx
2. The node of Dx6 is the fourth and twelfth diode D4.
, D12 connected to the cathode. Even if the connection is changed in this way, the circuit of FIG. 24 performs substantially the same operation as the circuit of FIG. 20, and the same effect can be obtained. The first and second switching loss reducing diodes Dx1,
It is also possible to change the connection of either one of Dx2 or one of the diodes Dx5 and Dx6 as shown in FIG.

[0049]

[Nineteenth Embodiment] The inverter device shown in FIG.
0, the third, fourth, eleventh and twelfth diodes D2,
The structure is the same as that shown in FIG. 20 except that the connection points of D4, D11 and D12 are changed. In FIG. 25, the cathodes of the third and eleventh diodes D3 and D11 are connected to the anodes of the first and fifth switching loss reducing diodes Dx1 and Dx5, and the fourth and twelfth diodes are connected. The nodes D4 and D12 are the second and sixth switching loss reducing diodes.
It is connected to the terminals Dx2 and Dx6. The circuit of FIG. 25 performs substantially the same operation as the circuit of FIG. 20, and can obtain the same effect. In FIG. 25, either one of the diodes D3 and D4 or the diodes D11 and D4 is used.
Only one of 12 can be connected as shown in FIG. 25 and the other can be connected as shown in FIG.

[0050]

[Twentieth Embodiment] The inverter device shown in FIG. 26 is a diode Dx for reducing the first and second switching losses shown in FIG.
It is formed in the same manner as in FIG. 22 except that the connection points of 1 and Dx2 are changed. In FIG. 26, the cathode of the first switching loss reducing diode Dx1 is connected to the node of the third diode D3, and the second switching loss reducing diode D2 is connected. It is connected to the cathode of the fourth diode D4. The circuit of FIG. 26 performs substantially the same operation as the circuit of FIG. 22 and can obtain the same effect. It is also possible to connect only one of the first and second switching loss reducing diodes Dx1 and Dx2 as shown in FIG. 26 and the other as shown in FIG.

[0051]

21st Embodiment The inverter device of FIG. 27 is the same as that of FIG. 22 except that the connection points of the third and fourth diodes D3 and D4 of FIG. 22 are changed. In FIG. 27, the cathode of the third diode D3 is connected to the anode of the first switching loss reducing diode Dx1,
The anode of the diode D4 is connected to the cathode of the second switching loss reducing diode Dx2. The circuit of FIG. 27 performs substantially the same operation as the circuit of FIG. 22 and can obtain the same effect. It is possible to connect either one of the third and fourth diodes D3 and D4 of FIG. 27 as shown in FIG. 27 and the other as shown in FIG.

[0052]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) It is possible to configure a three-phase or multi-phase bridge type inverter device by preparing three or a large number of ones corresponding to the first switch circuit 5a in each embodiment and connecting three-phase or multi-phase. . (2) Main switches TR1 to TR4, auxiliary switch S1
~ S4 can be a semiconductor switch such as a field effect transistor. Moreover, these can be made into the anti-parallel diode built-in element. (3) In each embodiment, for example, the time when the second auxiliary switch S2 is turned on is the time t0 in FIG. 4, that is, the time when the first main switch TR1 is turned off as shown by the dotted line in FIG. 4 (C). Alternatively, the time may be slightly before this time t0. Even in this way, Z at the turn-on and turn-off of the first and second main switches TR1 and TR2
VS, ZCS (zero current switch) when turning on the first and second auxiliary switches S1 and S2, and ZVS when turning off are possible. (4) In each embodiment, the charging resistors R1 to R4 can be omitted and the initial charging of each capacitor can be performed by an independent charging circuit. Further, the charging resistors R1 to R4 can be replaced with switches to selectively flow the charging current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an inverter device of a first embodiment.

FIG. 2 is a block diagram showing a control circuit of FIG.

FIG. 3 is a waveform diagram of each part of FIG.

FIG. 4 is a waveform diagram of each part of FIG.

FIG. 5 is a circuit diagram of an inverter device according to a second embodiment.

FIG. 6 is a circuit diagram of an inverter device according to a third embodiment.

FIG. 7 is a circuit diagram of an inverter device according to a fourth embodiment.

FIG. 8 is a circuit diagram of an inverter device according to a fifth embodiment.

FIG. 9 is a circuit diagram of an inverter device according to a sixth embodiment.

10 is a waveform diagram of each part of FIG.

FIG. 11 is a circuit diagram of an inverter device according to a seventh embodiment.

FIG. 12 is a circuit diagram of an inverter device according to an eighth embodiment.

FIG. 13 is a circuit diagram of an inverter device according to a ninth embodiment.

FIG. 14 is a circuit diagram of an inverter device according to a tenth embodiment.

FIG. 15 is a circuit diagram of an inverter device according to an eleventh embodiment.

FIG. 16 is a circuit diagram of an inverter device according to a twelfth embodiment.

FIG. 17 is a circuit diagram of an inverter device according to a thirteenth embodiment.

FIG. 18 is a circuit diagram showing an inverter device of a fourteenth embodiment.

FIG. 19 is a circuit diagram showing an inverter device of a fifteenth embodiment.

FIG. 20 is a circuit diagram showing an inverter device of a 16th embodiment.

21 is a waveform chart showing a state of each part of FIG. 20. FIG.

FIG. 22 is a circuit diagram showing an inverter device according to a 17th embodiment.

FIG. 23 is a waveform diagram showing a state of each part of FIG. 22.

FIG. 24 is a circuit diagram showing an inverter device of an eighteenth embodiment.

FIG. 25 is a circuit diagram showing an inverter device according to a 19th embodiment.

FIG. 26 is a circuit diagram showing an inverter device of a twentieth embodiment.

FIG. 27 is a circuit diagram showing an inverter device according to a 21st embodiment.

[Explanation of symbols]

 TR1 to TR4 Main switch S1 to S4 Auxiliary switch

Claims (19)

[Claims] 1. One or a plurality of switch circuits are connected between one end and the other end of a DC power supply, and the switch circuit connects a load with a current in a first direction and a second direction opposite thereto. In a bridge type, half bridge type, or multi-phase bridge type inverter device configured to flow current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). It is composed of a series circuit of first and second main switches (TR1, TR2), and includes the first and second main switches (TR1, T2).
R2) a main conversion circuit whose interconnection middle point is connected to a load, and first and second diodes (D1, D2) antiparallel connected to the first and second main switches (TR1, TR2).
), The first auxiliary switch (S1) and the first reactor (L1
) In a series circuit, the first auxiliary switch (S1) is arranged at one end side of the power source (1) with respect to the first reactor (L1), and the first auxiliary switch (S1) And the first reactor (L1) are connected to one end of the power source (1) and the first and second main switches (TR1).
, TR2) and a second auxiliary switch (S2) and a second reactor (L2) that are connected between the middle point of interconnection of
), The second auxiliary switch (S2) is arranged on the other end side of the power source (1) with respect to the second reactor (L2), and the second reactor (L2) A second auxiliary switch (S2) connected between the interconnection middle point of the first and second main switches (TR1, TR2) and the other end of the power supply (1). Auxiliary circuit and one end of which is connected to the first and second reactors (L1, L2).
) The first capacitor (C1
), And one end thereof has the first and second reactors (L1, L2).
A second capacitor (C2
), And a third diode (D3) connected between the other end of the first capacitor (C1) and the terminal of the first reactor (L1) on the first auxiliary switch (S1) side. And a fourth diode (D4) connected between the second auxiliary switch (S2) side terminal of the second reactor (L2) and the other end of the second capacitor (C2). , A fifth diode () connected in parallel to a circuit in which the first capacitor (C1), the second reactor (L2) and the second auxiliary switch (S2) are connected in series. D5), the first auxiliary switch (S1), the first reactor (L1), and the second capacitor (C2) are connected in parallel to a circuit connected in series to a sixth circuit. Diode (D6) and the first capacitor (C1) Third reactor connected between said third diode (D3) (L3)
And a fourth reactor (L4) connected between the second capacitor (C2) and the fourth diode (D4).
And a seventh diode (D7) connected in series with the third reactor (L3) between the first capacitor (C1) and the third diode (D3), An eighth diode (D8) connected in series to the fourth reactor (L4) between the second capacitor (C2) and the fourth diode (D4), and one end of which is connected to the power source ( 3) a third capacitor (C3) connected to one end of 1) and the other end connected between the third diode (D3) and the seventh diode (D7)
) And a fourth capacitor (one end of which is connected to the other end of the power source (1) and the other end of which is connected between the fourth diode (D4) and the eighth diode (D8)). C4
), And generating first and second main control pulses for alternately turning on the first and second main switches (TR1, TR2) at a constant cycle with a dead time, First
The first auxiliary control pulse for controlling the ON of the auxiliary switch (S1) of at least a part of the period from the trailing edge of the second main control pulse to the leading edge of the first main control pulse. A second auxiliary control pulse for ON-controlling the second auxiliary switch (S2) from at least the trailing edge of the first main control pulse to the leading edge of the second main control pulse. And a switch control circuit for generating a predetermined time gap between the first auxiliary control pulse and the first auxiliary control pulse. 2. Further comprising first and second auxiliary resonance capacitors (Ca, Cb) connected in parallel to the first and second main switches (TR1, TR2). An inverter device according to claim 1. 3. Further, one end thereof is connected to the other end of the power source (1), and the other end thereof is the first auxiliary switch (S1).
) And a first auxiliary diode (Da) connected to an interconnection point between the first reactor (L1) and the second reactor (L2) and the second auxiliary switch (S2). 3. An inverter device according to claim 1 or 2, characterized in that it has a second auxiliary diode (Db) which is connected to the interconnection point and whose other end is connected to one end of the power supply (1). 4. Further, one end thereof is connected to the other end of the power source (1), and the other end thereof is the third capacitor (C3).
And a seventh auxiliary diode (D7) connected between the first auxiliary diode (Da) and one end between the fourth capacitor (C4) and the eighth diode (D8). Inverter device according to claim 1 or 2, characterized in that it has a second auxiliary diode (Db) which is connected and whose other end is connected to one end of the power supply (1). 5. Further, one end thereof is connected to the other end of the power source (1), and the other end thereof is the third reactor (L3).
And a seventh auxiliary diode (D7) connected between the first auxiliary diode (Da) and one end of the first auxiliary diode (Da) between the fourth reactor (L4) and the eighth diode (D8). Inverter device according to claim 1 or 2, characterized in that it has a second auxiliary diode (Db) which is connected and whose other end is connected to one end of the power supply (1). 6. Further comprising first and second clamping diodes (De, Df) connected in parallel to said third and fourth capacitors (C3, C4). An inverter device according to item 1 or 2 or 3 or 4 or 5. 7. Further comprising first and second clamping diodes (De, Df) connected in anti-parallel to said first and second auxiliary switches (S1, S2). An inverter device according to claim 1, 2 or 3 or 4 or 5. 8. Further comprising the first and second parasitic capacitance discharge preventing diodes (Dg, Dh) connected in series to the first and second auxiliary switches (S1, S2). The inverter device according to claim 1, 2 or 3 or 4 or 5 or 6 or 7. 9. One or a plurality of switch circuits are connected between one end and the other end of a DC power supply, and the switch circuits connect a load with a current in a first direction and a second direction opposite thereto. In a bridge type, half bridge type, or multi-phase bridge type inverter device configured to flow current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). It is composed of a series circuit of first and second main switches (TR1, TR2), and includes the first and second main switches (TR1, T2).
R2) a main conversion circuit whose interconnection middle point is connected to a load, and first and second diodes (D1, D2) antiparallel connected to the first and second main switches (TR1, TR2).
), A series circuit of first and second auxiliary switches (S1, S2) connected between one end and the other end of the power source (1), and the first and second main switches (TR1, TR2) interconnection middle point and the first and second auxiliary switches (S1,
S2) a first reactor (La) connected between the interconnection middle point and one end of the first and second main switches (TR1, T1).
A first capacitor (C1) connected to the interconnection middle point of R2) and one end of which is the first and second main switches (TR1, T1).
A second capacitor (C2) connected to the interconnection middle point of R2) and the other end of the first capacitor (C1) and the first and second auxiliary switches (S1, S2) A third diode (D3) connected between the first and second auxiliary switches (S1, S2) and the other end of the second capacitor (C2). A circuit in which a fourth diode (D4) connected in between, the first capacitor (C1), the first reactor (La), and the second auxiliary switch (S2) are connected in series. A fifth diode (D5) connected in parallel with the first auxiliary switch (S1), the first reactor (La) and the second capacitor (C2) connected in series. Sixth diode (D6) connected in parallel to the current circuit And a second reactor (L3) connected between the first capacitor (C1) and the third diode (D3).
And a third reactor (L4) connected between the second capacitor (C2) and the fourth diode (D4).
A seventh diode (D7) connected in series with the second reactor (L3) between the first capacitor (C1) and the third diode (D3); An eighth diode (D8) connected in series to the third reactor (L4) between the second capacitor (C2) and the fourth diode (D4), and one end of which is connected to the power source ( 3) a third capacitor (C3) connected to one end of 1) and the other end connected between the third diode (D3) and the seventh diode (D7)
) And a fourth capacitor (one end of which is connected to the other end of the power source (1) and the other end of which is connected between the fourth diode (D4) and the eighth diode (D8)). C4
), And generating first and second main control pulses for alternately turning on the first and second main switches (TR1, TR2) at a constant cycle with a dead time, First
The first auxiliary control pulse for controlling the ON of the auxiliary switch (S1) of at least a part of the period from the trailing edge of the second main control pulse to the leading edge of the first main control pulse. A second auxiliary control pulse for ON-controlling the second auxiliary switch (S2) from at least the trailing edge of the first main control pulse to the leading edge of the second main control pulse. And a switch control circuit for generating a predetermined time gap between the first auxiliary control pulse and the first auxiliary control pulse. 10. Further comprising first and second auxiliary resonance capacitors (Ca, Cb) connected in parallel to the first and second main switches (TR1, TR2). An inverter device according to claim 9. 11. Further, one end thereof is connected to the other end of the power source (1), and the other end thereof is connected to the third capacitor (C3).
) And the seventh diode (D7), and a first auxiliary diode (Da) connected between the fourth capacitor (C4) and the eighth diode (D8).
) And a second auxiliary diode (Db) connected to the other end of the power supply (1), the inverter device according to claim 9 or 10. 12. Further, one end thereof is connected to the other end of the power source (1) and the other end thereof is connected to the second reactor (L3).
) And the seventh diode (D7), and a first auxiliary diode (Da) connected between the third reactor (L4) and the eighth diode (D8).
Inverter device according to claim 9 or 10, characterized in that it has a second auxiliary diode (Db) connected between the second auxiliary diode and the other end connected to one end of the power supply (1). 13. Further comprising first and second auxiliary diodes (Da, Db) connected in parallel with said first and second auxiliary switches (S1, S2). An inverter device according to Item 9 or 10. 14. Further comprising first and second clamping diodes (De, Df) connected in anti-parallel to said third and fourth capacitors (C3, C4). An inverter device according to claim 9 or 10. 15. Further, first and second parasitic capacitance discharge preventing diodes (Dg, Dh) are connected in series to the first and second auxiliary switches (S1, S2). Claim 9 or 10 or 11 or 12 or 1
Inverter device according to 3 or 14. 16. Further, said first capacitor (C1)
A second auxiliary charging diode (D21) connected between the other end of the first reactor (L1) and the first auxiliary switch (S1) side terminal of the first reactor (L1), and the second auxiliary charging diode (D21). A second auxiliary charging diode (D22) is connected between the other end of the capacitor (C2) and the second auxiliary switch (S2) side terminal of the second reactor (L2). The inverter device according to any one of claims 1 to 8, further comprising: 17. The first capacitor (C1) further comprising:
The other end of the first and second auxiliary switches (S1, S2)
), A first auxiliary charging diode (D21) connected between the first and second auxiliary switches (S1, S2) and the second auxiliary charging diode (D21). 16. The inverter device according to claim 9, further comprising a second auxiliary charging diode (D22) connected to the other end of the capacitor (C2). 18. The first reactor connected in parallel with the first reactor (L1).
And a series circuit of the switching loss reducing capacitor (Cx1) and the first switching loss reducing diode (Dx1), and a second circuit connected in parallel to the second reactor (L2).
Series circuit of the switching loss reducing capacitor (Cx2) and the second switching loss reducing diode (Dx2), and the first switching loss reducing capacitor (Cx1)
And a third switching loss reducing diode (Dx3) connected in parallel to a circuit in which the second reactor (L2) and the second auxiliary switch (S2) are connected in series, The second switching loss reducing capacitor (Cx2)
And a fourth switching loss reducing diode (Dx4) connected in parallel to a circuit in which the first reactor (L1) and the first auxiliary switch (S1) are connected in series with each other. The inverter device according to claim 1, further comprising: an inverter device. 19. Further, a first reactor connected in parallel with the first reactor (La).
A series circuit of a switching loss reducing capacitor (Cx1) and a first switching loss reducing diode (Dx1), and a second circuit connected in parallel to the first reactor (La).
A series circuit of a switching loss reducing capacitor (Cx2) and a second switching loss reducing diode (Dx2) having a polarity opposite to that of the first switching loss reducing diode (Dx1), and the first switching Loss reduction capacitor (Cx1)
And a third switching loss reducing diode (Dx3) connected in parallel to a circuit in which the first reactor (La) and the second auxiliary switch (S2) are connected in series with each other, The second switching loss reducing capacitor (Cx2)
And a fourth switching loss reducing diode (Dx4) connected in parallel to a circuit in which the first reactor (La) and the first auxiliary switch (S1) are connected in series with each other. The inverter device according to claim 9, wherein the inverter device is provided.