JP3104733B2 - Bridge type inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bridge type, a half bridge type or a polyphase inverter device.

[0002]

2. Description of the Related Art When a switch of a bridge type inverter for converting DC to AC is turned on / off, switching loss occurs. To solve this kind of problem, partial resonance is used to switch the switch to ZCS (Zero Current Switching) or ZVS.
(Zero voltage switching) has been proposed to reduce switching loss, surge voltage and noise. However, there is a demand for an inverter device capable of reliably and easily reducing the loss of not only the main switch but also the partial resonance switch. Further, there is a demand for simplifying the configuration of the partial resonance circuit.

Accordingly, an object of the present invention is to provide a bridge-type inverter device that can meet the above demand.

[0004]

The invention according to claim 1 for achieving the above object will be described with reference to the reference numerals in the drawings showing an embodiment. Alternatively, a plurality of switch circuits are connected, and the switch circuit applies a current in a first direction and a second
In a bridge-type, half-bridge-type, or multi-phase bridge-type inverter device configured to flow a current in the direction of, at least one of the switch circuits is connected between one end and the other end of the DC power supply 1. A main conversion circuit comprising a series circuit of first and second main switches TR1 and TR2, wherein an interconnection midpoint of the first and second main switches TR1 and TR2 is connected to a load; And a first main switch TR1, TR2 connected in anti-parallel to the second main switch TR1, TR2.
And a series circuit of second diodes D1, D2, a first auxiliary switch S1, and a first reactor L1,
The first auxiliary switch S1 is connected to the first reactor L
1 and one end of the power supply 1, the first auxiliary switch S1 and the first reactor L1 are connected to one end of the power supply 1 and the first and second main switches TR1 and T1.
A second auxiliary switch S2 and a second reactor L connected between the second intermediate switch R2 and the interconnection midpoint of R2.
2 in series with the second auxiliary switch S2
Is disposed on the other end side of the power supply 1 with respect to the second reactor L2, and the second reactor L2 and the second auxiliary switch S2 are connected to the first and second main switches TR.
1, a second auxiliary circuit connected between the interconnection middle point of TR2 and the other end of the power supply 1;
A first capacitor C1 connected to the interconnection midpoint between the first and second reactors L1 and L2, and a second capacitor C1 having one end connected to the interconnection midpoint between the first and second reactors L1 and L2. A capacitor C2 and the first capacitor C
A third diode D3 connected between the other end of the first reactor L1 and a terminal on the first auxiliary switch S1 side of the first reactor L1, and the second auxiliary switch S2 of the second reactor L2. A fourth diode D4 connected between the terminal on the side of the second capacitor C2 and the other end of the second capacitor C2, the first capacitor C1, the second reactor L2, and the second auxiliary switch S2 A fifth diode D5 connected in parallel with the circuit connected in series;
The first auxiliary switch S1 and the first reactor L
A sixth diode D6 connected in parallel to a circuit in which the first capacitor C1 and the second capacitor C2 are connected in series.
A third auxiliary switch S3 connected in parallel to the first reactor L1 via the third diode D3; and a fourth auxiliary switch S3 connected to the second reactor L2.
A fourth auxiliary switch S4 connected in parallel via a diode D4 to the first and second main switches TR1.
, TR2 for controlling the ON state of the first auxiliary switch S1 by generating a first and second main control pulses for controlling the ON state of the first auxiliary switch S1. Generating a pulse so as to include at least a part of a period from a trailing edge of the second main control pulse to a leading edge of the first main control pulse, and turning on the second auxiliary switch S2. The second auxiliary control pulse includes at least a part of a period from a trailing edge of the first main control pulse to a leading edge of the second main control pulse, and is predetermined between the second auxiliary control pulse and the first auxiliary control pulse. And a third auxiliary control pulse for turning on the third auxiliary switch S3 is simultaneously turned on by both the first auxiliary switch S1 and the first diode D1. At least one of the periods during which the state And generates a fourth auxiliary control pulse for turning on the fourth auxiliary switch S4 at least during a period in which both the second auxiliary switch S2 and the second diode D2 are simultaneously turned on. The present invention relates to an inverter device including a switch control circuit generated in a part thereof. Further, as shown in claim 2, third and fourth capacitors Ca and Cb can be connected in parallel with the first and second main switches TR1 and TR2. Further, as shown in claim 3, the first and second auxiliary switches S1, S2
2 and the first and second reactors L1 and L2 in series with the first and second backflow blocking diodes Da,
Db can be connected. Further, as described in claim 4, the first and second reactors L1 in claim 1 are provided.
, L2 is replaced by one reactor La for the first and second reactors.
Of the main switches TR1, TR2 of the first and second and second and third auxiliary switches S1, S2. Also, as shown in claim 5,
Third and fourth capacitors Ca and Cb can be added to the circuit of claim 4 in the same manner as in claim 2. Further, as shown in claim 6, first and second backflow preventing diodes Da and Db can be connected in series with the first and second auxiliary switches S1 and S2 in claim 4.

[0005]

According to the invention of each claim, the first aspect is as follows.
And the second auxiliary switches S1 and S2 act as the first switch.
And the ZVS effect of the second main switches TR1 and TR2 can be reliably obtained, and the auxiliary switches S1 and S2 can also be operated by ZCS or ZVS. According to the fifth and sixth aspects of the present invention, the resonance current flows only for a predetermined section by a simple circuit that does not use an auxiliary switch, and the first and second main switches TR1 and TR2 are turned off by ZVS and turned on by ZVS. ZCS operation can be performed. According to the second and fifth aspects of the present invention, energy can be supplied to the resonance circuit by the first and second auxiliary resonance capacitors Ca and Cb, and a stable resonance operation can be obtained. According to the third and sixth aspects of the present invention, the first
In addition, the discharge of the parasitic capacitance of the second auxiliary switches S1 and S2 can be prevented, and the efficiency can be improved. Further, according to the invention of each claim, a power supply for applying a midpoint potential to the switch circuit becomes unnecessary, and the configuration of the power supply is simplified.

[0006]

First Embodiment Next, a bridge type inverter device according to a first embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, this inverter device is configured to convert a DC voltage of a DC power supply 1 into an AC by a bridge type inverter circuit and supply the AC to a load 2. The DC power supply 1 includes a rectifier circuit or a battery, and the load 2 includes, for example, an output transformer 3 connected to load connection terminals 2a and 2b and a load circuit 4 connected thereto.

The inverter circuit comprises a combination of first and second switch circuits 5a and 5b having a half-bridge configuration. The first switch circuit 5a includes first and second main switches TR1 for forming a first arm of a bridge circuit.
, TR2 and first and second diodes D1, D2, in order to achieve ZVS or ZCS, the first,
The second, third and fourth auxiliary switches S1, S2, S3,
S4, the first and second capacitors C1, C2, and the first
And second and third reactors L1, L2 and third, fourth, fifth
And sixth diodes D3, D4, D5, D6 and first and second resistors R1, R2 as capacitor charging means.
And The second switch circuit 5b includes third and fourth main switches TR3 and TR4, and seventh and eighth diodes D7, to form a second arm of the bridge circuit.
In addition to having D8, to achieve ZVS, ZCS,
Fifth, sixth, seventh and eighth auxiliary switches S5, S6,
S7, S8 and third and fourth capacitors C3, C4
And third and fourth reactors L3 and L4, and ninth to twelfth diodes D9 to D12.

[0008] First and second for forming a main conversion circuit
The series circuit of the main switches TR1 and TR2 is connected between one end and the other end of the power supply 1, and the first and second main switches T
The midpoint of the interconnection between R1 and TR2 is connected to a first load connection terminal 2a as an output terminal. The first and second diodes D1, D2 are connected to the first and second main switches TR1.
, TR2 in anti-parallel. A series circuit of the third and fourth main switches TR3 and TR4 is also connected between one end and the other end of the power supply 1, and the third and fourth main switches TR3
, TR4 are connected to a second load connection terminal 2b. Seventh and eighth diodes D7, D8
Are connected in anti-parallel to the third and fourth main switches TR3 and TR4. The first to fourth main switches TR1 to TR1
TR4 is an insulated gate (MOS) field effect transistor having a source connected to a substrate, and the diodes contained therein are first, second, seventh and eighth diodes D1, D2, D7. , D8.

A first circuit consisting of a series circuit of a first auxiliary switch S1 and a first reactor L1 is provided between one end of a power supply 1 and an intermediate point between the first and second main switches TR1 and TR2. Auxiliary circuit is connected. A second auxiliary circuit composed of a series circuit of a second reactor L2 and a second auxiliary switch S2 is provided between the interconnection point of the first and second main switches TR1 and TR2 and the other end of the power supply 1. Is connected. One ends of the first and second capacitors C1 and C2 are respectively connected to an interconnection midpoint of the first and second reactors L1 and L2. The other end of the first capacitor C1 is connected to a first reactor L1 via a third diode D3.
The other end of the second capacitor C2 is connected to a terminal of the second reactor L2 via a fourth diode D4 having a direction opposite to that of the third diode D3. It is connected to the terminal on the second auxiliary switch S2 side. The fifth diode D5 is connected between the power supply 1 side terminal (emitter) of the second auxiliary switch S2 and the other end (upper end) of the first capacitor C1. That is,
The fifth diode D5 is connected in parallel to a series connection circuit of the first capacitor C1, the second reactor L2, and the second auxiliary switch S2. The sixth diode D6 is connected between the other end (lower end) of the second capacitor C2 and the terminal (collector) on the power supply 1 side of the first auxiliary switch S1. That is, the sixth diode D6 is connected in parallel to a series connection circuit of the first auxiliary switch S1, the first reactor L1, and the second capacitor C2. The charging resistors R1 and R2 are connected in parallel to the fifth and sixth diodes D5 and D6. The third auxiliary switch S3 is connected in parallel with the first capacitor C1, that is, the first auxiliary switch S3.
Are connected in parallel to each other via a third diode D3. The fourth auxiliary switch S4 is connected in parallel with the second capacitor C2, that is, in parallel with the second reactor L2 via the fourth diode D4.

The second switch circuit 5b is substantially the same as the first switch circuit 5a, and includes the third and fourth switch circuits 5b.
One end of the power supply 1 and the third and fourth main switches TR3, TR3, in order to achieve the ZVS of the main switches TR3, TR4.
A fifth auxiliary switch S5 between the interconnection middle point of TR4
And a third auxiliary circuit composed of a series circuit of a third reactor L3. Third and fourth main switches T
A fourth auxiliary circuit composed of a series circuit of a fourth reactor L4 and a sixth auxiliary switch S6 is connected between the interconnection point of R3 and TR4 and the other end of the power supply 1. Third
One end of each of the fourth and fourth capacitors C3 and C4 is connected to the third and fourth capacitors C3 and C4.
Are connected to the interconnection midpoint of the reactors L3 and L4. The other end of the third capacitor C3 is connected to a ninth diode D
The other end of the fourth capacitor C4 is connected to the terminal of the third reactor L3 on the side of the fifth auxiliary switch S5 via the ninth diode D9.
Of the fourth reactor L4 via the second diode D10.
Of the auxiliary switch S6. Eleventh
Is connected between the lower terminal (emitter) of the sixth auxiliary switch S6 and the other end (upper end) of the third capacitor C3. That is, the eleventh diode D11
Are the third capacitor C3, the fourth reactor L4 and the sixth
Is connected in parallel to the series connection circuit with the auxiliary switch S6. The twelfth diode D12 is connected between the other end (lower end) of the fourth capacitor C4 and the upper terminal (collector) of the fifth auxiliary switch S5. That is, the twelfth diode D12 is connected to the fifth auxiliary switch S5 and the third
Is connected in parallel to the series connection circuit of the reactor L3 and the fourth capacitor C4. A charging resistor R3,
R4 is connected in parallel with the eleventh and twelfth diodes D11 and D12. The seventh and eighth auxiliary switches S7,
S8 is connected in parallel to the third and fourth capacitors C3 and C4.

In FIG. 1, some of the interconnecting lines are omitted for the sake of illustration, but each of the switches TR1 to TR4
, S1 to S8 are connected to a switch control circuit 6. As shown in FIG. 2, the control circuit 6 includes first, second, third, and fourth main control pulse generation circuits 7, 8, 9, 10, and first to eighth auxiliary control pulse generation circuits. Circuits 11, 12, 13, 14, 15, 16, 1
7 and 18, an oscillator 19, and a phase control circuit 20. The first and second main control pulse generation circuits 7 and 8 are controlled by an oscillator 19 to generate first and second main control pulses shown in FIGS. To the bases of the main switches TR1 and TR2. The third and fourth main control pulse generation circuits 9 and 10 are controlled by the oscillator 19 and the phase control circuit 20 to generate the third and fourth main control pulses shown in FIGS. This is supplied to the bases of the third and fourth main switches TR3 and TR4. The first and second main control pulses and the third and fourth main control pulses are the same except that they have a phase difference therebetween. FIG.
The first and second main control pulses shown in FIGS. 3A and 3B are alternately generated with a time gap Ta therebetween.
The third and fourth main control pulses in (D) also occur alternately with a time gap Ta. This time gap Ta is such that the auxiliary switches S1, S2, S5, S6 are turned on when the capacitors C1, C2, C3, C4 are charged, and almost all of the charges of C1, C2, C3, C4 are turned on by the resonance operation. The time required for release is set. That is, Ta
Is 0 ° to 90 ° of the waveform of the resonance current of C1 L2 or
It is set to the degree section or more.

The first auxiliary control pulse generating circuit 11
3E, and the trailing edge time t of the second main control pulse shown in FIG. 3B as shown in FIG.
T8 after a predetermined time from time t7 after a predetermined time
A second auxiliary control pulse is generated up to a point in time. The first auxiliary control pulse can be generated in synchronization with the trailing edge time t6 of the second main control pulse, or can be generated slightly before this time t6. That is, the first auxiliary control pulse is formed so as to include at least a part of the period Ta from the trailing edge time t6 of the second main control pulse to the leading edge time t8 of the first main control pulse. The second auxiliary control pulse generation circuit 12 is connected to the first main control pulse generation circuit 7 and, as shown in FIG. 3 (F), a time after a predetermined time from the trailing edge time t0 of the first main control pulse. A second auxiliary control pulse is generated from t1 until time t3, which is a predetermined time later. The second auxiliary control pulse can be generated in synchronization with the trailing edge time t0 of the first main control pulse or can be generated slightly before this time t0. That is, the second auxiliary control pulse is formed so as to include at least a part of the period Ta from the trailing edge time t0 of the first main control pulse to the leading edge time t2 of the second main control pulse. The third auxiliary control pulse generation circuit 13 includes a second main control pulse generation circuit 8
And the width from the time t8 (the leading edge of the first main control pulse) after the trailing edge t6 of the second main control pulse in FIG. 3B to the time t9 after a predetermined time. And generating a third auxiliary control pulse having This third auxiliary control pulse comprises a first auxiliary switch S1 and a first diode D
1 are formed so as to include at least a part of a period during which both of them are simultaneously turned on. Preferably, the leading edge of the third auxiliary control pulse is later than the leading edge of the first auxiliary control pulse by a time Tb corresponding to 90 degrees of the resonance current of the C1 L2 resonance circuit. Fourth auxiliary control pulse generation circuit 14
Is connected to the first main control pulse generation circuit 7, and FIG.
A fourth auxiliary control pulse having a width from the time point t2 after the trailing edge time point t0 of the first main control pulse in FIG. The fourth auxiliary control pulse is supplied to the second auxiliary switch S2 and the second diode D2.
Are formed so as to include at least a part of a period during which both are turned on at the same time. It is desirable that the leading edge of the fourth auxiliary control pulse be later than the leading edge of the second auxiliary control pulse by a time Tb corresponding to 90 degrees of the resonance current of the C2 L1 resonance circuit. The fifth for the second switch circuit 5b
To the eighth auxiliary control pulse generation circuits 15 to 18,
It is formed to generate the fifth to eighth auxiliary control pulses of FIGS. 3 (I) to (L) by a method similar to that of the fourth auxiliary control pulse generation circuits 11 to 14. Note that the time points at which the first to eighth auxiliary control pulses are generated are determined using a counter.

[0013]

[Operation] The basic operation of the inverter circuit shown in FIG. 1 is the same as that of a known inverter. That is, while the main switches TR1 and TR4 in FIGS. 1 and 4 are simultaneously turned on, a current in the first direction is generated by a circuit including the power supply 1, the first main switch TR1, the load 2, and the fourth main switch TR4. Flow to load 2
During the period when the third main switches TR2 and TR3 are simultaneously turned on, a current in the second direction flows through the load 2 by a circuit including the power supply 1, the third main switch TR3, the load 2, and the second main switch TR2. .

Next, the first to fourth main switches TR1 to TR
The operation of R4 during the turn-on and turn-off periods will be described. However, the operation during the turn-off of the first main switch TR1 and the turn-on of the second main switch TR2 shown at t0 to t2 in FIG. 3 and its vicinity, and the operation of the second main switch TR2 shown at t6 to t8 and its vicinity are shown. During the turn-off period of the first main switch TR1 and during the turn-off period of the third main switch TR3 and the turn-off period of the fourth main switch TR4, and during the turn-off period of the fourth main switch TR4. Operation, turning off of the fourth main switch TR4 and the third main switch TR4
Since the operation during the turn-off period of FIG. 3 is substantially the same, the operation during t0 to t2 in FIG. 3 and the vicinity thereof will be described in detail with reference to FIG. 4, and the description of the operation during other periods will be omitted. .

[0015]

[Capacitor charging operation] In this embodiment, for example, it is necessary to previously charge the first and fourth capacitors C1 and C2 in the directions shown in FIG. To perform this charging, the first and fourth main switches TR1 and TR4 are turned on. As a result, a charging current flows through the circuit including the first main switch TR1, the first capacitor C1, and the first resistor R1, and the first capacitor C1 is charged to the power supply voltage V. Further, a fourth resistor R4, a fourth capacitor C4, and a fourth main switch T
A current also flows through the circuit of R4, and the fourth capacitor C4 is charged. Of course, conversely, the second and third capacitors C2 and C3 can be pre-charged. After the inverter operation by the first to fourth main switches TR1 to TR4 is started, the loss due to the resonance is reduced by the main switch TR.
Replenished via 1 to TR4.

[0016]

FIG. 4 shows the state of each section of FIG. 1 in the section between t0 and t5 in FIG. 3 and the vicinity thereof when the load circuit 4 is unloaded and the load 2 is a delayed load of only a transformer. When the first main switch TR1 is turned off at time t0 when the first capacitor C1 is almost charged to the power supply voltage V, and the second auxiliary switch S2 is turned on at time t1 slightly later than this, The energy of the first capacitor C1 is released by a resonance circuit including the first capacitor C1, the second reactor L2, the second auxiliary switch S2, and the fifth diode D5, and the voltage Vc1 of the first capacitor C1 is As shown in FIG. 4 (E), the waveform decreases in the waveform of the sine wave in the 90 to 180 degree section. At this time, since the fifth diode D5 is on, the second main switch T5 is turned on.
The potential Vc1 of the first capacitor C1 is applied to both ends of R2, and as shown in FIG.
Thus, the voltage Vtr2 of the second main switch TR2 decreases toward zero. Also, the voltage Vtr1 of the first main switch TR1
Is the voltage Vtr2 of the second main switch TR2 from the power supply voltage V.
, And slowly rises as shown in FIG. A first capacitor C1, a second reactor L2, a second auxiliary switch S2, and a fifth diode D5
As shown in FIG. 4 (G), the resonance current I2 of the closed circuit flows with a waveform of a sine wave of 0 to 90 degrees in the interval of t1 to t2. At time t2, the first capacitor C1
When the voltage Vc1 becomes zero, the reverse bias of the second diode D2 is released, and the current I2 due to the release of the energy stored in the second reactor L2 is diverted to the second diode D2, and the second reactor L2 and the second 2 auxiliary switches S
2 flows as a circulating current through a closed circuit of the second diode D2. Since the fourth auxiliary switch S4 is turned on at the time t2 when the reactor current I2 reaches the peak, a closed circuit of the second reactor L2, the fourth diode D4, and the fourth auxiliary switch S4 is formed. A circulating current also flows. During the period after t2, the voltage of the first capacitor C1 is zero volt, and the voltage Vtr2 of the second main switch TR2 is also zero volt. Therefore, when the second main switch TR2 is turned on after t2, ZVS is achieved. At time t0, the first main switch TR1 is set at ZVS.
Turned off at Even if the second auxiliary switch S2 is turned off at time t3 after the time t2 when the second main switch TR2 is turned on, the current I2 continues to flow as shown in FIG. 4G because the fourth auxiliary switch S4 is on. When the fourth auxiliary switch S4 is turned off at time t4, the second reactor L2
And a fourth diode D4 and a second capacitor C2 cause resonance. A resonance current having a sine wave in a 90-180 degree section flows as shown in FIG. The voltage Vc2 increases sinusoidally as shown in FIG. 4F, and reaches the power supply voltage V at t5. The fourth diode D4 is cut off at t5, blocks the negative resonance current, the voltage Vc2 of the second capacitor C2 is held at V, and the operation after t6 in FIG. 3 is completed. . As a result, when the second auxiliary switch S2 is turned off, Z
VS is achieved. The ZCS operation is performed when the second auxiliary switch S2 is turned on. Therefore, the switching loss of both the main switch TR1 and the auxiliary switch S2 is reduced.

When the second main switch TR2 is turned off, the first auxiliary switch S1 turns on, and the second capacitor C2, the sixth diode D6, the first auxiliary switch S1, and the first reactor L1 are connected. A resonance circuit is formed, and a current corresponding to a section between t1 and t2 in FIG. 4 flows in this circuit. A current corresponding to a section between t2 and t3 in FIG. 4 is supplied to the first reactor L1, the first diode D1, And a first reactor L1, a third auxiliary switch S3, and a third diode D3.
And a current corresponding to the section from t3 to t4 flows through a closed circuit of L1, S3 and D3.
The current corresponding to the period between the first reactor L1 and the first
Flows through the closed circuit of the capacitor C1 and the third diode D3. Therefore, the same operation and effect as when the first main switch TR1 is turned off can be obtained when the second main switch TR2 is turned off. The same operation occurs in the second switch circuit 5b, and the same operation and effect can be obtained.

In FIG. 4, the load is described as no load.
Can be regarded as a resistance, a current corresponding to the voltage applied to the load 2 is applied to the first to fourth main switches TR1 to TR4.
Flow through. At this time, even if the storage current of the main switches TR1 to TR4 flows, the power loss is small because the voltages of the first to fourth main switches TR1 to TR4 do not rise suddenly at the time of turn-off.

This embodiment has the following effects. (1) Soft switching (ZVS) of the first to fourth main switches TR1 to TR4 and the first to eighth auxiliary switches
Or ZCS) becomes possible, and a reduction in loss, a reduction in surge voltage, and a reduction in noise are achieved. (2) Since substantially no snubber circuit loss occurs,
Efficiency is improved. (3) PW of constant frequency of main switches TR1 to TR4
M control becomes possible, and the effect of improving efficiency by increasing the frequency of the inverter having the output transformer can be maintained. Further, the control circuit 6 can be simply configured. (4) A power source having a midpoint potential is unnecessary, and the configuration of the power source is simplified. (5) Since there is a circulating current period between t2 and t4 in FIG. 4, the degree of freedom at the time of turn-on is increased. (6) In the period from t2 to t3, for example, two circulating current circuits passing through the second diode D2 and two circulating current circuits passing through the fourth auxiliary switch S4 are formed. Is smaller than in the case of only the circulating current circuit passing through the second diode D2.

[0020]

Second Embodiment Next, a bridge type inverter device according to a second embodiment of the present invention will be described with reference to FIG.
However, in FIG. 5 and FIG. 6, FIG. 7, FIG. 9, FIG. 10, and FIG. Also, the second switch circuit 5b
Has the same configuration as the first switch circuit 5a, and is therefore shown by blocks.

The first switch circuit 5a of the inverter device of FIG. 5 has the same configuration as that of FIG. 1 except that first and second auxiliary resonance capacitors Ca and Cb are added to the switch circuit 5a of FIG. . The first and second auxiliary resonance capacitors Ca, Cb are connected to the first and second main switches TR1, TR1, respectively.
2 is connected in parallel.

The first and second main switches TR1 of FIG.
TR2 and the first to fourth auxiliary switches S1 to S4 are shown in FIG.
Is driven in the same manner as. Therefore, the basic operation of the circuit of FIG. 5 is the same as that of the circuit of FIG. In FIG. 5, the first auxiliary resonance capacitor Ca is connected in parallel with the first reactor L1 together with the second capacitor C2, and the second auxiliary resonance capacitor Cb is connected to the first reactor L2 with the first auxiliary resonance capacitor Cb.
Is connected in parallel with the capacitor C1. Therefore, for example, in the period from t1 to t2 in FIG. 4, two L2 C1 resonance circuits and L2 Cb resonance circuits are formed.
Since the first and second auxiliary resonance capacitors Ca and Cb are directly connected to the power supply 1, they are reliably charged to the power supply voltage V, and a desired resonance operation can be reliably obtained.
That is, in the circuit of FIG. 1, the first and second capacitors C1,
In some cases, C2 cannot be sufficiently charged to the power supply voltage V. Also, a surge voltage may be generated when the main switches TR1 and TR2 are turned on and off due to the inductance of the wiring. However, as shown in FIG.
The above problem is solved by adding the auxiliary resonance capacitors Ca and Cb. Therefore, the charging resistors R1 and R2 can be disconnected after the inverter is started.

[0023]

Third Embodiment In the inverter device shown in FIG. 6, first and second reverse current blocking diodes Da and Db are added to the circuit of FIG.
The configuration is the same as that of FIG. The first and second backflow blocking diodes Da and Db are connected in series to the first and second auxiliary switches S1 and S2 and the first and second reactors L1 and L2.

There is a parasitic capacitance between the collector and the emitter of the first and second auxiliary switches S1 and S2, which is the first capacitance.
When the second auxiliary switches S1 and S2 are turned off, the battery is charged to the power supply voltage. In the circuit shown in FIG. 1, when the first and second main switches TR1 and TR2 are turned on, the energy of the parasitic capacitance causes the first and second main switches TR1 and TR2 and the first and second reactors L1 and L2 to turn on. Discharge through. However, by providing the first and second reverse current blocking diodes Da and Db as shown in FIG. 6, this discharge is prevented, the power loss is reduced, and the efficiency is increased.

[0025]

Fourth Embodiment Next, an inverter device according to a fourth embodiment will be described with reference to FIGS. In the inverter device of FIG. 7, one reactor is used instead of the two reactors L1 and L2 of FIG.
It has two reactors La. Reactor La is connected between the interconnection point of first and second main switches TR1 and TR2 and the interconnection point of first and second auxiliary switches S1 and S2. The middle point of the interconnection between the first and second capacitors C1 and C2 is connected to the middle point of the interconnection between the first and second main switches TR1 and TR2. First
And the second auxiliary switches S1 and S2 are connected to each other in series without a reactor. The third and fourth diodes D3, D4 are connected to the first and second capacitors C1,
It is connected between the other end of C2 and the interconnection point of the first and second auxiliary switches S1, S2. In FIG. 7, the rest is configured the same as in FIG.

The operation of the inverter device of FIG. 7 is basically the same as that of FIG. 7 differs from FIG. 1 in that a resonance current flows through a common reactor La both when the first capacitor C1 is discharged and when the second capacitor C2 is discharged. That is, the first and second main switches TR1, TR2 and the first to fourth auxiliary switches S1 to S4 are controlled according to FIG.
In the section, the operation is performed as shown in FIG. FIG.
(A) and (B), when the first main switch TR1 is turned off and the second auxiliary switch S2 is turned on at time t1, the energy of the first capacitor C1 becomes the first energy. Of the capacitor C1, the reactor La and the second
In addition, the voltage is released by the resonance circuit including the auxiliary switch S2 and the fifth diode D5, and the potential V of the first capacitor C1 is
c1 decreases in the waveform of the sine wave in the 90 to 180 degree section as shown in FIG. At this time, since the fifth diode D5 is on, both ends of the second main switch TR2 are connected to the first diode D5.
The voltage Vc1 of the capacitor C1 is applied,
As shown in FIG. 8 (I), the voltage Vtr2 of the second main switch TR2 decreases toward zero between t1 and t2. The voltage Vtr1 of the first main switch TR1 has a value obtained by subtracting the voltage Vtr2 of the second main switch TR2 from the power supply voltage V, and slowly rises as shown in FIG. The resonance current Ia of the closed circuit including the first capacitor C1, the reactor La, the second auxiliary switch S2, and the fifth diode D5 has a sine wave of 0 to 0 in the interval t1 to t2 as shown in FIG. It flows with a 90-degree section waveform. t2
When the voltage Vc1 of the first capacitor C1 becomes zero at that time, the reverse bias of the second diode D2 is released, and the current Ia due to the release of the energy stored in the reactor La is commutated to the second diode D2, and the reactor La and the Second
Flows as a circulating current through the first closed circuit of the auxiliary switch S2 and the second diode D2. With this reactor L
a, a fourth diode D4 and a fourth auxiliary switch S4 form a second closed circuit, through which a circulating current flows.
After the second auxiliary switch S2 is turned off, the current Ia continues to flow in the second closed circuit in the section from t3 to t4 in FIG. t4
At this point, when the second auxiliary switch S2 is turned off, the reactor La, the fourth diode D4, and the second capacitor C
2, resonance occurs, and a resonance current having a sine wave in a 90-180 degree section flows as shown in FIG.
The voltage Vc2 of the capacitor C2 increases sinusoidally as shown in FIG. 8 (F), and reaches the power supply voltage V at t5. The fourth diode D4 is cut off at time t5, blocking the negative-direction resonance current, and the voltage V2 across the second capacitor C2.
Hold c2 at V. Thus, preparation for the next operation is completed.

When the second main switch TR2 is turned off, the first auxiliary switch S1 is turned on, and a resonance circuit of the second capacitor C2, the sixth diode D6, the first auxiliary switch S1, and the reactor La is formed. In this circuit, a current corresponding to the interval t1 to t2 in FIG. 8 flows, and a current Ia corresponding to the interval t2 to t3 in FIG. 8 is generated by the reactor La, the first diode D1, and the first auxiliary switch S1 A first closed circuit comprising: a reactor La and a third closed circuit;
Flows in a second closed circuit including the auxiliary switch S3 and the third diode D3. Further, the current Ia corresponding to the section from t3 to t4 in FIG. 8 flows in the above-mentioned second closed circuit. The current corresponding to the section between t4 and t5 in FIG.
Flows through the closed circuit of the capacitor C1 and the third diode D3.

FIG. 8 shows the reactor current I2 of FIG.
7 is the same as that of FIG. 4 except that Ia is changed to Ia, so that the inverter device of FIG. 7 has the same operation and effect as the inverter device of FIG.

[0029]

Fifth Embodiment The inverter device shown in FIG. 9 is the same as that shown in FIG. 7 except that first and second auxiliary resonance capacitors Ca and Cb are added to the inverter device shown in FIG. Things. Also in FIG. 9, the second and first auxiliary resonance capacitors Cb and Ca are connected in parallel to the first and second capacitors C1 and C2, and the same operation and effect as in FIG. 5 can be obtained.

[0030]

Sixth Embodiment The inverter device shown in FIG. 10 is different from the inverter device shown in FIG. 7 in that first and second reverse current blocking diodes Da are provided.
, Db in the same manner as in FIG. Therefore, the same operation and effect as in FIG. 6 can be obtained by the inverter device in FIG.

[0031]

Seventh Embodiment Next, a description will be given of a half-bridge type inverter device according to a seventh embodiment of FIG. The inverter device shown in FIG. 11 includes first and second conversion capacitors C1 instead of the second switch circuit 5b of the inverter device shown in FIG.
1, C12 is provided. A series circuit of capacitors C11 and C12 having a larger capacity than C1 and C2 is connected between one end and the other end of the power supply 1, and a load 2 is connected to this interconnection point. Switch circuit 5a of this half bridge device
Are the same as those in FIG. 1, so that the same operation and effect as in FIG. 1 can be obtained. Note that a half-bridge circuit similar to that of FIG. 11 can be configured using the switch circuit 5a of FIGS. 5 to 7 and FIGS.

[0032]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) A three-phase or multi-phase inverter device can be configured by connecting three or many switch circuits 5a in FIGS. 1, 5 to 7, and 9 to 10 in a three-phase or multi-phase connection. (2) Main switches TR1 to TR4, auxiliary switch S1
S8 can be a semiconductor switch such as a field effect transistor. (3) The charging resistors R1 to R4 can be omitted by initial charging the capacitors C1 and C4 with independent charging devices. Further, the charging current can be selectively passed by replacing the charging resistors R1 to R4 with switches.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an inverter device according to a first embodiment.

FIG. 2 is a block diagram showing a control circuit of FIG. 1;

FIG. 3 is a waveform chart of each part in FIG. 2;

FIG. 4 is a waveform chart of each part in FIG. 1;

FIG. 5 is a circuit diagram of an inverter device according to a second embodiment.

FIG. 6 is a circuit diagram of an inverter device according to a third embodiment.

FIG. 7 is a circuit diagram of an inverter device according to a third embodiment.

8 is a waveform chart of each part in FIG. 7;

FIG. 9 is a circuit diagram of an inverter device according to a fourth embodiment.

FIG. 10 is a waveform chart of each part in FIG. 9;

FIG. 11 is a circuit diagram of an inverter device according to a fifth embodiment.

[Explanation of symbols]

 TR1 to TR4 Main switch S1 to S8 Auxiliary switch

Claims (6)

(57) [Claims] 1. One or more switch circuits are connected between one end and the other end of a DC power supply, and the switch circuits supply a load with a current in a first direction and a current in a second direction opposite thereto. In a bridge-type, half-bridge-type, or multi-phase bridge-type inverter device configured to flow a current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). It comprises a series circuit of first and second main switches (TR1, TR2), and the first and second main switches (TR1, T2)
R2), a main conversion circuit having an interconnection midpoint connected to the load, and first and second diodes (D1, D2) anti-parallel connected to the first and second main switches (TR1, TR2).
), A first auxiliary switch (S1) and a first reactor (L1
), Wherein the first auxiliary switch (S1) is disposed closer to one end of the power supply (1) than the first reactor (L1), and the first auxiliary switch (S1) is connected to the first auxiliary switch (S1). And the first reactor (L1) are connected to one end of the power supply (1) and the first and second main switches (TR1).
, TR2), a second auxiliary switch (S2) and a second reactor (L2).
), Wherein the second auxiliary switch (S2) is disposed on the other end side of the power supply (1) with respect to the second reactor (L2), and the second reactor (L2) And the second auxiliary switch (S2) is connected between the interconnection point of the first and second main switches (TR1, TR2) and the other end of the power supply (1). And one end of which is connected to the first and second reactors (L1, L2).
) Is connected to the first capacitor (C1
), And one end of which is connected to the first and second reactors (L1, L2).
) Is connected to a second capacitor (C2
) And a third diode (D3) connected between the other end of the first capacitor (C1) and a terminal of the first reactor (L1) on the side of the first auxiliary switch (S1). And a fourth diode (D4) connected between a terminal of the second reactor (L2) on the side of the second auxiliary switch (S2) and the other end of the second capacitor (C2). A fifth diode connected in parallel to a circuit in which the first capacitor (C1), the second reactor (L2), and the second auxiliary switch (S2) are connected in series; D5), a sixth auxiliary switch (S1), a sixth reactor (L1), and a sixth capacitor (C2) connected in parallel to a circuit in which the second capacitor (C2) is connected in series. Diode (D6) and the first reactor (L1) On the other hand, a third auxiliary switch (S3) connected in parallel via the third diode (D3), and the second reactor (L2) via the fourth diode (D4). A fourth auxiliary switch (S4) connected in parallel; and first and second main control pulses for controlling the first and second main switches (TR1, TR2) to be turned on for a predetermined time. A first auxiliary control pulse generated with a gap (Ta) for turning on the first auxiliary switch (S1) is supplied at least from the trailing edge of the second main control pulse to the first main control pulse. A second auxiliary control pulse generated to include a part of the period up to the leading edge of the control pulse and for turning on the second auxiliary switch (S2) is provided at least after the first main control pulse. From the edge to the leading edge of the second main control pulse And a third auxiliary control pulse for generating a predetermined time gap between the first auxiliary control pulse and the third auxiliary switch (S3) for turning on the third auxiliary switch (S3). Occurs during at least a part of a period during which both the first auxiliary switch (S1) and the first diode (D1) are simultaneously turned on, and controls the fourth auxiliary switch (S4) to be turned on. And a switch control circuit for generating a fourth auxiliary control pulse for at least part of a period during which both the second auxiliary switch (S2) and the second diode (D2) are simultaneously turned on. An inverter device characterized in that: 2. The method according to claim 1, wherein first and second auxiliary resonance capacitors (Ca, Cb) are connected in parallel with said first and second main switches (TR1, TR2). An inverter device according to item 1. 3. The first auxiliary switch (S1).
A first reverse current blocking diode (Da) connected in series with the first reactor (L1), and a second reverse switch (S2) and the second reactor (L2) with respect to the second auxiliary switch (S2). 3. The inverter device according to claim 1, further comprising a second reverse current blocking diode (Db) connected in series. 4. One or more switch circuits are connected between one end and the other end of the DC power supply, and the switch circuits apply a current in a first direction and a current in a second direction opposite to the load to a load. In a bridge-type, half-bridge-type, or multi-phase bridge-type inverter device configured to flow a current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). It comprises a series circuit of first and second main switches (TR1, TR2), and the first and second main switches (TR1, T2)
R2), a main conversion circuit having an interconnection midpoint connected to the load, and first and second diodes (D1, D2) anti-parallel connected to the first and second main switches (TR1, TR2).
), A series circuit of first and second auxiliary switches (S1, S2) connected between one end and the other end of the power supply (1), and the first and second main switches (TR1, TR2) and the first and second auxiliary switches (S1,.
A reactor (La) connected between the interconnection middle point of S2) and one end of the reactor (La) connected to the first and second main switches (TR1, T1).
R2) and a first capacitor (C1) connected to the interconnection midpoint of the first and second main switches (TR1, T1).
R2), a second capacitor (C2) connected to the interconnection midpoint of the first capacitor (C1) and the other end of the first capacitor (C1) and the first and second auxiliary switches (S1, S2). A third diode (D3) connected between the first and second auxiliary switches (S1, S2) and the other end of the second capacitor (C2). A fourth diode (D4) connected between the first capacitor (C1) and the reactor (La);
) And the second auxiliary switch (S2) are connected in parallel to a circuit connected in series with the fifth diode (D5); the first auxiliary switch (S1) and the reactor ( L
a) and a second diode (D6) connected in parallel to a circuit in which the second capacitor (C2) is connected in series; and a third diode (D3) for the reactor (La). A third auxiliary switch (S3) connected in parallel via (D3); and a fourth auxiliary switch connected in parallel via the fourth diode (D4) to the reactor (La). (S4) and first and second main control pulses for turning on the first and second main switches (TR1, TR2) are generated with a predetermined time interval (Ta) therebetween. A first auxiliary control pulse for turning on the first auxiliary switch (S1) is provided at least during a period from a trailing edge of the second main control pulse to a leading edge of the first main control pulse. And the second auxiliary switch The second auxiliary control pulse for turning on the switch (S2) includes at least a part of a period from a trailing edge of the first main control pulse to a leading edge of the second main control pulse, and A third auxiliary control pulse, which is generated so as to have a predetermined time interval between the first auxiliary switch (S1) and the first auxiliary switch (S1), is turned on by the first auxiliary switch (S1). ) And the first diode (D1) are generated at least in part during a period in which they are simultaneously turned on, and a fourth auxiliary control pulse for controlling the fourth auxiliary switch (S4) to be on is generated. An inverter device comprising a switch control circuit for generating at least a part of a period during which both the second auxiliary switch (S2) and the second diode (D2) are simultaneously turned on. . 5. The method according to claim 1, wherein first and second auxiliary resonance capacitors (Ca, Cb) are connected in parallel to said first and second main switches (TR1, TR2). An inverter device according to item 4. 6. A first backflow blocking diode (Da) connected in series with the first auxiliary switch.
6. The inverter device according to claim 4, further comprising a second backflow prevention diode (Db) connected in series with said second auxiliary switch (S2).