JPH0746849A - Inverter - Google Patents

Abstract

PURPOSE:To make uniform the loss of switching elements by employing semiconductor devices having low forward voltage drop for the second and third switching elements and semiconductor elements having high switching rate for the first and fourth switching elements. CONSTITUTION:When a series multiplex inverter 1 is subjected to V/f control, the interval where the output voltage goes zero in proportion to the output frequency decreases thus increasing the average current of outside switching elements in proportion to the output frequency although the average current of inside switching elements is substantially constant. In this regard, switching elements having low forward voltage drop are employed for the inside switching elements S2, S3 constituting each phase whereas switching elements having short turn OFF time are employed for the outside switching elements S1, S4. Consequently, the loss due to forward voltage drop of the inside switching element decreases more than the increase of loss due to forward voltage drop of the outside switching element. This constitution prevents increase of loss even it the switching frequency is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial multiple inverter device, and more particularly to an inverter device which prevents deviation of loss due to current in a switching element and operates at a high switching frequency.

[0002]

2. Description of the Related Art Conventionally, a PWM inverter device has been used to control the rotation speed of an AC motor.
Since the output voltage of the M inverter has two levels, positive and negative, there is a problem that the harmonic component contained in the output current is large. Therefore, in the past, as a method for reducing the harmonic component contained in the output current of the PWM inverter, Japanese Patent Laid-Open No.
No. 74088, the PWM inverter is multiplexed in series, and the output voltage of the inverter is positive, 0, or negative.
There has been proposed a method of reducing the harmonic components by setting the level. Further, there is a problem that one switching element is damaged due to overvoltage due to the difference in turn-off characteristics of the switching elements connected in series. As a method for preventing this, there is a method described in Japanese Patent Publication No. 51-47848. As described above, a method has been proposed in which the pulses of the switching elements connected in series have a certain phase relationship, or the switching element with a slow turn-off is placed inside and the switching element with a fast turn-off is placed outside. There is.

[0003]

However, in the above-mentioned prior art, loss imbalance occurs due to a difference in average current of switching elements connected in series, or the switching elements are operated at a high switching frequency. Due to the accompanying increase in loss, excessive loss of the switching element may occur and damage may occur, but no consideration is given to the imbalance of the loss and the increase in loss. An object of the present invention is to equalize the loss of switching elements connected in series, prevent an increase in loss due to operating the switching elements at a high switching frequency, and output an AC output with few harmonics. It is to provide an inverter device.

[0004]

A direct current power supply, a direct current circuit having an output terminal of the direct current power supply and a neutral point output terminal, and both terminals of first to fourth switching elements connected in series are provided in the direct current circuit. Connected to both terminals of the second and third terminals
Connecting the interconnection point of the switching elements to the inverter output terminal, and connecting the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements to the neutral point of the DC circuit. It is connected to the
In an inverter device in which the third and third switching elements and the second and fourth switching elements are on / off controlled by a mutually conjugate relationship, a semiconductor having a small forward voltage drop is provided in the second and third switching elements. A device is used, and a semiconductor device with fast switching is used for the first and fourth switching elements. Also, based on the characteristics of the turn-off time and forward voltage drop of the switching element,
Elements having a short turn-off time are used for the first and fourth switching elements, and elements having a smaller forward voltage drop are used for the second and third switching elements than the switching elements used for the first and fourth. Select and combine.

[0005]

The serial multiple inverter selects only the mode in which the positive output voltage is positive and the mode in which it is zero, and the negative mode when the output voltage is negative. Select mode only. As a result, the current sharing of the switching elements of the serial multiple inverter changes according to the electric and regenerative operation modes and the magnitude of the output voltage. Particularly, in the electric operation mode, the output current constantly flows through the inner switching elements related to the mode in which the output voltage is set to 0, so that the loss due to the forward voltage drop increases. The output current increases in the outer switching element according to the magnitude of the output voltage, but the magnitude thereof is less than half that in the inner side, and the switching loss is large. Therefore, a power semiconductor device with a small forward voltage drop is used for the inner switching element,
A power semiconductor device with fast switching is used on the outer side, and as a result, the loss due to the forward voltage drop of the inner switching element is reduced, and the switching loss of the outer switching element is reduced, so that the inner side and the outer side are reduced. The loss of the switching elements can be equalized. This makes it possible to equalize the losses of the switching elements connected in series, prevent an increase in loss due to operating the switching elements at a high switching frequency, and output an AC output with few harmonics. Can be provided.

[0006]

FIG. 1 shows an embodiment of the present invention. In FIG. 1a, the serial multiplex inverter 1 has two DC power sources 2, 3
The mutual connection point of is used as a neutral point of the power supply, and the DC voltage is converted into positive, 0, and negative three-level AC voltage. The switching circuit is a gate turn-off thyristor (hereinafter referred to as GT
It is abbreviated as O. ) S1U to S4W and each output terminal U,
Clamp diodes CD1U to CD2W and flywheel diodes D1U to D4W for clamping V and W to the neutral point potential are formed. This serial multiplexer
The switching elements S1U to S4W forming the switch 1 are 3
It is turned on / off by an on / off pulse signal made by comparing the phase AC voltage commands vu *, vv *, vw * (not shown) with a carrier signal, but in normal operation, S1 and S3
Each of S2 and S4 operates as a set of inverters so as to be turned on and off by a conjugate relationship. As a result, the relationship between the on-condition and the voltage at the output end is as shown in (Table 1) of FIG. 1b. For example, looking at the U phase, S1U
When S2U is turned on, the output terminal U becomes + E potential. On the contrary, when S3U and S4U are turned on, the output terminal U has a potential of -E. When S2U and S3U are turned on, the output terminal U is S2U and S3U and clamp diode CD1U,
It is connected to the connection point of the smoothing capacitors 12 and 13 via CD2U and has a zero potential. As a result of this operation, output terminal U
Potential changes between + E, 0, and -E, and the harmonic component of the inverter output is reduced. The operation of this inverter is the same as that of the conventional serial multiplex inverter.

The operation of the present invention will be described below. Figure 2
The phase relationship between the output voltage command v * for one phase and the output current i is shown, and each of the polarities can be divided into four sections a to d. In the sections A and B, the switching element S2 is constantly turned on, and the switching elements S1 and S3 are alternately turned on. In the sections C and D, the switching element S3 is constantly turned on, and the switching elements S2 and S4 are alternately turned on. In Figure 3a,
The element that performs the switching operation for each section is indicated by a circle, and the output current at that time is indicated by a dotted line. For example, when the output voltage is + E, the output current in the section A flows to the flywheel diode D2 → D1 → DC power supply 2, and when the output voltage is 0, the switching element S3 → the clamp diode CD2.
→ It flows to the neutral point. Further, the output current in the section B flows to the switching element S1 → S2 → load when the output voltage is + E, and the clamp diode CD1 → when the output voltage is 0.
The switching element S2 flows to the load. As a result, the output current flows through the path shown in (Table 2) of FIG. 3b depending on the polarities of the output voltage and the output current. From (Table 2), a larger amount of output current flows through the inner switching elements S2, S3 (see the broken line) than in the outer switching elements S1, S4 during the period in which the output voltage is zero. Further, the currents of the switching elements S2 and S3 on the inner side are not affected by the switching operation, and a continuous current flows. On the other hand, the output current of the outer switching element is intermittent during the period when the output voltage is 0, and is affected by the switching operation. For example, in the case where the V / f control for controlling the output voltage in proportion to the output frequency is applied to the serial multiple inverter 1, the inverter is
Since the period during which the output voltage is 0 decreases in proportion to the output frequency of the inverter, the average current of the switching element on the inner side is almost constant, while the average current of the switching element on the outer side changes to the output frequency of the inverter. It increases proportionally and becomes as shown in FIG. In FIG. 4, the horizontal axis represents the inverter output frequency and the vertical axis represents the average current, and shows the average current characteristics of the inner switching element and the outer switching element in the electric operation mode.

As a result, as shown in FIG. 5A, the loss of the inner switching element is large due to the forward voltage drop, and the loss of the outer switching element is occupied by the switching loss in the inner switching element. The loss is increased when the switching frequency is increased. In FIG. 5A, the horizontal axis represents the inverter output frequency, the vertical axis represents the loss, the dashed line represents the loss due to forward voltage drop, the diagonal line represents the switching loss, and the solid line represents the total loss obtained by integrating these. Therefore, in this embodiment,
For the inner switching elements S2 and S3 that form each phase,
A switching element having a smaller forward voltage drop than the outer switching elements S1 and S4 is used, and the turn-off time of the outer switching elements S1 and S4 forming each phase is greater than that of the inner switching elements S2 and S3. Uses a fast switching element. As a result, as shown in FIG. 5B, the loss due to the forward voltage drop in the loss of the inner switching element is reduced. Further, the loss of the outer switching element is reduced as a whole, though the switching loss is reduced but the loss due to the forward voltage drop is increased. Therefore, in this embodiment, it is possible to prevent an increase in loss even if the switching frequency of the switching element is increased. Furthermore, the losses of the inner and outer switching elements can be equalized (that is, the difference between the losses can be reduced as is clear from FIG. 5B), and the cooling structure can be manufactured symmetrically.

FIG. 6 shows a second embodiment of the present invention. Figure 1
The difference from the first embodiment of a is that the switching elements S1U to S4W constituting the serial multiplex inverter 1 are IGBTs.
(Insulated Gate Bipolar Transistor) and GTO. FIG. 6 shows a switching element for one phase which constitutes the serial multiplex inverter 1.
The switching elements S1 and S4 are IGBTs, and the switching elements S2 and S3 are GTOs. IGBT and GT
FIG. 7 shows the relationship between the forward voltage drop of O and the switching loss. The IGBT has a small switching loss, but has a high forward voltage drop, and the GTO has a small forward voltage drop, but has a large switching loss. In this embodiment, these IGBTs are
From the characteristics of T and GTO, a combination that matches the current sharing and switching operation of the serial multiplex inverter 1 is adopted, and when the same switching element is used, selection of necessary characteristics can be omitted. it can.

FIG. 8 shows a third embodiment of the present invention. Figure 1
The difference from the first embodiment of a is that the switching elements S1U to S4W that constitute the serial multiplex inverter 1 are configured by IGBTs and BJTs (Bipolar Junction Transistors). FIG. 8 shows a serial multiplex inverter 1.
1 shows a switching element for one phase. The switching elements S1 and S4 are IGBTs, and the switching elements S2 and S3 are BJTs. Also in this embodiment, the same effect as that of the second embodiment shown in FIG. 6 can be obtained.

FIG. 9 shows a fourth embodiment of the present invention. Figure 1
The difference from the first embodiment of a is that the switching elements S1U to S4W constituting the serial multiplex inverter 1 are connected to the n-IGB.
T (n-channel Insulated Gate Bipolar Transistor) and p-IGBT (p-channel Insulated Gate Bipolar Tra
nsistor). Figure 8
Is a switching element for one phase which constitutes the serial multiplex inverter 1. The switching elements S1 and S4 are n-I
It is a GBT, and the switching elements S2 and S3 are p-IG.
It is BT. Also in this embodiment, the same effect as that of the second embodiment shown in FIG. 6 can be obtained.

In the above embodiments, the switching elements constituting the serial multiplex inverter 1 are individually combined and used, but the switching elements S1, S2 and D1, D are used.
By accommodating 2 as one set of switching elements in one package, it is possible to reduce the size of the series multiplex inverter, eliminate the difference in heat generation between the packages, and simplify the cooling structure.

FIG. 10 shows switching elements n-IGBT, p-IGBT and BJ which form a serial multiple inverter.
For T and GTO, the characteristics of the forward voltage drop with respect to the turn-off time are shown as a distribution. The turn-off time on the horizontal axis can be read as the switching loss because the switching loss is proportional to the turn-off time. The forward voltage drop on the vertical axis can be read as the loss due to the forward voltage drop because a loss occurs due to the product of the magnitude of the average current of the switching element. The principle of combination of the switching elements S1 to S4 forming the serial multiplex inverter of the present invention will be described with reference to FIG. In the present invention, as is apparent from the above-described embodiment, the switching elements S2 and S3 on the inner side are elements having a small forward voltage drop, and the switching elements S1 and S4 on the outer side are elements having a small switching loss. . That is,
When the n-IGBT shown in FIG. 10 is used for the outer S1 and S4, the inner S2 and S3 have p-IGBT, BJT or GTO having a lower forward voltage drop than the n-IGBT.
To use. When BJTs are used for the outer S1 and S4, p-IGBTs or GTOs having a lower forward voltage drop than the BJTs are used for the inner S2 and S3. As described above, from the characteristics of the turn-off time and the forward voltage drop of the switching element, the outside S of the series multiple inverter is configured.
The combination is selected so that the elements having a short turn-off time are used for 1 and S4, and the elements having a smaller forward voltage drop are used for the inner S2 and S3 than the elements used for the outer S1 and S4. This principle is based on the switching element n-IGBT, p
Needless to say, the present invention is not limited to IGBTs, BJTs, and GTOs, and can be applied to all elements that can be used as switching elements of a series multiple inverter.

[0014]

According to the present invention, the losses of switching elements connected in series can be equalized, and
It is possible to prevent an increase in loss caused by operating the switching element at a high switching frequency. Further, it is possible to output an AC output with few harmonics. Further, the switching element and the diode forming the serial multiplex inverter are used as one set of switching elements, and one package is used.
By accommodating in a package, the serial multiple inverter can be downsized, and the heat generation difference between the packages can be eliminated to simplify the cooling structure.

[Brief description of drawings]

FIG. 1a is a configuration diagram showing a main circuit of a serial multiplex inverter showing an embodiment of the present invention.

FIG. 1b is a table (Table 1) showing output voltages corresponding to ON states of switching elements of a serial multiple inverter.

FIG. 2 is a waveform diagram showing a phase relationship between an output voltage command and an output current.

FIG. 3a is a circuit diagram illustrating an operation of a switching element of a serial multiplex inverter.

FIG. 3b is a table (Table 2) showing the current paths of the switching elements of the serial multiple inverter.

FIG. 4 is a characteristic diagram illustrating an average current of a switching element of a serial multiple inverter.

FIG. 5 is a characteristic chart of a loss with respect to an inverter output frequency.

FIG. 6 is a circuit diagram showing a configuration of a switching element showing another embodiment of the present invention.

FIG. 7 is a characteristic diagram showing the relationship between the forward voltage drop of GTO and IGBT and the switching loss.

FIG. 8 is a circuit diagram showing a configuration of a switching element showing another embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a switching element showing another embodiment of the present invention.

FIG. 10 is a characteristic diagram of turn-off time and forward voltage drop of a switching element.

[Explanation of symbols]

 1 series multiplex inverter 2,3 DC power supply S1U-S4W switching element D1U-D4W diode CD1U-CD2W diode

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 27, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title of the invention Inverter device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial multiplex inverter device, and more particularly to an inverter device which prevents biased loss due to current in a switching element and operates at a high switching frequency.

[0002]

2. Description of the Related Art Conventionally, a PWM inverter device has been used to control the rotation speed of an AC motor.
Since the output voltage of the M inverter has two levels, positive and negative, there is a problem that the harmonic component included in the output current is large. Therefore, in the past, as a method of reducing the harmonic component contained in the output current of the PWM inverter, Japanese Patent Laid-Open No.
No. 74088, a PWM inverter is multiplexed in series, and the output voltage of the inverter is positive, 0, negative 3
There has been proposed a method of reducing the harmonic components by setting the level. Further, there is a problem that one switching element is damaged due to overvoltage due to a difference in turn-off characteristics of switching elements connected in series. As a method of preventing this, as described in Japanese Patent Publication No. 51-47848. A method has been proposed in which pulses of switching elements connected in series have a certain phase relationship, or a switching element with a slow turn-off is placed inside and a switching element with a fast turn-off is placed outside.

[0003]

However, in the above-mentioned prior art, loss imbalance occurs due to a difference in average current of switching elements connected in series, or the switching elements are operated at a high switching frequency. Due to the accompanying increase in loss, excessive loss of the switching element may occur and damage may occur, but no consideration is given to the imbalance of the loss and the increase in loss. An object of the present invention is to equalize the loss of switching elements connected in series, prevent an increase in loss due to operating the switching elements at a high switching frequency, and output an AC output with few harmonics. It is to provide an inverter device.

[0004]

A direct current power supply, a direct current circuit having an output terminal of the direct current power supply and a neutral point output terminal, and both terminals of first to fourth switching elements connected in series are provided in the direct current circuit. Connected to both terminals of the second and third terminals
Connecting the interconnection point of the switching elements to the inverter output terminal, and connecting the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements to the neutral point of the DC circuit and the diode. Connect through the first
In the inverter device in which the third and third switching elements and the second and fourth switching elements are on / off controlled by the mutually conjugate relationship, a semiconductor device having a small forward voltage drop is provided in the second and third switching elements. A semiconductor device with fast switching is used for the first and fourth switching elements. Also, based on the characteristics of the turn-off time and forward voltage drop of the switching element,
Elements having a short turn-off time are used for the first and fourth switching elements, and elements having a smaller forward voltage drop are used for the second and third switching elements than the switching elements used for the first and fourth. Select and combine.

[0005]

The serial multiple inverter selects only a positive mode and a zero mode when the output voltage is positive, and selects only a negative mode and a zero mode when the output voltage is negative. As a result, the current sharing of the switching elements of the series multiplex inverter changes according to the electric and regenerative operation modes and the magnitude of the output voltage. In particular, in the electric operation mode, since the output current always flows through the switching element on the inside related to the mode in which the output voltage is set to 0, the loss due to the forward voltage drop increases. The output current increases in the outer switching element according to the magnitude of the output voltage, but the magnitude thereof is less than half that in the inner side, and the switching loss is large. Therefore, a power semiconductor device with a small forward voltage drop is used for the inner switching element,
A power semiconductor device with fast switching is used on the outer side, and as a result, the loss due to the forward voltage drop of the inner switching element is reduced, and the switching loss of the outer switching element is reduced, so that the inner side and the outer side are reduced. The loss of the switching elements can be equalized. As a result, the loss of the switching elements connected in series is made uniform, and the loss increase caused by operating the switching elements at a high switching frequency is prevented, and an inverter device capable of outputting an AC output with few harmonics is provided. can do.

[0006]

FIG. 1 shows an embodiment of the present invention. In FIG. 1a, the series multiple inverter 1 includes two DC power sources 2, 3
The mutual connection point of is used as a neutral point of the power supply, and the DC voltage is converted into positive, 0, and negative three-level AC voltage. The switching circuit is a gate turn-off thyristor (hereinafter referred to as GT
It is abbreviated as O. ) S1U to S4W and each output terminal U,
It is composed of clamp diodes CD1U to CD2W for clamping V and W to the neutral point potential and flywheel diodes D1U to D4W. The switching elements S1U to S4W constituting this serial multiple inverter 1 are 3
It is turned on / off by an on / off pulse signal made by comparing the phase AC voltage commands vu ^* , vv ^* , vw ^* (not shown) with a carrier signal.
And S3 and S2 and S4 operate as a pair of inverters to turn on and off in a conjugate relationship. As a result, the relationship between the on-condition and the voltage at the output end is as shown in (Table 1) of FIG. 1b. For example, if you look at U phase, S
When 1U and S2U are turned on, the output terminal U has a potential of + E. Conversely, when S3U and S4U are turned on, the output end U
The potential becomes E. When S2U and S3U are turned on,
Output terminal U is S2U and S3U and clamp diode CD
It is connected to the connection point of the smoothing capacitors 12 and 13 via 1U and CD2U, and has 0 potential. As a result of this operation, the potential of the output terminal U changes between + E, O, and -E, and the harmonic component of the inverter output is reduced. The operation of this inverter is the same as that of the conventional serial multiple inverter.

The operation of the present invention will be described below. Figure 2
The phase relationship between the output voltage command v * for one phase and the output current i is shown, and each of the polarities can be divided into four sections a to d. In the sections A and B, the switching element S2 is constantly turned on, and the switching elements S1 and S3 are alternately turned on. In the sections C and D, the switching element S3 is constantly turned on, and the switching elements S2 and S4 are alternately turned on. In Figure 3a,
The element that performs the switching operation for each section is indicated by O, and the output current at that time is indicated by the dotted line. For example, the output current of the section a flows to the flywheel diode D2 → D1 → DC power supply 2 when the output voltage is + E, and the switching element S3 → the clamp diode CD2 when the output voltage is 0.
→ It flows to the neutral point. The output current of the section mouth flows to the switching element S1 → S2 → load when the output voltage is + E, and the clamp diode CD1 → when the output voltage is 0.
The switching element S2 flows to the load. As a result, the output current flows through the path shown in (Table 2) of FIG. 3b depending on the polarities of the output voltage and the output current. From (Table 2), a larger amount of output current flows through the inner switching elements S2, S3 (see the broken line) than in the outer switching elements S1, S4 during the period in which the output voltage is zero. Further, the currents of the switching elements S2 and S3 on the inner side are not affected by the switching operation, and a continuous current flows. On the other hand, the output current of the outer switching element is intermittent during the period when the output voltage is 0, and is affected by the switching operation. For example, when the V / f control that controls the output voltage in proportion to the output frequency is applied to the serial multiplex inverter 1, the period in which the output voltage becomes 0 in proportion to the inverter output frequency decreases, While the average current of the switching element of 1 is almost constant, the average current of the outer switching element increases in proportion to the inverter output frequency, as shown in FIG. In FIG. 4, the horizontal axis represents the inverter output frequency and the vertical axis represents the average current, and shows the average current characteristics of the inner switching element and the outer switching element in the electric operation mode.

As a result, as shown in FIG. 5A, the loss of the inner switching element is large due to the forward voltage drop, and the loss of the outer switching element is occupied by the switching loss in the inner switching element. The loss is increased when the switching frequency is increased. In FIG. 5A, the horizontal axis represents the inverter output frequency, the vertical axis represents the loss, the dashed line represents the loss due to the forward voltage drop, the diagonal line represents the switching loss, and the solid line represents the total loss obtained by integrating these. Therefore, in this embodiment,
For the inner switching elements S2 and S3 that form each phase,
A switching element having a smaller forward voltage drop than the outer switching elements S1 and S4 is used, and the turn-off time of the outer switching elements S1 and S4 forming each phase is shorter than that of the inner switching elements S2 and S3. A switching element is used. As a result, as shown in FIG. 5B, the loss due to the forward voltage drop in the loss of the inner switching element is reduced. Further, the loss of the outer switching element is reduced as a whole, though the switching loss is reduced but the loss due to the forward voltage drop is increased. Therefore, in this embodiment, it is possible to prevent an increase in loss even if the switching frequency of the switching element is increased. Furthermore, the losses of the inner and outer switching elements can be equalized (that is, the difference between the losses can be reduced as is clear from FIG. 5B), and the cooling structure can be manufactured symmetrically.

FIG. 6 shows a second embodiment of the present invention. Figure 1
The difference from the first embodiment of a is that the switching elements S1U to S4W forming the series multiple inverter 1 are IGBTs.
(Insulated Gate Bipolar T
It is to be configured by GTO. FIG. 6 shows switching elements for one phase which constitute the serial multiple inverter 1. The switching elements S1 and S4 are IGBTs, and the switching elements S2 and
S3 is a GTO. FIG. 7 shows the relationship between the forward voltage drop of the IGBT and the GTO and the switching loss. Although the IGBT has a small switching loss, it has a high forward voltage drop and
O has a small forward voltage drop, but has a large switching loss. In this embodiment, from the characteristics of the IGBT and the GTO, a combination that matches the current sharing and the switching operation of the series multiple inverter 1 is adopted, and when the same switching element is used, necessary characteristics can be selected. It can be omitted.

FIG. 8 shows a third embodiment of the present invention. Figure 1
The difference from the first embodiment of a is that the switching elements S1U to S4W constituting the serial multiplex inverter 1 are connected to IGBT and BJT (Bipolar Junction Tran).
It is configured by a system.
FIG. 8 shows switching elements for one phase which constitute the serial multiple inverter 1. The switching elements S1 and S4 are I
It is a GBT and the switching elements S2 and S3 are BJTs. Also in this embodiment, the same effect as that of the second embodiment shown in FIG. 6 can be obtained.

FIG. 9 shows a fourth embodiment of the present invention. Figure 1
The difference from the first embodiment of a is that the switching elements S1U to S4W forming the series multiple inverter 1 are n-IGB.
T (n-channel Insulated Gat)
e Bipolar Transistor) and p-I
GBT (p-channel Insulated Ga)
te Bipolar Transistor). FIG. 8 shows switching elements for one phase which constitute the serial multiple inverter 1.
The switching elements S1 and S4 are n-IGBTs, and the switching elements S2 and S3 are p-IGBTs. Also in this embodiment, the same effect as that of the second embodiment shown in FIG. 6 can be obtained.

In the above embodiments, the switching elements constituting the serial multiplex inverter 1 are individually combined and used, but the switching elements S1, S2 and D1, D are used.
By accommodating 2 as one set of switching elements in one package, the series multiple inverter can be downsized and the difference in heat generation between the packages can be eliminated to simplify the cooling structure.

FIG. 10 shows switching elements n-IGBT, p-IGBT and BJ which form a serial multiple inverter.
For T and GTO, the characteristics of the forward voltage drop with respect to the turn-off time are shown as a distribution. The turn-off time on the horizontal axis can be read as the switching loss because the switching loss is proportional to the turn-off time. The forward voltage drop on the vertical axis can be read as the loss due to the forward voltage drop because a loss occurs due to the product of the magnitude of the average current of the switching element. The principle of combination of the switching elements S1 to S4 forming the serial multiplex inverter of the present invention will be described with reference to FIG. In the present invention, as is apparent from the above-described embodiment, the switching elements S2 and S3 on the inner side are elements having a small forward voltage drop, and the switching elements S1 and S4 on the outer side are elements having a small switching loss. . That is,
When the n-IGBT shown in FIG. 10 is used for the outer S1 and S4, the inner S2 and S3 have a lower forward voltage drop than the n-IGBT, such as p-IGBT, BJT or GTO.
To use. When BJTs are used for the outer S1 and S4, p-IGBTs or GTOs that have a lower forward voltage drop than the BJTs are used for the inner S2 and S3. As described above, from the characteristics of the turn-off time and the forward voltage drop of the switching element, the outside S of the series multiple inverter is configured.
The combination is selected so that the elements having a short turn-off time are used for 1 and S4, and the elements having a smaller forward voltage drop are used for the inner S2 and S3 than the elements used for the outer S1 and S4. This principle is based on the switching element n-IGBT, p
Needless to say, the present invention is not limited to IGBTs, BJTs, and GTOs, and can be applied to all elements that can be used as switching elements of a series multiple inverter.

[0014]

According to the present invention, the losses of switching elements connected in series can be equalized, and
It is possible to prevent an increase in loss caused by operating the switching element at a high switching frequency. Further, it is possible to output an AC output with few harmonics. Furthermore, by accommodating the switching element and the diode that configure the series multiple inverter as one set of switching elements in one package, the series multiple inverter can be downsized, and the difference in heat generation between the packages can be eliminated, thus providing a cooling structure. Can be simplified.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a main circuit of a serial multiple inverter showing an embodiment of the present invention.

FIG. 2 (a) is a chart (Table 1) showing the output voltage corresponding to the ON state of the switching element of the series multiple inverter;
(B) A waveform diagram showing the phase relationship between the output voltage command and the output current.

FIG. 3A to FIG. 3D are circuit diagrams illustrating the operation of the switching element of the serial multiple inverter.

FIG. 4 is a diagram (Table 2) showing a current path of a switching element of a serial multiple inverter.

FIG. 5 is a characteristic diagram illustrating an average current of a switching element of a serial multiple inverter.

FIG. 6 is a characteristic diagram of loss with respect to inverter output frequency.

FIG. 7 is a circuit diagram showing a configuration of a switching element showing another embodiment of the present invention.

FIG. 8 is a characteristic diagram showing the relationship between the forward voltage drop of GTO and IGBT and the switching loss.

FIG. 9 is a circuit diagram showing a configuration of a switching element showing another embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a switching element showing another embodiment of the present invention.

FIG. 11 is a characteristic diagram of turn-off time and forward voltage drop of a switching element.

[Explanation of Codes] 1 series multiple inverter 2, 3 DC power supply S1U to S4W switching element D1U to D4W diode CD1U to CD2W diode

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Fig. 2]

[Figure 4]

[Figure 1]

[Figure 5]

[Figure 7]

[Figure 8]

[Figure 9]

FIG. 11

[Figure 3]

[Figure 6]

[Figure 10]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H03K 17/10 9184-5J 17/12 9184-5J 17/56 (72) Inventor Takayuki Matsui Ibaraki Prefecture 1070 Ichige, Katsuta-shi Mito Plant, Hitachi, Ltd. (72) Satoshi Horie 1070 Ichige, Katsuta-shi Katsuta, Ibaraki Prefecture (72) Inventor, Hideharu Saito 1070 Ige, Katsuta-shi, Ibaraki Hitachi, Ltd., Mito Plant (72) Inventor, Eiichi Toyota, 1070 Ichimo, Katsuta, Ibaraki Prefecture, Hitachi Ltd., Mito Plant, Hitachi, Ltd. (72) Kazuhiro Sakata, 1070, Ichige, Katsuta, Ibaraki, Hitachi, Ltd. Mito Factory (72) Inventor Takeshi Ando 1070 Imo, Katsuta City, Ibaraki Prefecture Hitachi Ltd. Mito Factory (72) Inventor Takashi Tsuboi Katsuta City, Ibaraki Prefecture 1070 Hitachi Co., Ltd. Mito Plant (72) Inventor Tetsuya Kawakami 4-3 Kanda Sugawadai, Chiyoda-ku, Tokyo Hitachi Techno Engineering Co. (72) Inventor Toshihiko Takaku 832 Horiguchi, Katsuta City, Ibaraki Hitachi Mito Engineering Co., Ltd.

Claims (7)

[Claims] 1. A DC power supply, a DC circuit having an output terminal of the DC power supply and a neutral point output terminal, and both terminals of first to fourth switching elements connected in series to both terminals of the DC circuit. And connecting the interconnection point of the second and third switching elements to the inverter output terminal, the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements. An inverter for connecting the neutral point of the DC circuit through a diode and performing on / off control of the first and third switching elements and the second and fourth switching elements in a conjugate relationship with each other. In the power supply device, semiconductor devices with a small forward voltage drop are used for the second and third switching elements, and semiconductor devices with fast switching are used for the first and fourth switching elements. Inverter device to collect. 2. A direct current power supply, a direct current circuit having an output terminal of the direct current power supply and a neutral point output terminal, and both terminals of first to fourth switching elements connected in series to both terminals of the direct current circuit. And connecting the interconnection point of the second and third switching elements to the inverter output terminal, the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements. An inverter for connecting the neutral point of the DC circuit through a diode and performing on / off control of the first and third switching elements and the second and fourth switching elements in a conjugate relationship with each other. In the switching device, the first and fourth switching elements are IGBTs.
(Insulated Gate Bipolar Tr
the second and third switching elements are GTO (Gate Turn-Off thy).
inverter). 3. A direct current power supply, a direct current circuit having an output terminal of the direct current power source and a neutral point output terminal, and both terminals of first to fourth switching elements connected in series to both terminals of the direct current circuit. And connecting the interconnection point of the second and third switching elements to the inverter output terminal, the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements. An inverter for connecting the neutral point of the DC circuit through a diode and performing on / off control of the first and third switching elements and the second and fourth switching elements in a conjugate relationship with each other. In the switching device, the first and fourth switching elements are IGBTs.
And the second and third switching elements are a transistor BJT (Bipolar JunctionTran).
Inverter device characterized in that it is a sistor). 4. A DC power supply, a DC circuit having an output terminal of the DC power supply and a neutral point output terminal, and both terminals of first to fourth switching elements connected in series to both terminals of the DC circuit. And connecting the interconnection point of the second and third switching elements to the inverter output terminal, the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements. An inverter for connecting the neutral point of the DC circuit through a diode and performing on / off control of the first and third switching elements and the second and fourth switching elements in a conjugate relationship with each other. In the switching device, the first and fourth switching elements are n-IG.
BT (n-channel Insulated Ga)
te Bipolar Transistor), and the second and third switching elements are p-IGB
T (p-channel Insulated Gat
e Bipolar Transistor). 5. A direct current power supply, a direct current circuit having an output terminal of the direct current power supply and a neutral point output terminal, and both terminals of first to fourth switching elements connected in series to both terminals of the direct current circuit. And connecting the interconnection point of the second and third switching elements to the inverter output terminal, the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements. An inverter for connecting the neutral point of the DC circuit through a diode and performing on / off control of the first and third switching elements and the second and fourth switching elements in a conjugate relationship with each other. In the switching device, based on the characteristics of the turn-off time of the switching element and the forward voltage drop, elements having a short turn-off time are used for the first and fourth switching elements, and the second and third switching elements are used.
Inverter device characterized in that the switching elements are selectively combined so as to use elements having a smaller forward voltage drop than the switching elements used in the first and fourth. 6. In claim 5, when the first and fourth switching elements are n-IGBTs, the second and third switching elements are p-IGBT, BJT or GTO.
, Or the first and fourth switching elements are BJ
Assuming T, p− is used as the second and third switching elements.
An inverter device characterized by combining an IGBT or a GTO. 7. The method according to claim 1, wherein both terminals of the first to fourth switching elements connected in series are connected to both terminals of the DC circuit and the second and third switching elements are connected. The interconnection point of the switching elements is connected to the inverter output terminal, and the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements are the neutral point of the DC circuit. A plurality of unit inverters are connected to each other through a diode, and the first and third switching elements and the second and fourth switching elements are on / off controlled by a conjugate relationship with each other. Inverter device comprising a unit inverter of