JPH05108345A - Branch instruction processor - Google Patents

Abstract

PURPOSE:To increase the data processing speed and to improve the data processing efficiency by using the hardware to carry out a branch instruction. CONSTITUTION:When a branch instruction is received, the branch destination address corresponding to the output of a program counter 100 is retrieved and outputted by the output through the branch address storing associative memories 611-613. At the same time, the increase of the count value of the counter 100 is stopped by the output of an instruction decoder 310. Then the branch addresses outputted from the memories 611-613 are selected based on the branch conditions and applied to the counter 100. The output of the counter 100 is applied to an instruction storing memory 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a stored program type arithmetic processing unit. The present invention particularly relates to a branch instruction processing device that efficiently executes multiway branching.

[0002]

2. Description of the Related Art Advances in LSI manufacturing technology have made it possible to inexpensively use microprocessors with high processing capabilities. In order to realize a microprocessor with high processing capability, the operating frequency has been increased and the hardware has been highly integrated.

Particularly, in recent microprocessors, the instruction system has a fixed word length in order to reduce the load on the decoder.
We are trying to improve performance. This one word fixed-length instruction is composed of a plurality of sub-instructions and can designate a plurality of hardware operations at the same time. For example, it is possible to perform all ALU operations, data transfer instructions, and other in-microprocessor control simultaneously in one word fixed length instruction. As the sub-instruction, a branch instruction or an immediate value load instruction may be used.
However, these two instructions hold a branch address part and an immediate data part, respectively, as operands. Therefore, the branch instruction and the immediate load instruction can be simultaneously executed only with the limited sub instruction having the short bit length. This is 1
This is a drawback when the bit length of the instruction is limited.

On the other hand, in order to improve the productivity of software, it is desired for the instruction system of the microprocessor to reduce the semantic gap with a high-level language. FO widely used for scientific computing
RTRAN branch statements include IF (K) branch target 1, branch target 2, and branch target 3. This is a three-way method in which conditional expression K is evaluated and execution is moved to one of branch destinations 1, 2, and 3 depending on whether the value is “negative”, “0”, or “positive”. This is a statement for branching. In realizing this sentence at the assembler level of the microprocessor, first, the case where the branch destination is two directions will be described with reference to FIG.

In the apparatus for performing branch processing in the numerical processing apparatus shown in FIG. 12, a program counter 100, an incrementer 150 of the program counter 100,
An instruction storage memory 200 for outputting an instruction 201 according to the current value 101 output by the program counter 100,
An instruction decoder 300 that decodes this instruction 201, a flag 400 that changes according to the calculation result of the ALU of the numerical processing unit, and a value 401 of the flag that the flag 400 outputs.
Is provided with a selection circuit 500 for selecting either the output 151 of the incrementer 150 or the output 301 of the instruction decoder 300.

Next, the branch processing operation in this apparatus will be described. When the conditional branch instruction in the instruction storage memory 200 is output to the instruction decoder 300, the branch destination address 301 in the instruction statement and the output 151 of the incrementer 150 are given to the selection circuit 500. The selection circuit 500 is
Of the two inputs, if the value of the flag 400 satisfies the condition in the conditional branch instruction, the branch destination address 301 is selected, and if not, the output 151 of the incrementer 150 is selected. The output 501 of the selection circuit 500 is used as the address to be executed next, and the program counter 100
Entered in.

To expand this in three directions, three conditional branch instructions are combined and executed. The actual program is as follows.

Cmp rl, 0 ... Comparing conditional expressions r1 and 0 jz 1000h ... When r1 is 0 to 1000h js 2000h ... When r1 is negative to 2000h jl 3000h ... When r1 is positive to 3000h cmp d, s ... Comparison instruction, set zero flag when comparison result is equal, set carry flag when d <s, jz D ... Conditional branch instruction, branch when zero flag is set, js D ... Conditional branch instruction, carry flag set , Jl D ... Conditional branch instruction, branch when zero flag and carry flag are not set,

[0009]

In order to realize a branch in three directions, it is necessary to execute a combination of a comparison instruction and three conditional branch instructions as shown in this program. However, with this method, the number of execution steps and the number of accesses to the memory for storing instructions increase, which reduces the data processing speed and processing efficiency.

The present invention solves the above-mentioned drawbacks by providing a plurality of associative memories for storing branch addresses,
An object of the present invention is to provide a branch instruction processing device that can realize branch instructions in three directions with one instruction and can increase data processing speed and processing efficiency.

[0011]

According to the present invention, there is provided an instruction storage memory for storing an instruction to be executed, an instruction decoder for decoding the instruction and outputting a conditional branch instruction, and a register for setting a branch condition. , A first selection circuit that selects and outputs a branch destination address according to the branch condition set in this register, and an instruction storage address to which the selected branch destination address is input and the next execution is for storing the instruction In a branch instruction processing device provided with a program counter for outputting to a memory and an incrementer for incrementing the output of the program counter, a plurality of program counters provided corresponding to the number of branch destinations and given to the instruction storing memory. The corresponding branch destination address is stored using the output of as a key and the branch destination address is output to the first selection circuit. And associative memory for Toki address storage, characterized in that the outputs of the above incrementer of said first selection circuit and a second selection circuit for selecting in accordance with the output of the instruction decoder.

An adder for adding the output of the program counter and the output of the associative memory for storing each branch address can be provided.

[0013]

The instruction output from the instruction storage memory is decoded by the instruction decoder. At the same time, the associative memory for storing the branch address retrieves the branch address using the value of the program counter as a key and outputs it. One of the branch addresses output from the plurality of associative memories for storing branch addresses is selected by the first selection circuit based on the output of the register. The selected branch address is given to the program counter by selecting either the branch address or the incrementer output according to the output of the instruction decoder. Therefore, when a branch instruction is being executed, the branch address output from each branch address storage associative memory is input to the program counter according to the value output from the register, and the branch instruction is executed. If it is not a branch instruction, the program counter is incremented.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a branch processing apparatus according to the first embodiment of the present invention. The first embodiment apparatus includes an instruction storage memory 200 for storing an instruction to be executed, an instruction decoder 310 for decoding the instruction and outputting a conditional branch instruction, a register 800 for setting a branch condition,
A first selection circuit 51 for selecting and outputting a branch destination address according to the branch condition set in the register 800.
0, a program counter 100 that inputs the selected branch destination address and outputs the instruction storage address to be executed next to the instruction storage memory, and an incrementer 1 that increments the output of the program counter 100.
In the branch instruction processing device including 50, a plurality of branch destination addresses provided corresponding to the number of branch destinations, which is a feature of the present invention, and provided to the instruction storing memory 200 is used as a key to set a corresponding branch destination address. Branch address storing associative memories 611, 612 and 613 for storing and outputting the branch destination address to the first selecting circuit, the output of the first selecting circuit 510 and the incrementer 150.
And a second selection circuit 550 for selecting the output of the instruction decoder 310 according to the output of the instruction decoder 310.

Numeral 151 is the output of the incrementer 150, 201 is the instruction selected from the instruction storing memory 200, 301 is the output of the instruction decoder 310, and 601 and 6
02 and 603 are associative memories 611 for storing branch addresses,
Outputs 612 and 613, 511 is an output of the selection circuit 510, and 551 is an output of the selection circuit 550.

Next, the operation of the first embodiment will be described.

When a 3-way branch instruction is given, the instruction decoder 310 outputs to the selection circuit 550 a signal 312 notifying that the 3-way branch instruction has been given.

The selection circuit 510 is configured as shown in FIG. 2 in order to select the output data depending on whether the value of the register 800 is "negative", "0" or "positive". In FIG. 2, reference numeral 521 indicates a gate which opens only when the value of the register 800 is “positive”, and which passes the address input to the gate. Reference numeral 522 indicates the same operation only when the value of the register 800 is “0”. Gate 523
Is a gate that operates similarly only when the value of the register 800 is "negative". In FIG. 2, the complement of “2” is used and the bit width of the register to be used is 5 bits.

It is assumed that the instruction storage memory 200 stores instructions as shown in FIG. Assume that branch address storage associative memories 611, 612, and 613 store data as shown in FIGS. 4, 5, and 6, respectively. In FIG. 3, “IF K” is FORTR
It is assumed that the instruction is equivalent to the statement of IF '(K) branch destination 1, branch destination 2, branch destination 3'of AN.

When the value 101 of the program counter 100 is "10", the instruction 201 output from the instruction storing memory 200 is decoded by the instruction decoder 310. At the same time, the associative memory 61 for storing the branch address
In 1, 612, and 613, the value “10” of the program counter 100 is used as a key to search for the branch address “1000000h” and the branch address “200000”.
0h ”and branch address“ 3000000h ”are output to the selection circuit 510, respectively. The selection circuit 510 selects one of the branch addresses according to the value of the register 800, and outputs it to the selection circuit 550. The selection circuit 550 provides either the output 511 from the selection circuit 510 or the output 151 of the incrementer 150 to the program counter 100 according to the output 312 of the instruction decoder 310.

For example, when the value of the register 800 is "positive", the value "1000000h" output from the associative memory 611 for storing the branch address and the value "11" of the output 151 of the incrementer 150 are supplied to the selection circuit 550. ..
However, since the selection circuit 550 indicates that the output 312 of the instruction decoder 310 is executing a three-way branch instruction, the value “10” output from the branch storage associative memory 611 is output.
"00000h" is output to the program counter 100. Similarly, when the value of the register 800 is "0", the value "2000000h" output from the branch address storage memory 612 is output to the program counter 100 via the selection circuits 510 and 550. The same applies when the value of the register 800 is "negative", and the value "3000000" output from the memory 613 for storing the branch address is the same.
“H” is output to the program counter 100 via the selection circuits 510 and 550.

Next, a second embodiment of the present invention will be described with reference to FIGS.
It will be explained based on.

This second embodiment is compared with the first embodiment,
The adder 711 and the program counter 10 which add the output of the program counter 100 and the value of the output 601 of the associative memory 611 for storing the branch address and give it to the selection circuit 510
An adder 7 that adds the output of 0 and the value of the output 602 of the associative memory 612 for storing the branch address to the selection circuit 510
12. The difference is that an adder 712 for adding the output of the program counter 100 and the value of the output 603 of the associative memory 613 for storing branch address and giving it to the selection circuit 510 is provided.

The operation of the second embodiment will be described.

The selection circuit 510 selects the data depending on whether the value of the register 800 is "negative", "0", or "positive", and thus is configured as shown in FIG.

It is assumed that the instruction storage memory 200 stores instructions as shown in FIG. The associative memories 611, 612, and 613 for storing branch addresses are shown in FIG.
It is assumed that the data as shown in FIGS. 10 and 11 is stored. In FIG. 8, it is assumed that “IFK” is an instruction equivalent to the statement of “IF (K) branch target 1, branch target 2, branch target 3” of FORTRAN.

The value of the program counter 100 is "10".
At this time, the instruction 201 is decoded by the instruction decoder 310. At the same time, the associative memory 6 for storing the branch address
In 11, 612 and 613, the program counter value “10” is searched as a key, and the branch address “100h”, the branch address “200h” and the branch address “300h” are added to the adders 711, 712 and 71, respectively.
Output to 3. The adder 711 adds the value of the output 601 of the associative memory for branch address storage 611 and the output 101 of the program counter 100 and outputs the result to the selection circuit 510. The same applies to the adders 712 and 713. The selection circuit 510 selects one of the outputs 701, 702, and 703 from each of the adders 711, 712, and 713 according to the value held in the register 800, and outputs it to the selection circuit 550. The selection circuit 550 outputs either the output 511 of the selection circuit 510 or the output 151 of the incrementer 150 to the program counter 100 according to the output 312 of the instruction decoder 310.

For example, when the value of the register 800 is "positive", "110h" output from the adder 711 and the value of the output 151 of the incrementer 150 are supplied to the selection circuit 550. However, the selection circuit 550 is
Since the output 312 from 0 indicates that the three-way branch instruction is being executed, the value “110h” of the output 701 of the adder 711 is output to the program counter 100.
Similarly, when the value of the register 800 is “0”, the adder 7
The value “210h” of the 12 output 702 is output to the program counter 100 through the selection circuit 550. The same applies when the value of the register 800 is “negative”, and the value “310h” of the output 703 of the adder 713 is the program counter 10
It is output to 0.

The difference between the second embodiment and the first embodiment is that the branch destination can be designated by a relative address.

In the above embodiment, the control of the selection circuit is described as being "2" complement and the data to be handled is 5 bits. However, it is clear that the same effect can be obtained even when the complement of "1" is used or the number of bits of data is 16-bit width or 32-bit width.

[0032]

As described above, by providing a plurality of associative memories for storing branch addresses, the present invention can realize a branch instruction in three directions, which was conventionally four instructions, with one instruction. As a result, the data processing speed and processing efficiency of the microprocessor can be increased. Also, the semantic gap with high-level languages can be reduced.

Further, since another sub-instruction can be designated in the bit portion which conventionally holds the branch address value in one instruction, the processing efficiency can be improved accordingly. The capacity of the memory for storing the branch address is sufficient if it is the total number of branch destinations of the branch instruction, and the capacity does not increase.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a selection circuit 510.

FIG. 3 is a diagram showing the contents of a memory for storing instructions according to the first embodiment.

FIG. 4 is a diagram showing the contents of an associative memory for storing a branch address according to the first embodiment.

FIG. 5 is a diagram showing the contents of an associative memory for storing a branch address according to the first embodiment.

FIG. 6 is a diagram showing the contents of an associative memory for storing a branch address according to the first embodiment.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing the contents of a memory for storing instructions according to the second embodiment.

FIG. 9 is a diagram showing the contents of an associative memory for storing a branch address according to the second embodiment.

FIG. 10 is a diagram showing the contents of an associative memory for storing a branch address according to the second embodiment.

FIG. 11 is a diagram showing the contents of an associative memory for storing a branch address according to the second embodiment.

FIG. 12 is a block diagram showing a conventional example.

[Explanation of symbols]

100 Program Counter 101 Program Counter Output 150 Incrementer 151 Incrementer Output 200 Instruction Storage Memory 201 Instructions to be executed 300, 310 Instruction Decoder 301 Output of Instruction Decoder 300 400 Flag 401 Flag Value 500, 510, 550 Selection Circuit 501 Output of selection circuit 500 511 Output of selection circuit 510 521, 522, 523 Selection gate 551 Output of selection circuit 550 601, 602, 603 Output of associative memory for storing branch address 611, 612, 613 Associative memory for storing branch address 701, 702, 703 Adder output 711, 712, 713 Adder 800 register

Claims (2)

[Claims] 1. An instruction storage memory for storing an instruction to be executed, an instruction decoder for decoding the instruction and outputting a conditional branch instruction, a register in which a branch condition is set, and a branch set in this register. A first selection circuit for selecting and outputting a branch destination address according to a condition; a program counter for inputting the selected branch destination address and outputting an instruction storage address to be executed next to the instruction storage memory; In a branch instruction processing device equipped with an incrementer that increments the output of this program counter, a plurality of branch instructions are provided corresponding to the number of branch destinations, and the corresponding branch is given using the output of the program counter given to the instruction storing memory as a key. Associating branch address storage for storing the destination address and outputting the branch destination address to the first selection circuit A branch instruction processing device comprising: a memory; and a second selection circuit that selects the output of the first selection circuit and the output of the incrementer according to the output of the instruction decoder. 2. The branch instruction processing according to claim 1, further comprising a plurality of adders for adding the branch address output from the associative memory for storing the branch address and the output of the program counter to the first selection circuit. apparatus.