JPH0487553A - Failure detection device of detector - Google Patents

Abstract

PURPOSE:To improve a failure detection rate without using a reference signal and hardware special for failure detection by, when the sum of phase voltages and the sum of phase currents read by a microprocessor are within a certain range with zero as the center, forming a judgment to be normal, otherwise, forming a judgment to be abnormal. CONSTITUTION:A sample hold circuit 4 samples, holds, and transmits the instantaneous values of the phase signals of three-phase voltage and a three-phase current at the same point of time. A multiplexer 5 selects and transmits the output signals of the sample hold circuit 4. A microprocessor 7 reads digital values converted with an analogue-to-digital converter 6, adds the phase values of the three-phase voltage, and, if the sum is larger than alpha (with the maximum error of the voltage system of a detectorapprox.=0), judges to be abnormal and handles the failure. When the sum is not larger than alpha, it adds the phase values of the three-phase current and, if the sum is larger than beta (with the maximum error of the current system of the detectorapprox.=0), judges to be abnormal and handles the failure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a detector failure detection device suitable for use in a digital control device of a three-phase power converter.

[Prior Art] Fig. 3 is a block diagram showing a conventional detector failure detection device disclosed in, for example, Japanese Patent Laid-Open No. 61-262477. The multiplexer (21) with this multiplexer (20
), a sample and hold circuit connected to the output side of (22
) is an A/D converter connected to the output side of the sample and hold circuit (21), (23) is a CPU connected to the output side of the A/D converter (22) through a bus, and (24) is the above-mentioned each. control logic connected to the component (25
) and (26) are reference voltage sources connected to the two input sides of the multiplexer (20).

The other input side of the multiplexer (20) receives an analog signal to be converted from analog to digital.

Next, the operation will be explained. The CPU (23), on the other hand, specifies the channels CH3 to CHN of analog input signals to be A/D converted via one internal bus B1. Control logic (24
) responds by providing a channel designation signal to the multiplexer (20) via the internal bus B2. The multiplexer (20) selects one analog input designated by the control logic (24) from among the N analog inputs, and outputs the selected one analog input to the sample and hold circuit (21). The output analog signal is supplied to the input side of the sample and hold circuit (21). Subsequently, the control logic (24) provides a hold command signal H to the sample and hold circuit (21). Sample hold (21)
outputs the input analog signal at the time when the hold command signal H is applied to the A/D converter (22), and holds the output voltage level. Next, control logic (24
) provides an A/D conversion start signal ST to the A/D converter (22). In response, the A/D converter (22) converts the input analog signal into a binary digital value according to the voltage level, and then the control logic (24) converts the input analog signal into a binary digital value corresponding to the voltage level.
) is given a conversion end signal E. control logic (
24) sends an end signal, which is an A/D conversion end signal, to the CPU (23) via the internal bus B1.

When the CPU (23) receives this end signal, it sends and receives the converted binary digital value from the A/D converter (22).

By the way, determination of failure or adjustment deviation of the A/D converter (22) is performed as follows. First, A/D
The minimum voltage of the analog input voltage range of the converter (22) is A
It is necessary to input the signal to the /D converter (22) and adjust the offset so that the digital conversion value is minimized. Next, it is necessary to input the maximum voltage in the analog input voltage range to the A/D converter (22) and adjust the gain so that the digital conversion value becomes maximum. Therefore, the multiplexer (20)
A minimum reference voltage source (25
), connect the maximum reference voltage source (26) to one other input channel CH2, and connect the remaining channels CH3 to
Analog signals that should originally be input to the CPU (23) for A/D conversion are connected to CHN. Under this state, the CPU (23) checks the offset deviation based on the digitally converted value of the minimum reference voltage MIN-V input from the minimum reference voltage source (25) to the channel CH1.

On the other hand, from the maximum reference voltage source (26) to channel C1 (2
The gain deviation is checked based on the digitally converted value of the maximum reference voltage MAX-V input to the MAX-V.

In this way, the configuration is such that the functions of each A/D converter (22) can be checked.

[The problem that the invention attempts to solve I! [] Since the conventional detector failure detection device is configured as described above, it can detect failures from the multiplexer to the A/D converter, but it can detect failures in stages before the multiplexer or some failures in the multiplexer itself. There were other problems, such as the failure cannot be detected and a reference signal is required for failure detection.

This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to obtain a fault detection device for a detector that has a high fault detection rate without requiring a special reference signal or hardware for fault detection. With the goal.

[Means for Solving the Problems] A detector failure detection device according to the present invention includes a detector that detects three-phase voltage and three-phase current related to a three-phase power converter, and A sample hold circuit samples and holds the analog detection signals of the three-phase voltage and three-phase current, and the analog detection signals of the three-phase voltage and three-phase current detected by the detector are sequentially selected and outputted one by one. an A/D converter that sequentially converts analog signals of the three-phase voltage and three-phase current sequentially selected by the multiplexer into digital values and outputs the digital values;
a microprocessor that reads digital values of the three-phase voltage and three-phase current sequentially converted by the A/D converter and performs control calculations using the values, and the voltage of each phase read by the microprocessor; If the sum of the values and the sum of the current values of each phase are each within a certain range centered on zero, it is determined to be normal, and if it deviates from that range, it is determined to be abnormal.

[Operation] In this invention, a control device having a microprocessor calculates the sum of voltages and currents of each phase input when controlling a three-phase power converter, and if the result is approximately 0, it is normal. If it is not O, it is determined to be abnormal.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the present invention. In FIG. say), (
2) is a current transformer (hereinafter referred to as CT) that detects the three-phase current of a power transformer, and (3) is a PT (1) or CT (2).
) is a signal conditioning circuit that converts the detected three-phase voltage and current into an appropriate signal level, (4) is a signal conditioning circuit (3
) Sample and hold circuit samples and holds the analog output signal of sample and hold circuit (4), (5) is a multiplexer that selects one signal at a time from the plurality of analog output signals of sample and hold circuit (4), (6) is a multiplexer (5) ()) is a microprocessor that inputs the digital output value of the A/D converter (6) and controls the power converter. Sample / for hold circuit (4)
The hold command signal (8) is sent to the multiplexer (5), and the input channel selection signal (9) is sent to the A/D converter (6).
), the A/D conversion command signal (10) is output to each of them.

Next, the operation of FIG. 1 will be explained with reference to the flowchart of FIG. 2. Note that the control of the three-phase power converter is a subject of the present invention, so a description thereof will be omitted.

The microprocessor (7) inputs the voltage and current of each phase when controlling the three-phase power converter. Its operation begins with the microprocessor (7) using the sample and hold circuit (4).
In response to this, the sample/hold circuit (4) outputs the sample/hold command signal (8) to the signal conditioning circuit (3) and outputs the sample/hold command signal (8) to the signal conditioning circuit (3). The instantaneous values of each phase current signal at the same time are sampled, halted, and output.

Second, the microprocessor (7) outputs a channel selection signal (9) to the multiplexer (5) to designate the first input channel (step 32).

In response, the multiplexer (5) selects and outputs the signal input to the first channel from among the output signals of the sample and hold circuit (4) (step 33).

Third, the microprocessor (7) has an A/D converter (6
) outputs the A/D conversion command signal (10) (step 34). In response, the A/D converter (6) inputs the analog output signal of the sample hold circuit (4) and converts it into a digital value. Convert to

Fourth, the microprocessor (7) is connected to the A/D converter (6).
) is read (step 35).

Fifth, perform the operations from second to fourth above for all input channels below the second one of the multiplexer (5), and convert all the digital values of each phase signal of the three-phase voltage and current to the microprocessor ( 7) (step 36)
．． 37).

Now, if the three-phase voltage is a line voltage, the sum of each line voltage is 0.
, and in the case of three-phase current, the sum of the currents in each layer is zero. Therefore, sixthly, the microprocessor (7) adds each phase value of the read three-phase voltage (step 38), and the sum is less than or equal to α (increase value of the error of the voltage system of the detector -, = 0). If the sum is less than or equal to α, it is determined that it is abnormal and a failure process is performed.Step 40)
If it is below, then the microprocessor (A) adds each phase value of the read three-phase current.Step 41) Is the sum less than or equal to β (the maximum value of error in the current system of the detector is 0)? Step 42) If the sum is less than or equal to β, it is determined that it is abnormal and a failure process is performed Step 40)
If it is below, the control calculation is performed.Step 45), step (
Return to 31).

Note that in reality, each part of the detector has some error, so if the error exceeds the range, it is determined to be abnormal. The above-described first to sixth operations constitute one cycle of three-phase voltage/current detection and detection circuit abnormality detection, and are periodically executed.

In the case of a three-phase four-wire system, the current signal is determined by adding the neutral line current signal and the sum of four signals.

If the three-phase voltage is a phase voltage, the sum will not be O if there is an unbalance between the phases, but if it exceeds the range of values corresponding to the expected unbalance, it is determined to be abnormal.

Also, if the sample/hold command signal (8), channel selection signal (9) + A/D conversion command signal (10) is generated by the signal logic circuit, the microprocessor (7)
The calculation time can be reduced.

Further, in the above embodiment, an individual sample bold circuit #r (4) is provided before the multiplexer (5), but if the conversion speed of the A/D converter (6) is fast, the multiplexer (5) ) before the separate sample bold circuit (4
) may be omitted and a single sample and hold circuit may be inserted or omitted between the multiplexer (5) and the A/D converter (6). However, this is limited to cases where the simultaneity of each three-phase voltage and current value read into the microprocessor is almost ensured, and the error is to the extent that there is no practical problem.

[Effects of the Invention] As described above, the present invention provides a detector for detecting three-phase voltage and three-phase current related to a three-phase power converter, and a detector for detecting three-phase voltage and three-phase current related to a three-phase power converter. a sample hold circuit that samples and holds an analog current detection signal; a multiplexer that sequentially selects and outputs the three-phase voltage and three-phase current analog detection signals detected by the detector one by one; ) An A/D converter that sequentially converts analog signals of three-phase voltages and three-phase currents sequentially selected by a multiplexer into digital values and outputs them;
A microprocessor that reads digital values of three-phase voltage and three-phase current that are sequentially converted by a D converter and performs control calculations using the values, the sum of the voltage values of each phase read by the microprocessor. If the sum of the current values of each phase is within a certain range centered on zero, it is determined to be normal, and if it deviates from that range, it is determined to be abnormal, so an analog detector that detects three-phase voltage and current Detection reliability is high because the failure can be detected even if any of the detection parts from the to the A/D converter fails, and it is economical because it does not require a reference signal or special hardware to detect failures. Furthermore, by determining a failure before using the three-phase voltage and current values read into the microprocessor for control calculations, it is possible to prevent malfunctions of the control device, which improves the reliability of the device. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a detector failure detection device according to the present invention, FIG. 2 is a flowchart showing its operation, and FIG. 3 is a block diagram showing a conventional detector failure detection device. . In the figure, (1) is a potential transformer, (2) is a current transformer, and (3)
is a signal adjustment circuit, (4) is a sample hold circuit, and (5
) is a multiplexer, (6) is an A/D converter, and (7) is a microprocessor.

Claims (2)

[Claims] (1) A detector that detects the three-phase voltage and three-phase current related to the three-phase power converter, and a sample hold that samples and holds the analog detection signals of the three-phase voltage and three-phase current detected by the detector. a multiplexer that sequentially selects and outputs the analog detection signals of the three-phase voltage and three-phase current detected by the detector one by one; An A/D converter that sequentially converts analog signals into digital values and outputs them; reads the digital values of three-phase voltage and three-phase current that are sequentially converted by the A/D converter, and performs control calculations using those values. a microprocessor that performs A failure detection device for a detector, characterized in that a deviation is determined to be abnormal. (2) The detector failure detection apparatus according to claim 1, wherein if the A/D converter is high-speed, a sample and hold circuit is inserted between the multiplexer and the A/D converter or omitted.