JPH0449415A - Segmentation shifter - Google Patents

Abstract

PURPOSE:To shorten a segmentation shifting processing time and to improve a signal processing speed by providing this segmentation shifter with a 2nd masking circuit for aligning a required bit number part with one logical value and a bidirectional shifter for shifting the output of the 2nd masking circuit in a required direction by the required number of bits. CONSTITUTION:The segmentation shifter is provided with the 1st and 2nd masking circuits 31, 32 for aligning a required bit number part to one logical value and the bidirectional shifter 35 for shifting the output 34 of the 2nd masking circuit 33 in a required direction by the required number of bits. Although this segmentation shifter is used for segmenting a required intermediate bit part 37 in data and shifting the part 37 into a required position, the shifter can be used also for segmenting a required bit part from the MSB side or the LSB side and shifting the segmented part to a required position. In any case, shifting operation can be attained only by one operation. Consequently, the segmentation shifting processing time can be shortened and the signal processing speed can be improved.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 10 to 14) Problems to be Solved by the Invention Means for Solving the Problems First to Third Inventions ( (Figs. 1 to 3) Functional Examples First Embodiment (Figs. 4 and 5) Second Embodiment (Figs. 6 and 7) Third Embodiment (Figs. 8 and 9) Effects of the invention [Summary] An extraction shifter used when executing a bit field instruction in a personal computer or workstation, that is, when extracting a part of data and shifting this extracted part to a desired position. Regarding the equipment used, in order to shorten the cut-out shift processing time and improve the signal processing speed, the data to be cut-out and shifted is processed by cutting a portion of the desired number of bits from the endmost bit side on one side. The first step is to perform mask processing and align the desired number of bits to one logical value.
and a second mask circuit for masking a desired number of bits from the other endmost bit side of the output of the first mask circuit and aligning the desired number of bits with the logic value of the one. and a bidirectional shifter for shifting the output of the second mask circuit by a desired number of bits in a desired direction.

[Industrial Application Field] The present invention is an extraction shifter used when executing a bit field instruction in a personal computer or a workstation. Regarding the equipment used when shifting to.

In recent years, microprocessors have been equipped with cut-out shifters to realize bit field instructions as microprocessor instructions.

``Prior Art'' Conventionally, a cutout shifter, the block diagram of which is shown in FIG. 10, has been proposed.

This cutout shifter 1 converts data into the most significant bit (hereinafter referred to as
A left shifter 2 that shifts data to the MSB (hereinafter referred to as MSB), a right shifter 3 that shifts data to the least significant bit (hereinafter referred to as LSB), and a left shifter 4 are connected in cascade. Inside the microprocessor,
For example, as shown in FIG. 11, it is arranged in the same line as an ALU (arithmetic logic unit) 5 and a BSU (barrel shifter unit) 6. In addition, 7.8 is a register, 9.10
．． 11 is a bus.

Such a cut-out shifter 1 is shown in FIG. 12, for example.
It is used when performing cut-out and shift processing as shown in the example. In the figure, 12.13 is, for example, 32 bits of data, and this signal processing example is based on C bits A and L from the MSB side of data (destination data) 12.
The middle b-bit part B is sandwiched between the C-bit part C from the SB side, and the intermediate b-bit part B is sandwiched between the C-bit part from the MSB side of data (source data) 13 and the f-bit part F from the LSB side. The purpose is to obtain new 32-bit data 14 by inserting the b-bit portion E of .

In this case, first, a mask pattern 15 is prepared.

This mask pattern 15 has a logic "1" for the C bit part from the MSB side, a logic "0" for the middle b bit part,
The C bit part from the LSB side is set to logic "1".

Therefore, the AND of data 12 and mask pattern 15 is calculated, and the C bit part A from the MSB side and the C bit part A from the LSB side are calculated.
Data 16 is obtained in which the middle b-bit part sandwiched between the bit parts C is set to logic "0".

On the other hand, data 13 is subjected to extraction shift processing using the extraction shifter 1 shown in FIG.

That is, first, data 13 is MS
The data 17 is shifted by C bits to the B side and the C bit part is set to logic "0" from the LSB side. Next, this data 17 is shifted to the LSB side by d10f bits in the rightward shifter 3, so that data 18 is obtained in which the d+f bits from the MSB side are set to logic "0". Next, this data 18 is sent to the left shifter 4 by MS
Shift C bits to the B side, set the C bit part from the MSB side to logic "0", make the logic state of the intermediate b bit part the same as data 13, and set the C bit part from the LSB side to logic "0". ” data 19 is obtained.

Therefore, next, the logical sum of data 16 and data 19 is calculated. Here, the intermediate b sandwiched between part A of C bits from the MSB side of data 12 and part C of C bits from the LSB side.
New 32-bit data 14 is created by inserting into bit part B an intermediate b-bit part E sandwiched between a C-bit part from the MSB side of data 13 and an f-bit part F from the LSB side. Obtainable.

[Problems to be Solved by the Invention] By the way, when using the conventional cutout shifter 1 shown in FIG. 10, for example, when performing the cutout shift process shown in FIG. It is necessary to perform a shift operation using the direction shifter 2, a shift operation using the right shifter 3, and a shift operation using the left shifter 4.

Furthermore, for example, as shown in FIG.
New data 20 obtained by inserting h-bit part J from the LSB side of data 13 into h-bit part H from the SB side
In order to obtain data 13, two shift operations are required for data 13, that is, each shift operation is required to obtain data 21 and 22. In addition, 23 is a mask pattern, 2
4 indicates data obtained by ANDing the data 12 and the mask pattern 23.

Furthermore, for example, as shown in FIG.
New data 25 obtained by inserting the C bit part G from the MSB side of data 13 into the C bit part G from the SB side
In order to obtain data 13, two shift operations are required for each data 13, that is, each shift operation is necessary to obtain data 26 and 27. In addition, 28 is a mask pattern, 2
One shows data obtained by ANDing the data 12 and the mask pattern 28.

In this way, when using the cut-out shifter 1 of the conventional example shown in FIG. 10, a maximum of three shifting operations and a minimum of two shifting operations are required. When carrying out a large amount of cutout and shift processing, it is desirable that the number of shift operations in the cutout shifter be as small as possible in terms of signal processing speed.

In view of the above, an object of the present invention is to provide a cutout shifter that can shorten cutout shift processing time and improve signal processing speed.

[Means for Solving the Problems] The present invention includes the first to third inventions described below, and the above object is to shift the cut out portion to any position in the middle of the data. This can be achieved by any one of the first to third inventions depending on whether the signal is shifted to the most significant bit side, the least significant bit side, or the least significant bit side.

1 Day 1 ゛As shown in FIG. 1, the extraction shifter according to the first aspect of the present invention, as shown in FIG. , MSB) from the desired number of bits,
A first mask circuit (for example, upper mask circuit) 31 for aligning this desired number of bits to one logic value (for example, logic "O"); ) 31, mask a desired number of bits from the other endmost bit (for example, LSB) side, and align this desired number of bits with one logic value (for example, logic "0"). a second mask circuit (for example, a lower mask circuit) 33, and a shifter for shifting the output 34 of the second mask circuit (for example, a lower mask circuit) 33 by a desired number of bits in a desired direction, a so-called bidirectional shifter. A shifter 35 is provided.

Second invention (FIG. 2) In the present invention, the cut-out shifter according to the second invention, as shown in FIG. 37 is located on the LSB side, a so-called rightward shifter 38, and of the output 39 of this rightward shifter 38, a portion 40 other than the cutout target portion 37 is masked, and this cutout target portion 37 is masked. It is constructed by providing a mask circuit, a so-called upper mask circuit 41, for aligning the portion 40 other than the portion 37 to one logic value, for example, logic "0".

More specifically, for example, the number P of bits one bit below the least significant bit of the extraction target portion 37 is supplied to the right shifter 38 as a shift value, and the bit number P of the most significant bit of the extraction target portion 37 is supplied as a shift value. Q and cutout target part 3
Difference between the least significant bit of 7 and the number of bits P below 1 bit Q-
It can be configured to supply P to the upper mask circuit 41 as a mask value.

3rd day (3rd) As shown in FIG. 3, the extraction shifter according to the third invention, in the data 30 that is the object of the extraction shift processing, A shifter, so-called leftward shifter 43, which shifts the data 30 so that the data 30 is located on the MSB side, and of the output 44 of this leftward shifter 43, a portion 45 other than the cutout target portion 37 is masked, and this cutout target portion is It is constructed by providing a mask circuit, a so-called lower mask circuit 46, for aligning the portion 45 other than 37 to one logic value, for example, logic "0".

In addition, more specifically, for example, the number of bits Z of the data 30 and the number of bits Q of the most significant bits of the extraction target portion 37
The difference 1-Q between them is supplied as a shift value to the leftward shifter 43, and the difference Z-Q between the number of bits Z of the data 30 and the number Q of the most significant bits of the cut-out target part 37 and the cut-out target part It can be configured such that the sum Z-Q+P of the number of bits P one bit below the 37 least significant bits is supplied to the lower mask circuit 46 as a mask value.

[Operation] The first invention is mainly used when cutting out a desired intermediate bit portion 37 of data 30 and shifting this intermediate bit portion 37 to a desired position.
It can also be used to extract a desired number of bits from the MSB side or LSB side and shift it to a desired position. In any case, one shift operation is sufficient.

In addition, in FIG. 1, 36 is the output of the bidirectional shifter 35.

The second invention is mainly used when cutting out a desired intermediate bit portion 37 or a part of the MSB side of the data 30 and positioning it on the LSB side,
One shift operation is sufficient. In addition, in FIG. 2, 42 is the output of the upper mask circuit 41.

The third invention is mainly used when cutting out a desired intermediate bit portion 37 or a part of the LSB side of the data 3o and positioning it on the MSB side,
One shift operation is sufficient. In addition, in FIG. 3, 47 is the output of the lower mask circuit 46.

[Embodiments] Hereinafter, first to third embodiments of the present invention will be described with reference to FIGS. 4 to 9.

First Embodiment (FIGS. 4 and 5) FIG. 4 is a circuit diagram showing a first embodiment of the present invention (an embodiment of the first invention).

In this embodiment, the first mask circuit, for example, the upper mask circuit 31, includes AND circuits 48 to 52 and OR circuits 53 to 55. Note that R(R3
~Ro) is the input data to be cut out and shifted, and Q (Q2 to Qo) is a signal indicating the number of bits (digits) of the most significant bit of the part to be cut out. In this embodiment, the upper mask circuit It is used as a mask value to be supplied to 31. Further, 5 (S3 to So) is the output of the upper mask circuit 31.

Here, Q can take a value from [000] to [100], and the input data R when changing Q
The relationship between S and the output S of the upper mask circuit 31 is shown in Table 1.

Table 1. Further, T (T3 to To) is the output of the lower mask circuit 33.

Here, P can take a value from [000] to [100], and the relationship between the output S of the upper mask circuit 31 and the output T of the lower mask circuit 33 when P is changed is shown in Table 2. It becomes as shown in .

Table 2 In this way, this upper mask circuit 31 passes input data R from the LSB side by the number of bits indicated by Q.
The other bit parts are masked and their logic is set to "0".

Further, a second mask circuit, for example, a lower mask circuit 33
are the AND circuits 56 to 6o, the NOT circuit 61, and the NO circuit.
It is configured by providing R circuits 62 to 64. In addition, P
(P2~Po) is 1 of the least significant bit of the part to be cut out
This signal indicates the number of bits (digits) below the bits, but in this embodiment, this signal is used as a mask value to be supplied to the lower mask circuit 33. In this way, the lower mask circuit 33 uses the word length of the input data R. The data S is passed from the MSB side by the number of bits (4-P, which is 4 bits in this example) minus P, and the other bits are masked and their logic is set to [0].

In addition, the bidirectional shifter 35 includes a 2-bit leftward shifter 5
．． A circuit consisting of a cascade connection of a 1-bit left shifter 66 and a three-stit buffer circuit array 67, a 2-bit right shifter 68, a 1-bit right shifter 69, and a three-stit buffer circuit array 70 connected in parallel. It is configured by providing circuits connected in cascade and a NOT circuit 71.

Note that Ud indicates a shift direction display signal, Ul and Uo indicate shift amount display signals, and V (V, to Vo) indicates output data.

Here, the 2-bit left shifter 65 and the 2-bit right shifter 68 are configured to perform a shift operation when Ul-1. Further, the 1-bit left shifter 66 and the 1-bit right shifter 69 are configured to perform a shift operation when Uo=1. Further, the three-state buffer circuit array 67 is turned on when Ud=O, and is turned on when Ud=O.
When Ud=1, the three-stitch buffer circuit array 70 is off, and when Ud=1, it is on, and when Ud=O, it is off.

Here, a shift direction display signal Ud, a shift amount display signal U
1. The relationship between the output T of the lower mask circuit 33 and the output data V when Uo is changed is as shown in Table 3.

Table 3 In this way, this bidirectional shifter 35 shifts the output T of the lower mask circuit 33 to the left side (MSB side) or the right side (LSB side).
This is to shift 1 bit to 3 bits.

In the first embodiment, a signal Q indicating the number of bits (digits) of the most significant bit of the part to be extracted is supplied to the upper mask circuit 1i'J31, and the signal Q indicating the number of bits (digits) of the most significant bit of the part to be extracted is supplied to the upper mask circuit 1i'J31, A signal P indicating the number of one bit (digit) is supplied to the lower mask circuit 33, and signals Ud and U1 indicating the desired shift direction and shift amount.
, Uo to the bidirectional shifter 35, a desired portion to be cut out can be shifted to a desired position.

For example, as shown in FIG. 5, input data [R3°R2
+ R1, RO], and when trying to obtain [0, R1, O, O] as output data ■, the bit (digit) of the most significant bit of the part to be extracted.
The signal Q that displays the number is [010], the signal P that displays the number of bits (digits) one bit below the least significant bit of the part to be cut out is [001], and the shift direction display signal Ud is [O]
, if the shift amount display signals U1 and Uo are set to [01], the output S of the upper mask circuit 31 becomes [0, 0, R1, Ro
], the output T of the lower mask circuit 33 is [0, 0, R1,
O], and the output data ■ is [0, R1, O, O]
can be obtained.

Similarly, on the premise that the input data R is 4 bits 1 to 20, a desired portion of the input data R can be cut out and this portion can be shifted to a desired position. Furthermore, only one shift operation is required. Incidentally, in the case of the conventional example shown in FIG. 10, three shift operations are required.

2 (FIGS. 6 and 7) FIG. 6 is a circuit diagram showing a second embodiment of the present invention (an embodiment of the second invention).

In this embodiment, the right shifter 38 is configured by connecting a 4-bit right shifter 72, a 2-bit right shifter 73, and a 1-bit right shifter 74 in series. In addition, in this embodiment, a signal P (P2 to P
a) is used as the shift value to be supplied to the rightward shifter 38.

Here, when the 4-bit rightward shifter 72 is R21,
It is configured to perform a shift operation. Furthermore, the 2-bit right shifter 73 is configured to perform a shift operation when P1=1. Further, the 1-bit rightward shifter 74 is set to P.

When it is 1, it is configured to perform a shift operation.

Note that the relationship between the input data R and the output W of the rightward shifter 38 when P is changed is as shown in Table 4.

Table 4 QP is supplied as a mask value via the subtractor 83. Here, Q-P-X (X2~X
o), the relationship between the output W of the rightward shifter 38 and the output data V when the mask value X is changed is as shown in Table 5.

Table 5 As described above, the right shifter 38 shifts the input data R to the right (LSB side) by 1 bit to 4 bits.

Further, the upper mask circuit 41 is configured by providing AND circuits 75 to 79 and OR circuits 80 to 82, and this upper mask circuit 41 has three pins. The data W is passed from the LSB side by the number of bits indicated by the mask value X, and the other bits are masked and their logic is set to "0".

In the second embodiment, a signal P indicating the number of bits (digits) one bit below the least significant bit of the portion to be cut out is supplied to the right shifter 38 and the 3-bit subtractor 83, and The bits of the most significant bit of (
By supplying the digit>number Q to the 3-bit subtracter 83, it is possible to extract a portion to be extracted from the input data R and shift it to the LSB side. Moreover, this can be done in one shift operation.

For example, as shown in FIG. 7, input data [R3°R2
, R1, RO] to obtain [0, 0, 0, R2] as the output data ■, the bit (digit) 1 bit below the lowest bit of the part to be extracted ), the output W of the rightward shifter 38 becomes [0°0]. , R3, R2], and [00, O, R2] can be obtained as output data (2).

Similarly, on the premise that the input data R is 4 bits, a desired portion of the input data R can be extracted and this portion can be shifted to the LSB side. Furthermore, only one shift operation is required. Incidentally, in the case of the conventional example shown in FIG. 10, two shift operations are required.

Third Male Side (FIGS. 8 and 9) FIG. 8 is a circuit diagram showing a third embodiment of the present invention (one embodiment of the third invention).

In this embodiment, the left shifter 43 is configured by connecting a 1-bit left shifter 84, a 2-bit left shifter 85, and a 1-bit left shifter 86 in series.

Here, Q2 is supplied to the 1-bit left shifter 84, and this 1-bit left shifter 84 is configured to perform a shift operation when Q2=O. Further, the 2-bit left shifter 85 is supplied with the logical sum Q2+Q1 of Q2 and Ql via the OR circuit 87, but the 2-bit left shifter 85 is configured to perform a shift operation when Q2+Q1=O. ing. Additionally, a 1-bit left shifter 86
is the logical sum Q2+ of Q2 and Qo via the OR circuit 88.
QO is supplied, and the 2-bit left shifter 86 is configured to perform a shift operation with Q2+QO=O. Note that the circuit 99 including the OR circuits 87 and 88 constitutes a (4-Q) arithmetic unit.

Here, the relationship between the input data R and the output data W of the leftward shifter 43 when Q is changed is shown in Table 6.

Table-6 ~93, NOT circuit 94, NOR circuit 95~97
The lower mask circuit 46 is supplied with 4Q+P as a mask value via a 3-bit subtracter 98. Here, 4 Q
In the case where +P=Y (Y2 to Yo), the relationship between the output W of the leftward shifter 43 and the output data V when the mask value Y is changed is as shown in Table 7.

Table 7 In this way, this leftward shifter 43 shifts input data R to the right side (LSB side) by 1 bit to 4 bits, depending on Q.
It is a shift.

Furthermore, the lower mask circuit 46 is connected to the AND circuit 89. In this way, the lower mask circuit 46 passes the output W of the leftward shifter 43 from the MSB side only by QP, masks the other bit parts, and logic It is set to "0".

In the third embodiment, a signal P indicating the number of bits (digits) one bit below the least significant bit of the part to be cut out is supplied to the 3-bit subtracter 98, and a signal P indicating the number of bits (digits) one bit below the least significant bit of the part to be cut out is supplied to the 3-bit subtracter 98; By supplying the number of bits (digits) Q to the 3-bit subtracter 98 and nine (4-Q) arithmetic units, it is possible to extract a portion to be extracted from the input data R and shift it to the MSB side. However, this can be done in one shift operation.

For example, as shown in FIG. 9, input data [R3R2,
Rt, Ro] to obtain [R2, R1, O, O] as output data ■, the bit (digit) 1 bit below the lowest bit of the part to be extracted. If the signal P that displays the number is set to [001] and the signal Q that displays the number of bits (digits) of the most significant bit of the part to be extracted is set to [011], the output W of the left shifter 43 becomes [R2°R1 , RO, O], and [R2°R1, O, O] can be obtained as the output data V.

Similarly, on the premise that the input data R is 4 bits, a desired portion of the input data R can be extracted and this portion can be shifted to the MSB side. Moreover, only one shift and toggle operation is required. Incidentally, in the case of the conventional example shown in FIG. 10, two shift operations are required.

[Effects of the Invention] According to the first aspect of the present invention, when a desired portion of data to be subjected to cut-out and shift processing is cut out and this portion is shifted to a desired position, a single shift operation is performed. , since this can be done, when using this first invention when performing this type of cut-out shift processing, it is possible to shorten the cut-out shift processing time and improve the signal processing speed. can.

According to the second aspect of the present invention, a desired part of the data to be subjected to the cut-out and shift processing is cut out, and this part is transferred to the LS.
When shifting to the B side, this can be done with one shift operation, so when using this second invention when performing this type of cut-out shift processing,
It is possible to shorten the cut-out shift processing time and improve the signal processing speed.

According to the third aspect of the present invention, a desired portion of the data to be subjected to the cut-out and shift processing is cut out, and this portion is transferred to the MS.
When shifting to the B side, this can be done with one shift operation, so when using this third invention when performing this type of cut-out shift processing,
It is possible to shorten the cut-out shift processing time and improve the signal processing speed.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the first invention, Fig. 2 is an explanatory diagram of the principle of the second invention, Fig. 3 is an explanatory diagram of the principle of the third invention, and Fig. 4 is a circuit showing the first embodiment. 5 is a diagram showing an example of the operation of the first embodiment, FIG. 6 is a circuit diagram showing the second embodiment, FIG. 7 is a diagram showing an example of the operation of the second embodiment, and FIG. 8 is a diagram showing an example of the operation of the second embodiment. is a circuit diagram showing the third embodiment, FIG. 9 is a diagram showing an example of the operation of the third embodiment, FIG. 10 is a block diagram showing a conventional cut-out shifter, and FIG. 11 is a microprocessor with a built-in cut-out shifter. 12 is a diagram showing an example of the cut-out shift process, FIG. 13 is a diagram showing another example of the cut-out shift process, and FIG. 14 is a diagram showing still another example of the cut-out shift process. It is a diagram. (In FIG. 1) 30... Data to be cut out and shifted 31... First mask circuit (upper mask circuit) 33.
...Second mask circuit (lower mask circuit) 35...Bidirectional shifter 36...Output data (in Fig. 2) 38...Rightward shifter 41...Upper mask circuit 42...Output data (In Fig. 3) 43...Leftward shifter 46...Lower mask circuit 47...Output data

Claims (1)

[Claims] 1. For the data (30) to be cut out and shifted, a desired number of bits is masked from one endmost bit side, and the desired number of bits is set to one logical value. A first mask circuit (31) for alignment, and a desired number of bits of the output (32) of the first mask circuit (31) are masked from the other endmost bit side, and the desired bits are a second mask circuit (33) for aligning the number part to the one logical value; and a bidirectional shifter for shifting the output (34) of the second mask circuit (33) by a desired number of bits in a desired direction. (35
). 2. Among the data (30) that is the target of the cut-out and shift processing,
a rightward shifter (38) for shifting the data (30) so that the extraction target portion (37) is located on the least significant bit side; It is configured by providing an upper mask circuit (41) for masking a portion (40) other than the target portion (37) and aligning the portion (40) other than the cutout target portion (37) to one logical value. A cut-out shifter characterized by: 3. The number of bits (P) one bit below the least significant bit of the cut-out target portion (37) is supplied as a shift value to the rightward shifter (38), and the cut-out target portion (
37) and the number of bits (P) 1 bit below the least significant bit of the cutout target portion (37), using the difference (Q-P) as a mask value for the upper mask. The cut-out shifter according to claim 2, characterized in that it is configured to be supplied to a circuit (41). 4. Among the data (30) that is the target of the cut-out and shift processing,
a leftward shifter (43) for shifting the data (30) so that the cutout target portion (37) is located on the most significant bit side; It is configured by providing a lower mask circuit (46) for masking a portion (45) other than the target portion (37) and aligning the portion (45) other than the cutout target portion (37) to one logical value. A cut-out shifter characterized by: 5. The left shifter (4) uses the difference (Z-Q) between the number of bits (Z) of the data (30) and the number of most significant bits (Q) of the cutout target portion (37) as a shift value.
3), and the difference (Z-Q) between the number of bits (Z) of the data (30) and the number of bits (Q) of the most significant bit of the part to be cut out (37), and the number of bits to be cut out. The number of bits one bit below the least significant bit of part (37) (
5. The cut-out shifter according to claim 4, wherein the cutout shifter is configured to supply the sum (Z-Q+P) of P) to the lower mask circuit (46) as a mask value.