JP2507183B2 - Floating point addition / subtraction unit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to IEEE (Th
e institute of Electroical and Electronics Enginee
rs) standard floating-point adder / subtractor circuit.

2. Description of the Related Art According to the IEEE754 standard, a normalized number and a denormalized number for 32-bit floating point format data are defined as shown in equation (1).

Normalized number (-1) ^S 2 ^E-127 (1.F) Denormalized number (-1) ^S 2 ^O-126 (1.F) (1) where S is the sign value and E is biased Index value before
F represents a mantissa value below the decimal point. However, E is a number of 1 or more. S is 1 bit, E is 8 bits, F is 23
Expressed in bits. From the equation (1), it can be seen that the exponent value of the denormalized number is 0, and the bias value of the exponent value differs by 1 between the normalized number and the denormalized number.

FIG. 3 is a block diagram of a conventional floating point addition / subtraction device. The two input operands are X and Y, and the sign part, exponent part, and mantissa part of each are Xs, Ys, Xe, Ye, and Xf, Yf. The denormalized number detection circuit 301 uses the operand exponent part (Xe, Y
It is a circuit that inputs e) and detects whether or not each is a denormalized number. The swap circuit 302 is a circuit which inputs an operand mantissa part (1.Xf or 0.Xf, 1.Yf or 0.Yf) and outputs it as it is or swaps and outputs it. The subtraction circuit 303 is a circuit that subtracts the operand exponent part (Xe, Ye) and outputs the absolute value (| Xe−Ye |) and the sign (S (Xe−Ye)). The subtraction circuit 304 is a circuit that subtracts 1 from the absolute value (| Xe−Ye |). The right barrel shift circuit 305 is
It is a circuit that shifts the input value from the data line L32 to the right by any number of bits up to 24 bits. The right shift circuit 306 is
Input value from the data line L31 and the right barrel shift circuit 305
The output value (data value L33) is shifted to the right by one digit based on the signal from the shift signal generation circuit 310 (the signal indicating addition), or is output as it is. The adder / subtractor circuit 307 is a circuit that adds or subtracts the output value of the right shift circuit 306 to perform rounding processing. Left shift circuit 308
Is a circuit that shifts the output value (data line L34) of the adder / subtractor circuit 307 to the left by 1 bit or outputs it as it is. The multiplexers 309 and 311 are 2-input / 1-output selectors. The shift signal generation circuit 310 is a circuit that outputs a signal that the execution operation is addition based on the code values (Xs, Ys) of the two input operands and the subtraction execution signal sub. The adder / subtractor circuit 312 determines whether to perform addition or subtraction based on the signal output from the shift signal generation circuit 310, and if it is addition, the exponent value output from the multiplexer 311 and "0" are set. And the addition of the exponent value and "1" are executed in parallel, and then either is selected by the signal (L35) output from the addition / subtraction circuit 307.

Next, the operation of the conventional example shown in FIG. 3 will be described. The two input operand exponents (Xe, Ye) are subtraction circuits 3
03, the denormalized number detection circuit 301, and the multiplexer 311. At the same time, the mantissa of the operand (1.Xf or 0.
Xf, 1.Yf or 0.Yf) is also input to the swap circuit 302. First, in the subtraction circuit 303, the shift amount | Xe−Ye | of the operand mantissa part for making the exponent values the same and the sign S (Xe
−Ye) is calculated. When the two operands are normalized numbers or denormalized numbers, the bias value in the exponent part is the same between the two operands (normalized as shown in equation (1)). The number of shifts to the shift circuit 305 is
It becomes | Xe−Ye |. This is calculated by the subtraction circuit 303. However, when one of the two operands is a normalized number and the other is a denormalized number, the bias value of the exponent part differs by 1 between the normalized number and the denormalized number as shown in equation (1). The shift amount of the mantissa of the operand to make the values the same is | Xe
Must be −Ye | -1. That is, the subtraction circuit 303
It is necessary to correct the output value of. For example, assuming that the operand X is a normalized number and the operand Y is a denormalized number, this is shown in the equation (2).

X = (-1) ^Xs 1.Xf * 2 ^Xe-127 Y = (-1) ^Ys 0.Yf * 2 ^O-126 (2) At this time, the right hand side of the mantissa part of the operand Y calculated by the subtraction circuit 303 The shift amount is “| Xe−0 |”. However, in the operands X and Y, the bias values of the exponent part are different by 1 between "-127" and "-126". Therefore, the mantissa part "0.Yf" of the operand Y is right-shifted by "| Xe-0 |", and the exponent part "-126"
Even if "| Xe-0 |" is added to, the exponent parts of the operands X and Y do not become the same. In order to make the exponents of the operands X and Y the same, from the right shift amount | Xe-0 |
Therefore, the mantissa must be right-shifted by this value. Although the case of addition has been described above, the same can be said when subtracting two operands. That is, the subtraction circuit 304 corrects the shift amount of the operand mantissa part for making the exponent values the same when executing addition and subtraction of the normalized number and the denormalized number.

At the same time that the subtraction circuit 303 executes the exponential part subtraction, the denormalized number detection circuit 301 detects whether the operands X and Y are denormalized numbers. operand
If the exponent part of X and Y is 0, it is a denormalized number. If either one of the operands is a denormalized number, the multiplexer 309 outputs the output from the subtraction circuit 304 (| Xe
-Ye | -1) is selected. Also, if both operands are normalized or denormalized, the multiplexer
In 309, select the output (| Xe−Ye |) from the subtraction circuit 303,
The shift amount input to the right barrel shift circuit 305 is determined.

The multiplexer 311 selects and outputs the larger one of Xe and Ye based on the sign S (Xe-Ye) of the exponent subtraction value output from the subtraction circuit 303. This larger index value becomes a candidate for the index value of the addition / subtraction result.

Next, the operand mantissa part (1.Xf or 0.Xf, 1.Yf or 0.Yf) will be described. The operand mantissa part is a code S (Xe calculated by the subtraction circuit 303 in the swap circuit 302.
-Ye) swaps as follows: When Xe-Ye is positive or 0 (S (Xe-Ye)> = 0), the X operand (1.Xf or 0.Xf) is on the data line L31 and the Y operand (1.Yf or 0.Xf). Yf) is output to the data line L32. When the value is negative (S (Xe-Ye) <0), the input value is swapped and output. The data line L31 output from the swap circuit 302 is input to the right shift circuit 306 as it is, and the data line L32 is input to the right barrel shift circuit 305.

From the operation described above, a problem will be described below. Right barrel shift circuit from the time of two operand inputs
See the data delay up to 305. Operand mantissa (1.X
f or 0.Xf, 1.Yf or 0.Yf) is the right barrel shift circuit 3
The longest path until it is input to 05 is the swap circuit that obtains the sign (S (Xe-Ye)) of the difference in exponent values with the subtraction circuit 303
This is a path for controlling 302 and inputting to the right barrel shift circuit 305 one of the operand mantissa data having the smaller exponent value.

In addition, the longest path until the shift amount data is input to the right barrel shift circuit 305 uses the subtraction circuits 303 and 304 to calculate | Xe−Ye | −1, and multiplex this value.
It is a path that passes through 309 and is input to the right barrel shift circuit 305. Obviously, the latter path for calculating the shift amount has two delay stages because it passes through two subtraction circuits. That is, as described above, in the conventional floating-point addition / subtraction device, since two subtraction circuits are used to calculate the shift amount for digit alignment, the operation time becomes long and the circuit of the entire device becomes complicated and growing. In addition, there is a drawback that the power consumption increases as the circuit scale increases.

The operation of the conventional example will be further described below. The right shift circuit 306 is a data line based on the shift signal from the shift signal generation circuit 310 (this is a signal indicating addition).
This is a circuit for shifting the data of the L31 and the data line L33 to the right by one digit. The right shift circuit 306 is a circuit that corrects the deviation of the rounding position that occurs after the addition and subtraction of the data input from the data lines L31 and L33 by the addition / subtraction circuit 307.
The operation of the right shift circuit 306 will be described below.

There are three patterns in total when executing addition and subtraction.

Normalized number ± Normalized number (3-1) Normalized number ± Denormalized number (3-2) Denormalized number ± Denormalized number (3-3) Right shift when the above three patterns are executed Circuit 306
The case of not using is described below.

When the addition is executed in (3-1), (3-2), and (3-3), the result before the rounding process in the adder / subtractor circuit 307 is as follows. In the case of (3-1) and (3-2), the result before rounding is that the “1” at the top of the mantissa part is as shown in (4-1) and (4-2). It is in the state of being in the second digit higher than the decimal point or in the first digit higher than the decimal point. In the case of (3-3), the results before the rounding process are the same as those shown in (4-3) and (4-4).

1 *. ＊＊＊ －－－－ ＊ × 2 ^Xe-127 (4-1) 1. ＊＊＊ －－－－ ＊＊ × 2 ^Xe-127 (4-2) 1. ＊＊＊＊ －－－ ＊ * × 2 ^O-126 (4-3) 0. **** ---- * × 2 ^O-126 (4-4) Also, (3-1), (3-2), (3-3) ), The result before rounding is as follows. (3
-1) and (3-2), (5-1), (5-2),
As shown in (5-3), "1" is displayed in the first digit higher than the decimal point.
, Or "1" in the first digit lower than the decimal point, or "1" exists in the second digit lower than the decimal point for the first time. Further, in the case of (3-3), it is always a denormalized number like (5-4).

1. ＊＊＊＊ －－－ ＊＊ × 2 ^Xe-127 (5-1) 0.1 ＊＊＊ －－－ ＊＊ × 2 ^Xe-127 (5-2) 0.0 ＊＊＊ －－－ ＊＊ × 2 ^Xe-127 (5-3) 0. **** --- *** 2 ^O-126 (5-4) That is, as mentioned above, when the result of addition and subtraction becomes a normalized number. , The position where the numerical value "1" comes to the highest is 1
You can see that the numbers are off. This means that when the result is rounded to the number of significant digits, the position where the addition result is rounded is different from the position where the subtraction result is rounded. That is, it is necessary to provide a circuit for rounding for each of addition and subtraction, which causes an increase in hardware. This is obviously advantageous when the positions of rounding carry are the same in addition and subtraction and only one rounding processing circuit is used. For this reason, it is necessary to perform a process of digitizing one of the addition result and the subtraction result with the other result. In this conventional example, the shift signal generation circuit 310 determines the type of operation, the right shift circuit 306 shifts the input operand to the right by 1 bit in the case of addition, and the alignment is performed so that the rounding position is the same as the result in the case of subtraction. And By doing so, the addition result before rounding becomes as shown in equation (4) to equation (6),
The subtraction result before the rounding process and the rounding position can be made the same.

1. ＊＊＊＊ －－－ ＊ × 2 ^{Xe-127 + 1} (6-1) 0.1 ＊＊＊ －－－ ＊＊ 2 ^{Xe-127 + 1} (6-2) 0.1 ＊＊＊ －－ − ** × 2 ^{Xo-126 + 1} (6-3) 0.0 *** −−− ** × 2 ^{O-126 + 1} (6-4) At this time, since the addition operand is right-shifted,
The index value apparently increases by "+1". The correction of the increase in the index value will be described later. As described above, the right shift circuit 306 plays the role of making the rounding position the same as that of the subtraction by shifting the input operand right by one digit in the case of addition.

The data output from the right barrel shift circuit 305 is input to the addition / subtraction circuit 307, rounded after addition / subtraction, and the result is output to the data line L34. Further, the value of the first digit higher than the decimal point of the addition / subtraction result is output to the data line L35.

After that, the left shift circuit 308 and the addition / subtraction circuit 312 are used,
The normalization processing of the calculation result is executed. At the time of this normalization processing, the exponent value at the time of addition is corrected.

On the data line L34, the calculation result as shown in the mantissa part of the equations (5) and (6) is output. However, strictly speaking, expressions (5) and (6) are values before the mantissa part is rounded, but after rounding, any of these data formats will be used, so use these values. To do. The normalization processing will be described below for the case of addition and the case of subtraction.

In the case of addition, as shown in (6-1), when there is 1 in the first digit higher than the decimal point (data line L35 = 1), the left shift circuit 308 keeps the data (mantissa value) of the data line 34 as it is. Output. On the other hand, the exponent value is Xe + in the adder / subtractor circuit 312.
Execute 1 and output. By doing so, the bias value of the exponent value becomes "-127" and the mantissa value becomes "1. ***".
Is output in the normalized number format. Then (6
-2), (6-3), (6-4), when there is 0 in the first digit higher than the decimal point (data line L35 = 0, in the left shift circuit 308, the data of the data line L34 ( The mantissa value is shifted left one digit and output, while the exponent value is added and subtracted
At 312, Xe + 0 is executed and output. By doing this,
Normalization processing is executed for (6-2), and (6-
4) is output as a denormalized number by this processing.
For (6-3), the data is normalized in the next cycle using another hardware.

In the case of subtraction, as shown in (5-1), when “1” exists in the first digit higher than the decimal point (data line L35 = 1), the left shift circuit 308 changes the data (mantissa value) of the data line L34. Output without shifting. On the other hand, in the addition / subtraction circuit 312, the subtraction X
e-0 is executed, output as an exponent value, and the normalization processing is realized. When "0" exists in the first digit higher than the decimal point (data line L35 = 0) like (5-2), (5-3), (5-4), the left shift circuit 308 outputs the data. Line L34
Shift the data (mantissa value) by 1 digit to the left. On the other hand, the addition / subtraction circuit 312 executes subtraction Xe-1. By doing so, the normalization process is executed for (5-2).
Regarding (5-3) and (5-4), the normalization process or the non-normalization process is executed on the data in the next cycle by using another hardware.

From the above, it is clear that the right shift circuit 306 required for making the rounding positions the same in the case of addition and subtraction is in the critical path as seen from the whole floating-point addition / subtraction apparatus. That is, since the right shift circuit 306 is present, there is a drawback that the operation speed of the floating point adder / subtractor is further reduced.

Problems to be Solved by the Invention In a conventional floating-point adder / subtractor, two subtraction circuits are required for digit alignment, which slows down the operation speed, complicates the circuit, and increases the circuit scale. Was becoming. Also, to match the positions when adding and subtracting. The right shift circuit had to be placed in the critical path, which further slowed down the calculation speed.

In view of the above problems, the present invention uses only one subtraction circuit for calculating the shift amount for digit alignment by placing the left and right shift circuits in front of the right barrel shift circuit, and the circuit is simple. It is an object of the present invention to provide a floating point addition / subtraction device that consumes less power and requires less calculation time.

Means for Solving the Problems The present invention provides a floating-point addition / subtraction device that adds or subtracts two operand data in a floating-point format consisting of a mantissa part operand, an exponent part operand, and a sign part operand. Is a normalized number, a denormalized number, or whether the execution operation is addition or subtraction, the mantissa operand before the addition and subtraction of the two mantissa operands. Is a floating point addition / subtraction device having shift means for not shifting or shifting by one digit to the right or left.

The present invention has the above-described configuration, and therefore only one subtraction circuit for calculating the operand mantissa shift amount needs to be used, and a shift circuit for making the rounding processing positions the same for addition and subtraction is included in the critical path. A floating point adder / subtractor is realized.

Embodiment 1 FIG. 1 is a block diagram of a floating point adder / subtractor according to the first, second and fourth claims.

The two input operand exponents (Xe, Ye) are subtraction circuits 10
4, input to the denormalized number detection circuit 101. At the same time, the mantissa part of the operand (1.Xf or 0.Xf, 1.Yf or 0.Yf)
Is also input to the left / right shift circuit 103. Then, the subtraction circuit 104 subtracts the operand exponent values Xe and Ye to obtain an absolute value | X.
e−Ye | and the code value S (Xe−Ye) are calculated. Further, the denormalized number detection circuit 101 detects whether or not each input operand is a normalized number, and outputs a signal (NORX, NORY) that the two operands are normalized numbers.

The two detection signals (NORX, NORY) output from the denormalization number detection circuit 101 are input to the shift signal generation circuit 102, and the operand code values (Xs, Ys) and the subtraction execution signal sub
Along with this, control signals (Rx, Ry, Lx, Ly, Nx, Xy) for shifting the two input operand mantissa values to the left or right by one digit are created. The left / right shift circuit 103 shifts the two input operand mantissas to the right or left based on the control signals (Rx, Ry, Lx, Ly, Nx, Xy) from the shift signal generation circuit 102. Left and right shift circuit
The output of 103 swaps the input data (Xf ', Yf') based on the code (S (Xe-Ye)) output from the subtraction circuit 104 in the swap circuit 105, and the right barrel shift circuit 106 and the addition / subtraction circuit. Output to 107 (Xf ″, Yf ″).

The right barrel shift circuit 106 shifts the input value to the right by the absolute value | Xe−Ye | of the difference between the operand exponent values output from the subtraction circuit 104. After the addition / subtraction circuit 107 executes addition / subtraction and rounding processing, the left shift circuit 108 outputs the output value of the addition / subtraction circuit 107 to the first digit (data line L).
When "1" does not exist in 18), the output value of the addition / subtraction circuit 107 is shifted to the left by one digit and output.

For the exponent, the subtractor circuit 1
Using the code value S (Xe-Ye) output from 04, select the one with the larger exponent value. Then, the output of the multiplexer 109 is input to the adder / subtractor circuit 110, and the operation of the adder / subtractor circuit 110 is determined (addition or subtraction) based on the execution operation signal (Add) output from the shift signal generation circuit 102. When it is determined that the operation of the adder / subtractor circuit 110 is addition, the result of adding "1" to the exponent value and the result of adding "0" are generated in parallel. Then, either the addition / subtraction result is selected and output by the data line L18 output from the addition / subtraction circuit 107. The data line L18 is a signal that the first digit higher than the decimal point of the result of the adder / subtractor circuit 107 is "1".

Next, an outline of the present invention will be given. As shown in the conventional example, the rounding position is shifted by one digit when the mantissa part is added and when the mantissa part is subtracted. According to the present invention, the addition result is matched with the subtraction result, the rounding position is made the same for addition and subtraction, and the shift amount for shifting the mantissa operand having the smaller exponent value necessary for digit matching is set to one subtraction circuit. The left / right shift circuit 103 is controlled as required by. The control of the left / right shift circuit 103 and the fact that the mantissa shift amount is obtained by one subtraction circuit will be described below.

Here, for simplicity, as mentioned above, 32-bit IEEE754
The case where standard floating point data is used is shown. First, from the case of addition, (3-1), (3-2), (3-
3) will be described.

When the case of addition of the normalized numbers of (3-1) is expressed in an expression, it becomes as shown in expression (7). However, * is 0 or 1
And Xe> = Ye. This condition also applies to all the following expressions. Also, since both operands are normalized numbers, Xe and Ye are not 0.

1. ＊＊＊＊ －－－ ＊＊ × 2 ^Xe-127 +) 1. ＊＊＊＊ －－－ ＊＊ × 2 ^Ye-127 －－－－－－－－－－－－－－－－ −−−−−−−−−
-(7) At this time, as the addition result, two kinds of results are obtained as in the equations (8-1) and (8-2).

1 *. ＊＊＊＊ －－－ ＊＊ × 2 ^Xe-127 (8-1) 1. ＊＊＊＊ －－－ ＊＊ × 2 ^Xe-127 (8-2) When adding normalized numbers , The digit with 1 in the highest digit exists in the second and first digits higher than the decimal point. Therefore, in order to match the rounding position with the subtraction result, the left and right shift circuits 103 shift the input operand mantissa parts to the right by one digit in advance respectively, and apparently set the exponent bias value to −.
Leave it at 126. At this time, since the exponent bias values are the same, the right shift amount of the mantissa part for executing the digit alignment of the exponent part may remain as | Xe−Ye |, which is calculated by the subtraction circuit 104.

The addition of the normalized number and the denormalized number in (3-2) will be described. The formula is as shown in formula (9).

1. ＊＊＊ －－－ ＊＊ × 2 ^Xe-127 +) 0. ＊＊＊＊ －－－ ＊＊ × 2 ^O-126 －－－－－－－－－－－－－－－ −−−−−−−−−
-(9) At this time, as the addition result, two kinds of results are obtained as in the equations (10-1) and (10-2).

1 *. ＊＊＊＊ －－－ ＊＊ × 2 ^Xe-127 (10-1) 1. ＊＊＊＊ －－－ ＊＊ 2 ^Xe-127 (10-2) That is, also at this time (8-1) , (10-2), and in order to make the rounding positions the same as in the case of subtraction, it is necessary to shift the input operand mantissa part by the left and right one-digit shift circuit 103. Here, only the operand mantissa input value (1.Xf) of the normalized number is shifted to the right by one digit. That is, (9)
The formula is as shown in formula (11).

0.1 *** −−− * ×× 2 ^{Xe-127 + 1} +) 0. **** −−− * ×× 2 ^O-126 −−−−−−−−−−−−−−−−− −−−−−−−−−
-(11) By performing the equation (11), the position where "1" exists in the highest order of the addition result becomes equal to the subtraction result. At the same time, the exponential bias value is apparently "-126" for both the normalized number and the denormalized number, and therefore the mantissa operand right shift amount required for digit alignment is | Xe-0 |. This is calculated by the subtraction circuit 104.

(3-3) Addition of denormalized numbers and denormalized numbers will be described. The formula is as shown in formula (12).

0. **** --- *** 2 ^O-126 +) 0. **** --- ** 2 ^O-126 -------------------- −−−−−−−−−
-(12) At this time, the addition result is either a denormalized number or (1
You can get the normalized number like the formula 3).

1. ＊＊＊＊ －－ ＊＊ × 2 ^1-127 (13) At this time, the rounding position is the same as in the case of subtraction without shifting the input operand mantissa by the left / right shift circuit 103. ing. Also, the exponent bias value is the same as "-126", so the mantissa shift amount for digit alignment is | 0-0 |
Which is calculated by the subtraction circuit 104.

As described above, when the addition is executed, the left and right shift circuit 103 shifts the mantissa part operand of the normalized number to the right by one digit, so that the subtraction result and the rounding position can be the same, and the bias value of the exponent part is Apparently set to "-126". By doing so, the shift amount when right-shifting the mantissa operand having the smaller exponent value in the subsequent digit alignment processing is obtained by simply taking the absolute value of the difference between the two exponent operands.

 Next, the case of subtraction will be described.

First, (3-1) the normalized number and the subtraction of the normalized number will be described. The formula is as shown in formula (14).

1. ＊＊＊＊ －－－ ＊＊ × 2 ^Xe-127 －) 1. ＊＊＊＊ －－－ ＊＊ × 2 ^Ye-127 －－－－－－－－－－－－－－－ −−−−−−−−−
-(14) At this time, the subtraction result is two kinds of results as in the expressions (15-1) and (15-2), or is a denormalized number.

1. ＊＊＊＊ －－－ ＊ × 2 ^Xe-127 (15-1) 0.1 ＊＊＊ －－－ ＊＊ × 2 ^Xe-127 (15-2) Since it is not necessary to shift the input operand and the exponent bias value is the same, the shift amount for aligning the exponent part is | Xe
−Ye | This is calculated by the subtraction circuit 104.

Subtraction of the normalized number and the non-normalized number in (3-2) will be described. The formula is as shown in formula (16).

1. ＊＊＊ －－－ ＊＊ × 2 ^Xe-127 －) 0. ＊＊＊＊ －－－ ＊＊ × 2 ^O-126 －－－－－－－－－－－－－－－－ −−−−−−−−−
-(16) At this time, the subtraction result becomes two kinds of results as in the equations (17-1) and (17-2) or a denormalized number.

1. ＊＊＊＊ －－－ ＊ ×× 2 ^Xe-127 (17-1) 0.1 ＊＊＊ －－－ ＊＊ × 2 ^Xe-127 (17-2) In equation (16), two input operands are used. Has a bias value of 1
Since it is different, the mantissa part of the denormalized number is left-shifted by one digit. Then, equation (16) becomes equation (18).

1. ＊＊＊ －－－ ＊＊ × 2 ^Xe-127 －) ＊. ＊＊＊＊ －－－ ＊ 0 × 2 ^O-126-1 －－－－－－－－－－－－－－－－－－－－－－－－
-(18) As a result of mantissa subtraction from Eq. (18), the value will be as shown in Eq. (17). Therefore, by the left / right shift circuit 103,
By shifting the mantissa part of the denormalized number to the left by one digit, the mantissa part shift amount for digit alignment is apparently a bias value (-12
Since 7) is the same, | Xe−0 |
Calculated as 104.

The denormalization of (3-3) and the subtraction of the denormalization will be described. The formula is as shown in formula (19).

0. **** --- *** × 2 ^O-126- ) 0. **** ---- *** 2 ^O-126 ----------------------- −−−−−−−−−
-(19) At this time, the denormalized number is always obtained as the subtraction result. In this case, there are two methods of controlling the left / right shift circuit 103. First, do not shift the mantissa operand,
The second method is to shift both mantissa operands to the left.

First, the case where the first method is executed will be described. When the input operand mantissa is not shifted by the shift circuit 103, the exponent bias value is "-126", which is the same.
At this time, the mantissa shift amount for aligning the digits of the exponent is | 0
It may be −0 | and is executed by the subtraction circuit 104.

The second method is as follows. Shift circuit
To shift the operand mantissa input in 103 to the left,
The exponential bias value is apparently the same at "-127". At this time, the mantissa shift amount for aligning the exponent part is | 0.
−0 | In this case, it becomes as shown in Expression (20).

*. *** ---- * ^{0x2 O-126-1-} ) *. ＊＊＊＊ －－－ ＊ 0 × 2 ^O-126-1 －－－－－－－－－－－－－－－－－－－－－－－－
− (20) As can be seen from Eq. (20), the exponential bias value is apparent −
It becomes 127. Since the result of subtraction between denormalized numbers is always a denormalized number, the mantissa part is shifted to the right by one digit with respect to the result output from the addition / subtraction result 107 so that the bias value of the exponent part becomes −126. I have to That is, after the adder / subtractor circuit 107, a right one digit shift circuit for shifting the mantissa part one digit to the right becomes necessary. This causes an increase in hardware and an increase in calculation time. Therefore, in the present embodiment, the first method, that is, both operands are denormalized numbers, and in the case of subtraction, the left and right shift circuit 103 operates without shifting the mantissa operand.

When the subtraction is executed, by operating the left-right shift circuit 103 as described above, the shift amount when right-shifting the mantissa operand having the smaller exponent value in the digit alignment process is only two exponent parts. It can be calculated simply by taking the absolute value of the difference between the operands.

Above, operation type (addition, subtraction), input operand type (normalized number, denormalized number), input operand mantissa shift direction (right shift, left shift, no shift), shift required for digit alignment Figure 2 shows a table of the quantities. In FIG. 2, 201 is a type of operation and indicates whether the operation to be executed is addition or subtraction. This is obtained from the sign (Xs, Ys) of the operand and the subtraction signal sub. That is, the expression that the execution operation is addition is the logical expression shown in Expression (21).

This signal is the signal line indicated by Add in FIG.

The input operand type 202 indicates whether or not the two input operands (X, Y) are denormalized numbers. This is determined by whether or not each operand exponent value is 0, and is executed by the denormalized number detection circuit 101. If the operand exponent value is 0, it is a denormalized number. 203 is
It shows how the left / right shift circuit 103 operates according to the operation type 201 and the input operand type 202. N indicates no shift, R indicates right shift by one digit, and L indicates left shift. This is the signal lines Rx, Ry, Lx.Ly, Nx, Ny in FIG. Reference numeral 204 indicates the shift amount of the right barrel shift circuit 106. This is | Xe-Ye | output from the subtraction circuit 104 in FIG.

Next, the logic of the circuit shown in FIG. 1 is assembled. The denormalized number detection circuit 101 is a circuit that detects whether the two exponent part operands are a normalized number or a denormalized number. If all the exponent values are "0", it is a denormalized number. When this is made into a circuit, it becomes as shown in FIG. In FIG.
As output, signals that are "normalized numbers" (NORX, NOR
Y) is output with two gate delay stages.

The shift signal generation circuit 102 shifts the two mantissa operands input by the left and right shift circuit 103 by one digit to the right,
Generates a control signal for shifting left one digit or not, and a signal that the execution operation is addition (Ad
It is a circuit that generates d). If this is made into a circuit,
It becomes like the figure. As input, the sign part operands (Xs, Y
s), subtraction signal (sub), and signals that the X and Y operands are normalized numbers (NORX, NORY) are input, and the output is shifted by one digit to the left (Lx, Ly) and shifted by one digit to the right. (Rx, Ry) and no shift (Nx, Ny) signals are output. Also, a signal that the execution operation is addition (Add)
Will also be output. It is understood that the shift signal generation circuit 102 outputs the control signal with four gate delay stages after the sign part operand and the exponent part operand are input.

The left / right shift circuit 103 shifts the input two mantissa operands to the left by one digit based on the control signals (Rx, Ry, Lx, Ly, Nx, Ny) output from the shift signal generation circuit 102. It is a block that executes three operations of shifting by one digit or not. When this is used as an actual circuit, it becomes as shown in FIG. 601 is an arbitrary digit (k
The left and right shift circuit. If Rx, Ry is input, the value one digit higher is output, if Nx, Ny is input, the value of that digit is output, and if Lx, Ly is input, the value one digit lower is output. . The control signal (Rx,
It can be seen that the above-mentioned three shift operations are executed with one gate delay stage after Ry, Lx, Ly, Nx, Ny) comes in.

The swap circuit 105 uses the sign S (Xe−Ye) of the difference between the exponent values output from the subtraction circuit 104 to shift the right / left shift circuit 103.
This is a circuit for swapping the mantissa operand output from the. When this is used as an actual circuit, it becomes as shown in FIG. 701 is a swap circuit of an arbitrary digit (kth digit). When the signal S (Xe-Ye) is input, the input data is swapped and output.

The subtraction circuit 104 subtracts two exponent operands,
This is a circuit that outputs the sign S (Xe-Ye) of the subtraction value and the absolute value | Xe-Ye |. This circuit is described in Japanese Patent Application Laid-Open No. 1-205328, and a subtraction circuit constructed by using this answer is shown in FIG. The exponent operand is input and the sign value S
The number of gate delay stages until (Xe-Ye) is output is 5,
The number of gate delay stages until the absolute value | Xe−Ye | is obtained is seven.

Now, look at the data path to the swap circuit 105.
First, the non-normal mantissa detection circuit 101 and the shift signal generation circuit 10
2. The path for inputting the mantissa data to the swap circuit 105 through the left / right shift 103 is shown in FIG. 4, FIG. 5, and FIG.
It can be seen that the number of gate delay stages is five. On the other hand, it is understood from FIG. 7 that the control signal S (Xe-Ye) for swapping data from the subtraction circuit 104 to the swap circuit 105 has five gate delay stages. Therefore, when looking at the path from the input of floating point data to the operation of the swap circuit 105, it is understood that the former and the latter have the same number of gate delay stages.

Therefore, by using the left-right shift circuit of the present invention as described above, the time for the data shift operation for making the rounding positions the same at the time of addition and subtraction, which is a conventional problem, does not enter the critical path, and further, The mantissa shift amount for aligning the exponent digits is only required to use one subtraction circuit, and the calculation time can be shortened, and further, the circuit scale can be reduced, which is a great effect.

The normalization process of the addition / subtraction result is performed using the left shift circuit 108 and the addition / subtraction circuit 110 as in the conventional example.

As described above, in this embodiment, the case where 32-bit IEEE754 standard floating point data is used has been described. However, the longer the operand is, the time required for the exponent part subtraction to obtain the mantissa shift amount is to detect the denormalized number. The present invention is more effective because it takes longer than the time.

Further, in the above embodiment, the left / right shift circuit 103 comes before the swap circuit 105, but if the swap circuit 105 is brought before the left / right shift circuit 103 as in the embodiment shown in FIG. The effect is obtained. However, this is the subtraction circuit 104
And the sign S (Xe-Ye) of the exponent subtraction value is the shift signal Rx, Ry, L
This is the case when it is possible to obtain much faster than x, Ly, Nx, Ny.

As described above, according to the present invention, when performing the floating-point addition / subtraction of the IEEE standard, since the two operands are aligned with each other, the operand mantissa of the smaller exponent value is shifted rightward. No, or by providing a shift circuit that shifts to the right or left by one digit, only one subtractor may be used to calculate the shift amount of digit alignment of two operands, and the circuit is simple and the floating point time is short. An adder / subtractor can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a floating-point addition / subtraction device according to an embodiment of the present invention, and FIG. 2 is a diagram showing the operation of the left / right shift circuit in FIG. 1 and the shift amount output from the subtraction circuit.
Figure showing how it changes depending on the type of operand,
FIG. 3 is a block diagram of a conventional floating point addition / subtraction device, FIG. 4 is a logic diagram of the denormalized number detection circuit 101 in FIG. 1, and FIG. 5 is a logic of the shift signal generation circuit 102 in FIG. 6 and 6 are logic diagrams of the left / right shift circuit 103 in FIG. 1, FIG. 7 is a logic diagram of the swap circuit 105 in FIG. 1, and FIG. 8 is a logic diagram of the subtraction circuit 104 in FIG. FIG. 9 is a block diagram of a floating point adder / subtractor according to another embodiment of the present invention. 101 ... Denormalized number detection circuit, 102 ... Shift signal generation circuit, 103 ... Left / right shift circuit, 104 ... Subtraction circuit, 105 ...
… Swap circuit, 106 …… Right barrel shift circuit, 107 ……
Addition / subtraction circuit, 108 ... Left shift circuit, 109 ... Multiplexer, 110 ... Addition / subtraction circuit.

Claims (4)

(57) [Claims] 1. A floating point addition / subtraction device for adding or subtracting two operand data in a floating point format consisting of a mantissa operand, an exponent operand and a sign operand, wherein the two operands are normalized numbers. The mantissa operand is not shifted or right before the addition and subtraction of the two mantissa operands is performed, based on the information of whether there is a denormalized number or whether the operation is addition or subtraction. Or a floating-point addition / subtraction device having shift means for shifting left one digit 2. A floating-point addition / subtraction device for adding or subtracting two operand data in a floating-point format consisting of a mantissa operand, an exponent operand, and a sign operand, wherein the two operand data are normalized numbers. Generating a control signal that does not shift the mantissa operand or shifts it to the right or left by one digit based on the information whether it is a certain number, a denormalized number, or an execution operation is addition or subtraction Means for using the control signal output from the first means, second means for not shifting the input data or shifting the input data by one digit to the right or left, and subtracting the exponent operand, Third means for outputting a sign and an absolute value, fourth means for swapping input data with the sign of the subtraction result outputted by the third means and outputting the same, and third means for input data And fifth means for only right-shift the absolute value of the outputted subtraction result Ri, by adding or subtracting the input data,
And a sixth means for rounding and outputting the addition / subtraction result,
Two mantissa operands are input to the second means,
The mantissa operand is not shifted by the control signal output from the first means, or is shifted to the right or left by one digit and is output, and the output data is input to the fourth means, , The data having the smaller exponent value is used as the input data of the fifth means, and the output data of the fifth means and the input data having the larger index value of the input data of the fourth means are used as the input data of the fifth means. 6. A floating point addition / subtraction device characterized by being input as means of 6. 3. A floating point addition / subtraction device for adding or subtracting two operand data in a floating point format consisting of a mantissa operand, an exponent operand, and a sign operand, wherein the two operands are normalized numbers. Generating a control signal that does not shift the mantissa operand or shifts it to the right or left by one digit based on the information whether it is a certain number, a denormalized number, or an execution operation is addition or subtraction Means for using the control signal output from the first means, second means for not shifting the input data or shifting the input data by one digit to the right or left, and subtracting the exponent operand, Third means for outputting a sign and an absolute value, fourth means for swapping input data with the sign of the subtraction result outputted by the third means and outputting the same, and third means for input data And a sixth means for adding / subtracting the input data, rounding the addition / subtraction result, and outputting the rounded result. The fifth means has two means. The mantissa operand is input, and the significand of the subtraction result output from the third means causes the mantissa operand of the smaller exponent operand to be the fifth mantissa operand.
The output data is input to the second means, and the input data is not shifted by the control signal generated by the first means. Digit shift and output, the output data is input to the fifth means and the sixth means, and the input of the fifth means is shifted right by the absolute value of the subtraction result obtained by the third means and output. And the output data is input to the sixth means. 4. When the two floating-point operands are denormalized numbers and the execution operation is subtraction, the left and right shift means do not shift the operand mantissa part.
The floating point addition / subtraction device according to any one of 2 and 3.