JPH0392015A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To improve the resolution of one channel by connecting an idle A/D conversion circuit of other channel in parallel with the A/D conversion circuit of the one channel when only one channel is in use. CONSTITUTION:An analog switch SW1 and a data selector SW2 are selected in the high resolution mode, and a sum of an input a1 of a 1st A/D conversion circuit AD1 and the least significant digit identification voltage VX1/2 from an analog DC level generator G1 by an analog adder SF1 is inputted to an input of a 2nd A/D conversion circuit AD 2 as an analog signal a2. The AD conversion data of the A/D conversion circuits Ad1, Ad2 is added by a digital adder SF2 and outputted as a digital output dd1. Thus, the idle A/D conversion circuit is utilized to improve the resolution of one channel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to measuring devices and other devices equipped with a plurality of channels of analog-to-digital converters.

The present invention provides an advantage in that when only one channel out of multiple channels is used, the analog
The present invention relates to a device that uses a digital conversion circuit to improve the resolution of one channel.

〔overview〕

In an analog-to-digital converter equipped with a plurality of m channels, when only one channel is used, the vacant analog-to-digital converter circuits of other channels are connected in parallel to convert that one channel. This improves resolution.

[Conventional technology]

BACKGROUND ART Input circuits of measuring devices are widely used in which analog-to-digital conversion circuits each having equivalent performance are provided in correspondence with a plurality of analog inputs so that a plurality of channels can be used simultaneously. However, in many measurements, only one channel of the plurality of channels is used, and during that time, the analog-to-digital conversion circuits of the plurality of channels are in an idle state.

[Problem to be solved by the invention]

An object of the present invention is to provide a circuit that utilizes this idle analog-to-digital conversion circuit to improve the resolution of one channel that is being used.

That is, an object of the present invention is to provide an analog-to-digital converter with a simple circuit structure and high resolution.

[Means to solve the problem]

The present invention provides an analog-to-digital converter comprising a plurality of m analog inputs (m is a natural number raised to the power of 2), and independent analog-to-digital conversion circuits corresponding to the m analog inputs and their digital outputs. , a switching means to a high resolution mode is provided, and this switching means is
to the first input analog voltage of the analog inputs,
When V is the lowest digit identification voltage of each analog-to-digital conversion circuit, the voltage obtained by sequentially adding analog voltages of 1 V m to each analog-to-digital conversion circuit is input to each analog-to-digital conversion circuit, and m analog-to-digital conversion circuits are connected. The present invention is characterized in that it includes means for outputting a digital output obtained by adding together the respective digital outputs.

[Effect]

A plurality of m analog-to-digital conversion circuits are connected in parallel to one analog input.

However, each analog-to-digital conversion circuit
For each one, a voltage of ■ ● V m is added to the voltage of that one analog input. If the digital outputs are simply added digitally, if m is 2, it will be 1 digit, if m is 4, it will be 2 digits, if m is 8, it will be 3 digits, that is, log. A digital output with improved resolution by m orders of magnitude can be obtained.

A value obtained by simply dividing the digitally added value by m is a value representing the original value with high resolution. However, since m is a constant and operations of multiplying and dividing constants are generally performed arbitrarily at the stage of using the digital output, the scope of claims does not include operations of dividing by m.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

In this example, m=2'=2 This is the case.

In Figure 1, two first and second analog input channels
l, Ch2 and these two analog inputs Ch1, ch2
, and their respective digital outputs dd. , dd. Equipped with. These two analog-to-digital conversion circuits ADI and AD2 are mutually equivalent circuits.

The feature of the present invention lies in the provision of means for switching to high resolution mode. In other words, this high-resolution mode switching means operates by interlocking switches SWI and SW2.
including.

The illustrated states of the two switches SWI and SW2 in FIG. This lowest identification voltage V×1/2 is added to the input a by the analog DC level generator Gl, and the output of the second analog-to-digital conversion circuit AD2 is added to the output of the first analog-to-digital conversion circuit ADI. Digitally added.

The operation of this circuit will be explained. First, in normal mode, the analog switch SWI is connected to the analog input channel 2 side,
A data selector SW2 is connected to the digital bang generator G2 side. First analog-to-digital conversion circuit A
DI outputs digital data dd after AD converting the analog input chl and passing it through the digital adder SF2.

Digital pattern generator G2 has all n bits “O”
Since the level pattern is output, the input and output data of the digital adder SF2 are equal. Similarly, the second analog-to-digital conversion circuit AD2 performs AD conversion on the analog input ch2 and outputs digital data dd2. In other words, the analog data of the two channels is AD converted and output as two digital data.

Next, in the high resolution mode, the analog switch SW1 is connected to the analog DC level generator Gl side, and the data selector SW2 is connected to the second analog-to-digital conversion circuit AD2.
connected to the side. At this time, analog input Ch2 is not processed. In this case, the analog input chi becomes the analog signal a1 input to the first analog-to-digital conversion circuit ADI. On the other hand, the analog adder SFI adds the voltage generated by the analog value generator G1 and inputs the resultant signal as an analog signal a2 to the second analog-to-digital conversion circuit AD2 through the analog switch SWI. The AD conversion data of the two analog-to-digital conversion circuits ADL AD2 are added by a digital adder SF2 and output as a digital input dd,. At this time, digital output d
The data output as d2 has no particular meaning in this embodiment. Two analog-to-digital conversion circuits AD
Assuming that both L AD2s have the same performance and operate at the same sample rate, and their lowest digit identification voltage is V,
The output voltage of analog value generator G1 is preset to V/2. At this time, the threshold levels at which the digital data of the first analog-to-digital conversion circuit AD1 changes in response to the input signal are expressed as aOX al, a2, an-2 (aka a
y-i=V), the second analog-to-digital conversion circuit AD2 receives a signal added by V/2 on the way, so v v
vaOsa,
""'ah-2 -2
2 It has 2 threshold levels. Therefore, for the input signal of the first analog input chi, each analog-to-digital conversion circuit ADI and A
D2 operates with the change point of the digital data shifted by half the value of the lowest digit identification voltage. The digital output dd, which is the sum of these two data, is an n-bit analog signal.
If the digital converter operates ideally, n+l bits of data can be obtained.

FIG. 2 is a block diagram of a second embodiment of the present invention.

In this example m=22=4 This is the case.

The analog value generators Gll, G12, and G13 of this embodiment generate the lowest digit m 4 of each analog-to-digital conversion circuit. Therefore, the input a of the first analog-to-digital conversion circuit ADI and the 1/4v are added to the analog adder SFII, and the output becomes al +1/4v. Next, this output and the output (V/4) of the analog value generator G12 are added by the analog adder SF12, resulting in an output a, +2/4 v, and this output and the output (V/4) of the analog value generator G13 are added.
/4) is further added by the analog adder SF13, and is inputted to the fourth analog-to-digital conversion circuit AD4 as a+ +3/4 v.

That is, by using four analog-to-digital conversion circuits and shifting the input signal by V/4, it is possible to improve the resolution by +2 bits.

〔Effect of the invention〕

As described above, according to the present invention, there is an effect that resolution can be improved by switching the mode of an analog-to-digital converter that converts a plurality of analog inputs into digital outputs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention. FIG. 2 is a block diagram of a second embodiment of the present invention. ADI, AD2...first and second analog/digital conversion circuits, a1, a2...analog/digital conversion circuits, respectively
Analog signal input to digital conversion circuit, Ch1,
Ch2...first and second analog inputs a.
Sd2...Digital signals output from analog-to-digital conversion circuits, dd. , dd. ...Digital output, G1, Gll~G13...Analog DC level generator that generates a DC voltage value, G2, 021~G
23...Digital beat generator that generates a 10" level n-bit digital pattern, SF1...analog adder, SF2...digital adder that adds n-bit and n-bit digital values, SW1... ... Analog switch, SW2... Data selector that selects n-bit parallel data. First embodiment Fig. 1

Claims (1)

[Claims] 1. A plurality of m (m is a natural number power of 2) analog inputs;
In an analog-to-digital converter equipped with independent analog-to-digital conversion circuits and their digital outputs corresponding to the m analog inputs, a switching means to a high-resolution mode is provided, and this switching means The voltage obtained by sequentially adding an analog voltage of 1/m·v to the first input analog voltage of the analog inputs, where v is the lowest digit identification voltage of each analog-to-digital conversion circuit, is An analog-to-digital converter comprising means for inputting a digital converting circuit and outputting a digital output obtained by adding each digital output of m analog-to-digital converting circuits.