JP2616196B2 - Control device abnormality detection circuit - Google Patents

Description

The present invention relates to an abnormality detection circuit such as a process control device having an A / D conversion unit.

(B) Conventional technology FIG. 4 shows a conventional abnormality detection circuit of a process control device having an A / D converter. In this control device, the operation result 13 of the computer 1 is converted into an analog signal by the D / A converter 2 and a large number of outputs O ₁₁ ,..., 3 _−n are output by a plurality of switches 3 ₋₁ , 3 _{−2 ,. O 1m, ..., O n1,} ..., are output in time is switched sequentially in O _nm. Then, the abnormality detection of the output section including the D / A converter 2 is performed by detecting each output O ₁₁ ,.
O _1m ,…, On ₁ ,…, O _nm are set to switchers 4 _-1 , 4 _-2 ,
.., 4- _n , the outputs are input one by one to the A / D converter 5 and converted into a digital signal by the switching selection. The converted value is compared with the original operation result by the comparing unit 14 and the values are matched. No abnormalities,
If they do not match, an abnormal signal is output.

(C) Problems to be Solved by the Invention In the above-described abnormality detection circuit of the conventional control device, there is a problem that an A / D converter and a switching device are required for abnormality detection, which is expensive. Further, there is a problem that a control circuit (or a program) for the A / D converter and the switch is required.

The present invention has been made in view of the above problems, and has as its object to provide a simple and inexpensive abnormality detection circuit of a control device which does not require an A / D converter or a switch.

(D) Means and Action for Solving the Problems The abnormality detection circuit of the control device according to the present invention includes: a D / A converter that converts a calculation result of the digital calculation unit into an analog signal;
A switch that converts the analog signal from the D / A converter into a large number of analog outputs, and converts the digital signal into an analog signal in a time-series D / A converter, and converts the time-series analog signal into the analog signal. A control device for switching to a corresponding analog output with a switch, and allocating one of a large number of outputs of the switch for abnormality detection, and outputting a D / A signal from the digital arithmetic unit to the abnormality detection output during a test. A test signal having a predetermined value is passed through the converter, and a signal selection circuit for selecting a test signal under test from a large number of outputs of the switching device, and the selected test signal is compared with an upper reference value and a lower reference value. And a comparator that outputs an abnormal signal when the test signal is not between the upper reference value and the lower reference value on condition that the test is being performed.

In the abnormality detection circuit of this control device, when a test signal is derived from a certain output of a switch through a D / A converter from a digital operation unit, a signal selection circuit selects this test signal at that timing, It is compared with a predetermined upper reference value and a lower reference value. If the test signal is between the upper reference value and the lower reference value, it is determined that the test signal is normal. If the test signal exceeds the upper reference value and the lower reference value, an abnormal signal is output on the condition that the test is being performed. The abnormal signal indicates that there is an abnormality in the conversion operation of the D / A converter and the switching operation of the switch.

(E) Examples Hereinafter, the present invention will be described in more detail with reference to examples.

FIG. 1 is a block diagram of an abnormality detection circuit of a control device showing one embodiment of the present invention. In FIG. 1, a calculation result 13 of the computer 1 is converted into an analog signal by the D / A converter 2 and input to the switches _3-1 , _3-2 ,..., 3- _n . Each of the switching units _3-1 , _3-2 ,..., 3- _n has a plurality of outputs.
O _11, ..., having _{O 1 (m-1),} O 1m, ..., O n1, ..., O n (1m), the O _nm. Switch _3-1 of the output _{O 11, ..., O 1 (} m-1), O 1m are sequentially switching selection by the selection signal from the program control circuit 12, the operation result 13 is output time sequentially. Other switch
The same applies to the outputs of 3 _-2 , ..., 3 _-n . In addition, each switch
One channel output O _1m , O _2m , 3 _-1 , 3 _-2 , ..., 3- _n
, O _nm output test signals, and these test signals are input to the signal selection circuit 7. The signal selection circuit 7 selects one of the test signals O _1m , O _2m ,..., O _nm , inputs the selected signal to the comparator 8, and inputs a reference value from the reference value generator 9 to another input terminal of the comparator 8. You are typing. The reference value is given within a predetermined width. If the test signal is within the range of the reference value, the D / A converter 2, the switching units _3-1 ,..., 3- _n are normal, When the signal is out of the range of the reference value, the comparator 8 outputs an abnormal signal.

FIG. 2 shows a circuit specifically showing the signal selection circuit 7, the comparator 8, and the reference value generator 9 of this embodiment. Here, a case is shown in which n = 4 switches are provided. The signal selection circuit 7 includes maximum value circuits 23 _-1 , 23 _-2 ,..., 23 _-4 corresponding to the test signals, respectively.
23 _-1 , 23 _-2 , ..., 23 _-4 are amplifiers 21 _-1 , 21 _-2 , ..., 21 _-4
And diodes 22 _-1 , 22 _-2 ,..., 22 _-4 . The m-th output of each of the switches 3 _-1 ,..., 3 _-4 , that is, the test signals O _1m , O _2m , O _3m , O _4m are respectively connected to resistors R ₁ , R ₂ ,
…, Grounded via R ₄ and amplifiers 21 ₋₁ , 2
1 _-2, ..., it is connected to the + input of 21 _-4. Comparator 8
The two comparators 8a, one of 8b - reference value V _ref + alpha from the reference value generating unit 9a to the input end (upper reference value) is, the reference value generating unit 9b than V _ref to the other + input terminal - reference value of alpha (lower resistance) is added, the comparator 8a, the output of 8b is configured to be connected to + V ₅ via a resistor _{R 6, R 7, R 8} . Each output terminal of the maximum value circuit _23-1 , ..., _23-4 is a resistor
It is connected to the -V ₅ potential via the R _5, the comparator 8a + input terminal and the comparator 8b - are connected to the input terminal. Further, the output terminals of the comparators 8a and 8b are connected to the negative terminal of the input of the AND gate 10, and a signal indicating "under test" is input from the computer 1 to the other end of the AND gate 10.

If in the abnormality detecting circuit are outputted now for example the test signal from the channel m of the switch 3 _-1, which is not the test signal is output from the other of the switch, the switch 3 _-1
Test signal O _1m from the maximum value circuit _23-1 is output,
This signal is input to the comparators 8a and 8b. When the level of the test signal is within the reference value width of the V _ref + α~V _ref -α comparator 8a, 8b does not output a high level signal,
The AND gate 10 does not output an abnormal signal. However, if the test signal is larger than V _ref + α or smaller than V _ref −α,
The outputs of the comparators 8a and 8b become high, and the AND gate 10
A more abnormal signal is output.

The reason why the abnormal signal is output via the AND gate 10 is that none of the switches _3-1 ,..., _3-4 is outputting a normal operation result while the test signal is not being output. when on, the test signal O _{1 m,} ..., O _4m is all "0" (low), the maximum value circuit 23 _-1, ..., 23 _four output are both "0", and thus the comparator Since the signals input to 8a and 8b are smaller than _Vref- α, the device may output an abnormal signal as it is. In order to eliminate such inconvenience, the outputs of the comparators 8a and 8b are output as "under test" conditions.

FIG. 3 is a block diagram of an abnormality detection circuit according to another embodiment of the present invention. Although this embodiment circuit does not use the maximum value circuit as shown in FIG. 2, comparators are individually provided corresponding to the test signals O _1m ,..., O _4m from the switching units 3 _{-1 ,.} 8 _-1 , 8 _-2 ,
8 _-3 and 8 _-4 are provided, and each output of each of the comparators 8 _-1 , 8 _-2 ,..., 8 _-4 is connected to AND gates 10 _-1 , 10 _{-2 ,.} And output each of them. In this case, a signal indicating that the switching unit is being tested is input to the other ends of the inputs of the AND gates 10 _-1 ,..., 10 _-4 .

(F) Effects of the Invention According to the present invention, the abnormality detection circuit is composed of the signal selection circuit and the comparator, and therefore does not use an A / D converter or a switch. A detection circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of an abnormality detection circuit of a control device showing one embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the abnormality detection circuit, and FIG. FIG. 4 is a block diagram showing another specific example of the circuit, and FIG. 4 is a circuit diagram showing an abnormality detection circuit of a conventional control device. 1: Computer, 2: D / A _{converter, 3 -1 · 3 -2 · ...} · 3 -n: switcher, 7: signal selection circuit, 8: comparator, 9: reference value generating unit.

Claims (1)

(57) [Claims] A digital-to-analog (D / A) converter for converting an operation result of a digital operation unit to an analog signal; and a switch for converting the analog signal from the D / A converter to a large number of analog outputs. In a control device for converting a signal in time series to an analog signal by a D / A converter and switching and outputting the time-series analog signal to a corresponding analog output by the switch, one of the multiple outputs of the switch is used. Allocated for abnormality detection, a test signal of a predetermined value is put on the output for abnormality detection through the D / A converter from the digital arithmetic unit during the test, and a test signal under test is output from a large number of outputs of the switch. And a comparing section for comparing the selected test signal with the upper reference value and the lower reference value, and when the test signal is not between the upper reference value and the lower reference value, the comparing section outputs the test signal. Abnormality detection circuit of the control device in the halfway through outputs an abnormality signal to the condition.