JP6123900B2 - Inverter device - Google Patents

Description

  The present invention relates to an inverter device including a three-level circuit having a flying capacitor.

  Patent Document 1 discloses an inverter device that includes a three-level circuit that outputs a three-level voltage using four switch elements and a flying capacitor, and that is configured to output an AC voltage by PWM control of the switch elements. .

Japanese Patent Publication No. 06-67204

  Compared with a circuit that generates two times the input voltage using two capacitors connected in series, a circuit using a flying capacitor can reduce the size of the capacitor and the number of components. Therefore, it is advantageous for downsizing.

  In the three-level voltage generation circuit that outputs a three-level voltage using a flying capacitor, the switch element is controlled so that the charging time and the discharging time per unit time for the flying capacitor are equal. Therefore, the voltage across the flying capacitor is half the input voltage. The three-level voltage generation circuit is a circuit that uses this characteristic.

  However, the characteristics of the switch element and the characteristics of the drive circuit that drives the switch element vary, and due to errors in the on / off timing of the switch element, the charging time and discharge time per unit time for the flying capacitor A difference (charge / discharge time difference) may occur. This causes a phenomenon (voltage error) in which the voltage across the flying capacitor deviates from half the input voltage. This voltage error increases as the current value increases.

  As the voltage error increases, the maximum applied voltage to the switch element increases and the problem of withstand voltage arises. That is, the switch element may be destroyed. Moreover, in order to prevent destruction, a high voltage | pressure-resistant switch element must be used, A loss will increase and cost will increase.

  Moreover, when applied to a power system interconnection inverter device, the voltage error causes a deterioration in the quality of the output current of the inverter device.

  An object of the present invention is to provide an inverter device that has solved the problem of withstand voltage and the problem of current quality degradation caused by the voltage error of the flying capacitor.

(1) The inverter device of the present invention
The first end is connected to the first switch element to the fourth switch element connected in series between the first input terminal and the second input terminal of the DC power supply, and the first switch element and the second switch element. And a capacitor having a second end connected to a connection point between the third switch element and the fourth switch element, the connection point between the second switch element and the third switch element being an output terminal. A three-level voltage generation circuit,
By switching the first to fourth switching elements according to the comparison between the triangular wave signal and the modulation signal, the input voltage between the first input terminal and the second input terminal is changed (in a sine wave form). PWM modulation means for PWM modulation and outputting from the output end;
Capacitor voltage detection means for detecting the voltage of the capacitor;
Means for detecting an error from one half of the input voltage of the voltage of the capacitor;
Capacitor charge / discharge time adjusting means for adjusting the charge time and discharge time of the capacitor in a direction in which the error is reduced,
Modulation signal correction means for generating a first modulation signal in which the modulation signal is corrected in the upward direction by a correction amount and a second modulation signal in which the modulation signal is corrected in the downward direction by the correction amount;
The PWM modulation means, a first PWM modulation for generating the control signal of the first switch element and the fourth switching element in response to the comparison of the first triangular wave signal first modulated signal means and control of said first triangular wave signal and the second switch element and the third switch element in response to the comparison of the second triangular wave signal differing in phase by 180 ° the second modulation signal Second PWM modulation means for generating a signal for use,
The capacitor charge / discharge time adjusting means increases or decreases the correction amount according to the error.

(2) Further, the PWM modulation means, the first for generating a control signal of the first switch element and the fourth switching element in response to a comparison between the modulation signal and the first triangular wave signal a PWM modulation means, the control of the first triangular wave signal and the second switch element and the third switch element in response to a comparison between the modulation signal and the second triangular wave signal differing in phase by 180 ° are Second PWM modulation means for generating a signal,
A dead time for correcting the dead time of the PWM modulation signal by the first PWM modulation means in the increasing direction by a correction amount, and correcting the dead time of the PWM modulation signal by the second PWM modulation means in the decreasing direction by the correction amount. A correction means,
The capacitor charge / discharge time adjusting means preferably increases or decreases the correction amount according to the error.

(3) In the above (1) or (2), it is preferable that the correction amount is obtained by multiplying the error by a coefficient related to a capacitance of the capacitor and a coefficient related to a current flowing through the capacitor.

(4) In the above (1) to (3),
A differential amplifier circuit having a balanced input and an unbalanced output, the input unit being connected to both ends of the capacitor,
The capacitor voltage detection means includes an output voltage of the differential amplifier circuit in a charging current cutoff period after the capacitor is charged, and the differential amplifier circuit in a discharge current cutoff period after the capacitor is discharged. It is preferable that the voltage of the capacitor is detected by obtaining an average value of the output voltage of the capacitor.

(5) In the above (1) to (3), the capacitor voltage detecting means is configured such that the voltage at the output terminal at a central timing during a period in which the second switch element and the fourth switch element are on. It is preferable to detect this.

  According to the present invention, an inverter device is constructed in which the problem of the withstand voltage of the flying capacitor and the switching element and the problem of current quality due to the voltage error of the flying capacitor are solved.

FIG. 1 is a circuit diagram of an inverter device 201 according to the first embodiment. FIG. 2 is a diagram showing the relationship between the states of the four switch elements S1 to S4 of the three-level voltage generation circuit 20 and the output voltage (potential) Vo. FIG. 3 is an equivalent circuit diagram of the three-level voltage generation circuit 20 in four states. FIG. 4 is a waveform diagram showing PWM modulation of the four switch elements S1 to S4. FIG. 5 is a waveform diagram of the load current (current flowing through the inductor L1) Io, the voltage Vcf across the capacitor Cf, and the output voltage Vu of the inverter device 201 shown in FIG. FIG. 6 is a waveform diagram of the voltage and state of each part of the inverter device 201 when the target signal Fp is a sine wave signal. FIG. 7 is a diagram illustrating timing for detecting the voltage Vcf of the capacitor Cf. FIG. 8A is a waveform diagram showing PWM control for changing the average value of the voltage Vcf of the capacitor Cf, and is a waveform diagram of each part when the target signal Fp is less than the value corresponding to Vdc / 2. FIG. 8B is a waveform diagram showing PWM control for changing the average value of the voltage Vcf of the capacitor Cf, and is a waveform diagram of each part when the target signal Fp exceeds a value corresponding to Vdc / 2. FIG. 9 is a circuit diagram of the switching control circuit 100 shown in FIG. FIG. 10 is a truth table of the switch element driving circuit 90. FIG. 11 is a diagram showing the relationship between the load current Io and the coefficient k (Io) related to the load current Io. FIG. 12A is a waveform diagram of the voltage Vcf of the capacitor Cf of the inverter device 201 according to the first embodiment. FIG. 12B is a waveform diagram of the voltage Vcf of the capacitor Cf when the capacitor charge / discharge time is not corrected. FIG. 13 is a waveform diagram showing the timing for measuring the voltage of the flying capacitor of the inverter device according to the second embodiment. FIG. 14 is a block diagram showing an adjustment circuit for charging / discharging time of the flying capacitor of the inverter device according to the third embodiment. FIG. 15 is a circuit diagram of a main part of an inverter device 204A according to the fourth embodiment. FIG. 16 is a circuit diagram of a main part of another inverter device 204B according to the fourth embodiment. FIG. 17 is a circuit diagram of a main part of an inverter device 205A according to the fifth embodiment. FIG. 18 is a circuit diagram of a main part of another inverter device 205B according to the fifth embodiment. FIG. 19 is a block diagram of a three-phase inverter device according to the sixth embodiment.

  Hereinafter, several specific examples will be given with reference to the drawings to show a plurality of modes for carrying out the present invention. In each figure, the same reference numerals are assigned to the same portions. Each embodiment is an exemplification, and needless to say, partial replacement or combination of configurations shown in different embodiments is possible.

<< First Embodiment >>
FIG. 1 is a circuit diagram of an inverter device 201 according to the first embodiment. The inverter device 201 includes a first input terminal IN1 that inputs a DC power supply voltage, a second input terminal IN2, a first output terminal OUT1 that outputs an AC voltage, and a second output terminal OUT2. In this example, the second input terminal IN2 and the second output terminal OUT2 are commonly connected to a reference potential (ground). For example, a DC voltage generated by a photovoltaic power generation panel is applied to the first input terminal IN1 and the second input terminal IN2.

  A three-level voltage generation circuit 20 is connected between the first input terminal IN1 and the second input terminal IN2. The three-level voltage generation circuit 20 includes first to fourth switch elements (S1 to S4) connected in series between the first input terminal IN1 and the second input terminal IN2, the first switch element S1, and the first switch element S1. A flying capacitor (hereinafter simply referred to as “capacitor”) having a first end connected to the connection point of the second switch element S2 and a second end connected to the connection point of the third switch element S3 and the fourth switch element S4. ]) Cf.

  The switch elements S1 to S4 are all MOS-FETs, and the body diode is also shown in FIG. Note that the switch element is not limited to a MOS-FET, and may be another transistor.

  A connection point between the second switch element S2 and the third switch element S3 is an output terminal of the three-level voltage generation circuit 20, and between the output terminal of the three-level voltage generation circuit 20 and the first output terminal OUT1. An inductor L1 is connected in series. The output current detection circuit 2 is connected between the output terminal of the three-level voltage generation circuit 20 and the first output terminal OUT1.

  The input voltage detection circuit 1 is connected between the first input terminal IN1 and the second input terminal IN2. A capacitor voltage detection circuit 3 is connected to both ends of the capacitor Cf. The capacitor voltage detection circuit 3 is composed of a differential amplifier circuit.

  The switching control circuit 100 outputs a predetermined voltage to the output terminals OUT1 and OUT2 by performing PWM control of the switch elements S1 to S4. Since the second input terminal IN2 has a reference potential of 0 V and Vdc is applied to the first input terminal IN1, the inverter device 201 outputs a voltage in the range of 0 to Vdc.

  Further, as will be described later, the switching control circuit 100 is configured to output the output voltage of the capacitor voltage detection circuit 3 in the charging current cutoff period after the capacitor Cf is charged and the discharge current cutoff period after the capacitor Cf is discharged. The average value of the output voltage of the capacitor voltage detection circuit 3 is detected as the voltage of the capacitor Cf. The average calculation processing unit of the capacitor voltage detection circuit 3 and the switching control circuit 100 corresponds to “capacitor voltage detection means” according to the claims of the present application.

  The switching control circuit 100 adjusts the PWM control according to the detection results of the input voltage detection circuit 1, the output current detection circuit 2, and the capacitor voltage detection circuit 3. This adjustment will be described in detail later.

  FIG. 2 is a diagram showing the relationship between the states of the four switch elements S1 to S4 of the three-level voltage generation circuit 20 and the output voltage (potential) Vo. Here, the four switch elements S1 to S4 adopt four states H, Mc, Md, and L.

  FIG. 3 is an equivalent circuit diagram of the three-level voltage generation circuit 20 in the four states. In the state H, since the switch elements S1 and S2 are ON and S3 and S4 are OFF, the output voltage Vo is Vdc. In the state L, since the switch elements S3 and S4 are ON and S1 and S2 are OFF, the output voltage Vo is 0. In the state Mc, since the switch elements S1 and S3 are ON and S2 and S4 are OFF, the output voltage Vo is Vdc-Vc. Here, Vc is a charging voltage of the capacitor Cf. If Vc = Vdc / 2, the output voltage Vo = Vdc / 2. In the state Md, since the switch elements S2 and S4 are ON and S1 and S3 are OFF, the output voltage Vo is Vc. Here, assuming that Vc = Vdc / 2, the output voltage Vo = Vdc / 2. Since the charge amount and the discharge charge amount of the capacitor Cf can be regarded as equal, the output voltage Vo in the state Mc is equal to the output voltage Vo in the state Md. That is, the charging voltage Vc of the capacitor Cf is charged / discharged around Vdc / 2 which is 1/2 of Vdc. If the charging / discharging time constant for the capacitor Cf is sufficiently large with respect to the switching frequency, the fluctuation range of the charging voltage Vc is small and can be regarded as Vc≈Vdc / 2. Variations in the output voltage Vo due to charging / discharging of the capacitor Cf will be described later.

  FIG. 4 is a waveform diagram showing PWM modulation of the four switch elements S1 to S4. In FIG. 4, the first triangular wave signal Vcr1 and the second triangular wave signal Vcr2 have a phase difference of 180 ° (the polarity is inverted). The first PWM modulation signal AQ1 becomes high level (hereinafter referred to as “H level”) when the target signal Fp is higher than the first triangular wave signal Vcr1, and the second PWM modulation signal AQ2 has the second target signal Fp. It becomes H level when it is higher than the triangular wave signal Vcr2.

  The gate signal for the first switch element S1 rises with a delay of the dead time td from the rise of AQ1, and falls simultaneously with the fall of AQ1. The gate signal for the fourth switch element S4 falls simultaneously with the rise of AQ1, and rises with a delay of the dead time td from the fall of AQ1.

  The gate signal for the second switch element S2 rises with a delay of the dead time td from the rise of AQ2, and falls simultaneously with the fall of AQ2. The gate signal for the third switch element S3 falls simultaneously with the rise of AQ2, and rises with a delay of the dead time td from the fall of AQ2.

  In FIG. 4, STATE corresponds to the state shown in FIG. Thus, when the target signal Fp is less than Vdc / 2, the state transition of Mc → L → Md → L →... Is repeated. Similarly, if the target signal Fp is equal to or higher than Vdc / 2, the state transition of Mc → H → Md → H →.

  FIG. 5 is a waveform diagram by simulation of the load current (current flowing through the inductor L1) Io, the voltage Vcf across the capacitor Cf, and the output voltage Vu of the inverter device 201 shown in FIG. The conditions for obtaining this result are as follows.

Vdc = 100V
Cf capacitance = 75 μF
Inductance of inductor L1 = 500 μH
Parallel RC load: R = 20Ω, C = 1.1μF
Here, if there is a difference between the charging time for the capacitor Cf in the state Mc and the discharging time for the capacitor Cf in the state Md, the average value of the voltage Vcf across the capacitor Cf is displaced from 1/2 of the input voltage Vdc. Become. For example, assuming that the charge / discharge time difference per cycle of the capacitor Cf is 10 ns, the average value of the voltage Vcf of the capacitor Cf is 53.6 V when the duty ratio is 80%. That is, the unbalance amount (hereinafter referred to as “voltage error”) ΔV between the charge voltage and the discharge voltage is 3.6V. If the charge / discharge time difference is 100 ns, the average value of the voltage Vcf of the capacitor Cf is 89V (voltage error ΔV = 39V).

  The switching control circuit 100 of the inverter device 201 shown in FIG. 1 performs PWM control of the switch elements S1 to S4 so that the voltage error ΔV becomes zero. The control will be described later.

  FIG. 6 is a waveform diagram of the voltage and state of each part of the inverter device 201 when the target signal Fp is a sine wave signal. The switch elements S1, S4 are controlled by a signal having a dead time at the timing of the first PWM modulation signal AQ1, and the switch elements S2, S3 are controlled by a signal having a dead time at the timing of the second PWM modulation signal AQ2. Is controlled (see FIG. 4). However, in FIG. 6, the dead time is represented as 0 in order to avoid complication of the drawing. In FIG. 6, a voltage Vo ′ is an output voltage of the three-level voltage generation circuit 20 when the voltage of the capacitor Cf is considered to be always Vdc / 2. Actually, the capacitor Cf is charged in the period of the state Mc and discharged in the period of the state Md, so that the voltage Vcf of the capacitor Cf and the output voltage Vo of the three-level voltage generation circuit 20 are as shown in FIG. Displace.

  FIG. 7 is a diagram illustrating timing for detecting the voltage Vcf of the capacitor Cf. The voltage Vcf of the capacitor Cf rises during the state Mc and falls during the state Md. And it becomes a constant value in the state L or the state H. In the example shown in FIG. 7, the voltage Vcf is sampled during the period of the state L before and after the state Mc or Md (the timing indicated by a circle in FIG. 7), and the average value is handled as the voltage of the capacitor Cf. A period between the state Mc and the state Md corresponds to a “charge current cut-off period” in the claims of the present application, and a period between the state Md and the state Mc corresponds to a “discharge current cut-off period” in the claims of the present application.

  8A and 8B are waveform diagrams showing PWM control for changing the average value of the voltage Vcf of the capacitor Cf. FIG. 8A is a diagram when the target signal Fp is less than a value corresponding to Vdc / 2, and FIG. 8B is a diagram when the target signal Fp exceeds a value corresponding to Vdc / 2. If the target signal for the PWM modulation circuit that generates the first PWM modulation signal AQ1 is Fp + α, the rising timing of the first PWM modulation signal AQ1 is advanced by ΔT, and the falling timing is delayed by ΔT. That is, the pulse width is expanded by 2ΔT. If the target signal for the PWM modulation circuit that generates the second PWM modulation signal AQ2 is Fp-α, the rising timing of the second PWM modulation signal AQ2 is delayed by ΔT, and the falling timing is advanced by ΔT. That is, the pulse width is narrowed by 2ΔT. The target signal Fp + α corresponds to the “first modulation signal” in the present invention, and the target signal Fp−α corresponds to the “second modulation signal” in the present invention.

  The state transition when the adjustment of ± α is not performed is as shown in FIG. As is clear from comparison with FIG. 4, by adjusting the above ± α, the state Mc (charging period for the capacitor Cf) is lengthened, and the state Md (discharging period for the capacitor Cf) is shortened. As a result, the average value of the voltage Vcf of the capacitor Cf increases.

  In the above embodiment, the case where the current is in the positive direction, that is, the load current Io is in the direction shown in FIG. 1 has been described. When the current is “negative”, charging and discharging are reversed, and the periods of Mc and Md are interchanged. Therefore, the direction of correction is also reversed, and it is sufficient to deal with α by multiplying “−1”.

  FIG. 9 is a circuit diagram of the switching control circuit 100 shown in FIG. The switching control circuit 100 includes a capacitor charge / discharge time adjustment circuit 70, a PWM modulation circuit 80, and a switch element drive circuit 90. The PWM modulation circuit 80 corresponds to “PWM modulation means” in the present invention. The capacitor charge / discharge time adjustment circuit 70 includes a correction amount generation circuit 71, an addition circuit 73 that adds or subtracts a correction amount α to the target signal, and a subtraction circuit 74. The capacitor charge / discharge time adjustment circuit 70 corresponds to “capacitor charge / discharge time adjustment means” in the present invention. The correction amount generation circuit 71 determines the correction amount α of the target signal according to the input voltage Vdc, the voltage Vcf of the capacitor Cf, and the load current Io. The target signal generation circuit 72 is a circuit provided in a host controller (external to the switching control circuit 100), and is realized by, for example, arithmetic processing for sequentially obtaining a sine wave value.

  The PWM modulation circuit 80 includes triangular wave generation circuits 81 and 82 and comparators 83 and 84. The triangular wave generation circuit 81 generates a first triangular wave signal Vcr1, and the triangular wave generation circuit 82 generates a second triangular wave signal Vcr2.

  FIG. 10 is a truth table of the switch element driving circuit 90. The switch element drive circuit 90 generates gate signals for the four switch elements S1 to S4 as shown in FIGS. 8A and 8B.

  In the above description regarding PWM modulation, it is assumed that PWM modulation is performed by an analog circuit for easy illustration. However, PWM modulation can also be performed by a digital circuit and digital arithmetic processing. When the capacitor charge / discharge time adjusting circuit 70 and the PWM modulation circuit 80 shown in FIG. 9 are configured by digital circuits, the triangular wave generating circuits 81 and 82 are realized by counters, and the comparators 83 and 84 are realized by digital comparators. Then, the correction amount generation circuit 71 determines the correction amount of the target signal value or the triangular wave count value according to the correction amount. That is, the “triangular wave signal” in the present invention is not limited to an analog signal, but includes a “value changing in a triangular wave shape”.

  Here, the current flowing through the capacitor is represented by Ic, the charging time is Tc, the capacitance of the capacitor is represented by C, the voltage variation during charging of the capacitor voltage is represented by ΔVc, and the voltage variation during discharging is represented by ΔVd. It is represented by

ΔVc = Ic × Tc / C
ΔVd = -Ic × Td / C
Therefore, the voltage error ΔV is
ΔV = (Tc-Td) × Ic / C (1)
Are in a relationship. On the other hand, the error ΔT of the charge / discharge time is
ΔT = ΔV × C / Ic (2)
Are in a relationship. That is, the charge / discharge time error ΔT is directly proportional to the voltage error ΔV and the capacitance C of the capacitor Cf. The charge / discharge time error ΔT is inversely proportional to the capacitor current Ic. The capacitor current Ic is equal to the load current Io.

  The voltage error ΔV is obtained from the difference between 1/2 of the input voltage Vdc and the voltage Vcf of the capacitor Cf, and a value obtained by multiplying the voltage error ΔV by the feedback gain k is used as a correction amount for ΔT. The feedback gain k is obtained by multiplying a coefficient related to the reciprocal of the load current Io, a coefficient related to the capacitance C, and a coefficient for ensuring the stability of the feedback system.

  FIG. 11 is a diagram showing the relationship between the load current Io and the coefficient k (Io) related to the load current Io. The coefficient k (Io) relating to the load current Io is inversely proportional to the load current Io as shown by a broken line in FIG. 11, but does not need to be mathematically inversely proportional, and the coefficient k (Io) as shown by a solid line in FIG. The ranks may be switched in stages.

  12A is a waveform diagram of the voltage Vcf of the capacitor Cf of the inverter device 201 according to the first embodiment, and FIG. 12B is a voltage Vcf of the capacitor Cf when the charge / discharge time of the capacitor is not corrected. FIG. Both are waveform diagrams of one cycle of the target signal. If there is a difference between the charging time and the discharging time for the capacitor Cf, as shown in FIG. 12B, the average voltage of the capacitor Cf varies according to the voltage change of the sine wave that is the target signal. On the other hand, according to the present embodiment, the voltage error due to the difference between the charging time and discharging time for the capacitor Cf is corrected, so that the average voltage of the capacitor Cf is always approximately Vdc as shown in FIG. / 2.

  Note that limit values are set for these correction values. Here, the target signals Fp + α and Fp−α in FIGS. 8A and 8B are (1) within the range of the maximum value (Dmax) and the minimum value (Dmin) of the PWM control, and (2) the target. It is necessary to satisfy the following two conditions: ((Fp + α) + (Fp−α)) / 2 that is the average value of the signal does not change. Therefore, the absolute value of α is limited to a value between (Dmax−Fp) and (Fp−Dmin).

<< Second Embodiment >>
FIG. 13 is a waveform diagram showing the timing for measuring the voltage of the flying capacitor of the inverter device according to the second embodiment. The circuit configuration of the inverter device is the same as that of the first embodiment. Since the discharge starts at the start timing of the period of the state Md and ends at the end timing, the voltage Vcf at the center timing of the state Md represents the average voltage of the flying capacitor. 1 and 3, in the state Md, since the switch elements S2 and S4 are in the on state, the voltage of the flying capacitor Cf appears at the output terminal of the three-level voltage generation circuit 20 in this state Md. Therefore, if the output voltage Vo of the three-level voltage generation circuit 20 is sampled at the central timing tc of the state Md shown in FIG. 13, the average voltage of the flying capacitor can be obtained. The processing unit that performs the sampling of the switching control circuit corresponds to “capacitor voltage detection means” according to the claims of the present application.

  According to the present embodiment, the sampling cycle is longer than that of the first embodiment, and the calculation for calculating the average value is not necessary, so that the calculation load can be reduced. Further, since differential detection is unnecessary, the number of sensors can be reduced, and the cost can be reduced.

<< Third Embodiment >>
FIG. 14 is a block diagram showing an adjustment circuit for charging / discharging time of the flying capacitor of the inverter device according to the third embodiment.

  In the first embodiment, the charge / discharge time for the flying capacitor is adjusted by adjusting ± α with respect to the target signal in the PWM control. However, in the third embodiment, the dead time of the PWM modulation signal is adjusted. Thus, the charging / discharging time for the flying capacitor is corrected.

  The inverter device shown in FIG. 14 includes a dead time adjustment circuit 50, a PWM modulation circuit 60, delay circuits 51 to 54, and dead time increase / decrease circuits 55 and 56. In FIG. 14, the dead time adjusting circuit 50 obtains a voltage error ΔV from the voltage Vcf of the capacitor Cf and the input voltage Vdc, and the dead times of the switch elements S1 to S4 (in FIG. 4) according to the coefficient relating to the reciprocal of the load current Io. Td) is determined. The dead time adjusting circuit 50 corresponds to “dead time correcting means” in the present invention. The PWM modulation circuit 60 generates PWM modulation signals for the first switch element S1 and the fourth switch element S4, and PWM modulation signals for the second switch element S2 and the third switch element S3. The control signal (gate signal) for the first switch element S1 and the control signal (gate signal) for the fourth switch element S4 are in an inverted relationship, and the control signal (gate signal) for the second switch element S2 and the third signal The control signal (gate signal) for the switch element S3 has an inversion relationship. The delay circuits 51 to 54 delay the time that is increased or decreased by ΔT with respect to a certain dead time, and output the control signals of the switch elements S1 to S4.

  As in this embodiment, the charge / discharge time for the flying capacitor may be corrected by adjusting the dead time of the PWM modulation signal.

<< Fourth Embodiment >>
The fourth embodiment shows an example in which the neutral point potential of the DC input voltage is used as the reference potential of the output voltage of the inverter device.

  FIG. 15 is a circuit diagram of a main part of an inverter device 204A according to the fourth embodiment. Vdc is applied between the first input terminal IN1 and the second input terminal IN2 of the inverter device 204A, and the intermediate voltage (neutral voltage) is the potential of the second output terminal OUT2. Other configurations are the same as those of the circuit shown in FIG.

  FIG. 16 is a circuit diagram of a main part of another inverter device 204B according to the fourth embodiment. A series circuit of capacitors Ci1 and Ci2 is connected between the first input terminal IN1 and the second input terminal IN2 of the inverter device 204B, and the connection point of the capacitors Ci1 and Ci2 is the potential of the second output terminal OUT2. Other configurations are the same as those of the circuit shown in FIG.

<< Fifth Embodiment >>
In the fifth embodiment, an inverter device including an H bridge circuit 30 in the subsequent stage of the three-level voltage generation circuit 20 is shown.

  FIG. 17 is a circuit diagram of a main part of an inverter device 205A according to the fifth embodiment. An H bridge circuit 30 is connected to the subsequent stage of the three-level voltage generation circuit 20. Other configurations are the same as those of the circuit shown in FIG. The H bridge circuit 30 is a circuit in which four switch elements S11, S12, S21, and S22 are bridge-connected. By switching of these four switch elements S11, S12, S21, and S22, the output voltage of the three-level voltage generation circuit 20 is alternately inverted and output.

  The three-level voltage generation circuit 20 generates a voltage corresponding to a half wave of a sine wave, and the H bridge circuit 30 inverts the voltage with a period of the sine wave. As a result, a sine wave voltage is output to the load.

  FIG. 18 is a circuit diagram of a main part of another inverter device 205B according to the fifth embodiment. The inverter device 205B includes a first input terminal IN1, a second input terminal IN2, and a first output terminal OUT1 and a second output terminal OUT2 that output an AC voltage. For example, a DC voltage generated by a photovoltaic power generation panel is applied to the first input terminal IN1 and the second input terminal IN2. In FIG. 18, Su and Sw represent a single-phase three-wire power system having a U phase and a W phase.

  In the inverter device 205B, two three-level voltage generation circuits 20H and 20L are connected between the first input terminal IN1 and the second input terminal IN2. The configurations of 20H and 20L are the same as those of the three-level voltage generation circuit 20 shown in FIG. However, the polarity of the target signal has an inverse relationship between the three-level voltage generation circuits 20H and 20L. A connection point between the two three-level voltage generation circuits 20H and 20L is a neutral point potential of the inverter device. The output of the H-bridge circuit 30 is connected to a single-phase three-wire system via inductors L1 and L2. An AC voltage having an effective voltage of 100V is applied between the first output terminal OUT1 and the neutral point NP, and an AC voltage having an effective voltage of 100V is applied between the neutral point NP and the second output terminal OUT2. An AC voltage having an effective voltage of 200 V is applied between OUT1 and the second output terminal OUT2.

<< Sixth Embodiment >>
FIG. 19 is a block diagram of a three-phase inverter device according to the sixth embodiment. The inverter devices 206U, 206V, and 206W are inverter devices that use the neutral point potential of the DC input voltage as the reference potential of the inverter device, for example, as shown in FIG. The voltages at the output terminals U, V, and W of these inverter devices 206U, 206V, and 206W are sinusoidal voltages, and the phase differences differ by 120 ° in order.

  In each of the embodiments described above, an example in which a MOS-FET is used as the switch element has been described, but an IGBT (Insulated Gate Bipolar Transistor) may be used as the switch element.

AQ1, AQ2 ... PWM modulation signal Cf ... Flying capacitors Ci1, Ci2 ... Capacitors
Fp: Target signal H, Mc, Md, L ... State IN1 ... First input terminal IN2 ... Second input terminal
Io… Load current
k ... feedback gains L1, L2 ... inductor NP ... neutral point OUT1 ... first output terminal OUT2 ... second output terminal S1 ... first switch element S2 ... second switch element S3 ... third switch element S4 ... first 4 switch elements
tc ... Center timing
td ... Dead time U, V, W ... Output terminal
Vc: Charging voltage
Vcf: Capacitor voltage
Vcr1: First triangular wave signal
Vcr2: Second triangular wave signal
Vdc ... Input voltage
Vo: Output voltage
Vu ... Output voltage 1 ... Input voltage detection circuit 2 ... Output current detection circuit 3 ... Capacitor voltage detection circuits 20, 20H, 20L ... 3-level voltage generation circuit 30 ... Bridge circuit 50 ... Dead time adjustment circuits 51-54 ... Delay circuit 55 56 ... Dead time increase / decrease circuit 60 ... PWM modulation circuit 70 ... Capacitor charge / discharge time adjustment circuit 71 ... Correction amount generation circuit 72 ... Target signal generation circuit 73 ... Addition circuit 74 ... Subtraction circuit 80 ... PWM modulation circuit 81, 82 ... Triangular wave Generation circuits 83, 84 ... Comparator 90 ... Switch element drive circuit 100 ... Switching control circuit 201 ... Inverter devices 204A, 204B ... Inverter devices 205A, 205B ... Inverter devices 206U, 206V, 206W ... Inverter devices

Claims (5)

The first end is connected to the first switch element to the fourth switch element connected in series between the first input terminal and the second input terminal of the DC power supply, and the first switch element and the second switch element. And a capacitor having a second end connected to a connection point between the third switch element and the fourth switch element, the connection point between the second switch element and the third switch element being an output terminal. A three-level voltage generation circuit,
By switching the first to fourth switch elements according to the comparison between the triangular wave signal and the modulation signal, the input voltage between the first input terminal and the second input terminal is PWM-modulated, PWM modulation means for outputting from the output end;
Capacitor voltage detection means for detecting the voltage of the capacitor;
Means for detecting an error from one half of the input voltage of the voltage of the capacitor;
Capacitor charge / discharge time adjusting means for adjusting the charge time and discharge time of the capacitor in a direction in which the error is reduced;
Modulation signal correction means for generating a first modulation signal obtained by correcting the modulation signal in the upward direction by a correction amount and a second modulation signal obtained by correcting the modulation signal in the downward direction by the correction amount;
The PWM modulation means, a first PWM modulation for generating the control signal of the first switch element and the fourth switching element in response to the comparison of the first triangular wave signal first modulated signal means and control of said first triangular wave signal and the second switch element and the third switch element in response to the comparison of the second triangular wave signal differing in phase by 180 ° the second modulation signal Second PWM modulation means for generating a signal for use,
The inverter charging / discharging time adjusting means increases or decreases the correction amount according to the error. The first end is connected to the first switch element to the fourth switch element connected in series between the first input terminal and the second input terminal of the DC power supply, and the first switch element and the second switch element. And a capacitor having a second end connected to a connection point between the third switch element and the fourth switch element, the connection point between the second switch element and the third switch element being an output terminal. A three-level voltage generation circuit,
By switching the first to fourth switch elements according to the comparison between the triangular wave signal and the modulation signal, the input voltage between the first input terminal and the second input terminal is PWM-modulated, PWM modulation means for outputting from the output end;
Capacitor voltage detection means for detecting the voltage of the capacitor;
Means for detecting an error from one half of the input voltage of the voltage of the capacitor;
Capacitor charge / discharge time adjusting means for adjusting the charge time and discharge time of the capacitor in a direction in which the error is reduced,
The PWM modulation means includes a first PWM modulation means for generating a control signal of the first switch element and the fourth switching element in response to a comparison between the modulation signal and the first triangular wave signal, the generating the control signal of the first triangular wave signal and the second switch element and the third switch element in response to a comparison between the modulation signal and the second triangular wave signal differing in phase by 180 ° are Two PWM modulation means,
A dead time for correcting the dead time of the PWM modulation signal by the first PWM modulation means in the increasing direction by a correction amount, and correcting the dead time of the PWM modulation signal by the second PWM modulation means in the decreasing direction by the correction amount. A correction means,
The inverter charging / discharging time adjusting means increases or decreases the correction amount according to the error.   The inverter device according to claim 1, wherein the correction amount is obtained by multiplying the error by a coefficient related to a capacitance of the capacitor and a coefficient related to a current flowing through the capacitor. The inverter device includes a differential input circuit having a balanced input and an unbalanced output, and an input unit connected to both ends of the capacitor.
The capacitor voltage detection means includes an output voltage of the differential amplifier circuit in a charging current cutoff period after the capacitor is charged, and the differential amplifier circuit in a discharge current cutoff period after the capacitor is discharged. The inverter apparatus in any one of Claims 1-3 which calculates | requires the average value of these output voltages.   The said capacitor voltage detection means detects the voltage of the said output terminal in the center timing of the period when the said 2nd switch element and the said 4th switch element are in an ON state. The described inverter device.

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