JP4703251B2 - Operation method of power supply device and power supply device - Google Patents

Description

  The present invention relates to a power supply device in which a plurality of inverter devices are connected in parallel, and more particularly to an operation method and a power supply device for a power supply device in which a plurality of inverter devices whose equivalent internal impedance can be varied only by control parameters are connected in parallel.

  When a large amount of output power is required, particularly when a large amount of DC power is required, a plurality of rectifiers have been connected in parallel for a long time. When a plurality of rectifiers are connected in parallel and operated in parallel, for example, a backflow prevention diode is connected to the output of each rectifier, and then connected in parallel on the subsequent stage side so that another rectifier can be connected to another It is possible to prevent current from flowing through the rectifier, that is, cross current. In addition, various configurations for preventing the cross current have been proposed. In the case of the rectifier, since the cross current can be prevented by an easy means, the parallel operation of the rectifier is widely performed.

  However, in the case of parallel operation of inverter devices, it is difficult to limit the cross current to a small value while controlling the pulse width of each inverter device in order to control the AC output power. If the output voltage is brought close to the target value by controlling the pulse width of the switching element of the inverter device, a voltage difference and a current difference occur between the inverter devices, and in some cases, the polarity may be reversed. However, it is considered to be technically difficult, and various techniques for solving these problems have already been proposed.

For example, before the parallel operation of the main-slave inverter device is started, the phase of the zero-cross detection signal from the control circuit of the slave inverter device is matched with the phase of the zero-cross signal from the zero-cross detection circuit in the control circuit of the main inverter device. That corrects the phase of a reference pulse, which is a basic signal for control of the control circuit, with the phase correction signal, thereby stabilizing the parallel operation of the main-slave inverter device. Yes (see, for example, Patent Document 1). In addition, inventions that suppress cross current have been proposed (see, for example, Patent Document 2, Patent Document 3, Patent Document 4, Patent Document 5, and Patent Document 6).
Also, in parallel operation of a plurality of inverter devices, each load current corresponding value and each inverter device output current corresponding value are input to the respective cross current detection circuits, and a cross current corresponding value corresponding to the cross current flowing between the inverter devices. The active power deviation and reactive power deviation are output from the cross current corresponding value and the output voltage corresponding value of the inverter device, the voltage control value is output based on the active power deviation, and the phase control value is calculated from the reactive power deviation. Is output to control the instantaneous value to make the internal impedance of each inverter device equivalently zero, and the cross current is suppressed by stably controlling the transient deviation of the phase and amplitude of the output voltage. The thing is also proposed (for example, refer patent document 7).

  Furthermore, various basic proposals have already been made regarding a constant sampling type error tracking power supply technology which is an example to which the present invention is applied (Patent Documents 8 to 10). An outline of the constant sampling type error tracking power supply will be described. First current detection means for detecting an output current of an inverter device including an inverter and an output filter connected to the output side thereof, the inverter and the output 2nd electric current detection means to detect the alternating current which flows between filters, and AC voltage detection means to detect the voltage of the said output filter are provided. A signal obtained by multiplying the current detection signal from the first current detector by an output current feedforward gain β, a voltage detection signal from the AC voltage detector, and a command voltage represented by a sine wave reference voltage signal; A current target function signal J (t) obtained by adding a signal obtained by multiplying the voltage signal indicating the difference between the two by an output voltage feedback gain α is formed. Next, it is determined at every constant sampling period whether or not the error signal Δt indicating the difference between the current target function signal J (t) and the current detection signal from the second current detector is within the target tracking range. To do. Then, the error signal Δt is sampled to generate a high frequency PWM signal for controlling the instantaneous value of the current, and the switching mode of the switching element of the inverter is selected according to the error signal Δt.

When the error signal Δt is negative, since the output current of the inverter device is smaller than the current target function signal J (t), the switching mode for increasing the output current of the inverter device is selected, and the error signal When Δt becomes positive, the output current of the inverter device is larger than the current target function signal J (t). Therefore, the first current detection means is selected by selecting a switching mode for reducing the output current of the inverter device. The current detection signal is to be controlled within a predetermined range.
Japanese Patent Laid-Open No. 08-205543 Japanese Patent Laid-Open No. 08-223807 JP 09-140148 A JP 2001-177997 A JP 2002-262577 A JP 2004-236696 A Japanese Patent Laid-Open No. 08-223808 Japanese Patent Application Laid-Open No. 07-7950 JP 2000-125575 A JP 2000-341156 A

However, the cross current prevention measures disclosed in the inventions of Patent Documents 1 to 7 require various complicated functions or circuits, which increases the cost of the power supply device and increases the size of the power supply device itself. Not only that, but the reliability is lowered. In addition, there is a problem that even if such a complicated function or circuit is provided, it is impossible to prevent the occurrence of a cross current due to the occurrence of noise during operation.
Further, the constant sampling type error tracking type power supply technology disclosed in the inventions of Patent Documents 8 to 10 has various technical advantages, but the disclosure of the basic technology related to a single inverter device is disclosed. However, the technology relating to the parallel operation of the inverter device has not been disclosed yet.

  The present invention is applied not only to the constant sampling type error tracking power supply technology but also to the parallel operation of an inverter device that can vary the equivalent internal impedance only by the control parameter, and the equivalent internal impedance can be varied only by the control parameter. The main purpose is to greatly simplify the cross current suppression technology in a power supply device in which a plurality of inverter devices are connected in parallel.

In order to solve the above-mentioned problem, the first invention has an output voltage feedback gain α, an output current feedforward gain β, and an inverter current gain G, (1−β · G) / (α · G) An operation method of a power supply device configured by connecting a plurality of inverter devices having a DC resistance value represented by the equivalent internal impedance in parallel, each of which is provided with a command voltage synchronized with each other, and the command voltage and A signal obtained by multiplying the difference voltage from the voltage detection signal of the output voltage of the inverter device by the output voltage feedback gain α, which is a positive value, and a current detection signal of the output current of the inverter device, a numerical value of 1 or less. Is added to the signal obtained by multiplying the output current feedforward gain β, to form a current target value of the inverter device, and The direct current resistance value determined by the rated value of the output voltage and output current of the barter device is 100% equivalent internal impedance, and the control parameter of the inverter device is the allowable current value of the cross current flowing between the inverter devices. There is provided a method of operating a power supply apparatus, wherein the value of the equivalent internal impedance is changed by adjusting both or any one of an output voltage feedback gain α and an output current feedforward gain β .

The second invention is characterized in that the equivalent internal impedance is changed in a range of 2 to 10% with respect to the equivalent internal impedance determined by rated values of an output voltage and an output current of the inverter device. A method for operating a power supply device according to the first aspect of the invention is provided.

In order to solve the above-mentioned problem, the third invention is such that when the output voltage feedback gain is α, the output current feedforward gain is β, and the inverter current gain is G, (1−β · G) / (α · G Is a power supply device configured by connecting in parallel a plurality of inverter devices having a DC resistance value represented by an equivalent internal impedance, the voltage command means for giving a command voltage synchronized with each other, the command voltage and the inverter device Voltage gain means for multiplying the voltage of the difference between the output voltage and the voltage detection signal by the output voltage feedback gain α which is a positive numerical value, and the output which is a numerical value of 1 or less to the current detection signal of the output current of the inverter device Current gain means for multiplying the current feedforward gain β, and addition means for adding the output signal of the voltage gain means and the output signal of the current gain means , And a DC resistance value determined by a rated value of the output voltage and output current of the inverter device as an equivalent internal impedance of 100%, and an allowable current value of a cross current flowing between the inverter devices To adjust the value of the equivalent internal impedance by adjusting the output voltage feedback gain α and / or the output current feedforward gain β that are control parameters of the inverter device I will provide a.

4th invention changes the said equivalent internal impedance in 2-10% of range with respect to the said equivalent internal impedance defined by the rated value of the output voltage and output current of the said inverter apparatus, The said 1st is characterized by the above-mentioned . A power supply apparatus according to the third aspect of the invention is provided.

According to the first and second aspects of the present invention, there is provided a method of operating a power supply device that can reliably limit a cross current flowing between inverter devices in which a plurality of devices are connected in parallel to a small current value only by adjusting a control parameter. Can do.

According to the third and fourth aspects of the invention, the equivalent internal impedance is changed by changing both or either of the output voltage feedback gain α and the output current feedforward gain β, and the output of the inverter devices connected in parallel is changed. By adjusting, it is possible to provide a power supply device that can reliably limit the cross current flowing between the inverter devices to a small current value.

[Embodiment 1]
The best embodiment 1 for carrying out the present invention will be described with reference to FIGS. FIG. 1 is a diagram for explaining a constant sampling type error tracking type inverter device 80 which is a typical example of an inverter device capable of varying an equivalent internal impedance only by a control parameter adopted by the present invention. These are the figures for demonstrating the power supply device 100 of 1st Embodiment formed by connecting the constant sampling type | mold error follow-up type inverter apparatus 80 in parallel. First, the constant sampling type error tracking type single-phase inverter device 80 will be described with reference to FIG. 1. The inverter 2 is connected to both ends of the DC power supply 1. The DC power source 1 is a general one, and is, for example, a rectifier that rectifies the power of a commercial AC power source to convert AC to DC, or a solar cell panel. The inverter 2 is a single-phase inverter composed of four IGBT-like semiconductor elements S1 to S4 formed by full-bridge connection and diodes D1 to D4 connected in parallel to each of the semiconductor elements in reverse polarity. . However, the inverter 2 is not limited to a full-bridge configuration, for example, a half-bridge type single-phase inverter in which two semiconductor elements such as IGBT or MOSFET and two capacitors are connected in a full-bridge configuration, Alternatively, as shown in Patent Document 8, an inverter single-phase voltage doubler type inverter or the like in which two DC power sources 1 are connected in series to form a single-phase voltage doubler configuration may be used. A power switch SW is provided between the DC power source 1 and the inverter 2.

  The AC side line L1 of the inverter 2 is provided with a first current detector 3 such as a current transformer (CT) that detects an inverter current i1, and the AC side line L1 has a current holding inductor Lp. An output filter circuit 4 including a filter resistor Rf, a filter capacitor Cf, and a filter inductor Lf is connected between the load side of the current holding inductor Lp and L2. A filter voltage detector 5 is provided between terminals in which the filter resistor Rf and the filter capacitor Cf are connected in series. The output filter circuit 4 is not limited to the one composed of the filter resistor Rf, the filter capacitor Cf, and the filter inductor Lf. Further, a second current detector 6 such as a current transformer for detecting the output current i2 of the inverter device 80 flowing through the filter inductor Lf is provided. A load 50 is connected to the output terminals 7A and 7B of the inverter device 80 as an external circuit. The load 50 is a general AC load that receives power supply, a general DC load that receives power supply from a rectifier circuit, or a load that includes a general DC load that receives power supply from a transformer, a rectifier circuit, and the like. The inverter device 80 can supply power to various loads.

  Further, the constant sampling type error tracking type inverter device 80 performs a predetermined process (to be described later) on the output current detection signal and the output voltage detection signal to obtain a current target function signal J (t), and a current target value forming unit 8. And a gate command / PWM control unit 9 for selecting a switching mode of the semiconductor elements S1 to S4 of the inverter 2 from the current target function signal J (t) and the inverter current detection signal. These are preferably configured to be capable of digital control, such as a microcomputer. In the drawing, an A / D conversion circuit for analog-digital (A / D) conversion of each detection signal is omitted, but in the first embodiment, a microcomputer is used, and each value will be described as a digital value.

  The current target value forming unit 8 is a voltage command means 8A that gives a command voltage Va represented by a reference sine wave voltage whose polarity changes in positive and negative by 180 degrees, and the current of the output current i2 detected by the second current detector 6. Current gain means 8B for multiplying detection signal Δi2 by output current feedforward gain β, first subtraction means 8C for subtracting voltage detection value Δv1 of inverter voltage v1 detected by inverter voltage detector 5 from command voltage Va, and subtraction thereof Voltage gain means 8D that multiplies the output voltage by the feedback gain α, and adds the current signal corresponding to the voltage value multiplied by the output voltage feedback gain α and the current signal multiplied by the output current feedforward gain β to obtain a current target. It comprises second adding means 8E that generates a function signal J (t).

  The voltage command means 8A gives a command voltage Va which is a reference sine wave voltage (Esin ωt) that changes in positive and negative at 180 degrees in synchronization with a synchronization signal from the outside of the inverter device, or a reference sine wave voltage of a predetermined frequency A command voltage Va represented by (Esinωt) is generated. This reference sine wave voltage (Esinωt) determines the output frequency of the inverter device 80. For example, if the output frequency of the inverter device 80 is 50 Hz, the reference sine wave voltage (Esinωt) is determined to be 50 Hz. The command voltage Va typified by this reference sine wave voltage is important for the parallel operation of the inverter device, and the synchronization signal is generated in a cycle that determines each cycle of the reference sine wave voltage. The command voltage Va is given as a digital value corresponding to the instantaneous value of the reference sine wave voltage (Esinωt). When a plurality of inverter devices are operated in parallel, the reference sine wave voltage (Esinωt) may be synchronized with each other by synchronizing with a common synchronization signal from the outside, or each inverter device The voltage command means 8A may have the same frequency and generate a command voltage Va having a reference sine waveform at the same time while following each other. The command voltage Va may be a value corresponding to a target value of the terminal voltage of the filter capacitor Cf, for example. The command voltage Va is not necessarily a sine wave.

  The current gain means 8B multiplies the current detection signal Δi2 of the output current i2 of the inverter device 80 detected by the second current detector 6 by the output current feedforward gain β to give Δi2 · β. This output current feedforward gain β is a current gain for preventing the output voltage from being changed by the output current, and is an important factor of the present invention described later. In the present invention, the output current feedforward gain β can also be set by a sequence. In this embodiment, the current detection signal Δi2 of the output current i2 is a digital value corresponding to an instantaneous value sampled every short fixed time. Here, the output voltage feedback gain α is a numerical value larger than zero, and the output current feedforward gain β is a numerical value of 1 or less.

  The subtracting means 8C subtracts a digital value corresponding to an instantaneous value obtained by sampling the voltage detection value Δv1 of the inverter voltage v1 at short regular intervals from the command voltage Va to obtain a difference. The subtraction result is represented by (Va−Δv1). Therefore, the signal on the output side of the voltage gain means 8D becomes (Va−Δv1) · α obtained by multiplying (Va−Δv1) by the output voltage feedback gain α. This output voltage feedback gain α is also a voltage gain value that can be set to an optimum value according to a sequence in the same manner as the output current feedforward gain β. As will be described later, in the present invention, the output voltage feedback gain α and the output current feedforward are set. The gain β is a very important factor in determining the equivalent internal impedance of the inverter device. The adding means 8E adds Δi2 · β from the current gain means 8B and (Va−Δv1) · α from the voltage gain means 8D to generate a current target function signal J (t). The current target function signal J (t) is given to the gate command / PWM control unit 9.

  The gate command / PWM control unit 9 includes subtracting means 9A that subtracts the current target function signal J (t) from the current detection signal Δi1 of the inverter current i1 detected by the first current detector 3. As described above, the current detection signal Δi1 is also a digital value corresponding to an instantaneous value sampled every short fixed time. Therefore, the subtracting means 9A calculates (Δi1-J (t)) to obtain the error signal Δt. This error signal is input to the gate command / PWM circuit 9B, and a gate selection is made as to which of the semiconductor elements S1 to S4 of the inverter 2 is applied as described below.

The gate command / PWM circuit 9B issues a gate command according to the polarity of the difference between the current detection signal Δi1 of the inverter current i1 and the current target function signal J (t). The gate command is as follows. When Δt = Δi1−J (t) is negative, the inverter current i1 is smaller than the target value, so the switching mode for increasing the current is selected. When Δt = Δi1−J (t) is positive, since the inverter current i1 is larger than the target value, the switching mode for reducing the current is selected. That is, in error tracking type pulse width modulation, the switching mode is selected as follows according to the polarity of the error signal Δt.
(1) As switching mode 1, when Δt = Δi1-J (t) ≦ 0, the semiconductor elements S3 and S4 are on, and the semiconductor elements S1 and S2 are off.
(2) As switching mode 2, when Δt = Δi1−J (t)> 0, the semiconductor elements S1 and S2 are on, and the semiconductor elements S3 and S4 are off.
(3) As the switching mode 3, there is a recirculation mode in which power supply from the DC power source 1 is not performed. In this case, the semiconductor elements S1 and S4 are on, the semiconductor elements S2 and S3 are off, or the semiconductor elements S2, S3 is on and the semiconductor elements S1 and S4 are off.

  The semiconductor elements S1 to S4 of the inverter 2 are turned on based on the gate command from the gate command / PWM circuit 9C determined based on the polarity of the error signal Δt, or remain off. For example, if the state of Δt = Δi1-J (t) ≦ 0 continues, the semiconductor elements S1 and S2 remain on until Δt = Δi1-J (t)> 0, and the semiconductor element S3 S4 remains off. This point is different from the switching operation of PWM control by the triangular wave (sawtooth wave) comparison method that is usually used.

  As is well known, in general, an equivalent circuit viewed from the output terminal of a power supply is expressed by a voltage source and an equivalent internal impedance. If the equivalent internal impedance is 0, an ideal power source in which the output terminal voltage does not change no matter how much current flows. Actually, this equivalent internal impedance does not become 0 and cannot be freely controlled. The equivalent internal impedance is obtained by first finding that no current flows when the output terminal is opened (no load), and therefore the voltage drop due to the equivalent internal impedance is zero. Therefore, the no-load voltage Vo becomes the output voltage of the voltage source. Next, since the voltage difference between the output voltage Vc and the no-load voltage Vo when a load having an impedance Zx is connected is a voltage drop due to the equivalent internal impedance, assuming that the current flowing at that time is I, Vo−Vc = XI relationship. Therefore, the equivalent internal impedance X is X = (Vo−Vc) / I = (Vo−Vc) Zx / Vc.

  The constant-sampling error-following inverter device is characterized by the fact that the characteristics of the inverter as a current amplifier can be expressed by mathematical formulas. High-level control suitable for error-following PWM (control using current target forming means) is used. By adopting it, the equivalent internal impedance can be calculated. The equivalent internal impedance Z of the inverter 2 viewed from the output filter circuit 4 is composed of a resistor and a capacitor. The total resistance value decreases linearly with an increase in the current feedforward gain β that is a control parameter, and is inversely proportional to the voltage feedback gain α that is a control parameter. In most cases, the capacitance in the equivalent circuit is in parallel with a small resistance, and its time constant is negligibly short compared to the frequency component of the main circuit current, so the equivalent internal impedance Z of the inverter 2 can be considered as a resistance component. It decreases linearly as β increases, and is inversely proportional to the output voltage feedback gain α, which is another control parameter. For this reason, when the current gain of the inverter 2 is G, the equivalent internal impedance Z of the inverter 2 is expressed by the equation (1−β · G) / (α · G) [Ω]. Here, the current gain G of the inverter 2 is a value determined from the dead time of the inverter 2, a DC voltage, an AC voltage, etc., and is almost 0.99 in most cases, and can be approximated to 1. It is. The current gain G cannot be obtained by calculation or the like, but is a value unique to the inverter device obtained by actual measurement. However, in an inverter device having the same circuit configuration and substantially the same electrical characteristics, the current gain G has substantially the same value.

  Therefore, in the first embodiment, an inverter device exhibiting an equivalent internal impedance Z substantially equal to the DC resistance value represented by the equation (1-β · G) / (α · G) [Ω], that is, the same circuit configuration, Two constant sampling type error tracking inverter devices 80 (1) and 80 (2) having substantially the same electrical characteristics such as the same capacity are connected in parallel as shown in FIG. Set the output voltage feedback gain α and the output current feedforward gain β, which are control parameters, so that the equivalent internal impedance Z of the follow-up type inverter device becomes a value that can limit the cross current to an allowable value or less. By adjusting and setting a certain output current feed forward gain β, cross current is suppressed. Of course, the present invention can be applied in the same manner even when three or more constant sampling type error tracking type inverter devices are connected in parallel. Further, if the input / output characteristics of the inverter devices 80 (1) and 80 (2) are substantially the same, the inverter devices 80 (1) and 80 (2) are set to have the same equivalent internal impedance Z value. Shares the load voltage almost evenly.

  In the power supply device 100 of FIG. 2, the command voltages Va of the inverter devices 80 (1) and 80 (2) are required to be synchronized with each other as described above. The synchronization signal generation circuit 10 provides a synchronization signal to the voltage command means 8A of the inverter devices 80 (1) and 80 (2) through the signal line 10A. FIG. 2 shows an example in which a power supply device in which the output terminals 7A and 7B of two inverter devices 80 (1) and 80 (2) are connected in parallel to both ends of the load 50 is operated. As described above, the present invention is characterized in that a large number of inverter devices can be handled in the same manner as in the case where two inverter devices are operated in parallel. When a large number of inverter devices are operated in parallel, an optical fiber is used as the signal line 10A and an optical synchronization signal is given to each voltage command means 8A of each inverter device, so that it is not affected by noise. Even when the units are parallel, the cross current flowing between the inverter devices can be reliably suppressed.

  The synchronization signal generation circuit 10 generates a synchronization signal every half cycle or one cycle of a predetermined reference sine wave voltage or every predetermined cycle. That is, it is assumed that the synchronization signal is generated with a period for determining each period of the reference sine wave voltage as the command voltage Va. Each voltage command means 8A operates at the rising edge of each synchronization signal to generate a command voltage Va represented by a reference sine wave voltage (Esinωt). Therefore, the frequency of the output voltage of each inverter device is the same as the frequency of the reference sine wave voltage (Esin ωt), and the phase is also the same, so that the amplitude of the output voltage is not significantly different in a normal state. It should be noted that the voltage command means 8A of the respective inverter devices 80 (1) and 80 (2) generate reference sine waveform signals having the same frequency and are synchronized with each other, and the reference sine waveform signals at the same time while following each other. If generated, the synchronization signal generating circuit 10 can be omitted.

  The inverter devices 80 (1) and 80 (2) perform PWM control in synchronization with a constant sampling type error tracking method, but the magnitude of the output voltage of the inverter devices 80 (1) and 80 (2), that is, The amplitude is often different. In this case, a part of the output current tends to flow from the inverter device having a large amplitude of the output voltage to the inverter device having a small amplitude, but in the present invention, the inverter devices 80 (1) and 80 (2) reduce the cross current to an allowable value or less. Since it has an equivalent internal impedance Z that can be suppressed, the voltage drop of the output filter circuit 4 increases as the output current increases, and the output voltage of the inverter decreases. The error tracking type PWM control is performed so that the two are equal to each other.

  Therefore, even in the case of a power supply device in which a large number of inverter devices are connected in parallel, according to the power supply device 100 of the first embodiment, the cross current is limited to an allowable value or less without performing control for suppressing the cross current. can do. Here, since the equivalent internal impedance Z is an equivalent impedance, no power loss actually occurs. Therefore, even if the equivalent internal impedance Z is increased, the power loss does not increase, and the cross current can be suppressed to a small value. However, since the output voltage is greatly reduced, the equivalent internal impedance Z of each inverter device is Is a value that allows a sufficient rated current to flow, and a value that can limit the current to an allowable value for cross current. Since the allowable value of the cross current differs depending on the power supply device, it cannot be determined unconditionally. For example, the rated voltage of the inverter devices 80 (1) and 80 (2) is Vr, the rated current is Ir, and Vr / Ir = R. When R is 100 (%), 2 to 10% is a preferable equivalent internal impedance value. As a specific example, if Vr = 200V and Ir = 10A, 20Ω is the value of the equivalent internal impedance Z of 100%, 2% is 0.4Ω, and 10% is 2Ω. Therefore, first, the output voltage feedback gain α may be set based on various conditions of each inverter device, and the output current feedforward gain β may be set so as to have a predetermined equivalent internal impedance. The equivalent internal impedance of each inverter device does not need to be the same value when the output capacities are not the same or when the load sharing does not have to be uniform.

  The value of the equivalent internal impedance Z is a guideline until it gets tired. If the allowable current value of the cross current is large, the ratio of the equivalent internal impedance Z can be made smaller than the above, and conversely, If the current value is more severe, the ratio of the equivalent internal impedance Z may have to be made larger than the above. Therefore, when a plurality of the constant sampling type error tracking type inverter devices 80 are operated in parallel, the equivalent internal impedance Z of each inverter device is a control parameter so that the cross current becomes a resistance value that can be limited to an allowable value or less. Since a certain output voltage feedback gain α and output current feedforward gain β are set, troubles such as failure occur or unless the output voltage feedback gain α and output current feedforward gain β are changed to different values. Thus, it is possible to reliably limit the cross current to an allowable value or less without performing special control.

  The configuration of the inverter 2 may be a half-bridge configuration as described above, or a single-phase voltage doubler type inverter in which two DC power supplies 1 are connected in series to form a single-phase voltage doubler configuration. Is not explained because it has been described in the above-mentioned patent document, but even in a half-bridge configuration or a single-phase voltage doubler type inverter, etc. Exhibits an equivalent internal impedance substantially equal to the DC resistance value represented by the equation (1-β · G) / (α · G) [Ω]. Therefore, even when a plurality of these inverter devices are connected in parallel, the equivalent internal impedance Z expressed by the equation (1-β · G) / (α · G) [Ω] cannot be allowed. By adapting to this, the cross current between the inverter devices can be limited to an allowable value or less as described above without detecting the cross current and performing special control. In the above description, each inverter device connected in parallel has been described as having substantially the same output capacity. However, even if inverter devices having different output capacities are connected in parallel, the equivalent internal impedance is matched to the output sharing. It can be easily understood that the cross current can be limited to an allowable value or less by adjusting.

  In the first embodiment, the voltage limiter or current limiter for limiting the output signal of the subtracting means 8C or the adding means 8E to a predetermined range, the PWM control error correcting means, etc. are directly related to the present invention. However, these means are required for more preferable operation and accurate control. The same applies to the following embodiments, and the voltage limiter, current limiter, or PWM control error correction means will be described in a three-phase AC constant sampling type error tracking inverter device to be described later.

[Embodiment 2]
In the above embodiments, as an inverter device capable of varying the equivalent internal impedance only by the control parameter, a single-phase configuration constant sampling type error tracking type inverter device and a constant sampling type error tracking type power source device connected in parallel with each other are described. However, since the limitation of the cross current in the power supply device 200 in which a plurality of three-phase AC constant sampling type error tracking type inverter devices 90 are connected in parallel can be performed as in the first embodiment, FIGS. The three-phase AC constant sampling type error tracking type inverter device 90 and the power supply device 200 will be described. The power supply device 200 according to the second embodiment is also suitable for using a microcomputer, and does not particularly show an A / D conversion circuit. However, each analog detection signal is converted into a digital detection signal, and the subsequent processing is digital. It is assumed that processing is performed.

  3 and 4, the same symbols as those used in FIGS. 1 and 2 indicate members having the same names. In FIG. 3, an inverter 2 includes six switch elements U each composed of a semiconductor element S represented by a self-extinguishing voltage driving element such as a MOSFET or IGBT and a diode D connected in parallel to the semiconductor element S in the opposite direction. , V, W, X, Y, Z are three-phase inverters connected in a three-phase full-bridge configuration. The line connected to the connection point a between the switch elements U and X is connected to L1, the line connected to the connection point b between the switch elements V and Y is connected to L2, and the connection point c between the switch elements W and Z is connected. The line is L3. Current detectors 3A, 3B, and 3C that detect inverter currents i1a, i1b, and i1c flowing through the respective lines L1, L2, and L3 are provided. Inductors Lp1, Lp2, Lp3 for holding current are connected in series to the respective lines L1, L2, L3. Further, an output filter circuit 4 in which an output filter circuit including a filter resistor Rf, a filter capacitor Cf, and a filter inductor Lf is connected between the lines L1 and L2, between the lines L2 and L3, and between the lines L1 and L3 is configured. Is done. And filter voltage detector 5A, 5B, 5C which each detects the voltage between the terminals of filter resistance Rf and filter capacitor Cf between each phase is provided. Of course, the output filter circuit 4 for three-phase alternating current may have another circuit configuration that does not include the filter resistor Rf.

  Furthermore, output current detectors 6A, 6B and 6C for detecting output currents i2a, i2b and i2c of each phase are provided, and a load 50A is connected between the output terminals 7A and 7B, and the output terminals 7B and 7C A load 50B is connected between the output terminals 7A and 7C, and a load 50C is connected between the output terminals 7A and 7C. Note that the current detector for one phase and the filter voltage detector for one phase, for example, 3B, 6B, and 5B can be omitted. Similarly to the single-phase configuration constant sampling type error tracking type inverter device, the current target value forming unit 8 that generates the current target function signal J (t), the current target function signal J (t), the inverter current detection signal, To a gate command / PWM control unit 9 for selecting a switching mode of the semiconductor elements S1 to S6 of the inverter 2.

  Before explaining the current target value forming unit 8, dq conversion will be briefly described. The dq conversion is often used in handling a three-phase AC inverter, and the voltage and current of the three-phase AC are used as a power supply voltage. It converts to a synchronized value on the dq axis (rotating coordinate system). By performing dq conversion, three-phase alternating current can be handled in the same way as direct current. In the current target value forming unit 8, the filter voltage command means 8a is a DC voltage obtained by dq conversion of the command value of the three-phase balanced AC voltage, which is the target voltage to be output, here the target voltage value of the terminal voltage of the filter capacitor Cf. Command voltage value Vf is output. The capacitor current command means 8b gives a direct current command value If for correcting the current flowing through the filter capacitor Cf. Assuming that the voltage of the filter capacitor Cf is at the command voltage value Vf, the current flowing through the filter capacitor Cf at that time is calculated in advance, and the current command is added and corrected so as to be the current. In short, it is basically the same as feeding forward the current flowing through the load. Here, since the d-axis current is an active current and the q-axis current is a reactive current, in the case of a capacitor, the current command value If is only the q-axis component in the dq coordinate. Further, the PWM current error compensation means 8c corrects the deviation to zero because the deviation occurs in the output current with respect to the current command value If in the error tracking type PWM.

  The voltage detected by the filter voltage detectors 5A, 5B, and 5C is a matrix UM that performs dq conversion after three-phase to two-phase conversion (the matrix U is a rotation matrix and the matrix M is a three-phase to two-phase conversion matrix). After being dq transformed by the coordinate transformation means 8d having the above, it is inputted as a signal Δvf to the subtraction means 8f through the low-pass filter 8e. The subtracting unit 8f subtracts Δvf from the voltage command value Vf of the filter voltage command unit 8a and outputs (Vf−Δvf) = UΔv (t). This value UΔ (t) is limited in a predetermined range by the voltage limiter 8g, and is added to the adding means 8i after being multiplied by the output voltage feedback gain α which is a control parameter by the voltage feedback means 8h.

The current detection signals of the output currents i2a, i2b, i2c are dq transformed by the coordinate transformation means 8j having the dq transformation matrix, and then multiplied by the output current feed forward gain β which is another control parameter by the current gain means 8k. Above, it is added to the adding means 8i. Further, the current command value If from the capacitor current command means 8b is multiplied by the current feed forward gain γ by the current gain means 8l and then added to the adding means 8i. Here, the output current feedforward gain β is a numerical value of 1 or less, and the output voltage feedback gain α and the current feedforward gain γ are numerical values greater than zero. The signal obtained by adding the current signal corresponding to the voltage value by the adding means 8i, the current signal, and the current command signal is limited to a predetermined range by the signal limiter 8m, and then the PWM current error compensating means. The current compensation value Ic from 8c is added by the adding means 8n and processed by the coordinate conversion means 8p having the inverse coordinate conversion matrix (UM) ^−1, and the gate command / PWM control section as the current target function signal J (t) 9 is given.

  On the other hand, the inverter currents i1a, i1b, i1c flowing through the lines L1, L2, L3 are detected by the respective current detectors 3A, 3B, 3C, and these current detection signals are input to the gate command / PWM control unit 9. In the gate command / PWM control unit 9, an error signal Δt obtained by subtracting these current detection signals from the current target function signal J (t) is obtained, and the gate is determined according to the polarity of the error signal Δt as in the case of the single-phase inverter device. A command, that is, a switching mode is selected. The basic switching mode in the three-phase AC inverter device, that is, the gate command is the following six types.

The lines L1, L2, and L3 are a-phase, b-phase, and c-phase, and the differences between the current target function signal J (t) and the currents i1a, i1b, and i1c flowing through the phases are Δa, Δb, and Δc.
(1) Switching mode 1 is when Δa ≧ 0, Δb <0, and Δc <0. At this time, the switch elements U, Y, and Z are on and the switch elements V, W, and X are off. On the input side (inverter side) of the output filter circuit of each phase, the inductor Lp1 for holding the a-phase current The current flowing through increases.
(2) Switching mode 2 is a case where Δa ≧ 0, Δb ≧ 0, and Δc <0. At this time, the switch elements U, V, and Z are on, and the switch elements W, X, and Y are off. On the input side of the output filter circuit of each phase, the a-phase current holding inductor Lp1 and the b-phase inductor The current flowing through the current holding inductor Lp2 increases.
(3) Switching mode 3 is a case where Δa <0, Δb ≧ 0, and Δc <0. At this time, the switch elements V, X, and Z are turned on, and the switch elements U, W, and Y are turned off. On the input side of each phase output filter circuit, the current flowing through the inductor Lp2 for holding the b-phase current flows. To increase.
(4) Switching mode 4 is a case where Δa <0, Δb ≧ 0, and Δc ≧ 0. At this time, the switch elements V, W, and X are on and the switch elements U, Y, and Z are off. On the input side of each phase of the output filter circuit, the b-phase current holding inductor Lp2 and the c-phase current The current flowing through the current holding inductor Lp3 increases.
(5) Switching mode 5 is a case where Δa <0, Δb <0, and Δc ≧ 0. At this time, the switch elements W, X, and Y are on, and the switch elements U, V, and Z are off. On the input side of the output filter circuit of each phase, the current flowing through the inductor Lp3 for holding the c-phase current is To increase.
(6) Switching mode 6 is a case where Δa ≧ 0, Δb <0, and Δc ≧ 0. At this time, the switch elements U, W, and Y are on, and the switch elements V, X, and Z are off. On the input side of the output filter circuit of each phase, the a-phase current holding inductor Lp1 and the c-phase current The current flowing through the current holding inductor Lp3 increases.

  Then, a constant sampling type error following three-phase AC inverter device 90 controlled to make the error signals Δa, Δb, Δc zero by a gate command performed according to the polarities of the error signals Δa, Δb, Δc. Then, similar to the inverter device 80 of the above-described embodiment, it exhibits an equivalent internal impedance Z substantially equal to the DC resistance value represented by the equation (1-β · G) / (α · G) [Ω]. Therefore, as shown in FIG. 4, such a constant sampling type error tracking type three-phase AC inverter device 90 is connected to two or more units in parallel. Signals are given to the coordinate conversion means 8d, 8j, and 8p, respectively, to synchronize the inverter devices.

  Therefore, also in the second embodiment, the circuit configuration is the same as the example of the three-phase AC inverter device exhibiting the equivalent internal impedance Z expressed by the equation (1-β · G) / (α · G), and the electrical characteristics As shown in FIG. 4, two or more constant-sampling error-tracking inverter devices 90 having substantially the same value are connected in parallel, and the control parameters are set so that the equivalent internal impedance Z that can limit the cross current to an allowable value or less is obtained. By setting a certain output voltage feedback gain α and an output current feedforward gain β, particularly by adjusting and setting the output current feedforward gain β, the cross current can be suppressed by synchronizing all the inverters. As in the case of the single phase, in the case of the constant sampling type error tracking type three-phase AC inverter device 90, all the inverter devices connected in parallel have an equivalent internal impedance Z that is more than enough to suppress the cross current to an allowable value or less. Therefore, as the output current increases, the voltage drop of the filter circuits 4A and 4B increases, and the output voltage of the inverter decreases. Therefore, the error tracking type is used so that the output voltages of the respective inverter devices are equal to each other. PWM control is performed.

  Therefore, even in the case of the power supply device 200 in which a large number of constant sampling type error tracking type three-phase AC inverter devices 90 are connected in parallel, according to the present invention, the control for suppressing the cross current is not performed. It is possible to limit the cross current to an allowable value or less. Here, since the equivalent internal impedance Z is an equivalent impedance, no power loss actually occurs. However, if the equivalent internal impedance Z is increased, the cross current can be suppressed to a smaller value, but the output voltage is reduced. It gets bigger. Therefore, it is desirable that the equivalent internal impedance Z of each three-phase AC inverter device is a value that allows each three-phase AC inverter device to sufficiently flow a rated current and that can limit the cross current to an allowable value or less. The equivalent internal impedance Z of each three-phase AC inverter device is set to substantially the same value when the load sharing is made uniform, and the value of the equivalent internal impedance Z is also the same when the load sharing is not necessarily uniform. Not necessarily. Further, as described above, even if the output capacities of the inverter devices are not the same, the cross current can be limited to an allowable value or less by appropriately setting the value of the equivalent internal impedance. It is desirable that the equivalent internal impedance Z of each three-phase AC inverter device during operation is a value that allows a rated current to flow sufficiently. The present invention can also be applied to the case where the output voltage of the three-phase inverter is used as a sine wave having a phase difference of 180 °, that is, a single-phase three-wire voltage.

  As the load demand increases, it is necessary to connect the inverter devices 90 in parallel as shown in FIG. In this case, before the parallel connection, the equivalent internal impedance Z of the connected inverter device is changed to the first set value that is the set maximum value Zm, and the inverter device is not subjected to synchronous verification in that state. Connect in parallel. After the parallel connection, the output voltage feedback gain α and the output current feedforward gain β, which are control parameters, are adjusted according to the sequence, and the equivalent internal impedance Z is reduced to a value that can limit the cross current to an allowable value or less. Further, when the power supply of an inverter device is effectively stopped due to a decrease in load demand, an equivalent internal impedance Z is adjusted by adjusting the output voltage feedback gain α and the output current feedforward gain β that are control parameters of the inverter device. Is changed to the first set value which is the set maximum value Zm. As a result, the inverter device can be effectively put into a dormant state without being mechanically disconnected. If necessary, the inverter device may be disconnected by turning off a power switch (not shown) in this state.

  When any one of the three-phase inverter devices 90 (1) to 90 (N) is turned on as described above, or effectively stopped, or disconnected from the commercial AC power supply system or turned on, feedback is provided. It is not preferable to sharply change the gain α and the output current feedforward gain β. For example, when the three-phase inverter device is supplying power to a load, if any of the inverter devices effectively stops generating output power, the equivalent internal impedance Z of the inverter device is maximized. It is preferable to increase over the set time to the set value Zm. This set time is preferably not less than three times the output period t of the inverter device when not connected to a commercial AC power supply system. By applying this set time, the impact of surge is small in effect. Can be stopped. Further, when testing or maintaining / inspecting the inverter device that is being fed, the equivalent internal impedance Z of the inverter device to be tested or maintained / inspected is increased to the maximum set value Zm, and then the test or maintenance / inspection is performed, Alternatively, if the equivalent internal impedance Z of the inverter device is increased to the maximum set value Zm and then the power switch is turned off and then the test or maintenance / inspection is performed, the effect of the surge is also present in the test or maintenance / inspection. A small shockless power supply suspension is possible.

  In the above embodiment, the case where the constant sampling type error tracking type inverter device is operated independently from the commercial AC power supply system regardless of the single operation or the parallel operation is mainly described. And drive. In this case, it may be necessary to disconnect this constant-sampling error-tracking inverter device from the commercial AC power supply system, that is, to disconnect or switch on. When connecting to a commercial AC power supply system, the equivalent internal impedance Z of all inverter devices to be connected is set by adjusting the output voltage feedback gain α and the output current feedforward gain β, which are control parameters, according to a sequence in advance. The first set value, which is the maximum value Zm, is set to a practically inactive state, and in this state, the system is connected to the commercial AC power supply system without performing synchronization verification.

  Then, after the interconnection, the output voltage feedback gain α and the output current feedforward gain β are increased according to the sequence, so that the equivalent internal impedance Z of each inverter device is gradually increased from the set maximum value Zm to the value Zs during operation. While making it smaller, the phase of the inverter device is matched with the phase of the commercial AC power supply system. At this time, in order not to generate a surge voltage or the like in the commercial AC power supply system, the equivalent internal impedance Z of all the connected inverter devices is gradually reduced over a period of 50 times or more the period T of the commercial AC power supply system. Is preferred. Further, as described above, the equivalent internal impedance Z of each inverter device is set to a value that can limit the cross current to an allowable value.

  On the other hand, when any inverter device that has actually stopped supplying power starts to supply output power, the equivalent internal impedance Z of the inverter device set to the maximum set value Zm is set to the set time described above. If it is reduced to an equivalent internal impedance Zs smaller than the maximum set value Zm, shockless power supply can be started with less influence of surge. The same applies to testing or maintenance / inspection. When the equivalent internal impedance Z of the inverter device is the maximum set value Zm, the power switch is turned on, and then the output voltage feedback gain α and the output current feed forward gain β Without changing abruptly, the equivalent internal impedance Z of the inverter device may be gradually reduced to a small value during operation by changing it over the set time.

In the above description, the sampling type error tracking type power supply device has been described as an embodiment. However, the present invention is not limited to this, and control parameters such as the output voltage feedback gain α and the output current feedforward gain β are used. It can be applied to all power supply devices in which the equivalent internal impedance can be adjusted, that is, changed only by the above.

It is a figure which shows the constant sampling type | mold error follow-up type single phase inverter apparatus 80 used for Embodiment 1 which concerns on this invention. It is a figure which shows the block structure of the power supply device 100 formed by connecting the constant sampling type | mold error follow-up type single phase inverter apparatus in Embodiment 1 which concerns on this invention in parallel. It is a figure which shows the constant sampling type | formula error tracking type | formula three-phase inverter apparatus 90 used for Embodiment 2 which concerns on this invention. It is a figure which shows the block configuration of the power supply device 200 formed by connecting the constant sampling type | mold error tracking type | formula three-phase inverter apparatus in Embodiment 2 which concerns on this invention in parallel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... DC power supply 2 ... Inverter 3 ... Inverter current detector 4 ... Output filter circuit 5 ... Filter voltage detector 6 ... Output current detector 7 ... Output terminal 8. ..Current target value forming section 8A... Voltage command means 8B... Current gain means 8C... Subtraction means 8D... Voltage gain means 8E ... Addition means 8a. .. Capacitor current command means 8c... PWM current error compensation means 8d... Coordinate conversion means 8e... Low pass filter 8f... Subtraction means 8g ... Voltage limiter 8h ... Voltage feedback means 8i Addition means 8j Coordinate conversion means 8k Current gain means 8l Current gain means 8m Signal limiter 8n Addition means 8p Coordinate conversion means 9 Gate command P WM control unit 9A: Subtraction means 9B: Gate command / PWM circuit 10 ... Synchronization signal generation circuit 50 ... Load circuit

Claims (4)

When the output voltage feedback gain is α, the output current feedforward gain is β, and the inverter current gain is G, the DC resistance value represented by (1−β · G) / (α · G) is the equivalent internal impedance. An operation method of a power supply device configured by connecting a plurality of inverter devices in parallel,
A signal obtained by giving a command voltage synchronized with each other to each of the inverter devices, and multiplying a voltage of a difference between the command voltage and a voltage detection signal of the output voltage of the inverter device by the output voltage feedback gain α which is a positive value. And a signal obtained by multiplying the current detection signal of the output current of the inverter device by the output current feedforward gain β which is a numerical value of 1 or less to form a current target value of the inverter device,
The DC resistance value determined by the rated value of the output voltage and output current of the inverter device is 100% equivalent internal impedance, and the control parameter of the inverter device is based on the allowable current value of the cross current flowing between the inverter devices. A method for operating a power supply apparatus, wherein the value of the equivalent internal impedance is changed by adjusting both or any one of the output voltage feedback gain α and the output current feedforward gain β . 2. The power supply device according to claim 1, wherein the equivalent internal impedance is changed in a range of 2 to 10% with respect to the equivalent internal impedance determined by a rated value of an output voltage and an output current of the inverter device. Driving method . When the output voltage feedback gain is α, the output current feedforward gain is β, and the inverter current gain is G, the DC resistance value represented by (1−β · G) / (α · G) is the equivalent internal impedance. A power supply device configured by connecting a plurality of inverter devices in parallel,
Voltage command means for giving command voltages synchronized with each other; voltage gain means for multiplying a voltage of a difference between the command voltage and a voltage detection signal of the output voltage of the inverter device by the output voltage feedback gain α which is a positive numerical value; Current gain means for multiplying the current detection signal of the output current of the inverter device by the output current feedforward gain β which is a numerical value of 1 or less, and the output signal of the voltage gain means and the output signal of the current gain means are added. A current target forming unit having an adding means,
The DC resistance value determined by the rated value of the output voltage and output current of the inverter device is 100% equivalent internal impedance, and the control parameter of the inverter device is based on the allowable current value of the cross current flowing between the inverter devices. A power supply apparatus that adjusts both or any one of the output voltage feedback gain α and the output current feedforward gain β to change the value of the equivalent internal impedance . 4. The power supply device according to claim 3, wherein the equivalent internal impedance is changed in a range of 2 to 10% with respect to the equivalent internal impedance determined by rated values of an output voltage and an output current of the inverter device. 5. .

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