JP3413189B2 - Control device for pulse width modulation type inverter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation type inverter control device for controlling a motor for driving a vehicle at a variable speed. [0002] A so-called inverter train, which drives an induction motor by controlling a variable voltage / variable frequency (VVVF) inverter by a pulse width modulation method (PWM), has been put into practical use. In the case of locomotives, the inverter drive system is becoming mainstream. In current inverter systems for driving vehicles, a two-level voltage is
A so-called two-level inverter controlled using a TO thyristor occupies most. However, in the two-level GTO inverter, electromagnetic noise generated by the electric motor is large due to the restriction of the switching frequency and the like. Therefore, reduction of the noise and downsizing of the device including the main circuit element have been important issues. On the other hand, in the three-level inverter, since the number of steps of the output voltage is larger than that of the two-level inverter, the apparent switching frequency is increased, and a reduction in electromagnetic noise can be expected. Further, the voltage applied to the main circuit element is Since it is about half that of a two-level inverter, a low withstand voltage element can be used.
It has features that can solve the problems in the level inverter. Therefore, a three-level inverter system for a vehicle using a high-voltage IGBT as a main circuit element has been developed. This is an IGBT capable of high frequency switching
It is expected that the adoption of the element can greatly reduce electromagnetic noise in combination with the three levels. The PWM control of the three-level inverter includes a bipolar modulation in which positive and negative pulse trains are alternately output via an intermediate voltage during one cycle of the output voltage of the inverter, and a pulse train of the same polarity every half cycle of the output voltage of the inverter. Unipolar modulation to be output, partial dipolar modulation in which dipolar modulation and unipolar modulation are mixed in one cycle of the output voltage of the inverter, and a single pulse having the same polarity as the output voltage fundamental wave is output during a half cycle of the output voltage of the inverter 1 Pulse modulation schemes are well known. FIG. 6 shows a relationship between the inverter frequency and the output voltage, and also shows a region to which each system of dipolar modulation, partial dipolar modulation, and unipolar modulation is applied. In addition, 1
The pulse modulation method is applied in a region (not shown) higher than the inverter frequency to which the unipolar modulation region is applied. Unipolar modulation is generally used as a modulation method. However, unipolar modulation alone cannot control a minute voltage including zero voltage due to the restriction on the minimum on-time of the main circuit element as shown by a dotted line X in FIG. Therefore, as the control of the minute voltage, until the inverter frequencies F ₁ as shown in Figure 6, introduces a dipolar modulation for outputting a pulse alternately positive and negative through the zero voltage, further dipolar modulation and at the transition between the unipolar modulation ( the words between inverter frequencies F ₁ and the inverter frequency F _2), so that a smooth transition by suppressing variation of the inverter output current, by introducing a partial dipolar modulation where the dipolar modulation and the unipolar modulation are mixed in one cycle , The output voltage is continuously controlled from zero voltage. [0003] However, in dipolar modulation, the switching frequency for the main circuit element is about twice that of unipolar modulation, so that loss around the element is large. In particular, when the IGBT is adopted, the switching frequency can be set to be higher by one digit or more than that of the conventional two-level inverter, and thus may not be ignored. For this reason, in the operation mode in which the operation time is long in the vicinity of the dipolar modulation region or the partial dipolar modulation region, there is a possibility that the element may be broken due to heat loss. Of course, in the operation mode in which the operation time is long in the unipolar modulation region, there is a possibility that the element may be destroyed due to the heat loss. Generally, in the case of the operation mode in which the operation time is long in the pulse width modulation except the one pulse modulation,
The device may be destroyed due to heat loss. [0004] It is an object of the present invention to provide a pulse width modulation type inverter for performing variable speed control of a motor for driving a vehicle, wherein the operation time of the inverter has exceeded a predetermined time in pulse width modulation control except one pulse modulation control. An object of the present invention is to provide a control device for a pulse width modulation type inverter that suppresses element loss by lowering a switching frequency for a predetermined time. In order to solve the above-mentioned problems, in order to solve the above problem, a pulse width modulation control is performed in a low speed range, and a variable frequency variable voltage AC is output from a DC power supply voltage in a high speed range by one pulse control. In an inverter control device that performs variable speed control of an electric motor for driving a vehicle, means for measuring an operation time of the inverter by pulse width modulation control excluding one pulse modulation control, and when the operation time exceeds a predetermined time,
Means are provided for changing a sampling period related to setting of the inverter switching frequency by pulse width modulation control so as to lower the inverter switching frequency by a predetermined time. According to the present invention, in an operation mode in which dipolar modulation, partial dipolar modulation, and unipolar modulation other than one-pulse modulation last for a long time, an operation mode in which pulse width modulation other than one-pulse modulation lasts for a long time. In this case, by forcibly reducing the switching frequency, heat loss of the main circuit element due to switching can be suppressed. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a main circuit configuration (in the case of three phases U, V, W) of a three-level inverter device for driving a vehicle to which a control device for a pulse width modulation type inverter of the present invention is applied. In FIG. 1, 60 is a train line which is a DC voltage source,
61 and 62 are capacitors that are divided (divided) to generate an intermediate point N (hereinafter, referred to as a neutral point) from the voltage of the DC voltage source 60, and 70 to 73, 80 to 83, and 90 to 93 are for reflux. The self-extinguishing switching element (the IGBT is used in this example, but may be a GTO, a transistor, or the like) provided with the rectifier element described above, and 74, 75, 84, 85, 94, and 95 are the neutral point potentials of the capacitors. It is an auxiliary rectifying element to be derived. Also, the load shows the case of the induction motor 10.
The basic operation of the switching arms 7 to 9 that can be operated independently for each phase will be described by taking the switching arm 7 as an example. Capacitors 61 and 6
2, the voltages ed1 and ed2 are completely smooth DC voltage sources, and ed1 = ed2 = Ed / 2 (Ed: total DC voltage). Now, when the switching elements 70 to 73 are turned on and off as shown in FIG. 2 (Table 1), the three-level output voltage e of Ed / 2, 0, and -Ed / 2 is applied to the AC output terminal U. obtain. Sp to Sn and S are switching elements 70
This is a switching function that expresses the conduction state of ７３73 as 1, 0, −1, and the output voltage e is represented by e = Sp × ed1-Sn × ed2 = S × Ed / 2 (1). e has a size of Ed / 2, 0, -Ed / 2
, The pulse width modulation (PW) so that e approaches a sine wave.
M) Control. The PMW control device can determine the conduction state of the switching element by preparing Sp and Sn. Next, FIG. 3 shows an embodiment in which the present invention is applied to control of a three-level inverter device for driving a vehicle. In FIG. 3, the counter unit 1 performs an up or down counting operation in response to a counter operation signal 201. In this embodiment, the counter unit 1 counts up when the counter operation signal 201 is "1" and counts down when the counter operation signal 201 is "0". In the case of up-counting, the up-count setting unit 11 counts a preset count amount 112, and in the case of down-counting, the down-count setting unit 12 counts a preset count amount 113. Count limit part 2
Limits the count output 101 of the counter unit 1,
The lowest value is zero, and the highest value is selected in consideration of the operating environment of the inverter. The comparator 21 compares the output 102 of the count limit unit 2 with a detection level signal 114 preset by the detection level setting unit 13 and outputs a detection signal 103. Output 102 of count limit unit 2
Is "1" if is equal to or higher than the detection level signal 114, and "0" otherwise. The time delay unit 3 receives the detection signal 103 and outputs a switching frequency drop detection signal 104. When the detection signal 103 becomes “1”,
The switching frequency drop detection signal 104 is also set to “1”, but even if the detection signal 103 returns to “0”, the counter unit 1
Counts down and the output 1 of the count limit unit 2
By providing a time delay equal to or longer than the time until 02 becomes zero, the switching frequency drop detection signal 104 is set to “0”.
To return to. The timer count unit 4 receives the switching frequency drop detection signal 104, outputs a sampling conversion signal 105 for converting a sampling period 110 related to setting of the switching frequency to a predetermined value, and continuously controls the sampling period. Set the timer to run. The counter operation signal 201 will be described. Since it is not necessary to reduce the switching frequency in the one-pulse modulation, the comparator 20 compares the output voltage command E * with the limit output 115 of the command value limit unit 14 in which the one-pulse voltage command value is set in advance. The output 202 outputs “1” for modulation, and “0” for other dipolar, partial dipolar, and unipolar modulation. The output 202 is inverted by the inverter 32, and the output 203 is output in one-pulse modulation.
Becomes "0", and the counter operation signal 201 output from the AND gate 30 becomes "0". Further, the operation signal GST of the inverter is input to the AND gate 30. In the present embodiment, GST = "1" when the inverter operates and "0" when the inverter stops. Further, an output 204 obtained by inverting the switching frequency drop detection signal 104 by the inverter 31 is also input to the AND gate 30. Therefore, while the switching frequency drop detection signal 104 is being output, the counter operation signal 201 is “0”, and the counter unit 1 performs a down-count operation. The phase calculator 5 calculates the fundamental phase of the output voltage of the inverter from the inverter frequency command Fi *. Although not shown, the inverter frequency command Fi * is obtained by calculating the rotation frequency of the electric motor from the output of the rotation frequency detector attached to the wheel, and adding the calculated rotation frequency to the slip frequency command. The output 106 of the phase calculator 5 is converted into a sine wave signal 107 by the sine wave calculator 6. The amplitude setting unit 7 obtains a required instantaneous output voltage of the inverter from the output voltage command E * of the inverter. The output voltage command E * is
A command value of the inverter output voltage determined from the inverter frequency command Fi * and a filter capacitor voltage and a motor current (not shown) so that the V / F characteristic is constant. Output 108 of amplitude setting unit 7 and sine wave signal 1
07 in the multiplier 22 to obtain an instantaneous output voltage signal 301. The bias setting unit 8 outputs the output 108 of the amplitude setting unit 7.
, An addition / subtraction is performed on the instantaneous output voltage signal 301, and a bias amount 109 for continuously realizing dipolar modulation, partial dipolar modulation, and unipolar modulation is set.
The instantaneous output voltage signal 301 and the bias amount 109 are added by the adder 33, and the positive-side instantaneous output voltage signal 302 and the subtractor 3
4 to obtain negative side instantaneous output voltage signals 303, respectively. The sampling setting unit 9 performs a sampling period 110 from the clock Tc to a timer included in the pulse generation unit 10.
Set. Although it depends on the type of the timer, as a normal pulse generation timer, the rising or falling of the pulse is set for each sampling cycle, so that the switching frequency F
sw can be represented by Fsw = 1 / (2 × Ts) (2) where Ts is the sampling period. Sampling converter 23
Sets a preset sampling period 110 to a new sampling period 111 according to the value of the sampling conversion signal 105. The pulse generator 10 receives the positive-side instantaneous output voltage signal 302 and the negative-side instantaneous output voltage signal 303 and converts them into required instantaneous output voltage time conversion data for each sampling period 111. A positive PWM signal 500 and a negative PWM signal 501 are obtained by setting the timer to be activated every period 111. Note that FIG. 3 illustrates a PWM signal for one phase, and furthermore, PWM signals 500 and 501.
Is processed into a signal corresponding to a three-level inverter by a pulse distributor (not shown). The operation of this embodiment will be described. Now, when the output voltage command E * and the inverter frequency command Fi * are given, the output 108 of the amplitude setting unit 7 and the sine wave signal 107 of the sine wave calculation unit 6 are multiplied by the multiplier 22 to obtain the instantaneous output voltage signal 301. Is output. On the other hand, the output 108 of the amplitude setting unit 7
In contrast, the bias setting unit 8 sets a bias amount 109 for continuously realizing dipolar modulation, partial dipolar modulation, and unipolar modulation. Here, the bias amount 1
FIG. 5 (a) shows the relationship between 09 and each modulation. When the output voltage command E * is low, i.e. the modulation factor A is between 0 to A ₀ sets the bias amount B to B _0, realizing dipolar modulation. When the output voltage command E * has an intermediate value, that is, when the modulation factor A is between A _{0 and} A ₁ , the bias amount B is set so as to gradually decrease from B ₀ to realize partial dipolar modulation. Further, when the output voltage command E * is a high value, i.e. the modulation factor A is when greater than A ₁ sets the bias amount B to zero, implementing the unipolar modulation. The output voltage command E
When * is the maximum value, one-pulse modulation is realized. continue,
The instantaneous output voltage signal 301 and the bias amount 109 are added by the adder 33, and the positive-side instantaneous output voltage signal 302 and the subtractor 3
4 to obtain a negative instantaneous output voltage signal 303, which is input to the pulse generator 10. Also, the clock Tc is input to the sampling setting unit 9, a preset sampling period 110 is output from the sampling setting unit 9, and a new sampling period 111 (described later) is set via the sampling conversion unit 23 to generate a pulse. Input to the unit 10. The pulse generator 10 converts the positive-side instantaneous output voltage signal 302 and the negative-side instantaneous output voltage signal 303 into required instantaneous output voltage time conversion data for each sampling period 111, and converts this data for each sampling period 111. Set the timer to be started and set the positive PWM
A signal 500 and a negative PWM signal 501 are output. PWM
The signals 500 and 501 are processed by a pulse distributor (not shown) into signals corresponding to a three-level inverter.
PWM control of the three-level inverter device. Next, the relationship between the operating state of the inverter and the switching frequency Fsw created by the new sampling period 111 will be described with reference to FIG. Let A be the timing at which the inverter is started (started) from the state where the vehicle is stopped. Since the output 202 (1 pulse detection) of the comparator 20 and the switching frequency drop detection signal 104 are “0” and the inverter operation signal GST is “1”, the counter operation signal 2 output from the AND gate 30 is output.
01 becomes "1", the counter unit 1 performs an up-count operation, and the output 102 increases by a fixed amount. The new sampling period 111 at this time has the same value as the sampling period 110 of the sampling setting unit 9, and the switching frequency is the initial value Fsw1. When the inverter is stopped (stopped) at B, the output of the AND gate 30 becomes "0", the counter section 1 performs a down-count operation, and the output 102 decreases by a fixed amount. When the inverter is started again at C, the counter unit 1 starts an up-count operation, and the output 102 increases again by a constant amount. At D, control shifts to one-pulse modulation. In the one-pulse modulation, the switching frequency has the same value as the inverter frequency, so there is no influence of the switching loss. Therefore, in the one-pulse modulation region, the counter unit 1 is operated to count down. E shifts from one-pulse modulation to another modulation area. Since the inverter is still operating, the output 102 increases by a certain amount and reaches the detection level at F. At a level higher than the detection level, the switching frequency drop detection signal 104 is output as “1”. When 104 becomes "1", the counter operation signal 201 which is the output of the AND gate 30 becomes "0", and the counter unit 1 immediately starts the down-count operation. At the same time, when the value of 104 becomes “1”, the timer count unit 4 counts up the timer and increases the sampling conversion signal 105 to a predetermined limit value. The sampling conversion unit 23 converts the sampling period 110 to a new sampling period 111 according to the value of the sampling conversion signal 105, and changes the switching frequency from Fsw1 to Fsw1.
It is continuously reduced to sw2. In the switching frequency drop detection signal 104, the time delay unit 3 sets a sufficient time delay Td until the counter unit 1 is cleared to "0". Even if the inverter is stopped at G and operated again at H, the switching frequency is Fsw because the switching frequency drop detection signal 104 remains "1".
It is fixed to 2. At I, the switching frequency detection signal 104 returns to "0" after the elapse of Td. At this time, since the inverter is operating, the counter unit 1 performs the up-counting operation again. Further, when the switching frequency detection signal 104 becomes “0”, the timer count unit 4 counts down the timer and decreases the sampling conversion signal 105 until it becomes zero. As a result, the new sampling period 111 returns to the sampling period 110, and the switching frequency continuously returns from Fsw2 to Fsw1. At J, the output 102 of the count limit unit 2 reaches the detection level again. The operation in this case is the same as in the case of FI. The switching frequency is fixed to Fsw2 even when the operation shifts to one-pulse modulation with K and the inverter is stopped in one-pulse modulation with M. At N, the switching frequency returns to Fsw1. N is the same as the state of A. As described above, in the present embodiment, the switching frequency is forcibly reduced in an operation mode in which dipolar modulation, partial dipolar modulation, and unipolar modulation other than one-pulse modulation last for a long time. Also, when the switching frequency changes, the switching frequency is changed from Fsw1 to Fsw2.
, And continuously returns from Fsw2 to Fsw1, so that the output current does not fluctuate and smooth control is performed. Next, the switching loss L will be described with reference to FIG. FIG. 5A shows the bias amount B as described above.
FIG. 5B shows the sampling period Ts, and FIG. 5C shows the switching loss L. When the sampling periods at the time of the dipolar modulation and the unipolar modulation are respectively Tso as shown in FIG.
In the dipolar modulation, the switching frequency with respect to the main circuit element is about twice that of the unipolar modulation. Therefore, the switching loss L substantially exhibits the characteristic L1 shown in the diagram P as shown in FIG. Therefore, in an operation mode in which the inverter operates in the dipolar modulation region for a long time, the heat loss of the element increases. On the other hand, if the sampling period is raised to Ts1 by dipolar modulation as shown in FIG. 5B and the switching frequency is made substantially the same as that of the unipolar modulation, the switching loss L becomes almost a diagram as shown in FIG. 5C. The characteristic L0 shown in Q is exhibited. Therefore, the heat loss of the hatched element shown in FIG. 5C is reduced. In the case of the partial dipolar modulation and the unipolar modulation, if the operation mode is such that the inverter is operated for a long time in each region, the heat loss of the element similarly increases. Therefore, similarly, the sampling frequency is increased to lower the switching frequency, and the heat loss of the element is reduced. Therefore, according to the present embodiment, in the operation mode in which the inverter is operated for a long time, by forcibly reducing the switching frequency, the heat loss of the element due to switching can be suppressed. As described above, according to the present invention,
In an operation mode in which dipolar modulation, partial dipolar modulation, and unipolar modulation other than one-pulse modulation last for a long time, forcibly lower the switching frequency to suppress heat loss of the main circuit elements due to switching. Can be. In particular, it is effective in a low constant speed operation in which the dipolar modulation is maintained for a long time. Also,
Even when the switching frequency changes, the switching frequency is continuously reduced and returned to the original value, so that the output current does not change and smooth inverter control can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a main circuit configuration diagram of a three-level inverter device for driving a vehicle to which the present invention is applied; FIG. 2 is a table illustrating output voltages of the three-level inverter; FIG. 4 is a diagram showing the relationship between the operation of the inverter and the switching frequency. FIG. 5 is a diagram showing the switching loss in dipolar modulation. FIG. 6 is a diagram showing the control of the minute voltage of the three-level inverter. [Description of Reference Codes] 1 ... Counter section, 3 ... Time delay section, 4 ... Timer count section, 9 ... Sampling setting section, 10 ... Pulse generation section, 11 ... Up count setting section, 12 ... Down count setting section , 13: detection level setting unit, 23: sampling conversion unit, 104: switching frequency drop detection signal,
105: sampling conversion signal, 110: sampling cycle, 111: new sampling cycle, 201: counter operation signal

Continuation of front page (56) References JP-A-5-344739 (JP, A) JP-A-6-30564 (JP, A) JP-A-5-146160 (JP, A) JP-A-5-308704 (JP) , A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 7/48

Claims (1)

(57) [Claim 1] In a low-speed range, pulse width modulation control is performed, and in a high-speed range, one-pulse control is performed to output an AC of a variable frequency voltage from a DC power supply voltage to generate a motor for driving a vehicle. A control device for an inverter that performs variable-speed control, comprising: means for measuring an operation time of the inverter by the pulse width modulation control excluding the one-pulse modulation control; and an inverter for a predetermined time when the operation time becomes equal to or longer than a predetermined time. A means for changing a sampling period related to setting of a switching frequency of the inverter by the pulse width modulation control so as to lower a switching frequency of the inverter.