JPH0515167A - Control method for neutral clamping power converter - Google Patents

Abstract

PURPOSE:To guarantee minimum ON/OFF times of a converter element and to eliminate uncontrollable region for a low input signal by extending a new first gate signal by a predetermined interval and bringing a new second gate signal to 1 for the predetermined interval half period after a carrier signal. CONSTITUTION:Signals g1, g2 are created, wherein g1=1 when an input signal ei>X and g1=0 when ei<=X, whereas g2=1 when ei<Y and g2=0 when ei<=Y. When DELTAt1 at g1=1 becomes shorter than DELTAt, a gate signal g11 having extended DELTAt1+DELTAt at g1=1 is obtained. A signal g22 which becomes 1 for a time DELTAt half period after a carrier signal is obtained and when the interval DELTAt2 of the signal g2=1 becomes shorter than the time DELTAt of element, the signal g22 is obtained at the interval DELTAt2+DELTAt of g2=1. Furthermore, the signal g22 is obtained at the interval DELTAt2+DELTAt of g2=1 and the signal g11 where the signal g1 is brought to 1 for the interval DELTAt half period after the carrier signal is also obtained. Consequently, S1 is turned ON when g11=1, S1 is turned OFF when g11=0, S4 is turned ON when g22=1 and S4 is turned OFF when g22=0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a pulse width modulation control (PWM control) converter for converting AC power into DC power, a PWM control inverter for converting DC power into AC power, and the like. The present invention relates to a control method for a neutral point clamp type power converter that generates a level output voltage.

[0002]

2. Description of the Related Art FIG. 6 shows a main circuit configuration of a neutral point clamp type inverter. The figure shows one phase (U phase) and 3
In the case of a phase output inverter, the V and W phases are similarly configured.

FIG. 6 (a) is a main circuit diagram showing V _d1 , V _d2.
Is a DC voltage source, S _{1 to} S ₄ are self-extinguishing elements, and D _{1 to} D ₄
Is a freewheeling diode, D ₅ and D ₆ are clamping diodes, and LOAD is a load. In addition, FIG.
(B) is a block diagram of a control circuit, and C _U , C ₁ , C
Reference numeral ₂ is a comparator, _Gu (S) is a current control circuit, TRG is a triangular wave generator, and SH ₁ and SH ₂ are Schmitt circuits.

The output voltage V _U of this inverter changes as follows by turning on and off the _four elements S _{1 to} S ₄ . However, the total DC voltage is V _d ,
Let V _d1 = V _d2 = V _d / 2. That is, when S ₁ and S ₂ are on, V _U = + V _d / 2 When S ₂ and S ₃ are on, V _U = 0 When S ₃ and S ₄ are on, V _U = −V _d / It becomes 2. At this time, two devices must be turned on each. If all three are turned on at the same time, the DC power supply is short-circuited and the device is destroyed due to overcurrent.

For example, when an ON signal is input to S _{1 to} S ₃ , the DC voltage V _d1 is short-circuited by the element S ₁ → S ₂ → S ₃ → diode D ₆ , and an excessive short-circuit current flows through the element, Will destroy.

In order to prevent such a DC short circuit, the elements S ₁ and S ₃ are operated in reverse and the elements S ₂ and S ₄ are operated in reverse. That is, when S ₁ is ON turns off the S _3, when S ₃ is turned on and turns off the S _1. Similarly, when S ₂ is on turns off the S _4, when S ₄ is on and turns off the S _2.

FIG. 7 is a time chart for explaining a conventional pulse width modulation control method for a neutral point clamp type inverter.

In the figure, X and Y are carrier wave signals for PWM control, X is a triangular wave varying between 0 and + E _max , and Y is 0 to 0.
It is a triangular wave that changes between −E _max . Also, e _i is P
WM control input signal.

The input signal e _i is compared with the triangular waves X and Y,
The gate signals g ₁ and g ₂ of the elements S _{1 to} S ₄ are produced. That is, when e _i > X, g ₁ = 1 and S _{1 is} turned on and S ₃ is turned off.

When e _i ≤X, when g ₁ = 0, S _{1 is} turned off and S ₃ is turned on.

When e _i <Y, g ₄ = 1 and S _{4 is} turned on and S ₂ is turned off.

When e _i ≧ Y, when g ₂ = 0, S _{4 is} turned off and S ₂ is turned on.

As a result, the output voltage V _U becomes as shown at the bottom of the figure. As described above, in the neutral point clamp type inverter, the output voltage V _U is three levels (+ V _d / 2,
0, the voltage of -V _d / 2) is obtained, and less voltage waveform of the harmonic component. In the case of a motor load, there are advantages that current pulsation is reduced and torque ripple is also reduced.

[0014]

However, the conventional control method of the neutral point clamp type inverter has the following problems.

Similar to FIG. 7, FIG. 8 shows a time chart for explaining the conventional PWM control method, and shows the operation when the input signal e _i is very small.

When the input signal e _i is small, the pulse width of the gate signals g ₁ and g ₂ becomes narrow. This width is the minimum on-time Δt of the self-extinguishing elements S _{1 to} S ₄ forming the inverter.
The problem occurs when it becomes narrower than.

That is, in a large capacity inverter, a GTO (gate turn-off thyristor) is used as a self-extinguishing element.
A snubber circuit is installed to suppress overvoltage at turn-off. In order to initialize (discharge) the voltage of the capacitor of this snubber circuit, when the GTO is turned on, the on state must be maintained for a certain time (minimum on time Δt: for example, about 100 microseconds).

In the case of FIG. 8, the input signal e _i becomes small,
The period in which the gate signal g ₁ = 1, that is, the period in which the element S ₁ is on (S ₃ is off) is shorter than the minimum on-time Δt. Therefore, in order to secure the minimum on-time of the element, the gate signal g ₁ is corrected as g ₁ ′. Similarly, the gate signal g ₂ is also corrected like g ₂ ′, and the output voltage V _U has the lowest waveform. Average value of output voltage AV
_As indicated by the broken line, _U becomes a positive or negative constant value regardless of the value of the input signal e _i .

That is, in the conventional PWM control method for the neutral point clamp type inverter, when the level of the input signal e _i becomes low, the output voltage V _U becomes a constant value regardless of the value of the input signal e _i. Therefore, the load current I _U cannot be controlled. In particular, when the output frequency is low, this voltage error is integrated and the load current I _U is increased, and in the worst case, the element is destroyed.

The present invention has been made in view of the above problems, and secures the minimum on-time of the element, and the input signal e _i
It is an object of the present invention to provide a control method for a neutral point clamp type power converter that generates an output voltage proportional to the input signal even when the power consumption is small and eliminates an uncontrollable region.

[0021]

In order to achieve the above object, the present invention is directed to _four self-extinguishing elements S _{1 to} S ₄ which are connected in series and are controlled in pulse width modulation, and antiparallel elements to each of them. Free wheeling diodes D _{1 to} D ₄ connected to
And clamping diodes D ₅ and D ₆
In a neutral point clamp type power converter that generates a level output voltage, a triangular wave X that changes between zero and positive side and a triangular wave Y that changes between zero and negative side are prepared as carrier signals for pulse width modulation control. When the triangular waves X and Y are compared with the PWM control input signal e _i , when e _i > X, g ₁ = 1 e _i ≦ X, when g ₁ = 0 e _i <Y, g ₂ = 1 e _{When i} ≧ Y, first and second signals g ₁ and g _{2 for} which g ₂ = 0 are generated, and the period Δt _{1 of the} first signal g ₁ = ₁ is the minimum on-time Δ of the element.
When it becomes shorter than t, the period Δt ₁ + Δt ^{* of} g ₁ = 1
To obtain a new gate signal g ₁₁ which has been expanded to a second signal g for a period Δt ^* after about half a cycle of the carrier signal.
Obtain a new gate signal g ₂₂ with _{2 set} to “1”, and
When the period Δt _{2 of} the second signal g ₂ = 1 becomes shorter than the minimum on-time Δt of the element, the period Δt ₂ + of g ₂ = 1.
A new gate signal g ₂₂ expanded to Δt ^* is obtained, and a new gate signal g _{11 in} which the first signal g _{1 is set} to “1” for a period Δt ^{* is obtained} after about half a cycle of the carrier signal. , The first and second new gate signals g ₁₁ and g ₂₂
When g ₁₁ = 1, S ₁ : ON (S ₃ : OFF) g ₁₁ = 0, S ₁ : OFF (S ₃ : ON) g ₂₂ = 1, S ₄ : ON ( S ₂ : OFF) When g ₂₂ = 0, the pulse width modulation control is performed as S ₄ : OFF (S ₂ : ON).

[0022]

According to the control method of the present invention, the minimum on-time of the element forming the neutral point clamp type power converter is secured, and the output voltage proportional to the input signal e _i is generated even when the input signal e _i is small. , The uncontrollable area can be eliminated.

[0023]

1 and 2 show an embodiment of a main circuit configuration diagram and a control block diagram for explaining a control method of a neutral point clamp type inverter of the present invention. The main circuit is shown in Figure 1.
As shown in a conventional example having the same configuration in FIG. 6, V _d1,
V _d2 is a DC voltage source, S _{1 to} S ₄ are self-extinguishing elements, and D ₁ to
D ₄ is freewheeling diode, D _5, D ₆ is clamping diode, LOAD is the load, CT _U is a current detector.

In FIG. 2, C _U , C ₁ and C ₂ are comparators, G _U (S) is a current control compensation circuit, and SH ₁ and SH ₂
Is a Schmitt circuit, MM _{11 to} MM ₁₄ and MM _{21 to} MM ₂₄ are mono-multi circuits, and OR ₁₁ , OR ₁₂ , OR ₂₁ and OR ₂₂ are OR circuits.

Although FIGS. 1 and 2 show only one phase (U phase), in the case of a three phase load, the other two phases (V and W phases) are similarly constructed.

[0026] The load current I _U of the U-phase detected by the current detector CT _U, is input to a comparator C _U of the current control circuit. The comparator C _U compares the current command value I _U ^* and the current detection value I _U, a deviation ^{_{ε U = I U * -I U}} . The deviation ε _U is amplified by the next control compensation circuit G _U (S) and used as the input signal e _{i for} PWM control.

The carrier wave generator TRG has two triangular waves X and Y.
Is generated and input to the comparators C ₁ and C ₂ .

The comparator C ₁ receives the triangular wave X and the input signal e _i.
And the gate signal g ₁ of the elements S ₁ and S ₃ is generated via the Schmitt circuit SH ₁ . Further, the comparator C ₂ compares the triangular wave Y with the input signal e _i, and outputs the Schmitt circuit SH.
Making the gate signal g ₂ of the element S ₂ and S ₄ via the _2.

FIG. 3 shows an example of a time chart for explaining the operation of the control method of the present invention.

The carrier wave X for PWM control is a triangular wave having a constant frequency which varies between 0 and + E _max . Also, carrier wave Y
Is a triangular wave of constant frequency that varies between 0 and -E _max ,
It is in phase with carrier wave X. That is, X = + E _max
When, Y = 0, and when X = 0, Y = −E _max .

The triangular wave X and the PWM control input signal e _i are compared to generate a first gate signal g ₁ for turning on and off the elements S ₁ and S ₃ .

When e _i > X, g ₁ = 1 When e _i ≦ X, g ₁ = 0 Further, the triangular wave Y and the PWM control input signal e _i are compared, and the elements S ₂ and S ₄ are turned on and off. Second gate signal g ₂
make.

When e _i <Y, g ₂ = 1 When e _i ≧ Y, g ₂ = 0 FIG. 3 is a time chart when the input signal e _i is a positive and small value. _{Since i} ≧ Y, g ₂ = 0.

If the period Δt ₁ during which the first gate signal g ₁ is “1” is narrow and is shorter than the minimum on-time Δt of the element, a new gate signal for actually turning on and off the elements S ₁ and S ₃ The period in which g ₁₁ becomes “1” is extended to Δt ₁ + Δt ^* (Δt ^* Δt). At this time, the new second gate signal g ₂₂ is set to “1” for the time Δt ^* after about 1/2 cycle of the cycle of the carrier signals X and Y.

[0035] As a result, the output voltage V _U of the converter, generates a pulse width Δt ₁ + Δt ^* positive voltage (+ V _d / 2), after which about half the period, pulse width Delta] t ^* of a negative voltage (- V _d
/ 2) is generated. Therefore, the positive and negative voltages of the width Δt ^* are canceled and only the voltage based on the initial pulse width Δt ₁ remains as the total output voltage V _U. That is, the output voltage V _U of the neutral point clamp type power converter of the present invention is the input signal e.
_The value becomes proportional to _i , and the uncontrollable region, which has been a problem in the past, disappears. As a matter of course, the ON period of the element becomes longer than the minimum ON time Δt, and it can take a sufficient time to initialize (discharge) the snubber circuit capacitor.

Since the pulse width at point b is Δt ₁ > Δt, g ₁₁ = g ₁ and Δt ^* is not added.
Further, g ₂₂ also remains “0”. That is, the pulse having the width Δt ^* is added to the positive side and the negative side only when the input signal e _i is small.

FIG. 4 is a time chart for explaining the control operation of the present invention in more detail, and is an enlarged view of points a to b in FIG. This will be described with reference to FIG.

In FIG. 4, g ₁ is a Schmitt circuit SH
_{1 is} an output signal of the first gate signal, m ₁₁ is an output signal of mono-multi MM ₁₁ , m ₁₂ is an output signal of mono-multi MM ₁₂ , g ₁ + m ₁₂ is an output signal of OR circuit OR ₁₁ , m ₁₃ Is the output signal of the monomulti MM ₁₃ , m ₁₄ is the monomulti MM ₁₄
, V _U is the output voltage of the converter.

The monomulti MM ₁₁ operates at the rising edge of the signal g ₁ and determines whether the period Δt ₁ of g ₁ = 1 is longer than the minimum on-time Δt of the element.

That is, the set time of the output m ₁₁ of the MM ₁₁ is Δt, and when the signal g ₁ falls during that time, the mono-multi MM ₁₂ is operated.

When Δt ₁ <Δt, the monomulti MM ₁₂ is operated at the fall of g ₁ and the signal of “1” is output during the period of Δt ^* . At this time, choose Δt ^* Δt.

The signal g ₁ and MM are supplied by the OR circuit OR _11.
ORs the output signal m ₁₂ of _12, a period of g ₁ = 1 delta
Expand to t ₁ + Δt ^* . The output of the OR circuit OR ₁₁ becomes a new gate signal g ₁₁ for turning on and off the elements S ₁ and S ₃ via the next OR circuit OR ₁₂ .

The mono-multi MM ₁₃ operates at the fall of the output signal m ₁₂ of the mono-multi MM ₁₂ , and the mono-multi MM ₁₄ operates at the fall of the output signal m ₁₃ of the mono-multi MM ₁₃ . Further, the output signal m ₁₄ of the monomulti MM ₁₄ is input to the logical sum circuit OR ₂₂ related to the second gate signal.
The output of the OR circuit OR ₂₂ is the new second gate signal g
₂₂ .

The set time T ₁₃ of the signal m ₁₃ is the carrier X, Y
It is set to about half the period of. When the frequencies of the carrier waves X and Y are f _C , the period T is (1 / f _C , and the set time T ₁₃ is given by, for example, T ₁₃ = (T / 2) −Δt ^* .

After that, the new second gate signal g _{22 is set} to “1” only for the period of m ₁₄ = 1 (set to Δt ^* ).

The output signals of the OR circuits OR ₁₂ and OR ₂₂ thus obtained are used as new gate signals g ₁₁ and g _22, and the elements S _{1 to} S ₄ are turned on and off as follows.

When g ₁₁ = 1, S ₁ : ON (S ₃ : OFF) When g ₁₁ = 0, S ₁ : OFF (S ₃ : ON) When g ₂₂ = 1, S ₄ : ON (S ₂ : OFF) When g ₂₂ = 0, S ₄ : OFF (S ₂ : ON) The output voltage V _U of the neutral point clamp type power converter is S ₁ and S ₂ when the DC voltage is V _d. Is on, V _U = + V _d / 2 S ₂ and S ₃ are on, and V _U = 0 When S ₃ and S ₄ are on, V _U = −V _d / 2. The output voltage V _U is shown at the bottom of FIG.

That is, the new first gate signal g ₁₁ =
The period of 1 is extended by Δt ^* , and the output voltage of the converter increases to the positive side by that amount, but a new second gate signal g
₂₂ also becomes “1” for a period Δt ^* after a half cycle of the carrier signal, increasing the output voltage of the converter to the negative side. As a result, the output voltage based on the period Δt ^* is canceled, and the voltage proportional to the initial pulse width Δt ₁ remains.

As described above, even when the input signal e _i of the PWM control becomes small, the minimum on-time of the element can be always secured, and the output voltage V _U of the converter has a value proportional to the input signal e _i. can get.

When Δt ₁ > Δt (when e _i is large), the mono-multi MM ₁₂ does not operate and remains at Δt ₁ during the period of g 11 = 1. Since the monomulti MM ₁₂ does not operate, the monomulti MM ₁₃ and MM ₁₄ do not operate and g ₂₂ = 0 remains. Naturally, the output voltage V _{U of the} converter
Is proportional to the input signal e _i .

The case where the PWM control input signal e _i is positive has been described above, but the same applies when the input signal e _i is negative. A brief description will be given without a time chart.

The monomulti MM ₂₁ operates at the rising edge of the signal g ₂ and determines whether the period Δt ₂ of g ₂ = 1 is longer than the minimum on-time Δt of the element.

When Δt ₂ <Δt, the monomulti MM ₂₂ is operated at the falling edge of g ₂ and the signal of “1” is output during the Δt ^* period. At this time, choose Δt ^* Δt. The logical sum circuit OR ₂₁ takes the logical sum of the signal g ₂ and the output signal m ₂₂ of the MM ₂₂ to extend the period of g ₂ = 1 to Δt ₂ + Δt ^* .

The mono-multi MM ₂₃ operates at the fall of the output signal m ₂₂ of the mono-multi MM ₂₂ , and the mono-multi MM ₂₄ operates at the fall of the output signal m ₂₃ of the mono-multi MM ₂₃ . Further, the output signal m ₂₄ of the monomulti MM ₂₄ is input to the logical sum circuit OR ₁₂ related to the first gate signal.

The time of the signal m ₂₃ is set to about half the period of the carrier waves X and Y, and thereafter, the period of m ₂₄ = 1 (Δ
⁽ set to t ^* ) only, the first gate signal g _{11 is set} to “1”.

That is, the period of the second gate signal g ₂₂ = 1 is expanded by Δt ^* , and the output voltage of the modulator is increased to the negative side by that amount, but the first gate signal g ₁₁ is also the carrier signal. After half a cycle of, the period Δt ^* becomes “1” and the output voltage of the converter is increased to the positive side. As a result, the period Δt ^*
The output voltage based on is canceled and the initial pulse width Δt ₂
A voltage proportional to remains.

When Δt ₂ > Δt, the monomulti MM ₂₂ does not operate and remains at Δt ₂ during the period of g ₂ = 1.

FIG. 5 shows the relationship between the positive-side voltage and the negative-side voltage of the converter with respect to the PWM control input signal value e _i .

When the input signal e _i is between −e _m and + e _m , a bias voltage corresponding to the pulse width Δt ^* is generated in both positive and negative directions, and e _i <−e _m or e _i <+ e _m There is no bias voltage in the region. The output voltage V _U is the sum of the positive side voltage V _{U (+)} and the negative side voltage V _{U (-)} , and is always the input signal e.
A value proportional to _i is obtained.

As described above, according to the control method of the present invention, regardless of the magnitude of the input signal e _i , the input e
_The output voltage V _U proportional to _i is obtained, and the uncontrollable region, which has been a problem in the past, is eliminated.

In the above description, a mono-multi circuit or an OR circuit is used as a means for creating a new gate signal.
It goes without saying that the same can be achieved by using other means such as a digital circuit, a counter or a microcomputer.

Although the U-phase inverter has been described here, the V-phase and W-phase are controlled in the same manner, and the conventional problems can be solved. Further, it goes without saying that the same can be applied to a three-phase, three-wire type load.

Although the frequencies of the carrier waves X and Y have been described as constant, it goes without saying that the same can be applied even if the carrier wave frequencies are changed.

Although the inverter for converting DC power into AC power has been described above, it goes without saying that the same can be applied to a converter for converting AC power into DC power.

[0065]

As described above, according to the control method of the neutral point clamp type power converter of the present invention, even if the PWM control input signal e _i becomes small, the minimum on-time or the minimum off-time Δt of the element is used. It ’s not out of control,
The output voltage V _U proportional to the input signal e _i is obtained. That is, the neutral point clamp type power conversion that secures the minimum on / off time of the elements of the converter, generates the output voltage proportional to the input signal e _i even when the input signal e _i is small, and eliminates the uncontrollable region. It is possible to provide a method for controlling a neutral point clamp type power converter in which a power generator is generated and an uncontrollable region is eliminated.

Further, according to this control method, the input signal e _i
The pulse width is widened only when the absolute value of
_{In the} area where _i is large, it becomes the same as the conventional control method, so
There is no reduction in converter utilization. Furthermore, the control method of the present invention can be easily digitized and can be a system with few adjustment elements.

[Brief description of drawings]

FIG. 1 is a main circuit configuration diagram for explaining a control method of a neutral point clamp type power converter of the present invention.

FIG. 2 is a block diagram of the control circuit of FIG.

FIG. 3 is a time chart for explaining a control method of the present invention.

FIG. 4 is a time chart for explaining a control method of the present invention.

FIG. 5 is a characteristic diagram for explaining the operation of the control method of the present invention.

FIG. 6 is a main circuit configuration diagram for explaining a control method of a conventional neutral point clamp type power converter.

FIG. 7 is a time chart for explaining a conventional control method.

FIG. 8 is a time chart for explaining a conventional control method.

[Explanation of symbols]

V _d1, V _d2 ... DC voltage source, S ₁ ~S ₄ ... self-turn-off device, D ₁ ~D ₄ ... freewheeling diode, D _5, D ₆ ... clamping diodes, LOAD ... load, CT _U ... current _{detector, C U, C 1, C} 2 ... comparator, G _U (S) ... current control compensation circuit, TRG ... triangular wave generator, SH _1, SH ₂ ... Schmitt _{circuit, MM 11 ~MM 14, MM 21} ~ MM ₂₄ ... Mono-multi circuit, OR ₁₁ , OR ₁₂ , OR ₂₁ , OR ₂₂ ... OR circuit.

Claims (1)

Claims: 1. Self-extinguishing elements S _{1 to} S ₄ connected in series and controlled by pulse width modulation, and a freewheeling diode D ₁ connected in antiparallel to each of these elements. ~ D ₄
And clamping diodes D ₅ and D ₆
In a neutral point clamp type power converter that generates a level output voltage, a triangular wave X that changes between zero and positive side and a triangular wave Y that changes between zero and negative side are prepared as carrier signals for pulse width modulation control. When the triangular waves X and Y are compared with the PWM control input signal e _i , when e _i > X, g ₁ = 1 e _i ≦ X, when g ₁ = 0 e _i <Y, g ₂ = 1 e _{When i} ≧ Y, first and second signals g ₁ and g _{2 for} which g ₂ = 0 are generated, and the period Δt _{1 of the} first signal g ₁ = 1 becomes shorter than the minimum on-time Δt of the element. In case of g ₁ = 1, Δt ₁ +
A new gate signal g ₁₁ expanded to Δt ^* is obtained, and a new gate signal g _{22 in} which the second signal g _{2 is set} to “1” for a period Δt ^{* is obtained} after about a half cycle of the cycle of the carrier signal, When the period Δt _{2 of} the second signal g ₂ = 1 becomes shorter than the minimum on-time Δt of the element, the period Δ of g ₂ = 1.
A new gate signal g ₂₂ expanded to t ₂ + Δt ^* is obtained, and a new gate signal g _{11 in} which the first signal g _{1 is set} to “1” for a period Δt ^* is obtained about half cycle after the cycle of the carrier signal. seeking, by using the first and second new gate signal g _11, g _22, when g ₁₁ = 1, S _1: oN (S _3: off) when g ₁₁ = 0, S _1: off (S _3: oN) when the g ₂₂ = 1, S _4: oN (S _2: off) when g ₂₂ = 0, S _4: off (S _2: oN), characterized in that the pulse width modulation control as Control method for neutral point clamp type power converter.