JP2581712B2 - Automatic determination of external clock frequency - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a data processing device having a plurality of controlled devices that are individually controlled by clocks having different frequencies supplied from the outside, an external clock supplied to the controlled device is Regarding the automatic frequency determination method, the purpose is to automatically determine a clock supplied from the outside and to selectively switch a plurality of control target devices, and operate with a clock 1 generated by an oscillator inside the device. A first count circuit that counts the number of pulses of the clock 1 and a second count circuit that operates with an externally supplied clock 2 and counts the number of pulses of the clock 2. The number of pulses of the clock 1 and the number of pulses of the clock 2 counted by the first count circuit and the second count circuit are compared, and supplied from the outside. The frequency of the clock 2 to be performed is determined, and the plurality of control target devices are selectively switched based on the determination result signal.

[Industrial applications]

The present invention relates to a method for automatically determining the frequency of an external clock applied to a controlled device in a data processing device having a plurality of controlled devices individually controlled by clocks having different frequencies supplied from the outside.

FIG. 3 is a diagram for explaining an example in which the control target is switched by a different clock.

As shown in the figure, for example, there is a data processing device in which a channel device (CHP) 2 that operates in synchronization with a clock is connected to a central processing device (CPU) 1 that operates with a clock having a cycle of 150 ns. At the request of the user, in order to improve the processing capacity of the central processing unit (CPU) 1,
When the period of the clock of the central processing unit (CPU) 1 is reduced to, for example, 100 ns, most of the channel devices (CHP) 2 can sufficiently cope with the clock of 100 ns, but a part of them needs a design change. Often happen.

In such a case, newly designing and manufacturing a channel device (CHP) that operates with the clock of 100 ns is a waste of resources, and thus a part of the channel device (CHP) 2 designed for 150 ns is used. In general, it is considered that a change is made and the central processing unit (CPU) 1 of 150 ns and 100 ns commonly uses the change.

Specifically, a circuit 21 that operates with a clock of 100 ns and a circuit 22 that operates with a clock of 150 ns are provided at the interface of the channel device (CHP) 2 ′ with the central processing unit (CPU) 1, and are provided from outside. The interface circuit with the central processing unit (CPU) 1 is selectively switched according to the frequency of the supplied clock (100 ns / 150 ns), and most of the circuits operating with the conventional 150 ns clock are used with the 100 ns clock. To make effective use of resources.

In the channel device (CHP) 2, the input / output interface circuit is designed to operate at a clock of, for example, 150 ns based on the operation speed of the input / output interface. When it is necessary to connect an input / output device and it is necessary to operate a logical block related to the input / output interface with a clock of 100 ns, most of the channel device (CHP) 2
Since it can operate with a clock of ns, only the portion related to the input / output interface is designed and manufactured according to the speed of the input / output device connected to the input / output interface.
Switch to logical block for s, channel device (CHP) 2
There is a case where we want to share resources.

In any of the above two examples, it is necessary to input a clock (100 ns or 150 ns) required for control from the outside and switch the target control block (logic circuit) in accordance with the frequency of the input clock. For this reason, there is a need for an automatic determination method of an external clock frequency capable of automatically determining the frequency of a clock supplied from the outside and selectively switching a control target block.

[Problems to be solved by conventional technology and invention]

FIG. 4 is a diagram for explaining a conventional control target block switching method.

As shown in the figure, in the conventional method, for example, a short circuit (SC) 24 is provided with a clock switching terminal (selecting the logic circuits 21 and 22 to be controlled in accordance with clocks having different frequencies supplied from outside. T1 and T2), and a signal for selecting the control target logic circuits 21 and 22 is created by physical setting such as changing the short-circuit route between the terminals (T1 and T2).

However, in such a method, the terminals (T1, T2)
The person who configures the settings needs to know how to configure it,
There is a problem that those who do not have the knowledge cannot change the setting.

In addition, even if the user knows the setting method, he or she has to perform the setting operation manually.

The present invention has been made in view of the above-mentioned conventional drawbacks, and in a device having a logic block that operates with a clock having a different frequency, the device itself requires an external device to selectively switch the logic block according to the frequency of a clock supplied from the outside. To determine the frequency of a clock supplied from an external clock, and to provide an automatic determination method of an external clock frequency that generates a signal for selecting a device suitable for the supplied clock based on the determination result. It is assumed that.

[Means for solving the problem]

FIG. 1 is a diagram showing the principle of an automatic determination method of an external clock frequency according to the present invention.

The above problem can be solved by an automatic determination method of the external clock frequency configured as described below.

In a data processing device having a plurality of controlled devices that are individually controlled by clocks having different frequencies supplied from the outside, the data processing device operates on a clock 1 generated by an internal oscillator, and outputs a pulse of the clock 1 A first count circuit 230 for counting the number of clocks; and a second count circuit 231 for operating with a clock 2 supplied from the outside and counting the number of pulses of the clock 2
The number of pulses of the clock 1 and the number of pulses of the clock 2 counted by the two first count circuits 230 and the second count circuit 231 are compared, and the number of pulses of the clock 2 supplied from the outside is compared. The frequency is determined, and the plurality of control target devices are selectively switched based on the determination result signal.

[Action]

That is, according to the present invention, it operates with an external clock signal,
An external clock pulse count circuit (second count circuit) for counting the clock pulse, and an internal clock pulse count circuit (first count circuit) operated by a clock signal generated inside the device and counting the clock pulse The number of clock pulse counts (a circuit that counts internal clock pulses) for one of the two clock pulse count circuits (for example, an external clock pulse count circuit) and the other clock pulse count number for a given count number Whether the clock pulse has been counted is compared by a count number comparison circuit, and a control switching signal for the target device is generated based on the comparison result. Even if no setting work is performed, That the frequency of the clock automatically determined to an effect capable of performing optimum control.

〔Example〕

FIG. 1 is a diagram showing the principle of an automatic determination method of an external clock frequency according to the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention. 2) 231, an internal clock pulse count circuit (counter-1) 230, and a count number comparison circuit {AND gate} 232 are necessary means for implementing the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, referring to FIG. 1, FIG.
An embodiment of a circuit that automatically determines s and an external clock of 150 ns and generates a control switching signal for switching a control target will be described.

In FIG. 2, a counter-1230 is a 6-bit counter generated inside the device and operated by an internal clock of 125 ns, for example, and the count-up enable signal from the counter-2231 is changed from "0". When it becomes "1", all 6 bits are cleared, and the internal clock pulse of 125 ns is counted only when the count-up enable signal is "1".

Then, when the count-up enable signal changes from '1' to '0', the count-up operation is stopped, and while the count-up enable signal is '0', the value at the time of the last count-up is held. ing.

The counter-2 231 is operated by an external clock pulse, for example, a 6-bit counter, and repeats a count-up operation every time an external clock is input. Then, the output of the most significant (MSB) bit of the counter-2 231 is passed through the flip-flops (FF1) and (FF2) 234 operated by the internal clock operating the counter-1230, The synchronization signal is sent to the counter-1230 as the count-up enable signal in synchronization with the internal clock of 125 ns.

The AND gate 232 sets the output signal to "1" when the count-up enable signal is "0" and the most significant (MSB) bit of the counter-1230 is "0".

A flip-flop (FF3) 233 is a flip-flop (FF) that holds the output signal of the AND gate 232 when the count-up enable signal is “0”. It functions to indicate that the clock cycle is 100 ns, and when the output signal is “0”, indicates that the external clock cycle is 150 ns.

That is, the time when the MSB of the counter-2 231 is "1" is 3200 ns when the cycle of the external clock is 100 ns.
Therefore, the count-up enable signal synchronized with the internal clock of 125 ns becomes “1” only during the period of 24 to 26 internal clock pulses having the period of 125 ns. Only during this period, the counter-1230 is counted up,
At the end of the count-up, the counter-123
The MSB of 0 remains '0'.

Therefore, when the count-up enable signal changes from “1” to “0”, the output signal of the AND gate 232 changes to “1”, and the flip-flop (FF3) 233 is set to “1”. I do.

Thereafter, when the out-up enable signal changes from “0” to “1”, the clock to the flip-flop (FF3) 233 is suppressed, and the above state remains as it is.

Hereinafter, since the same operation is repeated, the flip-flop (FF3) 233 indicates “1” while the period of the external clock is 100 ns.

Similarly, when the cycle of the external clock is 150 ns, the count-up enable signal becomes '1' for 37 to 38 clock pulses having a cycle of 125 ns.
At the end of counting up of the counter-1 230, the MSB of the counter-1 230 becomes "1", and when the count-up enable signal changes from "1" to "0", the AND gate 232 is turned on. The output signal becomes "0", the flip-flop (FF3) 233 is set to "0", and this state is maintained thereafter.

In this way, the external clock input cycle (100 ns / 15
0 ns).

The control switching signal may be used to control the above-described logic blocks (for 100 ns and 150 ns) 21 and 22 to be selected.

As described above, according to the present invention, in order to determine the period of the clock input from the outside, the counter operating with the clock generated inside the device and the counter operating with the clock input from the outside are used. 2 is provided, and the number of pulses counted by the two counters is compared with each other to automatically determine the period of the clock input from the outside. The feature is that a logical block suitable for the cycle of the external clock is selected.

〔The invention's effect〕

As described above in detail, the automatic determination method of the external clock frequency of the present invention operates with an external clock signal,
An external clock pulse count circuit (second count circuit) for counting the clock pulse, and an internal clock pulse count circuit (first count circuit) operated by a clock signal generated inside the device and counting the clock pulse And the number of times the other clock pulse count circuit (a circuit that counts internal clock pulses) corresponds to a certain count of one of the two clock pulse count circuits (for example, an external clock pulse count circuit). Whether the clock pulse has been counted is compared by a count number comparison circuit, and a control switching signal for the target device is generated based on the comparison result signal. Even if you do not need to perform the setting To determine the frequency automatically, there is an effect that it is possible to perform optimum control.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of an automatic determination method of an external clock frequency according to the present invention, FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 illustrates an example in which a control target is switched with a different clock. FIG. 4 is a diagram for explaining a conventional control target block switching method. In the drawing, 1 is a central processing unit (CPU), 2, 2 'are channel devices (CH).
P), 21 and 22 are the logic blocks or logic circuits to be controlled, 230 is the internal clock pulse count circuit, or counter-1, 231 is the external clock pulse count circuit, or counter-2, 232 is the AND gate , 233 indicates a flip-flop (FF3), 234 indicates a flip-flop (FF1, FF2), 24 indicates a short circuit (SC), and MSB indicates the most significant bit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-103333 (JP, A) JP-A-57-55644 (JP, A) JP-A-60-52144 (JP, A) 119254 (JP, U)

Claims (1)

(57) [Claims] 1. A data processing apparatus having therein a plurality of controlled devices individually controlled by clocks having different frequencies supplied from the outside, wherein each of the plurality of controlled devices is controlled by an internal oscillator. A first counting circuit that operates on the generated clock 1 and counts the number of pulses of the clock 1, and operates on the clock 2 supplied from the outside,
And a second count circuit for counting the number of pulses of the clock signal. The first count circuit and the second count circuit compare the number of pulses of each of the clocks 1 and 2 counted by the second count circuit. A frequency of the clock 2 supplied from the external device, and selectively switching the plurality of control target devices based on the determination result signal.