JP2001282384A - Timer unit programmable by software - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that it is impossible to flexibly cope with the use of a user since preliminarily decided bit length or the number of timer channels is prepared in a manufacturing process although the generation of various time cycles is requested for a timer to be used for a semiconductor circuit such as a microcomputer. SOLUTION: This timer unit is provided with plural timer counters having various bit length and capable of arbitrarily selecting an input signal from a clock signal supplied from the outside of a timer, and those timer counters are constituted so as to be used as a timer group in which those timer counters are connected according to arbitrary combination or individual independent timer counters. Also, this timer unit is provided with arithmetic parts for performing arbitrary signal processing inside the timer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer unit which is built in a semiconductor integrated circuit such as a microcomputer (hereinafter referred to as a microcomputer) and controls time in the semiconductor circuit.

[0002]

2. Description of the Related Art A timer generates a time period required for a purpose of use for a time generation and a clock function for controlling time inside and outside a microcomputer chip. For this reason, the fact that various times can be generated by the timer enables more accurate time control and system control.

[0003] The operation of the timer will be briefly described. The timer counts a clock signal by a set of registers called a timer counter register. When a clock signal is input, the timer counter register alone has the property of inverting the logic value held at the rising edge (or falling edge depending on the setting) of the clock signal. The logic value corresponds to the potential held by the register. The logic value is “HIGH” when the voltage is high, and “L” when the potential is low.
Due to this property, when a clock signal is input, the logical value held at the first rising (falling) is inverted, and at the next rising (falling), the logical value is inverted again. Since the clock signal rises (falls) every cycle,
The logical value held in the register returns to the original logical value in two cycles of the clock signal, and outputs a carry signal. Therefore, one timer counter register becomes a binary counter for counting the input clock signal. When the value of the register is output, a signal obtained by dividing the input clock signal by two is obtained.

A timer counter has a configuration in which a plurality of registers as described above are connected in series. The clock signal externally input to the timer unit is divided by the first stage register. When the frequency-divided clock signal is input to the second-stage register, this register performs an operation in which the cycle of the first-stage register is doubled. Since the register itself operates as a binary counter, the logical value of the register in the second stage corresponds to the second digit of the binary number, and the output is obtained by dividing the input clock by four. Further, when the output of the second-stage register is input to the third-stage register, the logical value of the register is the third digit of the binary number, and the output is the clock signal input to the first stage that is divided by eight. For these reasons, a timer counter having an n-bit timer counter register generally has an n-digit binary counter. In this case, after counting 2 ⁿ , an overflow signal is output.

In general, a timer built in a microcomputer has a fixed bit length created in a manufacturing process in accordance with predetermined product specifications. The timer having a fixed bit length of n bits has a constant count of 2 ⁿ until the overflow signal is output, and the time width for generating the required time period is adjusted by the time period width of the input clock signal. Or by a compare match function using a comparator. An example of a timer having a compare match function is described in detail in "Hitachi, Ltd. H8 / 3887 Hardware Manual", and will be described below with reference to FIG.

In FIG. 8, a timer mode register 25
, The multiplexer selects an input signal, and the timer counter 27 counts the selected input signal. In this example, the comparison circuit 28 constantly compares the preset value of the output compare register 29 with the count value of the timer counter 27.
When the two values match, the comparison circuit 28 outputs a match signal, and the timer counter 27 is cleared.
This coincidence signal is output in a cycle for counting a value arbitrarily set in the output compare register 29.

An example of a timer in which an overflow signal of a timer counter is connected as an input signal of another timer counter is disclosed in detail in Japanese Patent Application Laid-Open No. 2-54321, and FIG. This will be described as follows.

The timer shown in FIG.
And two auxiliary registers 30, 32, input control circuits 34, 33, 35 for controlling input signals to the respective registers, and comparators 36, 37. Each of the registers 30, 31, and 32 is independently programmable and an input control circuit selects an input signal. The output terminal of the central register 31 is connected to the input control circuit 33 of the auxiliary registers 30 and 32,
It is connected to the input terminal of the auxiliary register 35, and by cascading with the auxiliary register, the bit length of the register can be increased. The comparators 36 and 37 also have the above-described compare match function.

As described above, since a timer is used within the range of a fixed-bit-length timer counter or the number of timer channels, it cannot meet the requirements of a multi-channel timer or the operation of an optimal circuit scale. Met.

[0010]

In the prior art, since the bit length of the timer circuit formed in the manufacturing process is fixed, the circuit scale is not dependent on the length of the time period to be generated by the timer. In particular, circuits that are not used when the required time period is short are redundant.

When a very long time period is required, a technique disclosed in Japanese Patent Application Laid-Open No. 2-54321 can cascade-connect a plurality of timers to increase the bit length. Anyway, it is not possible to cope with the setting of the time period having various demands with the optimum circuit scale.

The present invention provides a timer unit which is capable of generating a time with a circuit scale optimal for a required time period or a labor-saving circuit even when the bit length of the timer circuit is fixed.

[0013]

SUMMARY OF THE INVENTION The present invention provides a timer counter which can operate independently, a control circuit which software controls an input signal to be input to each timer counter, and a software after setting the product by software setting. Even so, it is possible to generate various time periods according to the purpose and operate with low power consumption.

Further, it is possible to generate more various time periods for the output signals of the respective timer counters via an arithmetic unit for performing signal processing.

[0015]

(Embodiment 1) An embodiment of the present invention is shown in FIG. This embodiment includes a group of timer counters having various bit lengths, an input selection circuit for selecting an input signal of each timer counter, and a control unit for controlling the connection of the group of timer counters by setting the input selection circuit. The control unit can be arbitrarily set by the user by software.

A plurality of clock signals are input to the input selection circuit from outside the timer counter. Among these clock signals, an appropriate clock signal is output to each timer counter according to the setting of the control circuit. The timer counter receives the clock signal, counts, and outputs a clock signal divided according to the bit length and an overflow signal. The overflow signal is output outside the timer counter and supplies the generated timing to various modules. The signal divided by the timer counter is also connected to the input selection circuit, and can be input to the timer counter again.

In this embodiment, a plurality of different timer counters 1-3, multiplexers 7-12 as input selection circuits for selecting signals to be input to each timer counter, and connection of each timer such as selection of input signals are controlled. Control unit 10
Here is an example of a basic configuration.

The timer counter can be composed of an arbitrary number and an arbitrary bit length can be used. In the embodiment, for convenience, the timer counter 1 has 4 bits, the timer counter 2 has 3 bits, and the timer counter 3 has 2 bits. And The signals to be input to each of the timer registers 1 to 3 can be selected by the multiplexers 4 to 9 from the clock signal supplied from outside the timer unit and the clock signal output from the timer counter register in the timer group.

The following are three examples of the configuration of the embodiment of the present invention shown in FIG.

In the first example, the timer counter 1
In this example, the multiplexers 4 and 5 are set so that 1 is input, the multiplexers 6 and 7 are set so that CLK2 is input to the timer counter 2, and the multiplexers 8 and 9 are set so that CLK3 is input to the timer counter 3. FIG. 2 is a block diagram when this setting is performed. In this use example, 4-bit, 3-bit, and 2-bit timer counters are operated by the clock signals CLK1, CLK2, and CLK3, respectively, which is equivalent to the use of three completely independent timers.

In the second example, the timer counter 1 is provided with multiplexers 4 and 5 so as to input CLK1 as in the previous example.
In the example, the multiplexers 6 and 7 are set so that CLK2 is input to the timer counter 2, and the timer counter 3 is set so that the clock signal divided by the timer counter 2 is input from the path 16. is there. FIG. 3 shows a block diagram in the case of this setting. This use example is equivalent to a case where three types of timers are used, that is, a 4-bit timer counter that operates on CLK1 and a 3-bit timer counter and a 5-bit timer counter that operate independently on CLK2.

In a third example, the timer counter 1 outputs CLK2
The multiplexers 4 and 5 are set so as to input a signal, and the timer counter 2 is stopped without receiving a signal. When the timer counter 1 outputs the overflow signal, the signal input to the timer counter 1 is closed by software, and the multiplexer 7 is set so that CLK2 is input to the timer counter 2 to operate. The clocks divided by these two timer counter registers 1 and 2 are input to the timer counter 3 via the multiplexer 9 via the paths 15 and 16, respectively. FIG. 4 shows a block diagram in the case of this setting.

An operation example in the case of this setting will be specifically described.

Assuming that the cycle of CLK1 is twice as long as the cycle of CLK2, when the 4-bit timer counter 1 is operated by CLK1, an overflow signal is output when CLK1 has counted 16 times. This is a cycle of 32 counts of CLK2. The clock input to the timer counter 1 is stopped by the overflow signal of the timer counter 1, and the clock signal CLK 2 is input to the timer counter 2. The timer counter 2 outputs an overflow signal when eight clock signals CLK2 are counted. Due to this overflow signal, the clock input of the timer counter 2 is stopped, and the clock signal CL is supplied to the timer counter 1.
K1 is input, and thereafter, these operations are repeated. Since the timer counter 3 receives an overflow signal alternately output from the two timer counters 1 and 2,
The count is incremented by two counts of CLK1 and eight counts of CLK2. Therefore, the timer counter 3 outputs 4 by the second overflow signal of the timer counter 2.
Since the count is counted and overflow occurs, 40 of CLK2
A time period of the count will be generated. Since this 40 count is not 2 ⁿ , it cannot be generated by a normal interval timer. (Embodiment 2) When timers having different bit lengths are used at the same time, the lower bits of the timer counter may perform duplicate counting operations. In this case, the lower bit portion of the timer counter is shared, and the clock signal divided by the timer counter is input to each timer counter, whereby the overlapping lower bit portions of the plurality of timer groups in FIG. 1 are shared. An example in the case of being used in the following manner is shown. By the common use, the number of bits of the operating timer counter can be reduced, and power consumption can be reduced.

In this embodiment, the control unit 10 performs the following operation.
Is set by software, and a block diagram is shown in FIG. The clock signal CLK1 input to the timer unit is supplied to the 4-bit timer counter 1 via the multiplexers 4 and 5, and the clock signal divided by the timer counter 1 is supplied to the 3-bit timer counter 2 via the multiplexer 7 from the path 15. input. Similarly, the signal is input to the 2-bit timer counter 3 from the path 15 via the multiplexer 9.

The clock signal CLK1 is supplied to the timer counter 1.
Is input, the 4-bit timer counter 1 outputs an overflow signal to the wiring 12 at 16 count intervals of the input signal CLK1 and outputs the clock signal divided by 16 to the wiring 15.
Output to In the second stage 3-bit timer counter 2,
When this clock signal is input, the overflow signal is output to the wiring 16 at an interval of 8 counts with respect to the input signal of the timer counter 2. The clock signal divided by the timer counter 1 is also input to the 2-bit timer counter 3. The overflow signal is output to the wiring 14 at 4 counts with respect to the input signal of the timer counter 3.

Therefore, in the second embodiment, CLK1 is input, and CLK1 is counted as 16 as overflow output.
A time period of 64 counts and 128 counts can be obtained. This is a time period obtained by a normal 4-bit, 6-bit, and 7-bit interval timer. When simultaneously operating the 6-bit and 7-bit counters, a timer counter for 13 bits is usually required, but in the second embodiment, the required time period can be obtained with 9 bits.

As described above, by giving each timer counter a bit length and associating each with the software, various bit lengths and a plurality of overflow signals are generated, and various time periods are set according to the required specifications. Can be generated, and the number of operation counters can be reduced.

Although the first embodiment operates a 9-bit counter, a time period similar to that of the 4-bit or 7-bit interval timer can be generated, so that the number of operating timer counters is reduced. (Embodiment 3) FIG. 6 shows an embodiment of the present invention. In addition to the timer unit shown in FIG. 2, an operation unit 24 capable of performing an operation process on an output signal of each timer counter is provided. The operation unit 24 performs an operation on the input output signals of the timers according to the settings of the control unit 10. The arithmetic unit 24 in FIG. 7 may be determined according to the specifications of the timer.

The multiplexers 4 and 5 are set by the control unit 10 so that CLK1 is input to the 4-bit timer counter 1. Further, the multiplexers 8 and 9 are set by the control unit 10 so that CLK2 is input to the 2-bit timer counter 3. In this case, the two timer counters 1 and 3 operate independently of each other.

CLK1 is divided by 16 by the timer counter 1 and CLK2 is divided by 4 by the timer counter 3. These clock signals are input to the arithmetic element 20 of the arithmetic unit 24 via the wirings 21 and 22. The control unit 10 is set so that the operation result is input to the timer counter 2 by the multiplexer 7 via the wiring 23. The arithmetic unit can perform any signal processing such as a logical operation and an inverted output. In this example, an example in which two signals are ANDed for convenience is shown. FIG. 7 shows the clock signals generated by the timer counter 1 and the timer counter 2 and the timing of the signal output from the arithmetic element 20.

Since the clock signal CLK1 is divided by 16 by the 4-bit timer counter 1 and the clock signal CLK2 passed through the 2-bit timer is divided by 4, the signals input to the arithmetic element 20 by these signals are divided by 2 When the logical value of the frequency-divided clock signal is “HIGH” level, a frequency-divided clock signal is output. If the logical value is "L"
The output in the case of the "OW" level is the "LOW" level.
The clock signal can be counted by inputting the signal generated by the arithmetic unit to another timer counter via the wiring 23.

According to the present invention, a clock signal or overflow signal generated by a different timer counter or a combination of timer counters is generated by the arithmetic unit to generate a new signal, so that more various time periods can be handled.

[0034]

According to the present invention, the operation of the timer counter can be optimized according to the intended use by the combination of the timer counter registers, so that the power consumption can be reduced. Also,
A plurality of various time periods can be generated, and more accurate time generation can be performed.

Also, since the present invention is very versatile,
Compatible with advanced specifications, and the range of applications can be further expanded by using with conventional technology.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing first and second embodiments of the present invention.

FIG. 2 is a first configuration example in the circuit diagram of FIG. 1;

FIG. 3 is a second configuration example in the circuit diagram of FIG. 1;

FIG. 4 is a third configuration example in the circuit diagram of FIG. 1;

FIG. 5 is a fourth configuration example in the circuit diagram of FIG. 1;

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a timing chart according to a third embodiment of the present invention.

FIG. 8 is an example of a compare match function according to the related art.

FIG. 9 is an example of a conventional timer circuit.

[Explanation of symbols]

1-3: timer counter, 4-9: multiplexer, 1
0: control unit, 11, 19: register, 12 to 14: overflow signal output, 15 to 17: divided clock output, 18: CPU, 20: arithmetic element, 21, 22: clock signal input to the arithmetic element Output, 23: arithmetic element output, 24: arithmetic unit, timer mode register, 27: timer counter, 28: comparison circuit, 29: output compare register, 30, 32: auxiliary register, 31: central register, 33 to 35 ... Input control circuit, 36,
37 ... Comparator.

Claims (3)

[Claims] 1. A timer unit used in a semiconductor integrated circuit, comprising: a plurality of timer counters; and a control unit for software-controlling an input signal to be input to each of the timer counters; Timer unit that operates as a group or individual timer counter. 2. The timer unit according to claim 1, wherein each timer group or timer counter configured for the purpose of generating a plurality of time periods has a function of sharing an overlapping count operation part. 3. An output signal of a timer group or a timer counter configured for generating a certain time period and another output signal generated by a timer group or a timer counter having a different configuration. And a timer unit provided with an arithmetic unit that performs signal processing on a clock signal generated separately from the above in any combination.