JPH03171820A - 2n-1 frequency dividing circuit - Google Patents

Abstract

PURPOSE:To obtain a 2n-1 frequency dividing circuit with a simple constitution by feeding back the NAND output between the Q output of a flip flop in the (n-1)th stage and that in the last stage to the D input of a flip flop in the first stage. CONSTITUTION:The n-number of D type flip flops 10 connected in series and a NAND gate 11 which operates NAND between a Q output Qn-1 of the flip flop 10 in the (n-1)th stage and a Q output Qn of the flip flop 10 in the n-th stage (last stage) are provided, and flip flops 10 constitute a series connection circuit where the Q output of each flip flop is connected to the D input of the flip flop in the next stage. The output of the NAND gate 11 is fed back to a D input D1 of the flip flop 10 in the first stage. That is, the NAND output between the Q output of the flip flop 10 in the (n-1)th stage and that in the last stage is fed back to the D input of the flip flop 10 in the first stage. Thus, odd frequency division is performed with simple constitution.

Description

[Detailed Description of the Invention] [R Required] Regarding a 2n-1 (odd number) frequency divider circuit configured using n D type flip-flops, to realize the odd number frequency divider circuit with a simple circuit. The purpose is to connect n D-type flip-flops in series, input a common clock to the clock input of each flip-flop, and output the Q output of the n-1st stage flip-flop and the Q output of the final stage flip-flop. A NAND gate is provided to take a NAND with the output, and the NAND gate output is fed back to the D input of the first stage flip-flop.

[Industrial Application Field] The present invention relates to a 2n-1 (odd number) frequency divider circuit configured using n D-type flip-flops.

[Prior Art] A circuit that divides a certain clock into a power of 2 is relatively simple to use by using a D-type flip-flop or counter, and is often used. FIG. 4 is a conceptual diagram of the structure of a 1/16 frequency divider circuit. 4 flip-flops = 1/
It constitutes a frequency dividing circuit of 2'-1/16. Generally, the output of a frequency divider circuit constructed using n flip-flops is divided by 1/2''.

FIG. 5 is a diagram showing operating waveforms of each part of the circuit of FIG. 4.

(a) shows the clock, (b) shows the first stage output QA, (c)
shows the second stage output QB, (d) shows the three stage output QC, and (e) shows the final stage output QD. Final stage output QD
It can be seen that 16 clocks are included within the period T of , and the frequency is divided by 1716.

On the other hand, in an odd frequency divider circuit, there is no fixed path,
Each time, he devises a circuit. FIG. 6 is a diagram showing an example of the configuration of a 1/7 frequency divider circuit. Compared to the circuit shown in FIG. 4, three stages of flip-flops 1 are connected in series, the Q outputs and NAND of all clip-flops are taken by a NAND gate 2, and the output of the NAND gate 2 is sent to the clear input CL of all flip-flops 1. I'm putting it in. As is clear from the QA, QB, and QC output waveform diagrams in Figure 5, they all become "1°" at the falling edge of clock 7 and 121. Therefore, 7
At the falling edge of the signal, the output of NAND gate 2 becomes "01", clearing all the flip-flops to 0 and realizing a 1/7 frequency divider circuit.

[Problem to be solved by the invention] As mentioned above, there is no specific circuit for dividing a certain clock by an odd number, and the same circuit must be devised every time it is needed. Also, it is easy to make an error in the same route setting = 1.

The present invention has been made in view of these problems, and it is an object of the present invention to provide an odd frequency division circuit using a simple Q1 circuit.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
10 is a D type flip-flop in which n pieces are connected in series. 11 is a NAND gate which NANDs the Q output Qn-1 of the n-1 stage flip-flop 10 and the Q output Qn of the n stage (final stage).

The flip-flop 10 has its Q output controlling a series connected circuit connected to the D input of the next stage. nand gate 1
1 is fed back to the D input D1 of the first-stage flip-flop 10.

The human clock is commonly input to the clock inputs CKI to CKn of the flip-flops 10 in each stage.

Then, the output of the frequency divider circuit is the final stage flip-flop 1
It is output from Q output Qn of 0.

[Sakukawa J The NAND output of the Q output of the n-1 stage flip-flop 10 and the Q output of the final stage flip-flop 10 is fed back to the D input of the first stage flip-flop 10.

As a result, the circuit shown in the figure is 2n when the system is stable.
It operates as a -1 frequency dividing circuit, that is, a 1/(2n-1) frequency dividing circuit. As is clear from the figure, according to the present invention, odd number frequency division can be performed with an extremely simple configuration.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

Components that are the same as those in FIG. 1 are designated by the same reference numerals.

In the embodiment shown in the figure, four D-type flip-flops 10 are connected in series, n-4, and 2n-1 -
8-1-7, indicating a 177 frequency divider circuit. Third
The NAND gate 11 takes the output Q3 of the flip-flop 10 in the fourth stage and the output Q4 of the flip-flop 10 in the fourth stage, and the output of the NAND gate 11 is connected to the output Q4 of the fourth stage flip-flop 10.
It is fed back to input D1. The operation of the circuit configured in this way will be explained as follows.

First, DI, D2, D3, D4. Set the initial state of Q4 to “1”
0000". At the first clock rise, D2 becomes "1", and at the second clock rise, D3 becomes "1".
1”, and D4 becomes “1” at the third rising edge of the clock.
”, and Q4 becomes “1” at the rising edge of the fourth clock.
becomes.

Here, since D4 and Q4 become '1', the output of the NAND gate 11 becomes '0°' and D1 becomes '0'. Furthermore, when the three clocks rise, D4 becomes "0°" and Q4 becomes "1", so the output of the NAND gate 11 becomes "1" and D1 becomes "1°". Thereafter, by repeating the same operation, an output frequency-divided by seven is obtained from Q4 of the flip-flop 10 at the final stage.

FIG. 3 is a timing chart showing operating waveforms of each part of the circuit of FIG. 2. The initial state shown in the figure is "10000", which is the same as in the above explanation. In the end, DI, D2, D
3, D4. The Q4 waveforms are clocks with the same period delayed by one clock, and there are 7 clocks within the period T.
It can be seen that the frequency is divided by 7.

In the above explanation, we have explained the case where the initial value is "1 0000", but this same route operates as a divide-by-7 same route not only for this initial value but also for other initial values, and the final value is The waveform will be as shown in FIG. Furthermore, in the above-mentioned embodiments, the case where four flip-flops are used, that is, n-4, is a divide-by-7 circuit is explained as an example, but the present invention is not limited to this, and all other white flip-flops are used. The same applies to the case of a natural number n.

[Effects of the Invention] As explained above in detail, according to the present invention, the NAND output of the Q output of the n-1 stage] 1 flip-flop and the Q output of the regroup (n stage) flip-flop is A 2n-1 frequency dividing circuit can be provided with a simple configuration of feeding back to the D input of the flip-flop, and the practical effect is extremely large.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram of the principle of the present invention.
Figure 4 is a timing chart showing the operating waveforms of each part of the circuit, Figure 4 is a conceptual diagram of the structure of the 1/16 frequency divider circuit, Figure 5 is the
FIG. 6 is a timing chart showing operating waveforms of each part of the circuit. FIG. 6 is a diagram showing an example of a conventional structure of a 1/7 frequency divider circuit. In FIG. 1, 10 is a D-type flip-flop, and 11 is a NAND gate.

Claims (1)

[Claims] n D-type flip-flops (10) are connected in series, a clock is commonly input to the clock input of each flip-flop, and the Q output of the n-1st stage flip-flop (10) and , a NAND gate (11) that takes NAND with the Q output of the final stage flip-flop (10) is provided, and the NAND gate (11)
1) A 2n-1 frequency dividing circuit configured by feeding back the output to the D input of the first-stage flip-flop (10), and whose output is the Q output of the final-stage flip-flop (10).