JP2020054072A - Series multiplex power conversion device and control method therefor - Google Patents

Abstract

To provide a series multiplex power conversion device in which losses generated in units and switching elements are uniformized.SOLUTION: In a pulse-width modulation circuit, for each unit, a voltage command value Vref is compared with two types of gate thresholds Vth1a, Vth1b each of which is a constant value during at least one cycle of a voltage command value Vref so that a gate signal of a switching element is generated. In the case where the number of units in each phase is two, gate thresholds Vth1a, Vth1b, Vth2a, Vth2b in each of the units in each phase become different from one another. The gate thresholds Vth1a, Vth1b, Vth2a, Vth2b are cyclically switched. The switching cycle of the gate thresholds Vth1a, Vth1b, Vth2a, Vth2b is set to an integral multiple of the cycle of the voltage command value Vref.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a modular multilevel cascade converter (MMCC) of a single star bridge cell (SSBC) linked to a three-phase AC system, and more particularly to a technique for equalizing thermal responsibility due to loss of each unit. About.

  Patent Literature 1 discloses an example of a power conversion device which is connected to a system power supply having a frequency of 50 Hz or 60 Hz, and three bridge cells B are connected in series to constitute one phase of an MMCC.

  FIG. 8 shows a configuration of a power converter in which two bridge cells B are connected in series per phase. As shown in FIG. 8, the bridge cell B (unit 11) includes four switching elements U1, V1, X1, Y1 and a capacitor C1.

  There is a method of obtaining a gate signal by comparing the voltage command value Vref with a fixed gate threshold instead of a carrier triangular wave. When the voltage command value is compared with the fixed gate threshold value, one pulse is driven per one cycle of the fundamental wave. Patent Document 1 is characterized by driving with one pulse per one cycle of the fundamental wave. FIG. 9 shows a driving waveform with one pulse in the configuration of two bridge cells B.

  In the example of FIG. 9, the relationship between the fixed gate thresholds Vth1a, Vth1b, Vth2a, Vth2b and the gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, GY2 (that is, the ON / OFF state of the switching element) is as follows. Assigned like.

  When Vref> Vth1a, the switching element U1 is turned on and the switching element X1 is turned off. When Vref <Vth1a, the switching element U1 is turned off and the switching element X1 is turned on.

  If Vref> Vth2a, turn on switching element U2 and turn off switching element X2; if Vref <Vth2a, turn off switching element U2 and turn on switching element X2.

  When Vref> Vth2b, the switching element Y2 is turned on and the switching element V2 is turned off. When Vref <Vth2b, the switching element Y2 is turned off and the switching element V2 is turned on.

  When Vref> Vth1b, the switching element Y1 is turned on and the switching element V1 is turned off. When Vref <Vth1b, the switching element Y1 is turned off and the switching element V1 is turned on.

  When the gate thresholds Vth1a, Vth1b, Vth2a, Vth2b and the voltage command value Vref have the same value, either of the two switching elements may be turned ON and either of the two switching elements may be turned OFF.

  By this operation, the waveform of FIG. 9 is obtained as the output voltages Vo1 and Vo2 of the first and second units 11 and 12, and the total output voltage Vo. FIG. 9 shows a configuration in which two first and second units 11 and 12 are connected in series. If a plurality of units are multiplexed and a plurality of gate thresholds are prepared, a total output voltage Vo close to a sine wave can be obtained.

  In addition, since each switching element performs switching at a maximum of one time (one turn-on and one turn-off) for one cycle of the fundamental wave of the output voltage, the gate signal is compared by comparing a carrier triangular wave having a high frequency with a voltage command value. The number of times of switching is smaller than that of the generation method, and the switching loss can be reduced.

  In the configuration of FIG. 8, only the reactive power can be handled because only the capacitor is connected to the DC portion of the unit. Therefore, it is used as a reactive power compensator. However, if a battery or other power converter is connected to the DC portion of the unit, it can be used as a device for inputting and outputting active power.

JP 2014-100026 A

  However, the gate signal generation method shown in FIG. 9 has a problem that the loss generated in each unit varies greatly. FIG. 10 shows such an example.

  In FIG. 10, the amplitude of voltage command value Vref is smaller than that in FIG. 9, and the absolute value of voltage command value Vref is smaller than the absolute values of gate thresholds Vth1a and Vth1b. At this time, the switching element X1 and the switching element Y1 are always ON, and only conduction loss occurs. Switching element U1 and switching element V1 are always OFF and the loss is zero. In the switching elements U2, V2, X2, and Y2, both conduction loss and switching loss occur.

  However, since the switching elements X2 and Y2 are always turned on when the output voltage Vo2 is zero, the time for the current to pass through the switching elements X2 and Y2 is longer than the time for the switching elements U2 and V2, and the switching elements X2 and Y2 Is larger than the switching elements U2 and V2.

  As described above, the loss (the sum of the conduction loss and the switching loss) generated in each unit and each switching element greatly varies depending on the output voltage. In this case, if the cooling design is performed in accordance with the unit or the switching element having the largest loss, the design of the unit having a small loss becomes excessive, and the cost and the volume of the device increase.

  On the other hand, if the cooling design is changed for each unit, it takes a long time to design, and there is a problem that the effect of mass production of the unit is not obtained, the cost is increased, and the assembly of the device is complicated.

  Furthermore, in the case of a grid-connected inverter, there is a case where a fold-ride-through (FRT) correspondence that continues operation even when an instantaneous sag occurs is required. At the moment of voltage sag, switching loss occurs only in a small number of units, and in most of the remaining units, the generated switching loss becomes zero. If the system is unstable and the frequency of voltage sags is high, thermal fatigue is caused by concentrating thermal responsibility only on a specific switching element, and the life of the device is shortened.

  As described above, in the serial multiplex power converter, it is an issue to make the loss generated in each unit and each switching element uniform.

  The present invention has been devised in view of the above-described conventional problems, and one aspect of the present invention is a system in which a plurality of bridge cell units are connected in series in each phase, and a series is connected to a three-phase AC system power supply. A multiplex power conversion device, wherein for each of the units, a voltage command value is compared with two types of gate thresholds having a constant value for at least one cycle of the voltage command value, and a gate signal of a switching element is compared. A pulse width modulation circuit that generates the gate threshold value in each unit in each phase takes a different value, the gate threshold value is periodically switched, the switching period of the gate threshold value of the voltage command value It is characterized by being an integral multiple of the period.

  In one embodiment, the gate threshold value is switched at the time of a positive peak of the voltage command value.

  In one embodiment, a first unit and a second unit are provided in each phase as the bridge cell, and the gate thresholds Vth1a and Vth1b of the first unit are values having the same absolute value and opposite signs, respectively. The gate thresholds Vth2a and Vth2b of the second unit have the same absolute value and opposite signs, and the gate thresholds Vth1a, Vth1b, Vth2a, and Vth2b have a magnitude relationship shown in Table 1 below. Features.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle.

  In another aspect, a first unit, a second unit, a third unit, and a fourth unit are provided in each phase as the bridge cell, and the gate thresholds Vth1a and Vth1b of the first unit are absolutely different from each other. The gate thresholds Vth2a and Vth2b of the second unit are equal in value but opposite in sign, and the gate thresholds Vth3a and Vth3b of the third unit are equal in value and opposite in sign. Have the same absolute value and opposite signs, and the gate thresholds Vth4a and Vth4b of the fourth unit have the same absolute value and opposite signs, and have the gate thresholds Vth1a, Vth1b, Vth2a. , Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b have a magnitude relationship shown in Table 2 below. And wherein the door.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle.

  In another aspect, a first unit, a second unit, a third unit, and a fourth unit are provided in each phase as the bridge cell, and the gate thresholds Vth1a and Vth1b of the first unit are the same as each other. Are the opposite values, and the gate thresholds Vth2a and Vth2b of the second unit have opposite signs, and the gate thresholds Vth3a and Vth3b of the third unit are the opposite signs. And the gate thresholds Vth4a and Vth4b of the fourth unit have opposite signs, and | Vth1a-Vth1b |, | Vth2a-Vth2b | and | Vth3a-Vth3b | for all input signals p. And | Vth4a−Vth4b | are constant values, and the gate threshold values Vth1a, Vth1b, Vth2 , Vth2b, Vth3a, Vth3b, Vth4a, Vth4b is characterized in that a magnitude relationship shown in Table 3 below.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle.

  ADVANTAGE OF THE INVENTION According to this invention, in a serial multiplex power converter, it becomes possible to make the loss which generate | occur | produces in each unit and each switching element uniform.

FIG. 2 is a block diagram illustrating a pulse width modulation circuit according to the first embodiment. 5 is a time chart illustrating an example of a gate threshold and each waveform according to the first embodiment. FIG. 9 is a block diagram illustrating a pulse width modulation circuit according to the second and third embodiments. 9 is a time chart illustrating an example of a gate threshold value and each waveform according to the second embodiment. 6 is a time chart showing an output active power of a unit according to a threshold switching pattern. 9 is a time chart illustrating an example of a gate threshold and each waveform according to the third embodiment. 9 is a time chart illustrating an output active power of a unit according to the third embodiment. FIG. 2 is a circuit configuration diagram illustrating an example of a serial multiplex power converter. 9 is a time chart showing an example of a gate threshold value and each waveform according to the related art. 7 is a time chart showing an example of a gate threshold value and each waveform when the amplitude of a voltage command value is small in the conventional technology.

  Hereinafter, the first to third embodiments of the serial multiplex power converter according to the present invention will be described in detail with reference to FIGS.

[Embodiment 1]
In the first embodiment, a method of making the loss generated in each unit and each switching element uniform will be described by taking the serial multiplex power converter shown in FIG. 8 as an example. First, the configuration of the serial multiplex power converter shown in FIG. 8 will be described.

  As shown in FIG. 8, the serial multiplex power converter according to the first embodiment includes two first units 11, 21, 31 and second units 12, 22, 32 in each phase. The switching elements U1, V1, X1, and Y1 are bridge-connected to the first units 11, 21, 31, and the switching elements U2, V2, X2, and Y2 are bridge-connected to the second unit 12. A capacitor C1 is connected between a common connection point of the switching elements U1 and V1 and a common connection point of the switching elements X1 and Y1, and a connection between the common connection point of the switching elements U2 and V2 and the common connection point of the switching elements X2 and Y2. The capacitor C2 is connected therebetween.

  The common connection point of the switching elements U1 and X1 of the first units 11, 21, 31 is connected to each phase of the three-phase AC system power supply 1 via the reactor L. The common connection point of the switching elements V1, Y1 of the first units 11, 21, 31, and the common connection point of the switching elements U2, X2 of the second units 12, 22, 32 are connected. The common connection points of the switching element V2 and the switching element Y2 of the second units 12, 22, 32 are connected.

  The output voltage Vo1 of the first unit 11 is defined between the common connection point of the switching elements U1 and X1 and the common connection point of the switching elements V1 and Y1, and the common connection point of the switching elements U2 and X2 and the common connection point of the switching elements V2 and Y2. The output voltage Vo2 of the second unit 12 is set between the connection point and the connection point. The total output voltage Vo is defined between the common connection point of the switching elements U1 and X1 of the first unit 11 and the common connection point of the switching elements V2 and Y2 of the second unit 12.

  FIG. 1 shows a block diagram of the pulse width modulation circuit of the first embodiment. The input signal p is a signal that gradually increases from 0 to 1 in the gate threshold switching period. The input signal p corresponds to the horizontal axis (time axis) of the waveform shown in FIG.

  Table 2 receives the input signal p, refers to the gate threshold value Vth1a corresponding to the previously stored input signal p, and outputs the same.

  The adders 1a, 1b and 1c add fixed offset values 1/2, 1/4 and 3/4 to the input signal p, respectively. Table 2 inputs the input signals p + ２ ，, p + ４ ，, p + ／, and refers to numerical values after the decimal point of the input signals p + ／, p + ／, p + ３, and corresponding gate thresholds Vth1b, Vth2a. , Vth2b. The table 2 itself is the same as the table 2 for calculating the gate threshold Vth1a, and only the input signals are different from p, p + 1/2, p + ／, p + ３.

  Vth1a and Vth1b are gate thresholds for the first unit 11. Vth2a and Vth2b are gate thresholds for the second unit 12.

  The voltage command value Vref may be given a sine wave whose amplitude and frequency are determined in advance, or may be obtained by feedback control to make the output voltage or output current equal to the command value.

  The subtracters 3a to 3d calculate differences between the voltage command value Vref and the gate threshold values Vth1a, Vth1b, Vth2a, Vth2b, respectively.

  The comparators 4a to 4d receive the operation results of the subtracters 3a to 3d and compare them with zero. However, the magnitude relation is different between the comparators 4a and 4c and the comparators 4b and 4d.

  The comparator 4a outputs 1 when the operation result of the subtractor 3a is larger than 0, that is, when Vref> Vth1a, and outputs 0 when Vref ≦ Vth1a. Comparator 4b outputs 1 when the operation result of subtractor 3b is smaller than 0, that is, when Vref <Vth1b, and outputs 0 when Vref ≧ Vth1b. The comparator 4c outputs 1 when the operation result of the subtractor 3c is larger than 0, that is, when Vref> Vth2a, and outputs 0 when Vref ≦ Vth2a. The comparator 4d outputs 1 when the operation result of the subtractor 3d is smaller than 0, that is, when Vref <Vth2b, and outputs 0 when Vref ≧ Vth2b.

  The dead time processors 5a to 5d receive the outputs of the comparators 4a to 4d, add the dead time, and generate the gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, GY2. Note that GU1, GX1, GV1, GY1, GU2, GX2, GV2, and GY2 are gate signals of the switching elements U1, X1, V1, Y1, U2, X2, V2, and Y2 in FIG.

  FIG. 2 shows the contents of the table in the first embodiment. In FIG. 2, the horizontal axis is the input signal p, and the vertical axis is the gate threshold Vth for output. The gate threshold Vth1a corresponding to the input signal p is indicated by a thick solid line, and the gate threshold Vth1b corresponding to the input signal p + 1/2 is indicated by a broken line. Similarly, the gate threshold Vth2a corresponding to the input signal p + ／ is indicated by a thick solid line, and the gate threshold Vth2b corresponding to the input signal p + ３ is indicated by a broken line.

  The waveform of FIG. 2 shows a range of 0 <p <2. Even when the input signal p is out of the range of FIG. 2, if n is an integer, the waveform of the gate threshold Vth has a periodicity such that Vth (n + p) = Vth (p).

  In FIG. 2, there is a relationship of Vth1a = −Vth1b and Vth2a = −Vth2b.

  Table 1 below is a table showing the magnitude relationship between the cycle of the voltage command value Vref and each gate threshold in FIG.

  As can be seen from FIG. 2 and Table 1, each gate threshold has a constant value for at least one cycle of the voltage command value Vref.

  In the first embodiment, the gate signal is switched to another unit by periodically changing the gate threshold values Vth1a, Vth1b, Vth2a, and Vth2b to be compared with the voltage command value Vref for generating the gate signal. This is to make the resulting loss uniform.

  FIG. 2 also shows the gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, GY2 of the respective switching elements and the output voltages Vo1, Vo2 of the unit obtained according to the first embodiment. When each gate signal is 1, the corresponding switching element is turned on. When each gate signal is 0, the corresponding switching element is turned off.

  The gate thresholds Vth1a, Vth1b, Vth2a, Vth2b are changed at the timing of the phase at which the voltage command value Vref becomes maximum (peak on the positive side). By periodically inverting the magnitude relationship between the gate threshold value Vth1a and the gate threshold value Vth1b, the ON times of all the switching elements are made uniform, and the conduction loss is made equal.

  As for the switching loss, since the switching elements that perform the switching operation in units of one cycle of the fundamental wave of the output voltage are replaced, it is possible to prevent a specific switching element from switching only at a specific phase. If the operation is in a steady state and the voltage command value Vref and the waveform of the output current do not change, the switching losses of all the switching elements U1, V1, X1, Y1, U2, V2, X2, and Y2 are made uniform under arbitrary conditions. Can be.

  In FIG. 2, since the amplitude of the voltage command value Vref is smaller than the gate threshold having the maximum absolute value, the waveform of the total output voltage Vo has the same three levels as in FIG. When the amplitude of the voltage command value Vref is larger than the gate threshold having the maximum absolute value, the waveform of the total output voltage Vo has five levels as shown in FIG. Even under this condition, the switching losses of all the switching elements can be made uniform.

  As described above, according to the first embodiment, the loss generated in each unit and each switching element can be made uniform. This facilitates the thermal design of the serial multiplex power converter and eliminates the situation where the temperature of only a specific unit fluctuates greatly when the load changes, so that thermal fatigue of the switching elements and units can be prevented.

  Thereby, the life of the serial multiplex power converter can be extended. Further, by making the loss uniform, there is no excess design for a unit having a small loss, and it is possible to reduce the cost and size of the serial multiplex power converter. In addition, each unit output power responsibility can be made uniform.

[Embodiment 2]
In the second embodiment, in each phase, the bridge cell B is expanded to four series multiple connections. In the first embodiment, the first and second units are provided for each phase. In the second embodiment, the first to fourth units are provided for each phase. FIG. 3 is a block diagram of the pulse width modulation circuit according to the second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

  The adders 1d, 1e, 1f, and 1g add 1/8, 5/8, 3/8, and 7/8 to the input signal p, respectively. Table 2 inputs the input signals p + ／, p + ５, p + ３, and p + ７, and refers to the decimal values of the input signals p + ，, p + ／, p + ３, and p + ７. And corresponding gate thresholds Vth3a, Vth3b, Vth4a, Vth4b.

  The subtracters 3e to 3h calculate the differences between the voltage command value Vref and the gate threshold values Vth3a, Vth3b, Vth4a, Vth4b, respectively. The comparators 4e to 4h receive the operation results of the subtracters 3e to 3h and compare them with 0. However, the magnitude relation differs between the comparators 4e and 4g and the comparators 4f and 4h.

  The comparator 4e outputs 1 when the operation result of the subtractor 3e is larger than 0, that is, when Vref> Vth3a, and outputs 0 when Vref ≦ Vth3a. Comparator 4f outputs 1 when the operation result of subtractor 3f is smaller than 0, that is, when Vref <Vth3b, and outputs 0 when Vref ≧ Vth3b. The comparator 4g outputs 1 when the operation result of the subtractor 3g is greater than 0, that is, when Vref> Vth4a, and outputs 0 when Vref ≦ Vth4a. The comparator 4h outputs 1 when the operation result of the subtractor 3h is smaller than 0, that is, when Vref <Vth4b, and outputs 0 when Vref ≧ Vth4b.

  The dead time processors 5e to 5h receive the outputs of the comparators 4e to 4h, add the dead time, and generate the gate signals GU3, GX3, GV3, GY3, GU4, GX4, GV4, GY4. GU3, GX3, GV3, GY3, GU4, GX4, GV4, GY4 are the gate signals of the switching elements U3, X3, V3, Y3 of the third unit and U4, X4, V4, Y4 of the fourth unit.

  FIG. 4 shows the contents of the table in the second embodiment. Since the number of units has increased to four in each phase, the gate threshold value Vth to be output also takes eight values. These eight values are periodically switched according to the input signal p, and output as gate thresholds Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b.

  In FIG. 4, the gate thresholds Vth1a, Vth2a, Vth3a, and Vth4a are indicated by solid lines, and the gate thresholds Vth1b, Vth2b, Vth3b, and Vth4b are indicated by broken lines. Further, there is a relationship of Vth1a = −Vth1b, Vth2a = −Vth2b, Vth3a = −Vth3b, and Vth4a = −Vth4b.

  Table 2 below is a table showing the magnitude relationship between the cycle of the voltage command value Vref and each gate threshold in FIG.

  The second embodiment also has the effect of reducing the capacitance of the unit capacitor during input and output of active power. This effect will be described with reference to FIG.

  The second waveform from the top in FIG. 5 shows the same waveform as the output voltage Vo1 in FIG.

  On the other hand, as another gate threshold value Vth (p), as shown in the third waveform from the top in FIG. 5, Vth (p) monotonically decreases when 0 <p <4/8, and Vth (pth when 4/8 <p <1. A method in which p) is monotonically increased is also conceivable. The output voltage of the first unit 11 generated based on the gate threshold is Vo1 '.

  Considering the case where the unit is outputting active power, the output current Io has the fifth waveform from the top in FIG. 5 (a sine wave having the same phase as the voltage command value Vref). The output power of the unit can be obtained by Po1 = Vo1 × Io1, Po1 ′ = Vo1 ′ × Io1. FIG. 5 shows the waveforms of the output power Po1 and the output power Po1 '.

  Looking at the output power Po1 ', the width of the pulse A is the smallest (it is zero), and the width of the pulse B is the largest. The change from the pulse A to the pulse B takes two periods of the fundamental wave, and the change from the pulse B to the pulse A takes two periods of the fundamental wave. The pulsation period of the output power is four periods of the fundamental wave.

  On the other hand, the output power Po1 includes the pulse C and the pulse D in the course of the change from the pulse A to the pulse B. The pulse width increases when changing from pulse A to pulse C, decreases when changing from pulse C to pulse D, increases when changing from pulse D to pulse B, and changes from pulse B to pulse A. The pulse width decreases with the change to. Each change of pulse A → pulse C, pulse C → pulse D, pulse D → pulse B takes one period of the fundamental wave, and the pulsation period of the output power is two periods of the fundamental wave.

  Since the impedance of the capacitor (= 1 / 2πfC, f: frequency, C: capacitor capacity) is inversely proportional to the frequency, the shorter the period of the power pulsation, the smaller the impedance and the smaller the capacitor voltage pulsation. Therefore, if the allowable capacitor voltage pulsation is of the same magnitude, the capacitance of the capacitor can be smaller in the case of the output power Po1 (Vo1) than in the case of the output power Po1 '(Vo1').

  That is, the pattern of the gate threshold value table according to the second embodiment for outputting the output power Po1 (Vo1) has an effect of reducing the capacitance of the capacitor as compared with the pattern for outputting the output power Po1 '(Vo1').

  As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained. In the second embodiment, since the cycle of the output power pulsation can be shortened, the capacity of the cell capacitor can be reduced, and the size and cost of the serial multiplex power converter can be reduced.

  In the second embodiment, since each unit does not output a zero-phase voltage as compared with a third embodiment described later, the design of insulation (withstand voltage) is facilitated.

[Embodiment 3]
The third embodiment is an example in which the main circuit configuration and the pulse width modulation circuit are the same as those of the second embodiment, but the gate threshold table 2 has a different pattern. FIG. 6 shows a pattern of the table 2 in the third embodiment.

  The third embodiment is characterized in that | Vth (p) −Vth (p +＋ １) | = 1 is always satisfied. That is, for all input signals p, | Vth1a-Vth1b |, | Vth2a-Vth2b |, | Vth3a-Vth3b |, and | Vth4a-Vth4b | are constant.

  Table 3 below is a table showing the magnitude relationship between the cycle of the voltage command value Vref and each gate threshold in FIG.

  FIG. 7 shows a waveform of the output active power (output power) Po1 (= Vo × Io) of the unit according to the third embodiment. As in FIG. 5, the output current Io is a sine wave having the same phase as the voltage command value Vref.

  In the waveform of the output active power (output power) Po1 in the third embodiment, large-width pulses and small-width pulses (or zero-width pulses) are alternately arranged. By this operation, the pulsation of the output power of the unit is centered on one cycle component of the fundamental wave. Therefore, if the allowable capacitor voltage pulsation has the same magnitude, the capacitance of the capacitor can be smaller than that of the second embodiment.

  On the other hand, since a zero-phase voltage is applied to the unit, an insulation (withstand voltage) design in consideration of the zero-phase voltage is required.

  As described above, according to the third embodiment, the same effect as that of the first embodiment can be obtained. In the third embodiment, since the cycle of the output power pulsation can be further shortened as compared with the second embodiment, the device can be configured with a smaller capacitor capacity.

  As described above, in the present invention, only the specific examples described have been described in detail.However, it is apparent to those skilled in the art that various modifications and variations are possible within the technical idea of the present invention. It is obvious that such variations and modifications belong to the scope of the claims.

  In the first to third embodiments, the switching period of the gate threshold value (that is, the period in which the gate threshold value is kept constant) matches the period of the voltage command value Vref. The present invention can be implemented even when the switching cycle of the gate threshold value is an integral multiple of the cycle of the voltage command value Vref.

  In each embodiment, the control method for the representative one-phase bridge cell unit in the serial multiplex power converter has been described. For the remaining two-phase units, a gate signal is generated in the same manner. The only difference between the control methods in each phase is that the phase of the voltage command value Vref is shifted by 120 °.

1a to 1g Adder 2 Table 3a to 3h Subtractor 4a to 4h Comparator 5a to 5h Dead time processor

Claims (6)

A series multiple power converter that is configured by connecting a plurality of bridge cell units in series in each phase and interconnects with a three-phase AC system power supply,
For each unit, a pulse width modulation circuit that generates a gate signal of a switching element by comparing a voltage command value and two types of gate thresholds that take a constant value for at least one cycle of the voltage command value. Prepared,
The gate thresholds in each unit per phase all take different values,
Periodically switching the gate threshold,
The switching cycle of the gate threshold value is set to an integral multiple of the cycle of the voltage command value.   2. The serial multiplex power conversion device according to claim 1, wherein the gate threshold value is switched at a peak on the plus side of the voltage command value. A first unit and a second unit provided in each phase as the bridge cell;
The gate thresholds Vth1a and Vth1b of the first unit are values having the same absolute value and opposite signs,
The gate threshold values Vth2a and Vth2b of the second unit are values having the same absolute value and opposite signs,
3. The serial multiplex power converter according to claim 2, wherein the gate thresholds Vth1a, Vth1b, Vth2a, and Vth2b have a magnitude relationship shown in Table 1 below.

p: a value that gradually changes from 0 to 1 in the switching period of the gate threshold As the bridge cell, a first unit, a second unit, a third unit, and a fourth unit are provided in each phase,
The gate thresholds Vth1a and Vth1b of the first unit are values having the same absolute value and opposite signs, respectively.
The gate threshold values Vth2a and Vth2b of the second unit are values having the same absolute value and opposite signs,
The gate threshold values Vth3a and Vth3b of the third unit are values having the same absolute value and opposite signs, respectively.
The gate thresholds Vth4a and Vth4b of the fourth unit are values having the same absolute value and opposite signs,
3. The serial multiplex power converter according to claim 2, wherein the gate thresholds Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b have a magnitude relationship shown in Table 2 below.

p: a value that gradually changes from 0 to 1 in the switching period of the gate threshold As the bridge cell, a first unit, a second unit, a third unit, and a fourth unit are provided in each phase,
The gate thresholds Vth1a and Vth1b of the first unit have opposite signs.
The gate thresholds Vth2a and Vth2b of the second unit have opposite signs.
The gate thresholds Vth3a and Vth3b of the third unit have opposite signs.
The gate thresholds Vth4a and Vth4b of the fourth unit have opposite signs.
In all the input signals p, | Vth1a-Vth1b |, | Vth2a-Vth2b |, | Vth3a-Vth3b | and | Vth4a-Vth4b | 3. The serial multiplex power converter according to claim 2, wherein Vth4a and Vth4b have a magnitude relationship shown in Table 3 below.

p: a value that gradually changes from 0 to 1 in the switching period of the gate threshold A control method of a series multiplex power conversion device configured by connecting a plurality of bridge cell units in series in each phase and interconnecting with a three-phase AC system power supply,
For each of the units, a voltage command value and at least two types of gate thresholds that take a constant value during at least one cycle of the voltage command value are compared to generate a gate signal of a switching element,
The gate thresholds in each unit per phase all take different values,
Periodically switching the gate threshold,
A method for controlling a serial multiplex power converter, wherein a switching cycle of the gate threshold value is an integral multiple of a cycle of the voltage command value.

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