JP2019140858A - Serial multiple inverter device and control method therefor - Google Patents

Abstract

To provide a serial multiple inverter device, outputting a single-phase voltage of a high frequency, capable of making loss generated by each unit and/or each switching element.SOLUTION: A comparison is made between a voltage command value Vref and two types of gate threshold values Vth1a, Vth1b, Vth2a, Vth2b for taking a constant value at least during a half period of the voltage command value Vref for each of a first and a second units 11, 12 to generate a gate signal of a switching element. As all the gate threshold values Vth1a, Vth1b, Vth2a, Vth2b in the first and the second units 11, 12, different values from each other are taken and the gate threshold values Vth1a, Vth1b, Vth2a, Vth2b are periodically switched so that loss of each of the units and the switching elements are uniform.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a series multiple inverter device that outputs two or more single-phase inverter units in series and outputs a high-frequency single-phase voltage. In particular, the thermal duty due to loss is equalized by each unit and each switching element. Related to technology.

  In a high-frequency inverter device that outputs a single-phase voltage with an output frequency of 1 kHz or more, which is used for induction heating or the like, there may be a configuration in which single-phase inverters are connected in series as shown in FIG.

  Patent Document 1 discloses an example of a serial multiple inverter device in which two units of a single-phase inverter are connected in series to constitute one phase of a three-phase inverter. FIG. 13 shows the configuration of a series multiple inverter device in which two units of a single-phase inverter are connected in series.

  As a method for obtaining a gate signal (on / off signal) of each switching element of such a serial multiple inverter device, FIG. 4 of Patent Document 1 compares a plurality of carrier triangular waves having the same phase and different offsets with voltage command values. A method is disclosed.

  As shown in FIG. 14, there is also a method of obtaining a gate signal by comparing the voltage command value Vref with a fixed gate threshold instead of a carrier triangular wave. In the example of FIG. 14, the relationship between the fixed gate threshold values Vth1a, Vth1b, Vth2a, Vth2b and the gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, GY2 (that is, the on / off state of the switching element) is as follows. Assigned to.

  If Vref> Vth1a, switching element U1 is turned on, switching element X1 is turned off. If Vref <Vth1a, switching element U1 is turned off, and switching element X1 is turned on.

  If Vref> Vth2a, switching element U2 is turned on, switching element X2 is turned off. If Vref <Vth2a, switching element U2 is turned off, and switching element X2 is turned on.

  If Vref> Vth2b, switching element Y2 is turned on, switching element V2 is turned off, and if Vref <Vth2b, switching element Y2 is turned off, and switching element V2 is turned on.

  If Vref> Vth1b, switching element Y1 is turned on, switching element V1 is turned off, and if Vref <Vth1b, switching element Y1 is turned off, and switching element V1 is turned on.

  In addition, when each gate threshold value Vth1a, Vth1b, Vth2a, Vth2b and the voltage command value Vref are the same value, which of the two switching elements may be turned on and which may be turned off.

  By this operation, the waveforms of FIG. 14 are obtained as the output voltages Vo1 and Vo2 of the first and second units 11 and 12 and the total output voltage Vo. FIG. 14 shows a configuration in which two first and second units 11 and 12 of a single-phase inverter are connected in series. If a plurality of single-phase inverter units are connected in multiple and a plurality of gate thresholds are prepared, the total is close to a sine wave An output voltage Vo is obtained.

  In addition, since each switching element performs switching once at maximum for one period of the fundamental wave of the output voltage, switching loss can be reduced as compared with a method using a carrier triangular wave. This method is suitable for a high-frequency inverter device having a high output voltage frequency because the number of times of switching for one period of the fundamental wave of the output voltage may be small.

  However, the gate signal generation method shown in FIG. 14 and FIG. 4 of Patent Document 1 has a problem that the loss generated in each inverter unit varies greatly. For example, consider the case in FIG. 14 where the output current Io of each unit is in phase with the voltage command value Vref and has a power factor of 1. At this time, the turn-off current of the switching element U1 is always larger than the turn-off current of the switching element U2. The same applies to other switching elements, and the switching loss generated in the first unit 11 is larger than the switching loss generated in the second unit 12.

  As another example, in FIG. 15, the amplitude of the voltage command value Vref is smaller than the amplitude of FIG. 14, and the absolute value of the voltage command value Vref is smaller than the absolute values of the fixed gate threshold values Vth1a and Vth1b. At this time, the switching element X1 and the switching element Y1 are always ON and only conduction loss occurs. Switching element U1 and switching element V1 are always OFF, and the loss is zero.

  The switching elements U2, V2, X2, and Y2 generate both conduction loss and switching loss. However, since the switching elements X2 and Y2 are always turned on while the output voltage Vo2 is zero, the switching elements X2 and Y2 are on longer than the switching elements U2 and V2 are on, and the switching elements X2 and Y2 are on. The conduction loss generated in the above is also larger than that of the switching elements U2 and V2.

  In this way, when there is variation in the loss generated in each unit and each switching element, if cooling design is performed according to the unit switching element that maximizes the loss, the design becomes excessive for the unit with small loss, Cost and device volume increase. Further, if the cooling design is changed for each unit, the design takes time, and there is a problem that the mass production effect of the unit does not appear, the cost increases, and the assembly of the apparatus becomes complicated.

  Further, when the fluctuation of the output voltage amplitude frequently occurs, in the switching elements U1 and V1, the period in which the loss occurs and the period in which the loss does not occur alternately occur, and the temperature change increases. As a result, thermal fatigue occurs in the switching elements and units, and the life of the device is shortened.

  As a means for equalizing the thermal duty of each unit and each switching element, a method of periodically exchanging gate signals can be considered. Patent Document 1 is disclosed as an example of a method for exchanging gate signals.

JP 2000-324845 A

  In the method of Patent Document 1, there is a problem that the thermal duty of each unit and each switching element cannot be completely equalized depending on conditions. Examples thereof are shown in FIGS.

  FIG. 16 shows the result of generating a gate signal from the voltage command value Vref according to claim 3 of Patent Document 1. When the output voltage Vo1 of the first unit 11 is zero, there are a period in which the switching elements X1 and Y1 are turned ON and a period in which the switching elements U1 and V1 are turned OFF. As a result, the responsibility sharing of continuity loss is improved.

  Here, consider a case where the phase of the output current Io is slightly delayed from the phase of the voltage command value Vref as shown in FIG. At this time, since the turn-on current of the switching element V1 is positive, a switching loss occurs. However, the turn-on current of the switching element U1 is negative and no switching loss occurs due to the turn-on.

  In the second unit 12, the turn-off current of the switching element U2 is positive, the turn-off current of the switching element V2 is almost zero, and the switching loss of the turn-off is larger in the switching element U2. As described above, the switching loss generated in each switching element in the same unit varies.

  Further, when the output current Io flowing when the output voltage Vo1 of the first unit 11 and the output voltage Vo2 of the second unit 12 are negative is confirmed, the portion shown in black for the first unit 11 and the second unit 12 for the second unit 12 The location is indicated by hatching. In the first unit 11, a part of the current is positive and reactive power is generated. The active power corresponds to the shaded area.

  However, in the case of the second unit 12, all shaded portions are active power. This indicates that the duty of the active power is different between the first unit 11 and the second unit 12. For example, when a diode rectifier is used as the DC power supply, the conduction loss generated by the rectifier varies. Depending on the phase of the output current, the active power may be regenerated in some units, and in the diode rectifier, there is no destination for the regenerated active power, and the DC voltage of each unit may rise and the switching element may be damaged by overvoltage.

  As another example, FIG. 17 shows a result of generating a gate signal from a voltage command value Vref having an amplitude smaller than that in FIG. At this time, in the first unit 11, the ON time of the switching elements X1 and V1 is shorter than the ON time of the switching elements U1 and Y1. As a result, the conduction loss between the switching element X1 and the switching element V1 is reduced, resulting in variations in thermal duties.

  Further, as shown in FIG. 17, the output voltages Vo1 and Vo2 of the first and second units 11 and 12 do not match the width of the period for outputting the plus side and the width of the period for outputting the minus side. That is, a DC offset is superimposed on the output voltages Vo1 and Vo2 of the first and second units 11 and 12.

  For example, as shown in FIG. 18, when the DC power supply 13 of the first and second units 11 and 12 is shared and the AC output side is insulated and multiplexed by individual transformers Tr1 and Tr2, as shown in FIG. When the output voltages Vo1 and Vo2 are applied to the transformers Tr1 and Tr2, the transformers Tr1 and Tr2 are demagnetized, causing problems such as a significant decrease in the output voltage and breakage of the switching element due to a sudden increase in the inverter output current. Therefore, the gate signal of FIG. 17 is not suitable for the serial multiple inverter device having the transformers Tr1 and Tr2 as shown in FIG.

  As described above, in the serial multiple inverter device, it becomes a problem to make the loss generated in each unit and each switching element uniform.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is a series in which units of a plurality of single-phase inverters are connected in series to output a single-phase voltage having an output frequency of 1 kHz or more. In the multiple inverter device, for each unit, the voltage command value is compared with two kinds of gate threshold values that take a constant value for at least a half cycle of the voltage command value, and the gate signal of the switching element is obtained. A pulse width modulation circuit for generating, wherein the gate thresholds all take different values, the gate thresholds are periodically switched, and the switching period of the gate thresholds is an integral multiple of the period of the voltage command value. To do.

  As one aspect thereof, the gate threshold value is switched at the time of a positive peak of the voltage command value.

  Also, as one aspect thereof, the single-phase inverter includes a first unit and a second unit, and the gate threshold values Vth1a and Vth1b of the first unit are equal in value and opposite in sign, The gate threshold values Vth2a and Vth2b of the second unit are values having the same absolute value and opposite signs, and the gate threshold values Vth1a, Vth1b, Vth2a, and Vth2b have the magnitude relationship shown in Table 1 below. Features.

p: a value that gradually changes from 0 to 1 in the gate threshold switching cycle. Another aspect is characterized in that the gate threshold is switched at the negative peak of the voltage command value.

  Also, as one aspect thereof, the single-phase inverter includes a first unit and a second unit, and the gate threshold values Vth1a and Vth1b of the first unit are equal in value and opposite in sign. The gate threshold values Vth2a and Vth2b of the second unit have the same absolute value and opposite signs, and the gate threshold values Vth1a, Vth1b, Vth2a, and Vth2b have the magnitude relationship shown in Table 2 below. It is characterized by that.

p: a value that gradually changes from 0 to 1 in the gate threshold switching cycle In another aspect, the gate threshold switching timing is the output when the gate threshold before and after switching is a positive pattern. In the case of a pattern in which the gate threshold value other than the above is switched when the voltage command value is on the negative side peak, the voltage command value is on the positive side peak.

   Further, as one aspect thereof, the single-phase inverter includes a first unit and a second unit, and the gate threshold values Vth1a and Vth1b of the first unit have values opposite to each other, and the second unit The gate threshold values Vth2a and Vth2b have opposite signs, and the gate threshold values Vth1a, Vth1b, Vtb2a, and Vth2b have the magnitude relationship shown in Table 3 below.

p: a value that gradually changes from 0 to 1 in the gate threshold switching cycle As another aspect, the gate threshold switching timing is such that the gate threshold before switching is negative and is closest to zero. If it is other than the gate threshold, the voltage command value is at the positive peak, and if the gate threshold before switching is a positive value, the voltage command value is at the negative peak, and the gate threshold before switching is If the negative gate threshold value is closest to 0, the case where the voltage command value is at the positive peak and the negative peak are mixed.

   Further, as one aspect thereof, the single-phase inverter includes a first unit, a second unit, a third unit, and a fourth unit, and the gate threshold values Vth1a and Vth1b of the first unit have opposite signs. The gate threshold values Vth2a and Vth2b of the second unit have opposite signs, and the gate threshold values Vth3a and Vth3b of the third unit have opposite signs. The gate thresholds Vth4a and Vth4b of the fourth unit have opposite signs, and the gate thresholds Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b are shown in Table 4 below. It is characterized by large and small relationships.

p: a value that gradually changes from 0 to 1 in the gate threshold switching cycle As another aspect, the gate threshold switching timing is positive when the gate threshold before switching is positive and closest to 0. If the gate threshold value is other than the gate threshold, the voltage command value is at the negative peak, and if the gate threshold before switching is a negative value, the voltage command value is at the positive peak, and the gate threshold before switching is When the positive gate threshold value is closest to 0, the voltage command value has a positive peak time and a negative peak time.

  Further, as one aspect thereof, the single-phase inverter includes a first unit, a second unit, a third unit, and a fourth unit, and the gate threshold values Vth1a and Vth1b of the first unit have opposite signs. The gate threshold values Vth2a and Vth2b of the second unit have opposite signs, and the gate threshold values Vth3a and Vth3b of the third unit have opposite signs. The gate threshold values Vth4a and Vth4b of the fourth unit are opposite in sign, and the gate threshold values Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, Vth4b are shown in Table 5 below. It is characterized by large and small relationships.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle. Further, as one aspect thereof, a carrier triangular wave is superimposed on the gate threshold of each unit.

  According to the present invention, in the serial multiple inverter device, it is possible to make the loss generated in each unit and each switching element uniform.

1 is a block diagram showing a pulse width modulation circuit in Embodiment 1. FIG. 3 is a time chart illustrating an example of a gate threshold and each waveform in the first embodiment. 4 is a time chart showing another example of the gate threshold and each waveform in the first embodiment. The time chart which shows each waveform at the time of applying Embodiment 1 when the amplitude of a voltage command value is small. 10 is a time chart showing a gate threshold and each waveform in the second embodiment. The time chart which shows each waveform at the time of applying Embodiment 2 when the amplitude of a voltage command value is small. The circuit block diagram which shows the serial multiple inverter apparatus in Embodiment 3. FIG. FIG. 5 is a block diagram illustrating a pulse width modulation circuit according to a third embodiment. 10 is a time chart showing an example of a gate threshold and each waveform in Embodiment 3. 10 is a time chart showing another example of the gate threshold and each waveform in the third embodiment. FIG. 6 is a block diagram illustrating a pulse width modulation circuit according to a fourth embodiment. The time chart which shows the carrier triangular wave and voltage command value in Embodiment 4. The circuit block diagram which shows a serial multiple inverter apparatus. The time chart which shows an example of the gate threshold value and each waveform in a prior art. The time chart which shows an example of a gate threshold value and each waveform when the amplitude of a voltage command value is small in a prior art. The time chart which shows the gate threshold value and each waveform in a prior art. The time chart which shows a gate threshold value and each waveform when the amplitude of a voltage command value is small in a prior art. The circuit block diagram which shows the serial multiple inverter apparatus of the structure which insulated and multiplexed each unit with the transformer.

  Hereinafter, Embodiments 1 to 4 of the serial multiple inverter device according to the present invention will be described in detail with reference to FIGS.

[Embodiment 1]
In the first embodiment, a method for making the loss generated in each unit and each switching element uniform will be described using the series multiple inverter device shown in FIG. 13 as an example. First, the configuration of the series multiple inverter device shown in FIG. 13 will be described.

  As shown in FIG. 13, the series multiple inverter device according to the first embodiment includes two first units 11 and second units 12. In the first unit 11, switching elements U1, V1, X1, and Y1 are bridge-connected, and in the second unit 12, switching elements U2, V2, X2, and Y2 are bridge-connected.

  The common connection point of the switching elements V1, Y1 of the first unit 11 and the common connection point of the switching elements U2, X2 of the second unit 12 are connected. Thus, each unit has a single-phase inverter configuration.

  The output voltage Vo1 of the first unit 11 is between the common connection point of the switching elements U1 and X1 and the common connection point of the switching elements V1 and Y1, and the common connection point of the switching elements U2 and X2 is common to the switching elements V2 and Y2. The output voltage Vo2 of the second unit 12 is between the connection points. Further, a total output voltage Vo is defined between the common connection point of the switching elements U1 and X1 of the first unit 11 and the common connection point of the switching elements V2 and Y2 of the second unit 12.

  FIG. 1 shows a block diagram of a pulse width modulation circuit according to the first embodiment. The input signal p is a signal that gradually increases from 0 to 1 in the gate threshold switching cycle. The input signal p corresponds to the horizontal axis (time axis) of the waveform shown in FIG.

  The table 2 inputs the input signal p, refers to the gate threshold value Vth1a corresponding to the input signal p stored in advance, and outputs it.

  The adders 1a, 1b, and 1c add fixed offset values 1/2, 1/4, and 3/4 to the input signal p, respectively. Table 2 receives input signals p + 1/2, p + 1/4, and p + 3/4, refers to numerical values after the decimal point of the input signals p + 1/2, p + 1/4, and p + 3/4, and corresponding gate threshold values Vth1b and Vth2a. , Vth2b is output. The table 2 itself is the same as the table 2 for calculating the gate threshold Vth1a, and only the input signal is different from p, p + 1/2, p + 1/4, and p + 3/4.

  Vth1a and Vth1b are gate thresholds for the first unit 11. Vth2a and Vth2b are gate thresholds for the second unit 12.

  The voltage command value Vref may be obtained when a sine wave having a predetermined amplitude and frequency is given, or may be obtained by feedback control in which the output voltage and output current are in accordance with the command value.

  The subtractors 3a to 3d calculate differences between the voltage command value Vref and the gate threshold values Vth1a, Vth1b, Vth2a, and Vth2b, respectively.

  The comparators 4a to 4d receive the calculation results of the subtractors 3a to 3d and compare them with 0. However, the magnitude relationship is different between the comparators 4a and 4c and the comparators 4b and 4d.

  The comparator 4a outputs 1 when the operation result of the subtractor 3a is larger than 0, that is, when Vref> Vth1a, and outputs 0 when Vref ≦ Vth1a. The comparator 4b outputs 1 when the calculation result of the subtractor 3b is smaller than 0, that is, when Vref <Vth1b, and outputs 0 when Vref ≧ Vth1b. The comparator 4c outputs 1 when the calculation result of the subtractor 3c is larger than 0, that is, when Vref> Vth2a, and outputs 0 when Vref ≦ Vth2a. The comparator 4d outputs 1 when the calculation result of the subtractor 3d is smaller than 0, that is, when Vref <Vth2b, and outputs 0 when Vref ≧ Vth2b.

  The dead time processors 5a to 5d receive the outputs of the comparators 4a to 4d as input, and add dead time to generate gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, and GY2. Note that GU1, GX1, GV1, GY1, GU2, GX2, GV2, and GY2 are gate signals of the switching elements U1, X1, V1, Y1, U2, X2, V2, and Y2 in FIG.

  The contents of the table in the first embodiment are shown in FIGS. 2 and 3, the horizontal axis represents the input signal p, and the vertical axis represents the gate threshold value Vth. The gate threshold value Vth1a corresponding to the input signal p is indicated by a thick solid line, and the gate threshold value Vth1b corresponding to the input signal p + 0.5 is indicated by a broken line. Similarly, the gate threshold value Vth2a corresponding to the input signal p + 0.25 is indicated by a thick solid line, and the gate threshold value Vth2b corresponding to the input signal p + 0.75 is indicated by a broken line.

  2 and 3 indicate a range of 0 <p <1. Even when the input signal p is out of the range, if n is an integer, the waveform of the gate threshold value Vth has a periodicity that satisfies Vth (n + p) = Vth (p).

  2 and 3, there is a relationship of Vth1a = −Vth1b and Vth2a = −Vth2b.

  Table 1 below shows the relationship between the period of the voltage command value Vref and the magnitude of each gate threshold in FIG.

  As can be seen from FIG. 2 and Table 1, each gate threshold value takes a constant value for at least one cycle of the voltage command value Vref.

  In the first embodiment, the gate signals Vth1a, Vth1b, Vth2a, and Vth2b to be compared with the voltage command value Vref for generating the gate signal are periodically changed to switch the gate signal to that of another unit. The resulting loss is made uniform.

  FIG. 2 also shows the gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, GY2, and the output voltages Vo1, Vo2 of the units obtained by the first embodiment. When each gate signal is 1, the corresponding switching element is turned on. When each gate signal is 0, the corresponding switching element is turned off.

  Describe the equalization of duty of conduction loss. In FIG. 2, the magnitude relationship between the gate threshold value Vth1a and the gate threshold value Vth1b is periodically reversed. The ON periods of the switching elements X1 and Y1 are long at both ends of FIG. 2 where Vth1a> Vth1b, and the ON periods of the switching elements U1 and V1 are long near the center (p = 4/8) of FIG. 2 where Vth1a <Vth1b.

  In the average of eight periods of the fundamental wave, the ON times of all the switching elements are equal, thereby making it possible to align the conduction losses generated in the switching elements.

  Next, switching loss will be described. When attention is paid to the turn-on of the switching element U1, the turn-on when the output current Io is near the peak is four times, the turn-on when the output current Io is reduced to some extent is two times, and the turn-on near zero is two times.

  When the switching element Y2 is confirmed in the same manner, the turn-on is 4 times when the output current Io is near the peak, the turn-on is 2 when the output current Io is somewhat reduced, and the turn-on is near 2 when the output current Io is small. It can be seen that a current having the same magnitude as that of the switching element U1 is switched during the period. The same applies to all switching elements and also to turn-off.

  Since switching elements that switch in units of one period of the fundamental wave of the output voltage are replaced, it is possible to avoid that a specific switching element switches only at a specific phase. If the waveforms of the voltage command value Vref and the output current Io do not change, the switching loss can be made uniform with the arbitrary voltage command value Vref and the output current Io.

  In the first embodiment, as shown in FIG. 2, the loss generated in each switching element in any eight periods is equal, but if only one specific period is extracted, the loss of each switching element varies. However, the switching element and the cooling mechanism have a certain amount of heat capacity, and variations in temperature rise during one period of the fundamental wave are hardly generated because they are absorbed by this heat capacity.

  If the loss generated in the switching elements in a certain long period is made uniform, the temperature rise of each switching element can be made uniform, and the temperature pulsation can also be reduced.

  The first embodiment also has the effect of equalizing the active power duties of each unit. When the output voltages Vo1 and Vo2 are viewed, a narrow pulse width (shaded portion) and a wide pulse width (black portion) appear every two cycles.

  In a narrow pulse width, the polarities of the total output voltage Vo and the output current Io are equal, and only active power is output. In the wide pulse width, not only the active power (black portion) but also the reactive power (shaded portion) is output, and the output effective power is larger in the wide pulse width.

  For this reason, the active power duty varies in one specific cycle. However, since the pulse width of the voltage is periodically switched, the output power is also switched, and the active power duty of each unit can be made equal in an average of 8 periods.

  In general, in an inverter, a capacitor with a certain amount of capacitance is connected to the DC side in order to absorb switching surge and stabilize operation. Therefore, if the power pulsation has a short period, it can be absorbed by the capacitor. In the first embodiment, long-period power pulsations that cannot be absorbed by the capacitor can be suppressed. Thereby, the duty of the DC power input to each unit can be equalized.

  In the first embodiment, eight cycles of the voltage command value Vref are used as the gate threshold switching cycle, but this cycle can be changed. (However, the switching period of the gate threshold is an integral multiple of the period of the voltage command value Vref.) When the frequency of the voltage command value Vref is high and temperature pulsation is not a problem, or a DC capacitor with a sufficiently large capacity is connected to the inverter. In such a case, the gate threshold switching cycle may be lengthened.

  FIG. 4 shows a case where the first embodiment is applied when the amplitude of the voltage command value Vref is small. Unlike FIG. 17, no direct current offset occurs in the output voltages Vo1 and Vo2. Therefore, the first embodiment can be applied to a configuration in which the first and second units 11 and 12 are multiplexed by the transformers Tr1 and Tr2 as shown in FIG.

  Further, the first embodiment has a feature that the magnetic flux density of the transformers Tr1 and Tr2 in the configuration of FIG. 18 is reduced. The integration result ∫Vo1dt of the output voltage Vo1 is shown at the bottom of FIG. The integration result ∫Vo1dt swings equally between the plus side and the minus side and has a small absolute value. Since the integration result ∫Vo1dt is proportional to the magnetic flux density of the transformers Tr1 and Tr2, it indicates that the magnetic flux density of the transformers Tr1 and Tr2 is small. If the magnetic flux density is small, the transformers Tr1 and Tr2 are less likely to be demagnetized even if the core cross-sectional areas of the transformers Tr1 and Tr2 are reduced, and the cost, weight, and volume of the transformers Tr1 and Tr2 can be reduced.

  2 and 4, the gate threshold value is changed at the positive side peak of the voltage command value Vref. The gate threshold value may be changed at the negative peak of the voltage command value Vref. FIG. 3 is an example.

  In FIG. 3, the gate threshold values Vth1a = −Vth1b and Vth2a = −Vth2b. Table 2 below is a table showing the magnitude relationship between the cycle of the voltage command value Vref and each gate threshold value in FIG.

  As described above, according to the first embodiment, the loss generated in each unit and each switching element can be made uniform. As a result, the thermal design of the apparatus is facilitated, and the temperature of only a specific unit greatly fluctuates when the load fluctuates, so that thermal fatigue of the switching element and the unit can be suppressed.

  Thereby, the life of the inverter device can be extended. Furthermore, the loss leveling eliminates excessive design for low loss units, and it is possible to reduce the cost and size of the inverter device.

  Moreover, the active power duty of each unit can be made uniform. Further, since the output voltage Vo1 and Vo2 of each unit does not include a DC offset, the DC power supply 13 is shared as shown in FIG. 18 and the transformers Tr1 and Tr2 are connected to the AC side outputs of the first and second units 11 and 12. In the multiplexed configuration, the bias of the transformers Tr1 and Tr2 can be suppressed, and the cost and weight of the transformers Tr1 and Tr2 can be reduced.

[Embodiment 2]
FIG. 5 shows the state of each switching element and the output voltages Vo1 and Vo2 of each unit obtained by the second embodiment. The difference from FIG. 2 is only a partial difference in the input signal p when the gate threshold value changes.

  The second embodiment is different from the first embodiment in timing for changing the gate threshold. When both of the values before and after the change of the gate threshold value are positive, the gate threshold value is changed not at the positive peak of the voltage command value Vref but at the negative peak.

  In other cases, the gate threshold value is switched at the plus side peak of the voltage command value Vref.

  Table 3 below is a table showing the magnitude relationship between the cycle of the voltage command value Vref and each gate threshold value in FIG.

  As can be seen from FIG. 5 and Table 3, each gate threshold value takes a constant value for at least a half cycle of the voltage command value Vref.

  Compared with the first embodiment, the switching timing of each switching element and the output voltages Vo1 and Vo2 of the first and second units 11 and 12 are different, but the waveform of the total output voltage Vo is the same. Also in the second embodiment, the effects of equalizing the loss generated in each switching element and each unit and equalizing the unit output power can be obtained as in the first embodiment.

  The second embodiment has a feature that switching loss can be reduced as compared with the first embodiment when the amplitude of the voltage command value Vref is small. FIG. 6 shows the state of each switching element when the amplitude of the voltage command value Vref is small, and the output voltages Vo1 and Vo2 of the first and second units 11 and 12. In the first embodiment, as shown in FIG. 4, when the gate threshold value Vth is changed, the gate threshold value and the voltage command value Vref may cross each other (eg, point A).

  However, in the second embodiment, as shown in FIG. 6, when both the value before and after the change of the gate threshold is positive, the voltage command value Vref is changed at the negative peak, so the timing at which the gate threshold changes. Thus, the voltage command value Vref and the gate threshold do not intersect.

  In FIG. 6, it can be confirmed that the switching frequency of each switching element is reduced as compared with FIG. 4 times in FIG. 4 and 8 times in FIG. Since the switching loss decreases as the number of times of switching decreases, the second embodiment can improve the efficiency compared to the first embodiment.

  However, in the case where the first and second units 11 and 12 are multiplexed by the transformers Tr1 and Tr2 as shown in FIG. 18, the problem that the transformers Tr1 and Tr2 are more saturated in the second embodiment than in the first embodiment. There is. 6 shows the integration result ∫Vo1dt of the output voltage Vo1. Unlike FIG. 4, the integration result ∫Vo1dt fluctuates only to the negative side, and the absolute value is larger than that of FIG. This indicates that the magnetic flux density of the transformers Tr1 and Tr2 increases twice.

  In order to prevent the bias of the transformers Tr1 and Tr2, the core cross-sectional areas of the transformers Tr1 and Tr2 must be doubled compared to the first embodiment. However, if the configuration is such that the first and second units 11 and 12 are directly multiplex connected without using the transformers Tr1 and Tr2 as shown in FIG. 13, it can be applied without any problem, and the effect of reducing the switching loss can be obtained. It is done.

  As described above, according to the second embodiment, the same operational effects as those of the first embodiment can be obtained. In addition, since the number of times of switching does not increase even when the gate threshold value is switched, the switching loss can be reduced as compared with the first embodiment, and the life can be further extended. Furthermore, in the configuration in which the transformers Tr1 and Tr2 are not used, the cost and size of the inverter device can be reduced.

[Embodiment 3]
FIG. 7 shows a main circuit configuration diagram for one phase of the third embodiment. In the third embodiment, the first to fourth units 11 to 14 of the single-phase inverter are expanded to four multiple connections.

  FIG. 8 shows a control block diagram of the third embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.

  The adders 1d, 1e, 1f, and 1g add 1/8, 5/8, 3/8, and 7/8 to the input signal p, respectively. Table 2 inputs input signals p + 1/8, p + 5/8, p + 3/8, p + 7/8, and refers to the numerical values after the decimal point of input signals p + 1/8, p + 5/8, p + 3/8, p + 7/8. The corresponding gate threshold values Vth3a, Vth3b, Vth4a, Vth4b are output.

  The subtractors 3e to 3h calculate the difference between the voltage command value Vref and the gate threshold values Vth3a, Vth3b, Vth4a, Vth4b. The comparators 4e to 4h receive the calculation results of the subtractors 3e to 3h and compare them with 0. However, the magnitude relationship is different between the comparators 4e and 4g and the comparators 4f and 4h.

  The comparator 4e outputs 1 when the calculation result of the subtractor 3e is larger than 0, that is, when Vref> Vth3a, and outputs 0 when Vref ≦ Vth3a. The comparator 4f outputs 1 when the calculation result of the subtractor 3f is smaller than 0, that is, when Vref <Vth3b, and outputs 0 when Vref ≧ Vth3b. The comparator 4g outputs 1 when the calculation result of the subtractor 3g is larger than 0, that is, when Vref> Vth4a, and outputs 0 when Vref ≦ Vth4a. The comparator 4h outputs 1 when the calculation result of the subtractor 3h is smaller than 0, that is, when Vref <Vth4b, and outputs 0 when Vref ≧ Vth4b.

  The dead time processing units 5e to 5h receive the outputs of the comparators 4e to 4h and add the dead time to generate gate signals GU3, GX3, GV3, GY3, GU4, GX4, GV4, and GY4. Note that GU3, GX3, GV3, GY3, GU4, GX4, GV4, and GY4 are gate signals of the switching elements U3, X3, V3, Y3, U4, X4, V4, and Y4 in FIG.

  The contents of the table in the third embodiment are shown in FIGS. Since the number of units has increased to four, the gate threshold value Vth output takes eight values. These eight values are periodically switched according to the input signal p, and are output as gate threshold values Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, Vth4b.

  9 and 10, the gate threshold values Vth1a, Vth2a, Vth3a, and Vth4a are indicated by solid lines, and the gate threshold values Vth1b, Vth2b, Vth3b, and Vth4b are indicated by broken lines.

  In the third embodiment, the second embodiment is expanded to a four-multiplex connection of the first to fourth units 11-14. In the case of expansion, since the number of gate thresholds to be compared with the voltage command value Vref increases, it can be coped with by changing the table as shown in FIGS.

  Since the third embodiment has four multiplex connections, the gate threshold value is eight. 9 and 10 are examples of tables for periodically changing the eight gate threshold values. In FIG. 9 and FIG. 10, only the gate signals GU1, GX1, GV1, and GY1 of the first unit 11 are shown as representative gate signals.

  In the table of FIG. 9, if the sign of the gate threshold value Vth before switching is negative and other than the maximum negative value Vth−max, the gate threshold value Vth is switched at the timing of the positive peak of the voltage command value Vref. The maximum negative value Vth-max here is a negative gate threshold value closest to 0, as shown in FIG.

  If the sign of the gate threshold value Vth before switching is positive, the gate threshold value Vth is switched at the timing when the voltage command value Vref is at the negative peak.

  When the gate threshold Vth before switching is the maximum negative value Vth-max, the gate threshold Vth is switched at the timing of the positive peak of the voltage command value Vref, and the gate threshold Vth is switched at the timing of the negative peak of the voltage command value Vref. The case where the threshold value Vth is switched is mixed. An example is shown.

  At point A in FIG. 9, the gate threshold value Vth1a indicated by the thick line changes from Vth-max at the timing when the voltage command value Vref is at the plus side peak. At point B in FIG. 12, the gate threshold value Vth1a indicated by the thick line changes from Vth-max at the timing of the negative voltage command value Vref.

  Table 4 below is a table showing the relationship between the cycle of the voltage command value Vref and each gate threshold value in FIG.

  In the table of FIG. 10, if the sign of the gate threshold value Vth before switching is plus and other than the minimum plus value Vth + min, the gate threshold value Vth is switched at the timing when the voltage command value Vref is at the minus side peak. Here, the minimum positive value Vth + min is a positive gate threshold value closest to 0, as shown in FIG.

  If the sign of the gate threshold value Vth before switching is negative, the gate threshold value Vth is switched at the timing when the voltage command value Vref is at the plus side peak. When the gate threshold Vth before switching is the minimum positive value Vth + min, the gate threshold Vth is switched at the timing of the positive peak of the voltage command value Vref, and the gate threshold Vth at the timing of the negative peak of the voltage command value Vref. Are mixed with the case of switching.

  An example is shown. At point A in FIG. 10, the gate threshold value Vth1a indicated by the thick line changes from Vth + min at the timing of the negative peak value of the voltage command value Vref. At point B in FIG. 10, the gate threshold value Vth1a of the thick line changes from Vth + min at the timing of the voltage command value Vref at the plus side peak.

  Table 5 below is a table showing the magnitude relationship between the cycle of the voltage command value Vref and each gate threshold value in FIG.

  By this switching operation, switching is prevented from occurring by switching the gate threshold as in the second embodiment.

  In FIGS. 9 and 10, the gate threshold is partially changed by two stages when the gate threshold is switched (example: point C in FIG. 9). As a result, the interval at which the gate threshold is switched is basically maintained at one cycle of the voltage command value Vref as in the first and second embodiments, and the number of inverter units in series is doubled (2 series → 4 series). Even so, one cycle of the gate threshold can be suppressed to eight cycles of the voltage command value Vref.

  As an effect, it is possible to shorten the time required for one cycle of switching the gate threshold when the number of units is increased, and to reduce the variation in the temperature rise of each unit and each switching element. In addition, the fluctuation cycle of the output power duty of the unit can be shortened.

  However, the change in the output voltage pulse width at the time of switching the gate is larger than in the case of changing by one stage, and the transformer is likely to be demagnetized. In such a case, similarly to the first embodiment, it is possible to suppress the demagnetization by unifying the timing at which the gate threshold value Vth is switched at the plus side peak of the voltage command value Vref.

Although the third embodiment is a four-unit connection of units, the number of multiplexing can be increased by performing the same extension. When the multiplexing number is n, the offset value added to the lower left adder (1a to 1g in FIG. 8) is 1 / 2n, 2 / 2n,..., (2n-1) / 2n. (However, this is not the order.)
As described above, according to the third embodiment, the loss generated in each unit and each switching element can be made uniform.

  Further, according to the third embodiment, the cycle of the thermal duty fluctuation can be shortened, and the magnitude of the temperature fluctuation of each unit and each switching element can be reduced. For this reason, compared with Embodiment 1 and Embodiment 2, the effect which suppresses thermal fatigue is high and can further extend life.

[Embodiment 4]
FIG. 11 shows a control block of the fourth embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The carrier triangular wave generator 6 outputs a carrier triangular wave. The adders 7a to 7d add a carrier triangular wave to the gate threshold values Vth1a, Vth1b, Vth2a, and Vth2b output from the table 2. Outputs of the adders 7a to 7d are carrier triangular waves c1a, c1b, c2a, and c2b on which offsets are superimposed, and are input to subtracters 3a to 3d that calculate a difference from the voltage command value Vref.

  The table 2 of the fourth embodiment uses the same table as that of the first embodiment shown in FIG.

  The fourth embodiment uses a carrier triangular wave shown in Patent Document 1 instead of the fixed value shown in the first embodiment as a comparison signal for generating a gate signal.

In the fourth embodiment, the output voltage can be made closer to a sine wave as compared with the first to third embodiments, and the harmonic voltage can be suppressed. For this reason, it is not necessary to connect an LC filter for removing harmonics to the output of the series multiple inverter device of FIG. 13 or FIG. Alternatively, the LC filter can be downsized,
FIG. 12 shows the waveform of the carrier triangular wave c1a obtained in the fourth embodiment. By periodically switching the offset superimposed on the carrier triangular wave, the thermal duty of each unit and each switching element can be made equal as in the first embodiment.

  As described above, according to the fourth embodiment, when the gate signal is generated using the carrier triangular wave, the loss generated in each unit and each switching element can be made uniform, which is the same as in the first embodiment. An effect can be obtained.

  Further, in combination with the second embodiment, the offset to be superimposed can be changed to suppress an increase in the number of switching times. Further, a configuration in which three or more units in combination with the third embodiment are connected in series can be supported.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

Vref ... Voltage command value Vth1a to Vth4b ... Gate threshold value Vo1, Vo2 ... Output voltage Vo ... Total output voltage Io ... Output current

Claims (13)

A serial multiple inverter device configured by connecting a plurality of single-phase inverter units in series and outputting a single-phase voltage having an output frequency of 1 kHz or more,
A pulse width modulation circuit that generates a gate signal of a switching element by comparing a voltage command value with two types of gate threshold values that take a constant value for at least a half cycle of the voltage command value for each unit. Prepared,
The gate thresholds all take different values,
Periodically switching the gate threshold;
A switching circuit of the gate threshold value is an integer multiple of the period of the voltage command value.   2. The serial multiple inverter device according to claim 1, wherein the gate threshold value is switched at a plus-side peak of the voltage command value. The single-phase inverter includes a first unit and a second unit,
The gate threshold values Vth1a and Vth1b of the first unit are equal in absolute value and opposite in sign,
The gate threshold values Vth2a and Vth2b of the second unit are equal in absolute value and opposite in sign,
3. The serial multiple inverter device according to claim 2, wherein the gate threshold values Vth1a, Vth1b, Vth2a, and Vth2b have a magnitude relationship shown in Table 1 below.

p: Value that gradually changes from 0 to 1 in the gate threshold switching cycle   2. The serial multiple inverter device according to claim 1, wherein the gate threshold value is switched at a negative peak of the voltage command value. The single-phase inverter includes a first unit and a second unit,
The gate threshold values Vth1a and Vth1b of the first unit are equal in absolute value and opposite in sign,
The gate threshold values Vth2a and Vth2b of the second unit are equal in absolute value and opposite in sign,
5. The series multiple inverter device according to claim 4, wherein the gate threshold values Vth1a, Vth1b, Vth2a, and Vth2b have a magnitude relationship shown in Table 2 below.

p: Value that gradually changes from 0 to 1 in the gate threshold switching cycle The timing of switching the gate threshold is as follows:
In the case where the gate threshold value before and after the change is both positive, the negative peak of the output voltage command value,
2. The series multiple inverter device according to claim 1, wherein, in the case of a pattern for switching the gate threshold other than the above, the voltage command value is at a plus-side peak. The single-phase inverter includes a first unit and a second unit,
The gate threshold values Vth1a and Vth1b of the first unit are opposite to each other in sign.
The gate threshold values Vth2a and Vth2b of the second unit have opposite signs.
7. The serial multiple inverter device according to claim 6, wherein the gate threshold values Vth1a, Vth1b, Vtb2a, and Vth2b have a magnitude relationship as shown in Table 3 below.

p: Value that gradually changes from 0 to 1 in the gate threshold switching cycle The timing of switching the gate threshold is as follows:
If the gate threshold before switching is negative and other than the negative negative gate threshold closest to 0, the voltage command value is at the positive peak time,
If the gate threshold before switching is a positive value, the voltage command value at the negative peak,
The case where the voltage threshold value before the switching is a negative gate threshold value closest to 0 is mixed with the case where the voltage command value is at the positive peak and the negative peak. The serial multiple inverter device described. The single-phase inverter includes a first unit, a second unit, a third unit, and a fourth unit,
The gate threshold values Vth1a and Vth1b of the first unit are opposite to each other in sign.
The gate threshold values Vth2a and Vth2b of the second unit have opposite signs.
The gate threshold values Vth3a and Vth3b of the third unit are opposite in sign.
The gate threshold values Vth4a and Vth4b of the fourth unit have opposite signs.
9. The serial multiple inverter device according to claim 8, wherein the gate threshold values Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b have a magnitude relationship shown in Table 4 below.

p: Value that gradually changes from 0 to 1 in the gate threshold switching cycle The timing of switching the gate threshold is as follows:
If the gate threshold before switching is positive and other than the positive gate threshold closest to 0, the voltage command value is at the negative peak,
If the gate threshold before switching is a negative value, the voltage command value is at the positive peak,
When the gate threshold value before switching is a positive gate threshold value closest to 0, there are a mixture of cases where the voltage command value is set to a positive peak time and a negative peak value. Item 2. The serial multiple inverter device according to Item 1. The single-phase inverter includes a first unit, a second unit, a third unit, and a fourth unit,
The gate threshold values Vth1a and Vth1b of the first unit are opposite to each other in sign.
The gate threshold values Vth2a and Vth2b of the second unit have opposite signs.
The gate threshold values Vth3a and Vth3b of the third unit are opposite in sign.
The gate threshold values Vth4a and Vth4b of the fourth unit have opposite signs.
11. The serial multiple inverter device according to claim 10, wherein the gate threshold values Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b have a magnitude relationship shown in Table 5 below.

p: Value that gradually changes from 0 to 1 in the gate threshold switching cycle   The serial multiple inverter device according to claim 1, wherein a carrier triangular wave is superimposed on the gate threshold value of each unit. A control method for a serial multiple inverter device configured by connecting a plurality of single-phase inverter units in series and outputting a single-phase voltage having an output frequency of 1 kHz or more,
For each unit, the voltage command value is compared with two types of gate thresholds that take a constant value for at least a half cycle of the voltage command value, and a gate signal of the switching element is generated,
The gate thresholds all take different values,
Periodically switching the gate threshold;
The switching method of the gate threshold value is an integer multiple of the cycle of the voltage command value.

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