JP2013090358A - Series multiplex inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a series multiplex inverter device which can shorten the data transmission time between a detection unit for detecting the system voltage and a control unit for controlling the forward conversion unit of a single phase inverter unit, and can correct the delay time and the phase difference.SOLUTION: In the series multiplex inverter device, a forward conversion unit of each single phase inverter unit 1 performs 120° conduction control, and includes a master controller 5 and a slave controller 8. The master controller includes a system voltage detection unit 6 and a system voltage phase synchronization determination unit 7 connected to the AC input side of the forward conversion unit of each single phase inverter unit, and generates a synchronization signal synchronized with the system voltage phase. The synchronization signal generated in the master controller is transmitted to the slave controller, which generates a signal of 120° conduction width synchronized with the system voltage based on the synchronization signal thus transmitted, and controls switching operation of the forward conversion unit of each single phase inverter unit.

Description

  The present invention relates to a serial multiple inverter device in which a plurality of single-phase inverter units are connected in series, and more particularly to a serial multiple inverter device that enables regenerative control.

  In general, when an AC motor is controlled by directly receiving high voltage power such as 3.3 kV, 6.6 kV, 10 kV, etc., a series multiple inverter device is used. The conventional example of the series multiple inverter device is introduced mainly in a field where there is no sudden change in load such as a fan and a pump and a regenerative function is not required. However, in recent years, due to demands such as expansion of applications of high-voltage motors, it has been required to add a regenerative function to the serial multiple inverter device.

  In order to respond to this requirement, a serial multiple inverter device shown in FIG. 7 in which the system voltage phase and the output voltage phase of the inverter in regenerative control are synchronized has been proposed (see, for example, Patent Document 1). The serial multiple inverter device described in Patent Document 1 includes an input transformer Tr configured by a three-phase transformer with multiple windings, and performs insulation and step-down of the system voltage with the input transformer Tr. The U-phase, V-phase, and W-phase that have been stepped down by the input transformer Tr are respectively input to single-phase inverter units U1 'to U6', V1 'to V6', and W1 'to W6' for each phase.

The U-phase single-phase inverter units U1 ′ to U6 ′ are connected in series on the output side. One end on the output side of the single-phase inverter unit U1 ′ is grounded via a resistor, and the other end on the output side of the single-phase inverter unit U6 ′ is connected to the U-phase motor winding of the AC motor M.
Similarly, the output sides of the V-phase single-phase inverter units V1 ′ to V6 ′ are connected in series. One end on the output side of the single-phase inverter unit V1 ′ is grounded via a resistor, and the other end on the output side of the single-phase inverter unit V6 ′ is connected to the V-phase motor winding of the AC motor M.

Furthermore, the output sides of the W-phase single-phase inverter units W1 'to W6' are connected in series. One end on the output side of the single-phase inverter unit W1 ′ is grounded via a resistor, and the other end on the output side of the single-phase inverter unit W6 ′ is connected to the W-phase motor winding of the AC motor M.
The main circuit configuration of each single-phase inverter unit U1 'to U6', V1 'to V6' and W1 'to W6' is configured as shown in FIG. This main circuit configuration includes a forward conversion unit CV, a capacitor C connected to the output side thereof, and an inverse conversion unit IV.

  The forward conversion unit CV uses six IGBTs as switching elements, and 120 ° flow control is performed. The system voltage input to the forward conversion unit CV is detected by the voltage detection circuit 101, and the system voltage detected by the voltage detection circuit 101 is transmitted to the controller 102 common to each single-phase inverter unit. The controller 102 generates a gate signal for performing 120 ° conduction control synchronized with the system voltage phase based on the received voltage value, and outputs the gate signal to the IGBT of each forward conversion unit CV.

For this reason, when the AC motor M is in a regenerative state, the voltage generated in the AC motor M is once converted to DC through the diode of the inverse conversion unit IV and smoothed by the capacitor C, and then the voltage of the forward conversion unit CV. It is converted back to three-phase alternating current by the IGBT and regenerated to the alternating current power supply side.
In the main circuit configuration of the serial multiple inverter device, one voltage detection circuit 101 is shared by all single-phase inverter units, and a voltage value is sent from the voltage detection circuit to each single-phase inverter unit.

JP 2006-230027 A

Incidentally, in the conventional example described in Patent Document 1, the voltage value detected by the voltage detection circuit 101 is transmitted to the controller of each single-phase inverter unit. For this reason, there exists an unsolved subject that transmission time becomes long according to data amount.
In addition, since the voltage value is transmitted directly to the single-phase inverter unit, the system voltage phase and the synchronized gate signal are generated by the controller of each single-phase inverter unit using the “delay time of voltage detection circuit” and “ There is an unsolved problem that it is necessary to correct the “computation delay time of the CPU or the like”, resulting in a configuration with overlapping functions.

Furthermore, in order to synchronize the system voltage phase and the single-phase inverter unit, information on the phase difference or information on the input voltage phase is required, and the configuration described in Patent Document 1 cannot achieve synchronization. There are unresolved issues.
Therefore, the present invention has been made paying attention to the unsolved problems of the above-described conventional example, and data between the detection unit that detects the system voltage and the control unit that controls the forward conversion unit of the single-phase inverter unit. It is an object of the present invention to provide a serial multiple inverter device that can shorten the transmission time and correct the delay time and the phase difference.

  In order to achieve the above object, a first aspect of a series multiple inverter device according to the present invention is configured such that output sides of a plurality of single-phase inverter units having a forward conversion unit and an inverse conversion unit are connected in series, and each single-phase is connected. It is a serial multiple inverter device that inputs each AC power to the input side of the forward conversion unit of the inverter unit via an input transformer. In this series multiple inverter device, the forward conversion unit of each single-phase inverter unit performs 120 ° conduction control and includes a master control device and a slave control device. The master control device includes a system voltage detection unit and a system voltage phase synchronization determination unit connected to the AC input side of the forward conversion unit of each single-phase inverter unit, and generates a synchronization signal synchronized with the system voltage phase. The slave control device transmits the synchronization signal generated by the master control device, generates a signal having a 120 ° conduction width synchronized with a system voltage based on the transmitted synchronization signal, and generates each single-phase inverter. Controls the switching operation of the unit's forward converter.

  Moreover, the 2nd aspect of the serial multiple inverter apparatus which concerns on this invention connects the output side of the several single phase inverter unit which has a forward conversion part and an inverse conversion part in series, and the forward conversion part of each single phase inverter unit This is a serial multiple inverter device in which each AC power is input to the input side of each via an input transformer. This serial multiple inverter device includes one master control device and a plurality of slave control devices that individually control the single-phase inverter units. The master control device includes a system voltage detection unit that detects a system voltage on the system side of the input transformer and a system voltage phase synchronization determination unit, and generates a synchronization signal synchronized with the system voltage phase. The plurality of slave devices are individually input with the synchronization signals output from the master control device, generate 120 ° conduction width signals synchronized with the system voltage, and the forward conversion unit of each single-phase inverter unit. The switching operation is individually controlled.

In a third aspect of the serial multiple inverter device according to the present invention, the master device outputs a synchronization signal synchronized with the system voltage at a time point before a delay time such as a system voltage detection delay time or an operation delay time. Generate the system voltage phase and synchronize the output voltage phase of the single-phase inverter unit.
Moreover, the 4th aspect of the serial multiple inverter apparatus which concerns on this invention WHEREIN: When the said master control apparatus has a phase difference between the system voltage phase and the input voltage phase of the said single phase inverter unit, the said phase difference information is previously stored. The slave control device generates a 120 ° conduction width signal in which the phase difference is corrected with respect to the transmitted synchronization signal.

According to the present invention, the master control device includes the system voltage detection unit and the system voltage phase synchronization determination unit, and the synchronization signal generated by the system voltage phase synchronization determination unit is controlled to pass through the forward conversion unit of the single-phase inverter unit by 120 °. Since the signal is transmitted to the slave control device, the synchronization signal can be composed of 1 bit, for example, and the transmission time can be shortened.
As described above, since the synchronization signal is transmitted between the master control device and the slave control device, the output timing of the synchronization signal can be adjusted, and the delay time of the voltage detection circuit and the calculation delay time of the CPU can be adjusted. In addition, the phase difference between the system voltage phase and the input voltage phase of the single-phase inverter unit can be adjusted.

1 is a block diagram showing a first embodiment of a serial multiple inverter device according to the present invention. It is a time chart with which it uses for description of operation | movement of the 1st Embodiment of this invention. It is a block diagram which shows the 2nd Embodiment of this invention. It is a block diagram which shows the 3rd Embodiment of this invention. It is a time chart with which it uses for description of operation | movement of the 3rd Embodiment of this invention. It is a time chart with which it uses for description of the operation | movement of the 4th Embodiment of this invention. It is a block diagram which shows the conventional serial multiple inverter apparatus. It is a circuit diagram which shows the specific structure of the single phase inverter unit of FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a single-phase inverter unit applicable to the series multiple inverter device according to the present invention and its control circuit.
In the figure, 1 is a single-phase inverter unit. This single-phase inverter unit 1 constitutes the single-phase inverter units U1 ′ to U6 ′, V1 ′ to V6 ′ and W1 ′ to W6 ′ in FIG. 7 described above, and corresponds to FIG.

The single-phase inverter unit 1 is connected in parallel between a forward conversion unit 2 that converts three-phase alternating current into direct current, a capacitor 3 that smoothes the DC power output from the forward conversion unit 2, and both ends of the capacitor 3. The inverse conversion unit 4 is provided.
The forward conversion unit 2 includes six semiconductor switching elements Q1 to Q6 configured by, for example, IGBTs connected between the positive electrode side line Lp and the negative electrode side line Ln. Here, the semiconductor switching elements Q1 and Q2 are connected in series between the positive electrode side line Lp and the negative electrode side line Ln, and the series circuit of the semiconductor switching elements Q3 and Q4 and the series circuit of the semiconductor switching elements Q5 and Q6 are connected to the positive electrode side line. The semiconductor switching elements Q1 and Q2 are connected in parallel between Lp and the negative electrode side line Ln.

  In addition, the inverse conversion unit 4 includes four semiconductor switching elements Q7 to Q10 configured by, for example, IGBTs connected between the positive electrode side line Lp and the negative electrode side line Ln. Here, the semiconductor switching elements Q7 and Q8 are connected in series between the positive electrode side line Lp and the negative electrode side line Ln. The semiconductor switching elements Q9 and Q10 are also connected in series between the positive electrode side line Lp and the negative electrode side line Ln. Then, the other connection terminal of the semiconductor switching elements Q9 and Q10 is connected in series to the other output terminal of the single-phase inverter unit 1 on one side where the connection points of the semiconductor switching elements Q7 and Q8 are connected in series. It is connected to one output terminal of the single-phase inverter unit 1 on the side.

  A U-phase line Lu connected to the output side of the input transformer is connected to a connection point between the semiconductor switching elements Q1 and Q2 of the forward conversion unit 2. A V-phase line Lv connected to the output side of the input transformer is connected to a connection point between the semiconductor switching elements Q3 and Q4. Further, a W-phase line Lw connected to the output side of the input transformer is connected to a connection point between the semiconductor switching elements Q5 and Q6.

  Further, a U-phase line Lu, a V-phase line Lv, and a W-phase line Lw between the input transformer and the forward conversion unit 2 are connected to the master control device 5. The master controller 5 includes a system voltage detection unit 6 that detects a system voltage Vu of the U-phase line Lu, a system voltage Vv of the V-phase line Lv, and a system voltage Vw of the W-phase line Lw, and the system voltage detection unit 6 A system voltage phase synchronization determination unit 7 that generates a synchronization signal Sy based on the detected system voltages Vu, Vv, and Vw is provided.

Here, the system voltage phase synchronization determination unit 7 detects a zero cross point where the input system voltages Vu, Vv, and Vw are inverted from a negative value to a positive value. The synchronization signal Sy is output to the slave control device 8.
The slave control device 8 includes a 360 ° counter 9 that is reset to 0 ° at the rising edge of the synchronization signal Sy input from the master control device 5, and the above-described single control device 8 is based on the count value of the 360 ° counter 9. An individual gate signal is generated to control the semiconductor switching elements Q1 to Q6 of the forward conversion unit 2 of the phase inverter unit 1 through 120 °. That is, the slave control device 8 forms a U-phase gate signal that drives the gate of the semiconductor switching element Q1 that is turned on in the interval where the count value of the 360 ° counter 9 is 30 ° to 150 °.

  That is, the slave control device 8 forms a V-phase gate signal that drives the gate of the semiconductor switching element Q3 that is turned on in the interval where the count value of the 360 ° counter 9 is 150 ° to 270 °. Further, the slave control device 8 generates a W-phase gate signal that drives the gate of the semiconductor switching element Q5 that is turned on in the interval where the count value of the 360 ° counter 9 is 270 ° to 30 °.

  Similarly, the slave control device 8 generates an X-phase gate signal that drives the gate of the semiconductor switching element Q2 that is turned on in the interval where the count value of the 360 ° counter 9 is 210 ° to 330 °. In addition, the slave control device 8 generates a Y-phase gate signal that drives the gate of the semiconductor switching element Q4 that is turned on in the interval where the count value of the 360 ° counter 9 is 330 ° to 90 °. In addition, the slave control device 8 generates a Z-phase gate signal that drives the gate of the semiconductor switching element Q6 that is turned on in the interval where the count value of the 360 ° counter 9 is 90 ° to 210 °.

  Then, the U-phase, V-phase and W-phase gate signals generated by the slave control device 8 are supplied to the gates of the semiconductor switching elements Q1, Q3 and Q5 of the forward conversion unit 2 of the single-phase inverter unit 1. Similarly, the X-phase, Y-phase, and Z-phase gate signals generated by the slave control device 8 are supplied to the gates of the semiconductor switching elements Q2, Q4, and Q6 of the forward conversion unit 2 of the single-phase inverter unit 1.

Next, the operation of the above embodiment will be described with reference to the time chart shown in FIG.
Now, the U-phase system voltage Vu of the U-phase line Lu will be described as an example.
As shown in FIG. 2A, the U-phase system voltage Vu is a sine wave signal having a positive value between 0 ° and 180 ° and a negative value between 180 ° and 360 ° (0 °), for example. It becomes.
For this reason, when the U-phase system voltage Vu is detected by the system voltage detection unit 6 of the master controller 5, the U-phase system voltage Vu is supplied to the system voltage phase synchronization determination unit 7. For this reason, the system voltage phase synchronization determination unit 7 detects a point where the U-phase system voltage Vu is inverted from a negative value to a positive value, that is, a zero cross point, and as shown in FIG. A synchronization signal Sy that rises and continues in an on state for a relatively short period of time and then returns to an off state is generated.

  Then, the synchronization signal Sy generated by the system voltage phase synchronization determination unit 7 is transmitted to the slave control device 8. In the slave control device 8, the 360 ° counter 9 is reset to 0 ° at the rising edge of the synchronization signal Sy, and starts counting from 0 ° as shown in FIG. Therefore, the slave control device 8 generates a U-phase to Z-phase gate signal synchronized with the U-phase system voltage Vu shown in FIGS. 2 (d) to (i) according to the count value of the 360 ° counter 9. The generated U-phase, V-phase and W-phase gate signals are supplied to the gates of the semiconductor switching elements Q1, Q3 and Q5 of the forward conversion unit 2 of the single-phase inverter unit 1. The generated X-phase, Y-phase and Z-phase gate signals are supplied to the gates of the semiconductor switching elements Q2, Q4 and Q6 of the forward conversion unit 2 of the single-phase inverter unit 1. For this reason, the forward conversion unit 2 is controlled to conduct 120 ° in synchronization with the U-phase system voltage Vu, and converts the three-phase AC power into DC power.

Then, the DC power output from the forward conversion unit 2 is smoothed by the capacitor 3 and then supplied to the reverse conversion unit 4, whereby the connection point between the semiconductor switching elements Q 7 and Q 8 of the reverse conversion unit 4 and the semiconductor switching A single-phase alternating current that is phase-synchronized with the system voltage Vu is output between the connection points of the elements Q9 and Q10.
As described above, since the forward conversion unit 2 of the single-phase inverter unit 1 is controlled to flow 120 ° in synchronization with the U-phase system voltage Vu, it is generated in the motor M when the motor M is in a regenerative state. The voltage is once converted to direct current through the diode of the reverse conversion unit 4, smoothed by the capacitor 3, then reversely converted to three-phase alternating current by the semiconductor switching elements Q <b> 1 to Q <b> 6 of the forward conversion unit 2, and regenerated to the alternating current power supply side. The

  As described above, according to the first embodiment, the system voltage Vu to Vw supplied from the input transformer side to the single-phase inverter unit 1 is detected by the system voltage detection unit 6 of the master controller 5, and the detected system voltage is detected. Vu is supplied to the system voltage phase synchronization determination unit 7 to detect a zero cross point of the system voltage Vu and generate a synchronization signal Sy. Then, the generated synchronization signal Sy is supplied to the slave control device 8 to reset the 360 ° counter 9 to 0 °, thereby generating a U-phase to Z-phase gate signal synchronized with the system voltage Vu. Since the generated U-phase to Z-phase gate signal is supplied to the gates of the semiconductor switching elements Q1 to Q6 of the forward conversion unit 2 of the single-phase inverter unit 1, the forward conversion unit 2 is 120 with a gate signal phase-synchronized with the system voltage. ° Flow control can be performed.

  At this time, since the master control device 5 and the slave control device 8 are one-to-one, and transmission of signals between them is only a 1-bit synchronization signal Sy, the transmission time can be shortened and the phase of the system voltage can be reduced. It is possible to generate the gate drive signal in synchronization with the system voltage phase and accurately control the 120 ° conduction of the forward conversion unit 2 of the single-phase inverter unit 1.

Next, a second embodiment of the present invention will be described with reference to FIG.
In the second embodiment, no phase shift occurs in the system voltage from the input transformer Tr input to each single-phase inverter unit 1, so that a plurality of slave control devices 8 are synchronously controlled by one master control device 5. It is what you do.

  That is, in the second embodiment, as shown in FIG. 3, the system voltages Vu to Vw supplied from the system power source 10 are input to the common master controller 5 on the input side of the input transformer Tr. The master control device 5 includes a system voltage detection unit 6 and a system voltage phase synchronization determination unit 7 as in the first embodiment described above. And the synchronous signal Sy synchronized with the system voltage Vu-Vw output from the system voltage phase synchronization determination part 7 is each single-phase inverter unit U1-U3, V1-V3, and W1 connected to the output side of the input transformer Tr. To the slave control devices SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3 that individually control the forward conversion unit 2 of .about.W3.

  In the second embodiment, the slave signal for individually controlling the forward conversion units 2 of the single-phase inverter units U1 to U3, V1 to V3, and W1 to W3 with respect to the synchronization signal Sy output from the common master controller 5. Transmit to devices SCu1-SCu3, SCv1-SCv3, and SCw1-SCw3. For this reason, since the synchronization signal Sy transmitted from the master controller 5 to each of the slave controllers SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3 is only one bit, the transmission time is shortened as in the first embodiment described above. can do. Moreover, in the first embodiment described above, it is necessary to provide the same number of master control devices 5 as that of each single-phase inverter unit, but in the second embodiment, only one common master control device 5 needs to be provided. For this reason, in the second embodiment, the number of master control devices 5 can be reduced to reduce the cost, and the overall configuration can be reduced in size.

Next, a third embodiment of the present invention will be described with reference to FIG.
In the third embodiment, an accurate synchronization signal is generated in consideration of the delay time in the master control device.
That is, in the third embodiment, as shown in FIGS. 4 and 5, in the above-described second embodiment, the master controller 5 has the system voltage detection unit 6 and the system voltage detected by the system voltage detection unit 6. A synchronization signal generation unit 11 is provided that generates a synchronization signal in consideration of the delay time based on the above.

The synchronization signal generation unit 11 is generated by a delay time τd when the system voltage detection unit 6 of the master control device 5 detects the system voltage and a calculation delay time τc of a CPU included in the master control device 5. The synchronization signal Sy is generated earlier by τ. That is, since the delay time τ described above can be obtained at the design stage, the synchronization signal generator 11 generates the corrected synchronization signal Sya before the synchronization signal Sy by the delay time τ. Specifically, with reference to the voltage threshold Vth shown in the following equation (1), the correction synchronization signal Sya is generated at the moment when the voltage threshold Vth is exceeded from the state where the U-phase system voltage value is below.
Vth = −Vp × sin [{(τd + τc) / T} × 360 °] (1)
Here, Vp is a system voltage peak value [V], and T is a system period [s].

  According to the third embodiment, as shown in FIG. 5A, the synchronization signal generator 11 sets the voltage threshold Vth calculated by the above equation (1). In this state, the U-phase system voltage Vu detected by the system voltage detector 6 decreases toward the negative peak value, falls below the voltage threshold Vth at time t1, and then exceeds the negative peak value at time t2. When the voltage threshold value Vth is exceeded, a correction synchronization signal Sya is output at that moment as shown in FIG.

The correction synchronization signal Sya at this time is a system voltage detector for the synchronization signal Sy shown in FIG. 5B generated at time t3 when the U-phase system voltage Vu in the first embodiment is the zero cross point. 6 is generated earlier by a delay time τ obtained by adding the delay time τd at 6 and the operation delay time τc.
At this time, the detected voltage Vu detected by the system voltage detector 6 is delayed by a delay time τ with respect to the actual system voltage Vur shown by the dotted line as shown by the solid line in FIG. The signal Sya can be matched with the zero cross point of the actual system voltage Vur, and an accurate synchronization signal can be generated.

  Then, the generated correction synchronization signal Sya is transmitted to each of the slave control devices SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3. For this reason, based on this correction synchronizing signal Sya, each slave control device SCu1-SCu3, SCv1-SCv3 and SCw1-SCw3 uses U for the forward conversion unit 2 of each single-phase inverter unit U1-U3, V1-V3 and W1-W3. A phase-Z phase gate signal is generated. By these U-phase to Z-phase gate signals, the forward conversion units 2 of the single-phase inverter units U1 to U3, V1 to V3, and W1 to W3 are subjected to 120 ° flow control in phase synchronization with the actual system voltage.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
In the fourth embodiment, a case where a phase difference is generated in the input voltage phase input to the single-phase inverter unit 1 with respect to the system voltage is considered.
The phase difference Hd of the input voltage phase of the single-phase inverter unit 1 with respect to the system voltage phase can be obtained at the design stage of the main circuit of the single-phase inverter unit 1. For this reason, in the configuration of the second embodiment described above, the phase difference Hd of the input voltage phase of the single-phase inverter unit 1 with respect to the system voltage phase is set in the master controller 5 in advance. When the master control device 5 starts driving the serial multiple inverter device, the master control device 5 transmits the phase difference Hd to each of the slave control devices SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3 by serial transmission.

  When the slave controllers SCu1-SCu3, SCv1-SCv3, and SCw1-SCw3 receive the phase difference Hd from the master controller 5, the U-phase to Z-phase gate drive signals are compared with the count value of the built-in 360 ° counter 9. The value to be generated is corrected by the phase difference Hd. Thereby, a 120 ° gate drive signal synchronized with the input voltage phase of the single-phase inverter unit 1 can be generated.

Next, in the operation of the fourth embodiment, as shown in FIG. 6A, the input voltage Vui of the single-phase inverter unit 1 has a phase delay of 30 ° with respect to the U-phase system voltage Vu. The case will be described.
In this case, when driving the serial multiple inverter device is started, first, the phase difference Hd (= 30 °) is serially transmitted from the master control device 5 to each of the slave control devices SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3. Sent by. Therefore, in each of the slave control devices SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3, the value to be compared with the count value of the built-in 360 ° counter 9 is corrected by the phase difference Hd (= 30 °).

For this reason, when the U-phase system voltage Vu changes as shown by a solid line in FIG. 6A and reaches a zero crossing point that reverses from a negative value to a positive value at time t11, the master controller 5 changes to FIG. 6B. Is transmitted to each of the slave control devices SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3.
For this reason, in each of the slave control devices SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3, the 360 ° counter 9 is reset to 0 ° when the synchronization signal Sy is received, as in the second embodiment described above. The 360 ° counter 9 starts counting from 0 °.

At this time, in the above-described second embodiment, when the count value of the 360 ° counter 9 becomes 30 °, the U-phase gate signal is inverted to the ON state as shown in FIG. When the count value reaches 150 °, it returns to the off state.
However, in this embodiment, the value to be compared with the 360 ° counter 9 is corrected by the phase difference Hd (= 30 °), so that the count value of the 360 ° counter 9 is 60 as shown in FIG. The U-phase gate signal is inverted to the ON state at the time when the angle reaches °, and then returns to the OFF state when the count value reaches 180 °.

  Therefore, a U-phase gate signal whose phase is delayed by the phase difference Hd can be generated. Similarly, the V-phase to Z-phase gate signals can also be signals that are delayed in phase by the phase difference Hd. Since the U-phase to Z-phase gate signals whose phases are delayed are supplied to the semiconductor switching elements Q1 to Q6 of the forward converter 2 of each single-phase inverter unit 1, the forward converter 2 of each single-phase inverter unit 1 The 120 ° conduction control can be performed in synchronization with the input voltage Vui causing the phase delay.

In the fourth embodiment, the case where the phase difference Hd of the input voltage Vui of each single-phase inverter unit 1 is the same has been described. However, the present invention is not limited to this, and each single-phase inverter unit 1 When the phase difference Hd of the input voltage Vui is different, the master controller 5 sends individual phase differences Hd to the slave controllers SCu1 to SCu3, SCv1 to SCv3, and SCw1 to SCw3 at the start of driving of the serial multiple inverter device. You just have to do it.
Further, in the third and fourth embodiments, the case where the configuration of the second embodiment described above is applied has been described. However, the present invention is not limited to this, and the configuration of the first embodiment described above. It can also be applied to.

  DESCRIPTION OF SYMBOLS 1 ... Single phase inverter unit, 2 ... Forward conversion part, 3 ... Capacitor, 4 ... Inverse conversion part, 5 ... Master control apparatus, 6 ... System | strain phase voltage detection part, 7 ... System | strain voltage phase synchronization determination part, 8 ... Slave control Device: 9 ... 360 ° counter, SCu1-SCu3, SCv1-SCv3, SCw1-SCw ... Slave control device, 11 ... Synchronization signal generator

Claims (4)

The output side of a plurality of single-phase inverter units having a forward conversion unit and an inverse conversion unit are connected in series, and each AC power is input to the input side of the forward conversion unit of each single-phase inverter unit via an input transformer. A multiple inverter device,
The forward conversion part of each single-phase inverter unit performs 120 ° conduction control,
A master control device that includes a system voltage detection unit and a system voltage phase synchronization determination unit connected to the AC input side of the forward conversion unit of each single-phase inverter unit, and generates a synchronization signal synchronized with the system voltage phase;
The synchronization signal generated by the master control device is transmitted, a signal having a 120 ° conduction width synchronized with the system voltage is generated based on the transmitted synchronization signal, and the forward conversion unit of each single-phase inverter unit And a slave control device for controlling the switching operation of the serial multiple inverter device. The output side of a plurality of single-phase inverter units having a forward conversion unit and an inverse conversion unit are connected in series, and each AC power is input to the input side of the forward conversion unit of each single-phase inverter unit via an input transformer. A multiple inverter device,
A master control device that includes a system voltage detection unit that detects a system voltage on the system side of the input transformer and a system voltage phase synchronization determination unit, generates a synchronization signal synchronized with the system voltage phase, and is output from the master control device A plurality of slave devices that individually input the synchronization signal, generate a 120 ° conduction width signal synchronized with the system voltage, and individually control the switching operation of the forward conversion unit of each single-phase inverter unit; A serial multiple inverter device comprising:   The master device generates a synchronization signal synchronized with the system voltage at a time point before a delay time such as a system voltage detection delay time, an operation delay time, and the system voltage phase and an output voltage phase of the single-phase inverter unit. And the serial multiple inverter device according to claim 1, wherein   When the master control device has a phase difference between the system voltage phase and the input voltage phase of the single-phase inverter unit, the master control device transmits the phase difference information to the slave control device in advance, and the slave control device is transmitted 4. The serial multiple inverter device according to claim 1, wherein a 120 ° conduction width signal in which the phase difference is corrected with respect to the synchronization signal is generated. 5.

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