JP2011223667A - System interconnection inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system interconnection inverter which suppresses noise caused by resonance generated between an inter-winding capacitor of a common mode choke coil and a reactor of an output filter.SOLUTION: A system interconnection inverter 1 includes: a bypass line g of a common mode current which is formed by connecting a neutral point of a first capacitor set 41 arranged on an input side of the inverter 1 and a neutral point of a second capacitor set 42 arranged on an output side of the inverter 1; a common mode choke coil 3 which is provided between the first capacitor set and the second capacitor set and on the input side or the output side of the inverter and which suppresses a common mode current generated in the inverter; an output filter 2 comprising first reactors 21a, 21b and a third capacitor 22 which are for converting a pulse-width modulated voltage waveform outputted from the inverter into a sine-wave AC; and resonance suppression circuits 23, 24, and 25 which suppress resonance generated between the inter-winding capacitor of the common mode choke coil and the first reactors of the output filter.

Description

  The present invention relates to a grid-connected inverter that converts an output of a DC power source into AC and links it to an electric power system of an electric power company.

  In recent years, high-frequency switching has been progressing in grid-connected inverters that convert the output of a DC power source such as a photovoltaic power generation system or a fuel cell to AC and link it to the power system. Noise (EMI: Electro-Magnetic Interference) is a problem. Leakage current and EMI may affect the control of the inverter and other devices, and may cause the leakage breaker to malfunction. In Japan, the allowable amount of leakage current is regulated by the Electrical Appliance and Material Safety Law, and EMI is regulated by VCCI (Voluntary Control Council for Information Technology Equipment). In particular, regarding EMI, in recent years, movements to tighten regulations have been accelerating.

  In the photovoltaic power generation system, stray capacitance exists between the solar cell panel and the frame of the solar cell panel connected to the ground, which can be a path for high-frequency common mode noise. In general, an insulating layer made of a glass plate is formed on the surface of the solar cell panel. Since this glass plate has a large flat surface, when it gets wet with rain, the stray capacitance between the solar cell panel and the frame increases, and the high frequency common The mode current also increases. The fluctuation of the high-frequency voltage occurs when the inverter converts direct current into alternating current by switching the semiconductor element. For this reason, in the inverter, leakage current and high-frequency noise cannot be avoided.

  As a method for suppressing leakage current and high-frequency noise, there is a method of preventing a leakage current and high-frequency noise from flowing out by configuring a bypass path in the inverter that has a low impedance for the high-frequency common mode current as in Patent Document 1. .

  FIG. 9 is a configuration diagram showing a photovoltaic power generation system interconnection inverter as one of the grid interconnection inverters that constitute a high-frequency current bypass path. This photovoltaic power generation system interconnection inverter includes an inverter 1, an output filter 2, a common mode choke coil 3, a first capacitor pair 41, a second capacitor pair 42, a solar cell 5 and a system transformer 7 each composed of a semiconductor switching element. I have. The DC side neutral point c and the AC side neutral point f are connected by a bypass g. In FIG. 9, the common mode inductance of the common mode choke coil 3 is 31, the interwinding capacitance is 32, and the stray capacitance 6 existing between the solar cell 5 and the ground is shown as a capacitor 6a and a capacitor 6b. .

  The solar cell 5 generates a DC voltage. The DC voltage generated by the solar cell 5 is supplied to the inverter 1 via the common mode choke coil 3. The common mode choke coil 3 suppresses a common mode current flowing from the solar cell 5 to the inverter 1. The first capacitor pair 41 includes a capacitor 41a and a capacitor 41b, and is disposed between the positive terminal (point a) of the output of the solar cell 5 and the negative input terminal (point b). The second capacitor pair 42 includes a capacitor 42a and a capacitor 42b, and is disposed between the input terminal d and point e of the system transformer 7. The neutral point c of the first capacitor pair 41 and the neutral point f of the second capacitor pair 42 are connected by a bypass path g, and a bypass path having a low impedance for a high-frequency common mode current is configured. The inverter 1 performs pulse width modulation (PWM) on the DC voltage output from the solar cell 5. The output filter 2 includes reactors 21a and 21b and a capacitor 22, and converts the PWM voltage waveform output from the inverter 1 into a sinusoidal alternating current having the same frequency as the commercial frequency of the system.

  Since the bypass path g for the high-frequency common mode current is configured, and the current flowing through the bypass path g is suppressed by the common mode choke coil 3, the inverter 1 can be driven by a three-line PWM control system between lines. As shown in FIG. 10, the three-level PWM control between lines takes the output of three levels of −1, 0 and 1, so that the voltage amplitude is smaller than the two-level PWM control shown in FIG. The switching frequency is equivalently doubled by the number of times of switching. For this reason, the reactor 21 of the output filter 2 can be reduced in size, and loss can also be reduced. The three-level line-to-line PWM control has a problem that the common mode voltage fluctuates when outputting zero voltage, causing leakage current and noise, but as described above, a bypass path for high frequency common mode current is formed. By doing so, the above problem can be solved.

Japanese Patent Application No. 2008-289758

  However, in the photovoltaic power generation system interconnection inverter that constitutes the bypass path for the high-frequency common mode current described above, the voltage applied to the common mode choke coil 3 is large, and the number of turns of the common mode choke coil 3 is relatively large. The stray capacitance generated between the windings becomes large. FIG. 12 is a diagram illustrating a resonance route generated in the inter-winding capacitance of the common mode choke coil 3 and the reactor of the output filter 2. FIG. 13 is an equivalent circuit in which the common mode choke coil 3, the inverter 1, the output filter 2, and the capacitor pair 4 are viewed from the common mode.

  As shown in FIG. 12B, the common mode choke coil 3 has a winding 30b and a winding 30c wound around a core 30a constituting a closed magnetic circuit, and the winding 30b and the winding 30c are magnetically coupled. is doing. Each of the windings 30b and 30c has an inter-winding capacitance 32. For this reason, the common mode choke coil 3 is represented as if the common mode inductance 31 and the interwinding capacitance 32 are connected in parallel, as shown in FIGS.

  The reactors 21a and 21b of the output filter 2 are normal mode reactors, but when viewed from the common mode, the reactors 21a and 21b are connected in parallel. As shown in FIG. 12, when the bypass path g, which is a connection between the first capacitor pair 41a, 41b, the second capacitor pair 42a, 42b, and the neutral point thereof, is viewed from the common mode, as shown in FIG. , Represented by the connection between the input and output of the inverter by the capacitor 4.

  At a frequency equal to or higher than the resonance frequency of the common mode inductance 31 and the interwinding capacitor 32, the impedance of the interwinding capacitor 32 is smaller than the impedance of the common mode inductance 31. For this reason, resonance in the common mode occurs between the interwinding capacitor 32 and the reactor 21 of the output filter 2. This resonance passes through the bypass path g constituted by the capacitor pairs 41a, 41b, 42a, and 42b. Since the resonance power is relatively large, noise increases.

  The subject of this invention is providing the grid connection inverter which suppresses the noise resulting from the resonance which generate | occur | produces between the capacity | capacitance between windings of a common mode choke coil, and the reactor of an output filter.

  In order to solve the above-described problems, the present invention provides a single-phase or three-phase inverter that performs pulse width modulation on the output of a DC power source, and is arranged on the input side of the inverter and connected in series so as to form a neutral point. A first capacitor set consisting of the first capacitors, a second capacitor set consisting of the second capacitors arranged in series on the output side of the inverter and connected in series so as to form a neutral point, Between the first capacitor set and the second capacitor set, and on the input side or output side of the inverter, and the common mode current bypass path formed by connecting the neutral point and the neutral point of the second capacitor set. One or more common mode choke coils that are provided to suppress the common mode current generated by the inverter, and a pulse width modulated voltage waveform output from the inverter is a sinusoidal single waveform. Or, the resonance generated between the output filter composed of the first reactor and the third capacitor for converting to three-phase alternating current, the inter-winding capacitance of the common mode choke coil and the first reactor of the output filter is suppressed. And a resonance suppression circuit.

  According to the present invention, the resonance suppression circuit suppresses resonance that occurs between the inter-winding capacitance of the common mode choke coil and the first reactor of the output filter, and therefore can suppress noise caused by resonance. .

It is a block diagram which shows the structure of the grid connection inverter which concerns on Example 1 of this invention. It is a block diagram which shows the other structure of an output filter. It is a block diagram which shows the structure of a photovoltaic power system connection inverter as a three-phase system connection inverter. It is a block diagram which shows the structure of the grid connection inverter which concerns on Example 2 of this invention. It is a block diagram which shows the structure of the grid connection inverter which concerns on Example 3 of this invention. It is a block diagram which shows the structure of the grid connection inverter which concerns on Example 4 of this invention. It is a block diagram which shows the structure of the grid connection inverter which concerns on Example 5 of this invention. It is a block diagram which shows the structure of the grid connection inverter which concerns on Example 6 of this invention. It is a block diagram which shows the photovoltaic power system connection inverter as one of the system connection inverters which comprised the bypass path of the high frequency current. It is a figure which shows line 3 level PWM. It is a figure which shows 2 levels PWM between lines. It is a figure which shows the resonance route which generate | occur | produces in the capacity | capacitance between winding of a common mode choke coil, and the reactor of an output filter. This is an equivalent circuit of the common mode choke coil, inverter, output filter, and capacitor pair as seen from the common mode.

  Hereinafter, a grid interconnection inverter according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a grid interconnection inverter according to the present invention. The grid interconnection inverter which concerns on Example 1 is a single phase photovoltaic power generation grid interconnection inverter. In the following, the same or equivalent components as those of the grid interconnection inverter shown in FIG. 9 described in the background art will be described with the same reference numerals used in FIG. .

  This solar power generation system interconnection inverter includes an inverter 1, an output filter 2, a damping resistor 23, a capacitor 24, a transformer 25, a common mode choke coil 3, a first capacitor pair 41, a second capacitor pair 42, a solar cell 5, and a system. A transformer 7 and a DC line capacitor 8 are provided. In FIG. 1, the stray capacitance 6 existing between the solar cell 5 and the ground is shown as capacitors 6 a and 6 b, the common mode inductance of the common mode choke coil is 31, and the interwinding capacitance of the common mode choke coil is 32. ing.

  The solar cell 5 generates a DC voltage and supplies power to the inverter 1 via the first capacitor pair 41, the common mode choke coil 3, and the DC line capacitor 8. The direct current power source of the present invention is not limited to a solar cell, and a fuel cell or other devices that generate direct current voltage can be used.

  The common mode choke coil 3 is provided on the output side of the first capacitor pair 41 and in the preceding stage of the inverter 1, and a common mode voltage generated due to switching of the switching element included in the inverter 1 is generated. Suppresses the common mode current that flows.

  The inverter 1 includes a bridge circuit made of a semiconductor element such as an FET or an IGBT (Insulated Gate Bipolar Transistor). The inverter 1 is driven by the line-to-line three-level PWM control method, and the DC voltage supplied from the solar cell 5 has an amplitude that changes from +1 to 0 or from 0 to −1 as shown in FIG. And converting the pulse width into a PWM voltage waveform having a pulse waveform whose pulse width changes in a sine wave shape and outputting the PWM waveform.

  The output filter 2 has an interphase connected between the output end of the first reactor 21a, the second reactor 21b, and the first reactor 21a whose input ends are connected to the output terminal of the inverter 1 and the output end of the second reactor 21b. It is composed of a capacitor 22 (corresponding to a third capacitor). The output filter 2 converts the PWM wave output from the inverter 1 into a sine wave voltage waveform as indicated by a broken line in FIG.

  The first capacitor pair 41 is configured by connecting a capacitor 41 a and a capacitor 41 b in series, and is between the solar cell 5 and the common mode choke coil 3, and is an output terminal on the positive side of the common mode choke coil 3. It is arranged between (point a) and the output terminal (point b) on the negative electrode side. A DC line positive voltage appears at point a, and a DC line negative voltage appears at point b. A DC line neutral point c is formed at a connection point between the capacitor 41a and the capacitor 41b. The DC line neutral point c is neutralized by the neutral point connection line g. Connected to point f.

  The second capacitor pair 42 is configured by connecting a capacitor 42 a and a capacitor 42 b in series, and is disposed between the output terminals (point d, point e) of the output filter 2. A sine wave AC (AC output voltage) appears between points d and e. An AC output neutral point f is formed at the connection point between the capacitor 42a and the capacitor 42b, and the AC output neutral point f is connected to the DC line neutral point by the neutral point connection line g as described above. connected to c. This neutral point connection line g serves as a bypass for common mode current (leakage current).

  The system transformer 7 transforms the sine wave alternating current output from the system interconnection inverter and outputs it from the power system end h for connection to the power system. The neutral point of the system transformer 7 is connected to the ground by a neutral point ground line i.

  A damping resistor 23 (23a, 23b, corresponding to the first resistor) for suppressing resonance and a capacitor 24 (24a, 24b, corresponding to the fourth capacitor) are connected in series, and are connected to the reactor 21 (21a, 21b) of the output filter 2. Are connected in parallel. The series connection path of the damping resistor 23 and the capacitor 24 is coupled by a transformer 25 having a turns ratio of 1: 1. The transformer 25 exhibits an inductance and has a high impedance with respect to the normal mode, and with respect to the common mode. The magnetic flux cancels out and does not show an inductance. That is, the winding direction of the primary winding of the transformer 25 and the winding direction of the secondary winding are opposite, that is, the primary winding and the secondary winding are wound in opposite phases.

  In the grid-connected inverter configured as described above, a “leakage current (noise) path through which a high-frequency common mode current flows through a path such as the neutral point ground line i → the ground → the stray capacitance 6 of the solar battery 5 in the system transformer 7. Is formed. Further, a “bypass path” is also formed in which a high-frequency common mode current flows through a line such as the output of the inverter 1 → the second capacitor pair 42 → the neutral point connection line g → the first capacitor pair 41 → the input of the inverter 1. The high-frequency common mode current bypass path has an impedance sufficiently smaller than the leakage current path at the main frequency of the high-frequency leakage current (equal to the switching frequency of the inverter 1). Has a larger impedance than the bypass.

  Therefore, most of the high-frequency common mode current flows through a bypass having a low impedance, and the magnitude thereof is suppressed by the common mode choke coil 3. As a result, the high frequency common mode current flowing out of the grid interconnection inverter is suppressed.

  In the first embodiment, as shown in FIG. 13, a common mode resonance occurs between the interwinding capacitance 32 of the common mode choke coil and the reactor 21 of the output filter 2, and the resonance passes through the bypass path g. Since the resonance is attenuated by the resistor 23, the resonance is suppressed. In addition, since the capacitor 24 is connected in series to the damping resistor 23, the low frequency component current is cut off by the capacitor 24 and does not flow to the damping resistor 23. By setting the value of the capacitor 24 so as to cut off the current component below the resonance frequency, useless loss that occurs in the damping resistor 23 can be suppressed. The cut-off frequency is calculated from the resonance frequency by the reactor 21 and the capacitor 24.

  The transformer 25 has a high impedance for the normal mode and a low impedance for the common mode. For this reason, most of the current flowing through the damping resistor 23 is only the common mode component, and the damping resistor 23 can act only on the common mode. Since the normal mode current hardly flows to the damping resistor 23, it is possible to suppress useless loss that occurs in the damping resistor 23.

  In this way, by the action of the damping resistor 23 for suppressing resonance, the capacitor 24, and the transformer 25, between the interwinding capacitance 32 of the common mode choke coil 3 and the reactor 21 of the output filter 2 while minimizing the loss. Resonance generated in the above can be suppressed.

  In FIG. 1, the common mode choke coil 3 is arranged on the input side of the inverter 1. However, the common mode choke coil 3 may be arranged on the output side of the inverter 1. A plurality of both may be arranged. Further, when the winding resistance of the transformer 25 sufficiently acts as an attenuation component that suppresses resonance, the damping resistor 23 can be removed.

  In the first embodiment shown in FIG. 1, the output filter 2 is configured as shown in FIG. 2A. However, as shown in FIG. 2B, the primary winding and the secondary winding are magnetically connected. A combined reactor 26 may be used. In the common mode, the reactor 26 cancels out the magnetic flux and does not show the inductance, and in the normal mode, the magnetic flux is combined and shows the inductance. In this case, the common mode inductance of the reactor 26 does not exist. However, as shown in FIG. 2C, the reactor 26 has leakage inductances 27a and 27b. This causes resonance with the interwinding capacitor 32. The damping resistor 23, the capacitor 24, and the transformer 25 of the first embodiment also act on this resonance, and can suppress the resonance while minimizing the loss.

  The grid interconnection inverter according to the first embodiment is an example in which the present invention is applied to a single-phase grid interconnection inverter. However, the present invention can also be applied to a three-phase grid interconnection inverter.

  FIG. 3 is a block diagram showing a configuration of a photovoltaic power generation system interconnection inverter as a three-phase system interconnection inverter. This grid interconnection inverter is configured by changing the grid interconnection inverter according to the first embodiment described above as follows.

  That is, the first reactors 21a and 21b of the output filter 2 are replaced with the reactors 21u, 21v and 21w inserted in each phase, and the interphase capacitor 22 is replaced with three interphase capacitors 22a, 22b and 22c connecting the phases. The second capacitor pair 42 is configured to be replaced with three capacitors 42u, 42v and 42w to form a neutral point of each phase. The damping resistors 23a, 23b and the capacitors 24a, 24b are replaced with damping resistors 23u, 23v, 23w and capacitors 24u, 24v, 24w connected in parallel to the reactors 21u, 21v and 21w of each phase, and the transformer 25 is common. Transformers 25u, 25v, and 25w are connected so that the magnetic flux cancels out the mode and the impedance is lowered.

  One end of the primary side of the transformer 25u is connected to the reactor 21u, and the other end of the primary side of the transformer 25u is connected to the resistor 23u via the secondary side of the transformer 25w. One end of the primary side of the transformer 25v is connected to the reactor 21v, and the other end of the primary side of the transformer 25v is connected to the resistor 23v via the secondary side of the transformer 25u. One end of the primary side of the transformer 25w is connected to the reactor 21w, and the other end of the primary side of the transformer 25w is connected to the resistor 23w via the secondary side of the transformer 25v.

  In the embodiment, the booster circuit is not shown in the circuit, but an actual photovoltaic power generation system interconnection inverter often includes a booster circuit. The booster circuit is arranged on the input side of the DC line capacitor 8 in the first or second embodiment. When the booster circuit is disposed between the common mode choke coil 3 and the DC line capacitor 8, the leakage inductance of the common mode choke coil 3 can be used as a reactor of the booster circuit. The booster circuit boosts the output voltage of the solar cell 5 and sends it to the inverter 1 via the DC line capacitor 8. The present invention can suppress resonance while minimizing loss even in a grid-connected inverter having a booster circuit.

  FIG. 4 is a block diagram illustrating the configuration of the grid interconnection inverter according to the second embodiment of the present invention. This grid-connected inverter is configured by removing the capacitor 24 and the transformer 25 of the grid-connected inverter according to the first embodiment, and connecting only the damping resistor 23 to the reactor 21 in parallel.

  When loss of the damping resistor 23 does not become a problem, only the damping resistor 23 shown in the second embodiment is connected in parallel to the reactor 21, thereby reducing the number of parts and reducing the inter-winding capacitance of the common mode choke coil 3. It is possible to suppress the resonance that occurs between 32 and the reactor 21 of the output filter 2.

  In the grid-connected inverter according to the second embodiment, the common mode choke coil 3 may be arranged on the output side of the inverter 1 as in the grid-connected inverter according to the first embodiment. May be arranged on both the output side and the output side. Further, as the reactor of the output filter 2, a reactor 26 shown in FIG. 2B may be used. In addition, the present invention can be applied to a three-phase grid-connected inverter, and can also be applied to a grid-connected inverter including a booster circuit.

  FIG. 5 is a block diagram illustrating the configuration of the grid interconnection inverter according to the third embodiment of the present invention. This grid-connected inverter is configured by removing the transformer 25 of the grid-connected inverter according to the first embodiment and connecting a damping resistor 23, a capacitor 24, and a series circuit in parallel to the reactor 21.

  When the loss in the damping resistor 23 due to the normal mode current does not matter, only the damping resistor 23 and the capacitor 24 shown in the third embodiment are connected in parallel to the reactor 21, thereby reducing the number of components and reducing the common mode. Resonance generated between the interwinding capacitance 32 of the choke coil 3 and the reactor 21 of the output filter 2 can be suppressed.

  Further, in the grid-connected inverter according to the third embodiment, the common mode choke coil 3 may be disposed on the output side of the inverter 1 similarly to the grid-connected inverter according to the first or second embodiment. A plurality of them may be arranged on both the input side and the output side. Further, as the reactor of the output filter 2, a reactor 26 shown in FIG. 2B may be used. In addition, the present invention can be applied to a three-phase grid-connected inverter, and can also be applied to a grid-connected inverter including a booster circuit.

  FIG. 6 is a block diagram illustrating a configuration of a grid interconnection inverter according to the fourth embodiment of the present invention. This grid-connected inverter is configured by connecting a series circuit of a damping resistor 23 and a capacitor 24 of the grid-connected inverter according to the third embodiment in parallel to each phase of the common mode choke coil 3 instead of the reactor 21. Has been.

  Since resonance occurs between the interwinding capacitance 32 of the common mode choke coil 3 and the reactor 21 of the output filter 2, a damping resistor 23 is connected in parallel to each phase of the common mode choke coil 3. In addition, resonance that occurs between the interwinding capacitance 32 of the common mode choke coil 3 and the reactor 21 of the output filter 2 can be suppressed.

  FIG. 6 shows an example in which a series circuit of a damping resistor 23 and a capacitor 24 is connected in parallel to each phase of the common mode choke coil 3, but in the same way as the grid interconnection inverter according to the first embodiment shown in FIG. Alternatively, a transformer 25 may be added to the series circuit of the damping resistor 23 and the capacitor 24 so that only the common mode current flows through the damping resistor 23. When the winding resistance of the transformer 25 sufficiently acts as an attenuation component for suppressing resonance, the damping resistor 23 can be removed.

  Further, just like the grid-connected inverter according to the second embodiment, only the damping resistor 23 may be connected in parallel to each phase of the common mode choke coil 3.

  Further, in the grid-connected inverter according to the fourth embodiment, the common mode choke coil 3 may be arranged on the output side of the inverter 1 as in the grid-connected inverter according to the first to third embodiments. May be arranged on both the output side and the output side. Further, as the reactor of the output filter 2, a reactor 26 shown in FIG. 2B may be used. In addition, the present invention can be applied to a three-phase grid-connected inverter, and can also be applied to a grid-connected inverter including a booster circuit.

  FIG. 7 is a block diagram showing the configuration of the grid interconnection inverter according to the fifth embodiment of the present invention. This grid-connected inverter is configured by removing the damping resistor 23 of the grid-connected inverter according to the second embodiment and connecting a damping resistor 9 (corresponding to a second resistor) in series in the bypass path g. .

  Resonance occurs between the interwinding capacitance 32 of the common mode choke coil 3 and the reactor 21 of the output filter 2, and the resonance passes through the bypass g. For this reason, even if the damping resistor 9 is connected in series to the bypass path g, resonance that occurs between the interwinding capacitance 32 of the common mode choke coil 3 and the reactor 21 of the output filter 2 can be suppressed.

  Even if the damping resistor 9 is connected in series with each capacitor of the first capacitor pair 41 or the second capacitor pair 42 or both capacitor pairs, it is equivalent to providing the damping resistor 9 in the bypass path g.

  Further, in the grid-connected inverter according to the fifth embodiment, the common mode choke coil 3 may be disposed on the output side of the inverter 1 as in the grid-connected inverter according to the first to fourth embodiments. May be arranged on both the output side and the output side. Further, as the reactor of the output filter 2, a reactor 26 shown in FIG. 2B may be used. In addition, the present invention can be applied to a three-phase grid-connected inverter, and can also be applied to a grid-connected inverter including a booster circuit.

  FIG. 8 is a block diagram showing the configuration of the grid interconnection inverter according to the sixth embodiment of the present invention. This grid-connected inverter is configured by connecting a reactor 10 (corresponding to a second reactor) in parallel to a damping resistor 9 of the grid-connected inverter according to the fifth embodiment.

  If the damping resistor 9 is provided in the bypass path g, the damping resistor 9 acts as a resonance attenuation component, but the impedance of the bypass path g is increased, so that the action of bypassing the high-frequency common mode current is weakened.

  However, when the reactor 10 is connected in parallel to the damping resistor 9 provided in the bypass path g, the reactor 10 exhibits a low impedance for a low frequency and a high impedance for a high frequency. The magnitude of the impedance of g can be changed depending on the frequency.

  The main frequency of the high frequency common mode current passing through the bypass g is the switching frequency of the inverter 1. When this switching frequency is lower than the frequency of resonance that occurs between the interwinding capacitance 32 of the common mode choke coil 3 and the reactor 21 of the output filter 2, the common mode that passes through the bypass g at the switching frequency. Most of the current flows through the reactor 10 having a low impedance. At the resonance frequency, the impedance of the reactor 10 is high, and the damping effect of the damping resistor 9 can be applied to the resonance.

  In this way, by connecting the reactor 10 in parallel to the damping resistor 9 connected to the bypass path g, the interwinding capacitance 32 of the common mode choke coil 3 is not greatly impaired by the bypass action of the high frequency common mode current. And resonance between the reactor 21 of the output filter 2 can be suppressed.

  Moreover, the structure by the damping resistance 9 of the bypass path g of Example 5, or the structure by the damping resistance 9 and the reactor 10 of Example 6 can also be implemented in combination with the structure of Examples 1-4.

  Further, in the grid-connected inverter according to the sixth embodiment, the common mode choke coil 3 may be disposed on the output side of the inverter 1 similarly to the grid-connected inverter according to the first to fifth embodiments. May be arranged on both the output side and the output side. Further, as the reactor of the output filter 2, a reactor 26 shown in FIG. 2B may be used. In addition, the present invention can be applied to a three-phase grid-connected inverter, and can also be applied to a grid-connected inverter including a booster circuit.

  The present invention can be used as a grid interconnection inverter that connects a solar cell system or a fuel cell system to a power system.

DESCRIPTION OF SYMBOLS 1 ... Inverter 2 ... Output filter 3 ... Common mode choke coil 5 ... Solar cell 6 ... Stray capacity 7 ... System transformer 8 ... DC line capacitor 9 ... Damping resistor 10, 21 ... Reactor 22, 24, 41, 42 ... Capacitor 23 ... Damping resistor 25 · Transformer 31 · Common mode inductance 32 · Interwinding capacitance a · DC line positive voltage b · DC line negative voltage c · DC line neutral point d, e, j · AC output line f · AC side neutrality Point g ... Bypass path h ... Power system end i ... System transformer neutral ground wire

Claims (6)

A single-phase or three-phase inverter that performs pulse width modulation on the output of the DC power supply;
A first capacitor set comprising a first capacitor disposed on the input side of the inverter and connected in series to form a neutral point;
A second capacitor set comprising a second capacitor disposed on the output side of the inverter and connected in series to form a neutral point;
A bypass of a common mode current formed by connecting a neutral point of the first capacitor group and a neutral point of the second capacitor group;
One or more common mode choke coils provided between the first capacitor set and the second capacitor set and on the input side or output side of the inverter to suppress a common mode current generated in the inverter;
An output filter composed of a first reactor and a third capacitor for converting the pulse width modulated voltage waveform output from the inverter into a sinusoidal single-phase or three-phase alternating current;
A resonance suppression circuit for suppressing resonance generated between the interwinding capacitance of the common mode choke coil and the first reactor of the output filter;
A grid-connected inverter comprising:   The resonance suppression circuit includes a first resistor connected in parallel to a first reactor of each phase of the output filter or connected in parallel to windings at both ends of the common mode choke coil. Item 1. A grid-connected inverter according to item 1.   The resonance suppression circuit includes the first resistor and a fourth capacitor connected in parallel to a first reactor of each phase of the output filter or connected in parallel to windings at both ends of the common mode choke coil. The grid interconnection inverter according to claim 2, further comprising a series circuit. The resonance suppression circuit includes a winding connected in series in a path of a component connected in parallel to the first reactor of each phase of the output filter,
The winding of one phase and the winding of the other phase are magnetically coupled so as to have a low impedance with respect to the common mode and a high impedance with respect to the normal mode. The grid interconnection inverter according to any one of claims 1 to 3.   5. The grid interconnection inverter according to claim 1, wherein the resonance suppression circuit includes a second resistor in a bypass path of the common mode current. 6.   6. The grid interconnection inverter according to claim 5, wherein the resonance suppression circuit includes a second reactor connected in parallel with the second resistor provided in the common mode current bypass path.

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