JP2011188665A - Inverter control circuit and grid-connected inverter system equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter control circuit for generating a PWM signal so that an inverter circuit may stably continue operation even if a connected three-phase power system is in a voltage unbalance state. <P>SOLUTION: In the inverter control circuit 10 for PWM-controlling the inverter circuit 2, correction value signals ΔXu, ΔXv and ΔXw of the phases generated in a correction value generating part 11, are added to system command value signals Ku, Kv and Kw of the phases generated in a system command value generating part 12. Thus, command value signals Xu, Xv and Xw of the phases are generated. A PWM signal generating part 14 generates the PWM signals Pu, Pv and Pw of the phases, based on the command value signals of the phases. A system command value generating part 12 generates the system command value signals Ku, Kv and Kw from the system voltage signals Vs of the phases of the three-phase power system B, which are detected by a system voltage sensor 9. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention provides an inverter control circuit for PWM control of an inverter circuit that converts DC power to AC power, a grid-connected inverter system provided with the inverter control circuit, a program for realizing the inverter control circuit, and The present invention relates to a recording medium on which this program is recorded.

  In recent years, distributed power sources using natural energy such as sunlight have been in widespread use. A grid-connected inverter system that includes an inverter circuit that converts DC power generated by a distributed power source into AC power and supplies the converted AC power to a connected load or power system has also been developed. The grid-connected inverter system is provided with a function for detecting an overcurrent and stopping the inverter circuit in order to prevent damage to the inverter circuit due to an excessively large current (overcurrent) flowing.

  FIG. 10 is a block diagram for explaining a conventional grid-connected inverter system A ′ for supplying power to the three-phase power system B.

  In the grid-connected inverter system A ′, the inverter circuit 2 performs a power conversion operation based on the PWM signal input from the inverter control circuit 10 ′. The inverter control circuit 10 ′ receives the system voltage signal Vs (Vsu, Vsv, Vsw) and the alternating current signal I (Iu, Iv, Iw) from the system voltage sensor 9 and the current sensor 7, respectively. A PWM signal is generated. That is, the alternating current signal I input from the current sensor 7 is converted into each component of the rotating coordinate system. Hereinafter, the conversion is referred to as “dq conversion”, and the converted components are referred to as “d-axis component” and “q-axis component”. Correction values ΔXd and ΔXq for calculating the deviation amounts between the d-axis component Id and the q-axis component Iq after the dq conversion and the target values Id ′ and Iq ′ to “0” are calculated. Further, the system voltage signal Vs input from the system voltage sensor 9 is also dq converted to calculate the d-axis component Vsd and the q-axis component Vsq. Correction values ΔXd and ΔXq are added to the components Vsd and Vsq, respectively, and inversely transformed to a stationary coordinate system to calculate command values Xu, Xv, and Xw. Hereinafter, the inverse transformation is referred to as “inverse dq transformation”. A PWM signal is generated based on the command values Xu, Xv, and Xw subjected to inverse dq conversion.

JP 2004-153957 A

  Each dq conversion and inverse dq conversion perform conversion based on the phase θ of the system voltage detected from the system voltage signal Vs input from the system voltage sensor 9. At this time, the phase θ is a state in which the system voltage signals Vsu, Vsv, and Vsw of each phase are in an equilibrium state (a state in which the amplitude of the voltage of each phase is common and the phase difference of the voltage of each phase is 2π / 3, respectively). That is, it is detected on the assumption that the voltage of each phase of the three-phase power system B is in an equilibrium state. That is, the voltage phase of each phase of the three-phase power system B is not reflected in the d-axis component Vsd and q-axis component Vsq obtained by dq conversion of the system voltage signal Vs, but is a command calculated based on Vsd and Vsq. It is not reflected in the values Xu, Xv, and Xw.

  Therefore, when the voltages of the respective phases of the three-phase power system B are in an unbalanced state, the command values Xu, Xv, and Xw are obtained even though the voltage phases of the actual phases of the three-phase power system B are unbalanced. The voltage phase of each phase is calculated in an equilibrium state. Thereby, the control accuracy of the output current of the inverter circuit 2 is deteriorated, and the imbalance of the output current is increased. At this time, when an overcurrent is detected, the inverter circuit 2 is stopped, and the grid-connected inverter system A ′ is disconnected from the three-phase power system B. When the scale of the grid-connected inverter system A ′ is larger than that of the three-phase power system B, the grid-connected inverter system A ′ is disconnected from the three-phase power system B. There is a case where the equilibrium state expands or an instantaneous voltage drop occurs. In this case, there is a possibility that other grid-connected inverter systems connected to the three-phase power system B are also disconnected at the same time.

  The present invention has been conceived under the circumstances described above, and even when the connected three-phase power system is in a voltage unbalanced state, the inverter circuit can be stably operated. An object of the present invention is to provide an inverter control circuit that generates a PWM signal so as to be able to.

  In order to solve the above problems, the present invention takes the following technical means.

  An inverter control circuit provided by the first aspect of the present invention is an inverter control circuit for PWM control of an inverter circuit that converts DC power into AC power and outputs the AC power to a three-phase power system. Command value signal generating means for generating a command value signal of each phase for commanding a voltage of each phase to be output from the inverter circuit from each of the voltage signals of each phase of the three-phase power system detected by Correction value signal generating means for generating a correction value signal for each phase for controlling a measured value relating to input / output of the inverter circuit measured by a predetermined measuring means to a predetermined target value; and a command value for each phase A command value signal correcting unit that corrects the signal based on the correction value signal of each corresponding phase and outputs a corrected command value signal of each phase; and based on the corrected command value signal of each phase. There are, characterized in that it includes a PWM signal generating means for generating each phase of the PWM signal for PWM controlling said inverter circuit.

  In a preferred embodiment of the present invention, the command value signal correcting means corrects by adding the correction value signals of the phases respectively corresponding to the command value signals of the phases.

  In a preferred embodiment of the present invention, the command value signal generating means includes an effective value calculating means for calculating a voltage effective value of the voltage signal of each phase, and a phase of the voltage signal of each phase and a three-phase equilibrium time. From the phase difference detection means for detecting the phase difference with the phase of the phase, the voltage effective value of each phase calculated by the effective value calculation means and the phase difference of each phase detected by the phase difference detection means, Command value calculating means for calculating a command value for each phase, and outputting the command value for each phase calculated by the command value calculating means as a command value signal for each phase.

In a preferred embodiment of the present invention, the command value calculation means calculates each of the phase effective values Veu, Vev, Vew of the phases and the phase differences φu, φv, φw of the phases according to the following formulas. The phase command values Ku (t), Kv (t), Kw (t) are calculated. Ω is an angular frequency of the three-phase power system, ωt is a current phase of the U-phase system voltage, and Cm is a command value signal Ku (t), Kv (t), Kw at the three-phase equilibrium. (T) is an amplitude, Vin is a direct current voltage input to the inverter circuit, and Kt is a transformation ratio of a transformation means for transforming the output voltage of the inverter circuit.

  In a preferred embodiment of the present invention, the correction value signal generating means converts the output current signal of each phase of the inverter circuit detected by the current detecting means into each component of a rotating coordinate system; From a first correction value calculating means for calculating a first correction value for feedback control based on a deviation amount from the target value with respect to a measured value, and the first correction value for any one of the components And a second correction value calculating means for calculating a second correction value for feedback control based on the deviation amount, and reversely converting the second correction value into a correction value for each phase of the stationary coordinate system. Conversion means for outputting a correction value for each phase as a correction value signal for each phase.

  In a preferred embodiment of the present invention, the correction value signal generating means generates a correction value signal for controlling a DC voltage input to the inverter circuit to a predetermined target voltage.

  In a preferred embodiment of the present invention, the correction value signal generation means generates a correction value signal for controlling the reactive power output from the inverter circuit to a predetermined target reactive power.

  In a preferred embodiment of the present invention, the PWM signal generation means generates a PWM signal from a comparison result between the corrected command value signal and a triangular wave signal having a predetermined frequency.

  In a preferred embodiment of the present invention, a second command value of each phase for commanding a voltage of each phase to be output from the inverter circuit from any one of the voltage signals of each phase of the three-phase power system. A second command value signal generating means for generating a signal; and an unbalance detecting means for detecting that the voltage signal of each phase of the three-phase power system is in an unbalanced state, and the command value signal correcting means. While the unbalanced state is not detected by the unbalance detecting means, the second command value signal of each phase is corrected instead of the command value signal of each phase, and each phase is corrected. The corrected command value signal is generated.

  In a preferred embodiment of the present invention, a second command value of each phase for commanding a voltage of each phase to be output from the inverter circuit from any one of the voltage signals of each phase of the three-phase power system. A second command value signal generating means for generating a signal; and an unbalance detecting means for detecting that the voltage signal of each phase of the three-phase power system is in an unbalanced state, and the command value signal correcting means. Is a second command value signal for each phase instead of the command value signal for each phase when a state where the unbalanced state is not detected by the unbalance detection means continues for a predetermined time. Is corrected, and a corrected command value signal for each phase is generated.

  In a preferred embodiment of the present invention, the unbalance detection means has a predetermined difference between a voltage effective value of a voltage signal of any phase of the three-phase power system and a voltage effective value of a voltage signal of another phase. Or when the phase difference between the phase of the voltage signal of any phase of the three-phase power system and the phase at the three-phase equilibrium is equal to or greater than a predetermined phase difference. Detect that.

  The grid interconnection inverter system provided by the second aspect of the present invention includes the inverter circuit and the inverter control circuit provided by the first aspect of the present invention.

  A program provided by the third aspect of the present invention is a program for causing a computer to function as an inverter control circuit for PWM control of an inverter circuit that converts DC power into AC power and outputs the AC power to a three-phase power system. Each phase command for commanding a voltage of each phase to be output from the inverter circuit from each phase voltage signal of the three-phase power system detected by the voltage detection means. A command value signal generating means for generating a value signal, and a correction value for generating a correction value signal for each phase for controlling a measured value relating to input / output of the inverter circuit measured by the predetermined measuring means to a predetermined target value And correcting the command value signal of each phase based on the correction value signal of the corresponding phase, and generating the corrected command value signal of each phase. A command value signal correcting means for force, on the basis of the phase of the corrected command value signal, the inverter circuit to function as a PWM signal generating means for generating each phase of the PWM signal for PWM control.

  The recording medium provided by the fourth aspect of the present invention is a computer-readable recording medium that records the program provided by the third aspect of the present invention.

  According to the present invention, the command value signal for each phase is generated from each voltage signal for each phase of the three-phase power system. Therefore, even if the voltage of each phase of the three-phase power system is in an unbalanced state, the command value signal for each phase is generated based on the voltage signal of each phase in the unbalanced state. The voltage is also in an unbalanced state similar to the voltage of each phase of the three-phase power system. As a result, the control accuracy of the output current of the inverter circuit can be maintained, the increase in output current imbalance can be suppressed, and the detection of overcurrent can be suppressed. Therefore, even when the connected three-phase power system is in a voltage unbalanced state, the inverter circuit can be stably operated.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a block diagram for demonstrating the grid connection inverter system provided with 1st Embodiment of the inverter control circuit which concerns on this invention. It is a block diagram for demonstrating the internal structure of the correction value production | generation part of the inverter control circuit which concerns on 1st Embodiment. It is a block diagram for demonstrating the internal structure of the system | strain command value generation part of the inverter control circuit which concerns on 1st Embodiment. It is a figure for demonstrating the phase difference detection method. It is a figure for demonstrating a triangular wave comparison method. It is a figure for showing the change of the output current of an inverter circuit in simulation. It is a block diagram for demonstrating the internal structure of the system | strain command value generation part of the inverter control circuit which concerns on 2nd Embodiment. It is a figure for demonstrating an example of the internal structure of an unbalanced voltage difference detection part. It is a figure for demonstrating an example of the internal structure of an unbalanced phase difference detection part. It is a block diagram for demonstrating the conventional grid connection inverter system.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, taking as an example a case where the inverter control circuit according to the present invention is used in a grid-connected inverter system.

  FIG. 1 is a block diagram for explaining a grid-connected inverter system including a first embodiment of an inverter control circuit according to the present invention.

  As shown in the figure, the grid-connected inverter system A includes a DC power source 1, an inverter circuit 2, a filter circuit 3, a transformer circuit 4, a switch 5, a DC voltage sensor 6, current sensors 7 and 8, and a system voltage sensor 9. , And an inverter control circuit 10.

  The DC power source 1 is connected to the inverter circuit 2. The inverter circuit 2, the filter circuit 3, and the transformer circuit 4 are connected in series to the output lines of the U-phase, V-phase, and W-phase output voltages in this order. It is connected to a power system B (hereinafter abbreviated as “system B”). The DC voltage sensor 6 is installed on a connection line between the DC power source 1 and the inverter circuit 2, and the current sensor 7 is installed on a connection line between the inverter circuit 2 and the filter circuit 3. The current sensor 8 is installed on a connection line between the transformer circuit 4 and the switch 5, and the system voltage sensor 9 is installed on a connection line between the switch 5 and the system B. The inverter control circuit 10 is connected to the inverter circuit 2. The grid interconnection inverter system A is linked to the grid B by the switch 5, converts the DC power output from the DC power supply 1 into AC power, and supplies the AC power to the grid B. In addition, the structure of the grid connection inverter system A is not restricted to this. For example, a sensor that is not necessary for controlling the inverter circuit 2 may not be provided, or a so-called transformerless system in which a DC / DC converter circuit is provided between the DC power source 1 and the inverter circuit 2 instead of the transformer circuit 4. It may be.

  The DC power source 1 outputs DC power and includes, for example, a solar battery. A solar cell generates direct-current power by converting solar energy into electrical energy. The DC power source 1 outputs the generated DC power to the inverter circuit 2. Note that the DC power source 1 is not limited to one that generates DC power from a solar cell. For example, the DC power source 1 may be a fuel cell, a storage battery, an electric double layer capacitor, a lithium ion battery, or AC power generated by a diesel engine generator, a micro gas turbine generator, a wind turbine generator, or the like. It may be a device that converts to DC power and outputs it.

  The inverter circuit 2 converts a DC voltage input from the DC power source 1 into an AC voltage and outputs the AC voltage to the filter circuit 3. The inverter circuit 2 is a three-phase inverter, and is a PWM control type inverter circuit including three sets of six switching elements (not shown). The inverter circuit 2 converts the DC voltage input from the DC power source 1 into an AC voltage by switching each switching element on and off based on the PWM signal input from the inverter control circuit 10.

  The filter circuit 3 removes high frequency components due to switching from the AC voltage input from the inverter circuit 2. The filter circuit 3 includes a low pass filter including a reactor and a capacitor. The AC voltage from which the high frequency component has been removed by the filter circuit 3 is output to the transformer circuit 4. The configuration of the filter circuit 3 is not limited to this, and any known filter circuit for removing high frequency components may be used. The transformer circuit 4 boosts or steps down the AC voltage output from the filter circuit 3 to a level substantially equal to the voltage of the system B (hereinafter referred to as “system voltage”).

  The switch 5 connects the system interconnection inverter system A and the system B or disconnects the connection. The switch 5 connects the grid-connected inverter system A and the system B when the grid-connected inverter system A can supply power to the system B. The switch 5 disconnects the connection between the grid-connected inverter system A and the system B when an abnormality such as a system fault occurs in the system B. Actually, when an abnormality occurs in the system B, the system interconnection inverter system A is disconnected from the system B by a circuit breaker (not shown). At this time, in order to prevent the grid-connected inverter system A from being in a single operation state, the switch 5 is used to disconnect a load (not shown) connected between the grid-connected inverter system A and the circuit breaker. Is released.

The DC voltage sensor 6 detects a DC voltage output from the DC power supply 1. The detected DC voltage signal Vin is input to the inverter control circuit 10. The current sensor 7 detects the alternating current of each phase output from the inverter circuit 2. The detected alternating current signal I ₁ (I ₁ u, I ₁ v, I ₁ w) is input to the inverter control circuit 10. The current sensor 8 detects an alternating current of each phase output from the transformer circuit 4 (that is, an output current of the grid interconnection inverter system A). The detected alternating current signal I ₂ (I ₂ u, I ₂ v, I ₂ w) is input to the inverter control circuit 10. The system voltage sensor 9 detects the system voltage of each phase of the system B. The detected system voltage signal Vs (Vsu, Vsv, Vsw) is input to the inverter control circuit 10. Note that the output voltage output by the grid interconnection inverter system A substantially matches the grid voltage.

The inverter control circuit 10 controls the inverter circuit 2. The inverter control circuit 10 includes a DC voltage signal Vin input from the DC voltage sensor 6, an AC current signal I ₁ input from the current sensor 7, an AC current signal I ₂ input from the current sensor 8, and a system voltage sensor. A PWM signal is generated based on the system voltage signal Vs input from 9 and output to the inverter circuit 2. The inverter control circuit 10 generates a command value signal for commanding the waveform of the output voltage output from the inverter circuit 2 based on a detection signal input from each sensor, and a pulse generated based on the command value signal The signal is output as a PWM signal. The inverter circuit 2 outputs an alternating voltage having a waveform corresponding to the command value signal by switching each switching element on and off based on the input PWM signal. The inverter control circuit 10 controls the output current by changing the waveform of the output voltage of the inverter circuit 2 by changing the waveform of the command value signal. Thereby, the inverter control circuit 10 performs various feedback controls.

  In the present embodiment, the inverter control circuit 10 includes DC voltage control (feedback control performed so that the input DC voltage becomes a preset voltage target value), reactive power control (target value for which output reactive power is preset). Feedback control performed so as to be “0”), and output current control (feedback control performed by dq-converting the output current of the inverter circuit 2 so that the d-axis component becomes a correction value for reactive power control, and q-axis Feedback control is performed so that the component becomes a correction value for DC voltage control. The control method performed by the inverter control circuit 10 is not limited to this. For example, output voltage control or active power control may be performed.

  The inverter control circuit 10 includes a correction value generation unit 11, a system command value generation unit 12, an addition unit 13, and a PWM signal generation unit 14.

The correction value generation unit 11 generates a correction value signal for correcting the system command value signal output from the system command value generation unit 12 described later. The correction value generator 11 receives the DC voltage signal Vin from the DC voltage sensor 6, the AC current signal I ₁ from the current sensor 7, and the AC current signal I ₂ from the current sensor 8, and the system voltage sensor 9. Is supplied with the system voltage signal Vs, and the correction value signals ΔXu, ΔXv, ΔXw are generated and output to the adder 13. The correction value signals ΔXu, ΔXv, ΔXw are correction value signals for setting the deviation between the detection value of each sensor and the target value to “0”.

  FIG. 2 is a block diagram for explaining the internal configuration of the correction value generation unit 11.

  The correction value generator 11 includes a phase detection circuit 111, a PI control circuit 112, a reactive power calculation circuit 113, a PI control circuit 114, a dq conversion circuit 115, a PI control circuit 116, a PI control circuit 117, an inverse dq conversion circuit 118, and An unbalanced current compensation circuit 119 is provided.

  The phase detection circuit 111 detects the phase θ of the system voltage from the system voltage signal Vs input from the system voltage sensor 9 and is, for example, a PLL (Phase-Locked Loop) circuit. The detected phase θ is output to the dq conversion circuit 115 and the inverse dq conversion circuit 118.

The PI control circuit 112 performs PI control based on a deviation between the DC voltage signal Vin input from the DC voltage sensor 6 and a preset target DC voltage Vin ^*, and outputs a correction value. The reactive power calculation circuit 113 calculates and outputs an output reactive power Q from the AC current signal I ₂ input from the current sensor 8 and the system voltage signal Vs input from the system voltage sensor 9. The PI control circuit 114 performs PI control based on a deviation between the output reactive power Q output from the reactive power calculation circuit 113 and a preset target reactive power Q ^*, and outputs a correction value.

The dq conversion circuit 115 performs dq conversion on the alternating current signal I ₁ input from the current sensor 7. The dq conversion circuit 115 receives the alternating current signal I ₁ from the current sensor 7 and the phase θ from the phase detection circuit 111. The dq conversion circuit 115 converts the three-phase alternating current signal I ₁ into a two-phase signal and converts it into a d-axis component Id that is a phase difference component with respect to the phase θ and a q-axis component Iq that is an in-phase component. Output.

  The PI control circuit 116 performs PI control based on the deviation between the correction value output from the PI control circuit 112 and the d-axis component Id output from the dq conversion circuit 115, and outputs a correction value ΔXd. The PI control circuit 117 performs PI control based on the deviation between the correction value output from the PI control circuit 114 and the q-axis component Iq output from the dq conversion circuit 115, and outputs a correction value ΔXq. The inverse dq conversion circuit 118 performs inverse dq conversion between the correction value ΔXd input from the PI control circuit 116 and the correction value ΔXq input from the PI control circuit 117. The inverse dq conversion circuit 118 receives the correction value ΔXd from the PI control circuit 116, receives the correction value ΔXq from the PI control circuit 117, and receives the phase θ from the phase detection circuit 111. The inverse dq conversion circuit 118 converts the d-axis component correction value ΔXd and the q-axis component correction value ΔXq into a two-phase correction value by inverse dq conversion, and then converts the correction value into a three-phase correction value. Output as value signals ΔXu, ΔXv, ΔXw.

The unbalanced current compensation circuit 119 is for compensating for the unbalanced current. The unbalanced current compensation circuit 119 calculates and outputs a correction value for setting the negative phase component of the alternating current signal I ₁ input from the current sensor 7 to “0”. The correction value output from the unbalanced current compensation circuit 119 is added to the correction value signals ΔXu, ΔXv, ΔXw. Since the unbalanced current compensation circuit 119 controls the negative phase component of the alternating current signal I ₁ to be “0”, the unbalanced current is instantaneously suppressed.

  Returning to FIG. 1, the system command value generation unit 12 receives the DC voltage signal Vin from the DC voltage sensor 6 and the system voltage signal Vs from the system voltage sensor 9, and receives the system command value signals Ku, Kv, Kw. Is output to the adder 13. The system command value signals Ku, Kv, Kw serve as a reference for the command value signal for commanding the waveform of the output voltage output from the inverter circuit 2, and the system command value signals Ku, Kv, Kw are the correction value signal ΔXu. , ΔXv, ΔXw, the command value signal is generated.

  FIG. 3 is a block diagram for explaining the internal configuration of the system command value generation unit 12.

  The system command value generation unit 12 is an effective value calculation unit 121u, 121v, 121w, filter unit 122u, 122v, 122w, phase difference detection unit 123u, 123v, 123w, filter unit 124u, 124v, 124w, U phase system command value calculation. Unit 125u, V-phase system command value calculation unit 125v, and W-phase system command value calculation unit 125w.

  The effective value calculation units 121u, 121v, and 121w calculate respective effective values of the system voltage signal Vs (Vsu, Vsv, Vsw). The effective value calculation unit 121u calculates the effective value Veu of the U-phase system voltage signal Vsu and outputs it to the filter unit 122u, and the effective value calculation unit 121v calculates the effective value Vev of the V-phase system voltage signal Vsv and filters it. The effective value calculation unit 121w calculates the effective value Vew of the W-phase system voltage signal Vsw and outputs it to the filter unit 122w.

The effective values Veu, Vev, and Vew are calculated from the system voltage signals Vsu, Vsv, and Vsw by the following equations (1), (2), and (3).
Vu (ωt) is the current instantaneous value of the U-phase system voltage, and Vu (ωt−π / 2) is the instantaneous value of π / 2 before the U-phase system voltage. The same applies to the V phase and the W phase. Note that the effective value may be calculated by another method.

  The filter units 122u, 122v, and 122w are low-pass filters that remove high-frequency components from the effective values Veu, Vev, and Vew calculated by the effective value calculation units 121u, 121v, and 121w, respectively. The effective values Veu, Vev, Vew from which the high frequency components have been removed by the filter units 122u, 122v, 122w are the U-phase system command value calculation unit 125u, the V-phase system command value calculation unit 125v, and the W-phase system command value calculation unit, respectively. It is output to 125w. Note that the configuration of the filter units 122u, 122v, and 122w is not limited to this, and any known filter for removing high-frequency components may be used.

  The phase difference detectors 123u, 123v, 123w detect the phase difference between the phase of the system voltage signal Vs (Vsu, Vsv, Vsw) and the phase at equilibrium. The control system of the inverter control circuit 10 is processed in synchronization with the phase θ of the system voltage. The phase θ of the system voltage is detected by the phase detection circuit 111 (see FIG. 2). If the system B is in a voltage balanced state, the phases of the system voltage signals Vsu, Vsv, and Vsw are θ, (θ-2π / 3), and (θ + 2π / 3), respectively. The phase difference detectors 123u, 123v, 123w correspond to the phases θ, (θ-2π / 3), (θ + 2π / 3) in the equilibrium state of the phase of the actually detected system voltage signals Vsu, Vsv, Vsw. The phase differences φu, φv, and φw are detected. The phase difference detection unit 123u detects the phase difference φu of the U-phase system voltage signal Vsu and outputs it to the filter unit 124u. The phase difference detection unit 123v detects the phase difference φv of the V-phase system voltage signal Vsv and filters it. The phase difference detector 123w detects the phase difference φw of the W-phase system voltage signal Vsw and outputs it to the filter unit 124w.

  FIG. 4 is a diagram for explaining a method of detecting a phase difference.

  FIG. 5A shows the waveforms of the system voltage signals Vsu, Vsv, Vsw in a voltage balanced state. The thick line waveform is the waveform of the system voltage signal Vsu, the thin line waveform is the waveform of the system voltage signal Vsv, and the broken line waveform is the waveform of the system voltage signal Vsw. The arrow on the right side is a vector diagram showing the relationship between the system voltage signals Vsu, Vsv, and Vsw. The system voltage signal Vsu is synchronized with the synchronizing pulse based on the phase θ of the system voltage, and the rising edge of the synchronizing pulse coincides with the rising zero cross of the system voltage signal Vsu (timing when the voltage passes zero changing from minus to plus). ing. The system voltage signal Vsv is delayed in phase by 2π / 3 from the system voltage signal Vsu, and the rising zero cross of the system voltage signal Vsv is delayed by 2π / 3 from the rising edge of the synchronization pulse. The phase of the system voltage signal Vsw is advanced by 2π / 3 from the system voltage signal Vsu, and the rising zero cross of the system voltage signal Vsw is advanced by 2π / 3 from the rising edge of the synchronization pulse.

  FIG. 5B shows the waveforms of the system voltage signals Vsu, Vsv, Vsw in a voltage unbalanced state. The voltage unbalanced state in FIG. 6B shows a voltage unbalanced state when, for example, the V phase and the W phase are grounded, and the phase and amplitude of the system voltage signals Vsv and Vsw vary. The system voltage signal Vsv is delayed in phase by 2π / 9 from the equilibrium state (see the waveform Vsv in FIG. 9A), and the rising zero cross of the system voltage signal Vsv is 8π / 9 (= 2π / 3 + 2π / from the rising edge of the synchronization pulse. 9) It is late. The phase of the system voltage signal Vsw is advanced by 2π / 9 from the equilibrium state (see the waveform Vsw in FIG. 9A), and the rising zero cross of the system voltage signal Vsw is 8π / 9 (= 2π / 3 + 2π / from the rising edge of the synchronization pulse. 9) Go ahead. That is, the phase differences φu, φv, and φw can be calculated by comparing the rising zero crosses of the system voltage signals Vsu, Vsv, and Vsw with the rising zero crosses at the respective equilibrium times with reference to the rising edge of the synchronization pulse.

  For example, the phase difference φv is measured by, for example, counting the reference clock from the rising edge of the synchronizing pulse to the rising zero cross of the system voltage signal Vsv, and the reference clock is counted from the rising edge of the synchronizing pulse to the rising zero cross at equilibrium. For example, it is calculated by subtracting the phase difference measured in advance. In the case of the example in FIG. 5B, the phase difference φv is the phase difference between the rising zero cross of the system voltage signal Vsv and the rising edge of the synchronizing pulse −8π / 9 (the rising zero cross of the system voltage signal Vsv is the rising edge of the synchronizing pulse. Subtract the phase difference of −2π / 3 between the rising zero cross at the equilibrium and the rising edge of the sync pulse, and φv = −8π / 9 − (− 2π / 3) = − 2π / 9 Is calculated.

  Further, the phase difference φw is measured by, for example, counting the reference clock from the rising zero cross of the system voltage signal Vsw to the rising of the synchronization pulse, and counting the reference clock from the rising zero cross at the equilibrium to the rising of the synchronizing pulse. For example, it is calculated by subtracting the phase difference measured in advance. In the case of the example shown in FIG. 5B, the phase difference φw is obtained from the phase difference 8π / 9 between the rising zero cross of the system voltage signal Vsw and the rising edge of the synchronizing pulse, and the phase difference between the rising zero cross at equilibrium and the rising edge of the synchronizing pulse. By subtracting 2π / 3, φw = 8π / 9−2π / 3 = 2π / 9 is calculated.

  The filter units 124u, 124v, and 124w are low-pass filters that remove high-frequency components from the phase differences φu, φv, and φw detected by the phase difference detection units 123u, 123v, and 123w, respectively. The phase differences φu, φv, φw from which the high frequency components have been removed by the filter units 124u, 124v, 124w are respectively the U-phase system command value calculation unit 125u, the V-phase system command value calculation unit 125v, and the W-phase system command value calculation unit. It is output to 125w. The configuration of the filter units 124u, 124v, and 124w is not limited to this, and any known filter for removing high-frequency components may be used.

  The U-phase system command value calculation unit 125u, the V-phase system command value calculation unit 125v, and the W-phase system command value calculation unit 125w calculate system command values. The U-phase system command value calculation unit 125u calculates the U-phase from the effective value Veu input from the filter unit 122u, the phase difference φu input from the filter unit 124u, and the DC voltage Vin input from the DC voltage sensor 6. A system command value Ku is calculated. The V-phase system command value calculation unit 125v calculates the V-phase from the effective value Vev input from the filter unit 122v, the phase difference φv input from the filter unit 124v, and the DC voltage Vin input from the DC voltage sensor 6. A system command value Kv is calculated. The W-phase system command value calculation unit 125w calculates the W-phase from the effective value Vew input from the filter unit 122w, the phase difference φw input from the filter unit 124w, and the DC voltage Vin input from the DC voltage sensor 6. A system command value Kw is calculated. The calculated system command values Ku, Kv, Kw are output to the adder 13 as system command value signals.

System command values Ku (t), Kv (t), and Kw (t) are calculated by the following equations (4), (5), and (6).

Ω is the angular frequency of the system B, and ωt is the current phase of the U-phase system voltage. Cm is the amplitude of the system command value signals Ku (t), Kv (t), Kw (t) when the system B is in a voltage balanced state. φu, φv, and φw are the phase differences φu, φv, and φw input from the phase difference detectors 123u, 123v, and 123w, respectively, and Veu, Vev, and Vew are input from the effective value calculators 121u, 121v, and 121w, respectively. Are the effective values Veu, Vev, and Vew of the system voltage signal. Kt is the transformation ratio of the transformer circuit 4, if the number of primary winding of the line B side and N ₁ and the secondary winding speed of the inverter circuit 2 side and N _2, the Kt = N ₁ / N _2. Vin is a DC voltage signal Vin input from the DC voltage sensor 6.

  Below, the method of calculating said (4), (5), (6) Formula is demonstrated.

  As will be described later, the PWM signal generation unit 14 compares the command value signal generated from the system command value signals Ku, Kv, and Kw with a predetermined carrier signal (triangular wave signal) to generate a PWM signal. As shown in FIG. 5, in order to compare the command value signal X and the carrier signal C, it is desirable to match the amplitude of the command value signal X with the amplitude Cm of the carrier signal C. Therefore, the amplitude of the system command value signals Ku, Kv, Kw when the system B is in a voltage balanced state is set as the amplitude Cm of the carrier signal C.

In the present embodiment, the comparison processing in the PWM signal generation unit 14 is performed by digital processing. Therefore, Cm × 2 which is the peak-to-peak value of the amplitude of the carrier signal C is a resolution in digital processing (for example, when the bit width is 12 bits, the resolution is 2 ¹² = 4096 [number of bits]). Then, the output voltage change width ΔV of the grid interconnection inverter system A per bit number is
ΔV = Vin · Kt / (2 · Cm) [V] (7)
It becomes. Here, when the output gain of the system command value signal Ku is Gu, the effective value Vinv of the output voltage of the system interconnection inverter system A generated by the system command value signal Ku is
Vinv = (ΔV · 2 · Cm · Gu / 2) / √2
= ΔV · Cm · Gu / √2 [Vrms] (8)
It becomes. From this, in order to make the voltage levels of the grid-connected inverter system A and the grid B coincide with each other, an output gain Gu that satisfies Vinv = Veu may be calculated.

From the above equations (8) and (7),
Veu = Vinv = ΔV · Cm · Gu / √2
= {Vin · Kt / (2 · Cm)} · Cm · Gu / √2
Gu = Veu · 2√2 / (Vin · Kt)
= (2√2 / Kt) · (Veu / Vin)

Therefore, using the output gain Gu, the amplitude Cm, and the phase difference φu, the system command value signal Ku is
Ku = Gu · Cm · SIN (ωt + φu)
It is represented by Similarly, the output gain Gv of the system command value signal Kv and the output gain Gw of the system command value signal Kw are:
Gv = (2√2 / Kt) · (Vev / Vin)
Gw = (2√2 / Kt) · (Vew / Vin)
The system command value signal Kv and the system command value signal Kw are
Kv = Gv · Cm · SIN (ωt-2π / 3 + φv)
Kw = Gw · Cm · SIN (ωt + 2π / 3 + φw)
It is represented by

  Returning to FIG. 1, the adding unit 13 adds the correction value signals ΔXu, ΔXv, ΔXw input from the correction value generating unit 11 to the system command value signals Ku, Kv, Kw input from the system command value generating unit 12. Addition and output to the PWM signal generation unit 14 as command value signals Xu, Xv, Xw.

  The PWM signal generation unit 14 uses a triangular wave comparison method based on the command value signals Xu, Xv, Xw input from the addition unit 13 and a carrier signal generated as a triangular wave signal having a predetermined frequency (for example, 4 kHz). PWM signals Pu, Pv and Pw are generated. In the triangular wave comparison method, as shown in FIG. 5, the command value signal X and the carrier signal C are compared. For example, when the command value signal X is larger than the carrier signal C, the command value signal X becomes high level. When it is smaller than C, a pulse signal P that is at a low level is generated as a PWM signal. The generated PWM signals Pu, Pv, Pw are output to the inverter circuit 2.

  The inverter control circuit 10 may be realized as an analog circuit or a digital circuit. Further, the processing performed by each unit may be designed by a program, and the computer may function as the inverter control circuit 10 by executing the program. The program may be recorded on a recording medium and read by a computer.

  In the inverter control circuit 10, system command value signals Ku, Kv, Kw that serve as a reference for the command value signal are generated for each phase based on the voltage of each phase of the system B by the system command value generation unit 12. Therefore, even when the voltage of each phase of the system B is in an unbalanced state, a command value signal for each phase corresponding to the voltage of each phase in the unbalanced state is generated, so the output voltage from the inverter circuit 2 is also The unbalanced state is the same as the voltage of each phase of the system B. Thereby, since the control accuracy of the output current of the inverter circuit 2 is not deteriorated, it is possible to suppress an increase in the imbalance of the output current, and thus it is possible to suppress the detection of an overcurrent. Therefore, even when the connected system B is in a voltage unbalanced state, the inverter circuit 2 can be stably operated.

  FIG. 6 is a diagram for illustrating a change in the output current of the inverter circuit 2 in a simulation when the connected system is in a voltage unbalanced state.

  FIG. 6A shows the simulation result when the conventional inverter control circuit 10 'is used. The upper row shows changes in the system voltage of each phase, and the lower row shows changes in the output current of each phase. As shown in the upper stage, during the period T, the phase and amplitude of the V-phase voltage of the system voltage are changed to be in an unbalanced state. During the period T, a constant output current control was performed, and a simulation was performed with a 50% load to prevent overcurrent. According to the simulation, as shown in the lower stage, during the period T, the output current of each phase is also in an unbalanced state, and the current peak value increases. This current peak value is a level at which the inverter circuit 2 is stopped by the overcurrent prevention function in the case of 100% load.

  FIG. 7B shows the simulation result when the inverter control circuit 10 is used, and the simulation is performed under the same conditions as in FIG. According to the simulation, the output current of each phase can be controlled even during the period T as shown in the lower part. Further, an increase in output current can be suppressed.

  In the first embodiment, the system command value signals Ku, Kv, and Kw are generated for each phase based on the voltage of each phase of the system B even when the system B is in a voltage balanced state. Therefore, even a minute voltage fluctuation in the steady state is reflected in the system command value signals Ku, Kv, Kw, and the output current varies. In this case, there is a possibility that the fluctuation of the output current is increased. Therefore, in the second embodiment described below, a configuration is added in which the system command value signals Ku, Kv, Kw are switched to ideal three-phase AC waveforms in the equilibrium state.

  FIG. 7 is a block diagram for explaining an internal configuration of a system command value generation unit according to the second embodiment of the inverter control circuit 10 according to the present invention. In the figure, the same or similar elements as those of the system command value generation unit 12 (see FIG. 3) of the first embodiment are denoted by the same reference numerals.

  The system command value generation unit 12 ′ is provided with an unbalanced voltage difference detection unit 126, an unbalanced phase difference detection unit 127, an OR operation unit 128, and a switching unit 129, and the system command value generation unit of the first embodiment. 12 is different. The function of the unbalanced current compensation circuit 119 (see FIG. 2) in the second embodiment is also different from that in the first embodiment.

  7 detects the unbalanced state of the system B from the effective values Veu, Vev, and Vew input from the filter units 122u, 122v, and 122w, and ORs the unbalanced voltage difference detection signal. This is output to the calculation unit 128. The unbalanced voltage difference detection unit 126 determines that the system B is in an unbalanced state when any of the differences between the effective values Veu, Vev, and Vew is equal to or higher than the unbalanced voltage difference detection level that is a predetermined threshold value. The unbalanced voltage difference detection signal is turned “ON”. On the other hand, if any of the differences between the effective values Veu, Vev, and Vew is less than the unbalanced voltage difference detection level, the unbalanced voltage difference detection signal is set to “OFF”.

  FIG. 8 is a diagram for explaining an example of the internal configuration of the unbalanced voltage difference detection unit 126.

  As shown in the figure, the unbalanced voltage difference detection unit 126 includes subtraction units 126a, 126b, and 126c, absolute value conversion units 126d, 126e, and 126f, hysteresis comparators 126g, 126h, and 126i, an OR operation unit 126j, and a delay filter 126k. It has.

  First, the subtraction units 126a, 126b, and 126c and the absolute value conversion units 126d, 126e, and 126f perform the difference between the effective value Veu and the effective value Vev, the difference between the effective value Vev and the effective value Vew, and the effective value Vew and the effective value. The difference from the value Veu is calculated. Next, the hysteresis comparators 126g, 126h, 126i respectively compare the calculated differences with the unbalanced voltage difference detection level, and output an “ON” signal when each difference is equal to or greater than the unbalanced voltage difference detection level. . A hysteresis is provided to suppress chattering. The OR operation unit 126j calculates and outputs a logical sum of the outputs of the hysteresis comparators 126g, 126h, and 126i. Therefore, when any of the differences is equal to or higher than the unbalanced voltage difference detection level, the unbalanced voltage difference detection signal is output as “ON”. The delay filter 126k delays the falling time of the unbalanced voltage difference detection signal and is provided to suppress chattering. That is, chattering at the time of transition is suppressed by determining that the state is an equilibrium state when a state in which an unbalance state is not detected continues for a predetermined time.

  Note that the internal configuration of the unbalanced voltage difference detection unit 126 is not limited to this. For example, the delay filter 126k may not be provided, or the delay filter 126k may delay the rise time of the unbalanced voltage difference detection signal. In place of the hysteresis comparators 126g, 126h, and 126i, a comparator that does not provide hysteresis may be used.

  Returning to FIG. 7, the unbalanced phase difference detection unit 127 detects the unbalanced state of the system B from the phase differences φu, φv, and φw input from the filter units 124u, 124v, and 124w, and detects an unbalanced phase difference detection signal. Is output to the OR operation unit 128. The unbalanced phase difference detection unit 127 determines that the system B is in an unbalanced state when any of the absolute values of the phase differences φu, φv, and φw is greater than or equal to a predetermined threshold unbalanced phase difference detection level. The unbalanced phase difference detection signal is turned “ON”. On the other hand, when all of the absolute values of the phase differences φu, φv, and φw are less than the unbalanced phase difference detection level, the unbalanced phase difference detection signal is set to “OFF”.

  FIG. 9 is a diagram for explaining an example of the internal configuration of the unbalanced phase difference detection unit 127.

  As shown in the figure, the unbalanced phase difference detection unit 127 includes absolute value conversion units 127d, 127e, 127f, hysteresis comparators 127g, 127h, 127i, an OR operation unit 127j, and a delay filter 127k.

  First, the absolute value converters 127d, 127e, and 127f calculate absolute values of the phase differences φu, φv, and φw. Next, the hysteresis comparators 127g, 127h, 127i compare the calculated absolute values of the respective phase differences with the unbalanced phase difference detection levels, respectively, and when the absolute values of the respective phase differences are equal to or greater than the unbalanced phase difference detection level, ON "signal is output. A hysteresis is provided to suppress chattering. The OR operation unit 127j calculates and outputs a logical sum of the outputs of the hysteresis comparators 127g, 127h, and 127i. Therefore, when any of the absolute values of the phase differences is equal to or higher than the unbalanced phase difference detection level, the unbalanced phase difference detection signal is output as “ON”. Note that the delay filter 127k delays the falling time of the unbalanced phase difference detection signal, and is provided to suppress chattering. That is, chattering at the time of transition is suppressed by determining that the state is an equilibrium state when a state in which an unbalance state is not detected continues for a predetermined time.

  The internal configuration of the unbalanced phase difference detection unit 127 is not limited to this. For example, the delay filter 127k may not be provided, or the delay filter 127k may delay the rise time of the unbalanced voltage difference detection signal. In place of the hysteresis comparators 127g, 127h, and 127i, a comparator that does not provide hysteresis may be used.

  Returning to FIG. 7, the OR operation unit 128 calculates the logic between the unbalanced voltage difference detection signal input from the unbalanced voltage difference detection unit 126 and the unbalanced phase difference detection signal input from the unbalanced phase difference detection unit 127. The sum is calculated and output to the switching unit 129 and the unbalanced current compensation circuit 119 (see FIG. 2). That is, the OR operation unit 128 sets the output signal to “ON” when at least one of the unbalanced voltage difference detection signal and the unbalanced phase difference detection signal is “ON”, and outputs the output signal when both are “OFF”. Is set to “OFF”.

  Switching unit 129 switches input to U-phase system command value calculation unit 125u, V-phase system command value calculation unit 125v, and W-phase system command value calculation unit 125w in accordance with a signal input from OR operation unit 128. Is.

  When the input signal from the OR operation unit 128 is “ON”, that is, when it is determined that the system B is in an unbalanced state, the switching unit 129 has a U-phase system command value calculation unit 125 u and a V-phase system command value. The effective values input to the calculation unit 125v and the W-phase system command value calculation unit 125w are effective values Veu, Vev, and Vew output from the filter units 122u, 122v, and 122w, respectively, and the U-phase system command value calculation unit 125u, The phase differences input to the V-phase system command value calculation unit 125v and the W-phase system command value calculation unit 125w are referred to as phase differences φu, φv, and φw output from the filter units 124u, 124v, and 124w, respectively. In this case, a state similar to the internal configuration of the system command value generation unit 12 illustrated in FIG. 3 is obtained, and the system command value signals Ku, Kv, and Kw are generated for each phase based on the voltage of each phase of the system B.

  On the other hand, when the input signal from the OR operation unit 128 is “OFF”, that is, when it is determined that the system B is in an equilibrium state, the U-phase system command value calculation unit 125u, the V-phase system command value calculation unit 125v, The effective value input to the W phase system command value calculation unit 125w is the effective value Veu output from the filter unit 122u, and the U phase system command value calculation unit 125u, the V phase system command value calculation unit 125v, and the W phase system The phase difference input to the command value calculation unit 125w is set to “0”. In this case, the system command value signals Ku, Kv, and Kw are generated in an equilibrium state based on the U-phase voltage of the system B. In addition, the switch of the switching unit 129 shown in the figure describes the connection when the input signal is “OFF”.

  When the input signal from the OR operation unit 128 is “ON”, the unbalanced current compensation circuit 119 (see FIG. 2) compensates for the unbalanced current as in the first embodiment. On the other hand, when the input signal from the OR operation unit 128 is “OFF”, the compensation of the unbalanced current is stopped.

  In the present embodiment, whether the system B is in an unbalanced state based on the effective values Veu, Vev, Vew and the phase differences φu, φv, φw calculated from the system voltage signal Vs (Vsu, Vsv, Vsw). Is judged. When it is determined that the system B is in an unbalanced state, the system command value signals Ku, Kv, Kw are generated for each phase based on the voltage of each phase of the system B. On the other hand, when it is determined that the system B is not in an unbalanced state (equilibrium state), the system command value signals Ku, Kv, Kw are generated in an equilibrium state based on the U-phase voltage of the system B. . Therefore, when the system B is in an equilibrium state, the system command value signals Ku, Kv, and Kw are ideal three-phase AC waveforms, and instantaneous voltage fluctuations in a steady state are not reflected. There is no inconvenience that the fluctuation of the current is increased. Moreover, when the system | strain B is an unbalanced state, there can exist an effect similar to 1st Embodiment.

  In addition, although the said embodiment demonstrated the case where the inverter control circuit of this invention was used for the grid connection inverter system, it is not restricted to this. The inverter control circuit of the present invention is realized by reading a program that causes a conventional inverter control circuit to perform PWM control by the above-described method from a recording medium such as a ROM that is recorded in a computer-readable manner and executing the program. May be.

  The inverter control circuit according to the present invention and the grid-connected inverter system including the inverter control circuit are not limited to the above-described embodiments. The specific configuration of each part of the inverter control circuit according to the present invention and the grid-connected inverter system including the inverter control circuit can be varied in design in various ways.

A Grid-connected inverter system 1 DC power supply 2 Inverter circuit 3 Filter circuit 4 Transformer circuit 5 Switch 6 DC voltage sensor 7, 8 Current sensor 9 System voltage sensor 10, 10 ′ Inverter control circuit 11 Correction value generator (correction value signal) Generation means)
111 phase detection circuit 112 PI control circuit (first correction value calculation means)
113 reactive power calculation circuit 114 PI control circuit (first correction value calculation means)
115 dq conversion circuit (conversion means)
116 PI control circuit (second correction value calculating means)
117 PI control circuit (second correction value calculating means)
118 Inverse dq conversion circuit (inverse conversion means)
119 Unbalanced current compensation circuit 12 System command value generator (command value signal generator)
12 'system command value generation unit (command value signal generation means, second command value signal generation means)
121u, 121v, 121w Effective value calculation unit (effective value calculation means)
122u, 122v, 122w Filter unit 123u, 123v, 123w Phase difference detection unit (phase difference detection means)
124u, 124v, 124w Filter unit 125u U-phase system command value calculation unit (command value calculation means)
125v V-phase system command value calculation unit (command value calculation means)
125w W-phase system command value calculation unit (command value calculation means)
126 Unbalance voltage difference detector (unbalance detection means)
126a, 126b, 126c Subtraction unit 126d, 126e, 126f Absolute value conversion unit 126g, 126h, 126i Hysteresis comparator 126j OR operation unit 126j
126k delay filter 127 unbalanced phase difference detection unit (unbalance detection means)
127d, 127e, 127f Absolute value conversion unit 127g, 127h, 127i Hysteresis comparator 127j OR operation unit 127j
127k delay filter 128 OR operation unit (unbalance detection means)
129 switching unit 13 adding unit (command value signal correcting means)
14 PWM signal generator (PWM signal generator)
B Power system

Claims (14)

An inverter control circuit for PWM control of an inverter circuit that converts DC power to AC power and outputs it to a three-phase power system,
A command value signal for generating a command value signal of each phase for commanding a voltage of each phase to be output from the inverter circuit from each of the voltage signals of each phase of the three-phase power system detected by the voltage detection means Generating means;
Correction value signal generating means for generating a correction value signal for each phase for controlling a measured value related to input / output of the inverter circuit measured by a predetermined measuring means to a predetermined target value;
Command value signal correcting means for correcting the command value signal of each phase based on the correction value signal of the corresponding phase, and outputting a corrected command value signal of each phase;
PWM signal generating means for generating a PWM signal of each phase for PWM control of the inverter circuit based on the corrected command value signal of each phase;
An inverter control circuit comprising: The command value signal correcting means corrects by adding the correction value signals of phases corresponding to the command value signals of the phases,
The inverter control circuit according to claim 1. The command value signal generating means is
Effective value calculating means for calculating a voltage effective value of the voltage signal of each phase;
Phase difference detection means for detecting a phase difference between the phase of the voltage signal of each phase and the phase at the time of three-phase equilibrium;
Command value calculating means for calculating a command value for each phase from the voltage effective value of each phase calculated by the effective value calculating means and the phase difference of each phase detected by the phase difference detecting means;
With
Outputting the command value of each phase calculated by the command value calculating means as the command value signal of each phase;
The inverter control circuit according to claim 1. The command value calculation means calculates the command values Ku (t), Kv of the respective phases from the effective voltage values Veu, Vev, Vew of the respective phases and the phase differences φu, φv, φw of the respective phases according to the following equations. The inverter control circuit according to claim 3, wherein (t) and Kw (t) are calculated.
Ω is an angular frequency of the three-phase power system, ωt is a current phase of the U-phase system voltage, and Cm is a command value signal Ku (t), Kv (t), Kw at the three-phase equilibrium. (T) is an amplitude, Vin is a direct current voltage input to the inverter circuit, and Kt is a transformation ratio of a transformation means for transforming the output voltage of the inverter circuit.
The correction value signal generation means includes
Conversion means for converting the output current signal of each phase of the inverter circuit detected by the current detection means into each component of the rotating coordinate system;
First correction value calculating means for calculating a first correction value for feedback control based on an amount of deviation from the target value with respect to the measured value;
Second correction value calculating means for calculating a second correction value for feedback control based on a deviation amount from the first correction value for any of the components;
Inverse conversion means for inversely converting the second correction value into a correction value for each phase of the stationary coordinate system;
With
Outputting the correction value of each phase as the correction value signal of each phase;
The inverter control circuit according to claim 1. The correction value signal generating means generates a correction value signal for controlling a DC voltage input to the inverter circuit to a predetermined target voltage.
The inverter control circuit according to claim 1. The correction value signal generation means generates a correction value signal for controlling the reactive power output from the inverter circuit to a predetermined target reactive power.
The inverter control circuit according to claim 1. The PWM signal generating means generates a PWM signal from a comparison result between the corrected command value signal and a triangular wave signal having a predetermined frequency.
The inverter control circuit according to claim 1. A second command value signal for generating a second command value signal of each phase for commanding a voltage of each phase to be output from the inverter circuit from any one of the voltage signals of each phase of the three-phase power system Generating means;
Unbalance detection means for detecting that the voltage signal of each phase of the three-phase power system is in an unbalanced state;
Further comprising
The command value signal correcting means corrects the second command value signal of each phase instead of the command value signal of each phase while the unbalanced state is not detected by the unbalance detecting means. And generating a corrected command value signal for each phase,
The inverter control circuit according to claim 1. A second command value signal for generating a second command value signal of each phase for commanding a voltage of each phase to be output from the inverter circuit from any one of the voltage signals of each phase of the three-phase power system Generating means;
Unbalance detection means for detecting that the voltage signal of each phase of the three-phase power system is in an unbalanced state;
Further comprising
The command value signal correcting means replaces the command value signal of each phase when the state where the unbalanced state is not detected by the unbalance detection means continues for a predetermined time. Correcting the second command value signal to generate a corrected command value signal for each phase;
The inverter control circuit according to claim 1. The unbalance detection means is configured to detect a difference between a voltage effective value of a voltage signal of any phase of the three-phase power system and a voltage effective value of a voltage signal of another phase being a predetermined value or more, or When the phase difference between the phase of the voltage signal of any phase of the phase power system and the phase at the time of three-phase equilibrium is equal to or greater than a predetermined phase difference, the unbalanced state is detected.
The inverter control circuit according to claim 9 or 10. The inverter circuit and the inverter control circuit according to any one of claims 1 to 11,
A grid-connected inverter system. A program for causing a computer to function as an inverter control circuit for PWM control of an inverter circuit that converts DC power into AC power and outputs it to a three-phase power system,
The computer,
A command value signal for generating a command value signal of each phase for commanding a voltage of each phase to be output from the inverter circuit from each of the voltage signals of each phase of the three-phase power system detected by the voltage detection means Generating means;
Correction value signal generating means for generating a correction value signal for each phase for controlling a measured value related to input / output of the inverter circuit measured by a predetermined measuring means to a predetermined target value;
Command value signal correcting means for correcting the command value signal of each phase based on the correction value signal of the corresponding phase, and outputting a corrected command value signal of each phase;
PWM signal generating means for generating a PWM signal of each phase for PWM control of the inverter circuit based on the corrected command value signal of each phase;
Program to make it function.   A computer-readable recording medium on which the program according to claim 13 is recorded.