JP2007316961A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, easily monitoring a system. <P>SOLUTION: The device comprises a counter CUNT which generates a reset signal, for example, in the event of overflow; an alarm signal generation part WG_BLK 1 which outputs a warning signal when a part of bits of CUNT is equal to a preset value; and an interrupt signal generation part INT_BLK and an interrupt processing part INT_PRG which perform various interrupt processings in response to the warning signal. The WG_BLK 1 generates the warning signal when the CUNT value reaches, for example, 1/4, 1/2 or 3/4 of the overflowing value by setting, and the INT_BLK and INT_PRG perform interrupt processing in response to this warning signal to rewrite the CUNT value in an interrupt processing program in the INT_PRG. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device such as a microcomputer including a watchdog timer.

For example, Patent Document 1 includes a watchdog timer that can output a first overflow signal from fixed bits in the middle of a plurality of bits, and a program that receives the first overflow signal and outputs a watchdog timer clear signal. An anomaly detection circuit is shown. If this abnormality detection circuit is used, for example, it is possible to reduce the labor required in the past when inserting a watchdog timer clear instruction into the program.
JP 2000-311100 A

  For example, a microcomputer or the like is equipped with what is called a watchdog timer (hereinafter sometimes abbreviated as WDT) in order to monitor system or program runaway. 6A and 6B show a watchdog timer studied as a premise of the present invention. FIG. 6A is a conceptual diagram showing a configuration example and a usage example thereof, and FIG. 6B is an explanatory diagram showing an operation example thereof.

  As shown in FIG. 6A, a general WDT, for example, counts a counter CUNT with a count source clock CLK, and when the most significant bit overflows, an overflow detection unit OF is provided inside the microcomputer or the like. Forcibly reset. Therefore, normally, the user periodically inserts an instruction to rewrite CUNT in the program (S601), or reads the value of CUNT and implements a program that rewrites CUNT when the threshold is exceeded ( S602), the runaway of the system is monitored by executing the rewrite before the CUNT reaches the overflow. However, such a method may cause the following problem, for example.

  First, since the execution speed of a program depends on hardware such as a microcomputer, the position for inserting a CUNT rewrite instruction is determined when, for example, it is desired to create a program used in common by a plurality of microcomputers. It becomes difficult. That is, for example, even if a program that generates a CUNT rewrite command every 2 ms is created for a certain microcomputer, if the program is executed by a microcomputer that operates at this half speed, 4 ms Each time a rewrite command is generated. If the time to reach overflow is between 2 ms and 4 ms, the latter will cause an unintended reset. Secondly, an artificial mistake such as forgetting to insert this CUNT rewrite instruction in the program is likely to occur. In particular, when rewriting instructions are periodically inserted in consideration of the execution time of the program, mistakes such as forgetting to enter easily occur, and mistakes that miscalculate the execution time are likely to occur.

  Third, for example, when a low-accuracy clock such as a low-speed on-chip oscillator is used as the count source clock CLK, the rewrite timing of the CUNT is not stable. In other words, the CPU and WDT in the microcomputer are usually operated with different source clocks, but if the accuracy of the source clock of the WDT is low, even if the WDT is rewritten every 2 ms by the CPU (that is, the program). From the viewpoint of WDT, for example, a situation in which a rewrite command is input every 2 ms ± 10% can occur. In FIG. 6B, for example, the value of the WDT counter CUNT is periodically rewritten to H′20 by a WDT rewrite instruction, but the timing (the value of the CUNT) at which the rewrite occurs becomes unstable. Yes. If the rewrite timing exceeds H′FF due to this variation, an unintended reset occurs.

  In order to solve such a problem, for example, it is conceivable to use the technique of Patent Document 1. However, with this technique, since a WDT rewrite command can be generated only at a fixed timing, flexibility such as optimization of the monitoring timing according to system conditions cannot be obtained.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that can easily realize system monitoring. Another object of the present invention is to provide a semiconductor integrated circuit device capable of flexibly setting system monitoring conditions. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor integrated circuit device according to the present invention includes a counter circuit that outputs a first signal when an overflow occurs, and a first circuit that outputs a second signal when the value of the counter circuit becomes equal to a preset value. The second signal is processed as an interrupt factor, and various processing circuits are used to update the value of the counter circuit using a corresponding interrupt program. In other words, instead of updating the WDT value in software in a normal program, hardware that generates an interrupt signal at the timing when WDT needs to be updated is constructed, Update the value of WDT.

  This reduces the user's labor and human error when creating a program, and makes it possible to easily monitor the system. In addition, when updating the WDT value in software, there was a risk of unintentional overflow due to various timing variations and human error, but this can be prevented, and reliability when monitoring the system Improves. Furthermore, since the timing for generating the second signal can be changed by changing the setting value in the first circuit, it is possible to flexibly cope with various system conditions. The set value in the first circuit may be for comparing some bits of the counter circuit, or may be for comparing all the bits. When the former is used, the circuit area can be reduced as compared with the latter.

  If the effect obtained by the representative one of the inventions disclosed in the present application is briefly described, it is possible to easily realize monitoring of a system runaway or the like. In addition, system monitoring conditions can be set flexibly.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 shows an outline of the main part of a semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 1A is a conceptual diagram showing an example of the configuration, and FIG. It is explanatory drawing which shows the operation example. The semiconductor integrated circuit device shown in FIG. 1A includes a counter CUNT, an overflow detection unit OF, a warning signal generation unit (first circuit) WG_BLK1, an interrupt signal generation unit (second circuit) INT_BLK, and an interrupt processing unit. (Third circuit) INT_PRG is included. The counter CUNT here is, for example, an 8-bit (b0 to b7) watchdog timer (WDT), and sequentially performs a counting operation in synchronization with the count source clock (first clock signal) CLK. The overflow detection unit OF detects an overflow from the most significant bit (b7) of CUNT and generates a reset signal (first signal).

  The warning signal generation unit WG_BLK1 is configured by hardware, and generates a warning (WARNING) signal (second signal) when the values of some of the bits of the CUNT become preset values. Here, for example, the most significant bit (b7) of CUNT and its lower bit (b6) are referred to, and (b7, b6) is (0, 1), (1, 0) or (1, 1). In this case, the flag signal FG14, FG12 or FG34 is output. Further, any one of FG14, FG12, and FG34 can be selected and output as a warning signal, and it can be set in advance which one is selected. As a result, WG_BLK1 generates a warning signal when FG14 is set and CUNT reaches ¼ of the maximum value. Similarly, when FG12 and FG34 are set, a warning signal is generated when CUNT reaches 1/2, 3/4 of the maximum value, respectively.

  The interrupt signal generation unit INT_BLK is a so-called interrupt controller, and performs priority processing using the warning signal from the WG_BLK1 as an interrupt factor to generate an interrupt signal. The interrupt processing unit INT_PRG is, for example, a CPU and a memory in which a program is stored. The interrupt processing unit INT_PRG receives an interrupt signal, executes the interrupt processing program, and rewrites CUNT in the interrupt processing program.

  When such a configuration is used, for example, an operation as shown in FIG. In FIG. 1B, the above-described counter value setting (1/4, 1/2, or 3/4) is performed in advance on WG_BLK1, and when the value of CUNT reaches this setting value. A warning signal is generated, and then the value of CUNT is rewritten to H'00 in the interrupt processing program. Although not shown, for example, when the interrupt processing program is not executed due to a system malfunction such as a program runaway or hardware abnormality, the CUNT overflows, so that the system abnormality can be detected. In FIGS. 1A and 1B, the counter value is set to 1/4, 1/2, or 3/4. However, of course, the present invention is not limited to this, and a desired value in CUNT can be set by WG_BLK1. It can be changed as appropriate by referring to the bit.

  As described above, the use of the semiconductor integrated circuit device of FIG. 1 eliminates the need for the user to periodically insert a WDT rewrite instruction into the program as in the prior art, and only the interrupt processing program needs to be described. Therefore, it is possible to easily monitor the system. In addition, the use efficiency of a ROM or the like for storing programs is improved. Furthermore, the reliability when monitoring this system is improved. In other words, as in the prior art, the clock frequency of the CPU and the WDT is based on the clock cycle of the WDT itself rather than the clock cycle of the CPU (program), so that rewriting is performed before it overflows. Regardless of the difference or the presence or absence of the error, an unintended reset due to overflow does not occur in principle. That is, the rewrite timing of the WDT is always stable as shown in FIG. 1B and does not become unstable as shown in FIG. 6B, so that an unintended reset does not occur.

  In addition, since the timing for generating an interrupt (warning signal) can be selected, it is possible to flexibly cope with various system conditions. For example, in a system that requires a certain amount of time for interrupt processing after a warning signal is generated, the counter value may be set to a small value with a margin, or in a system that can perform interrupt processing at high speed. It is possible to reduce the frequency of interrupt processing by setting a larger value. In addition, the occurrence frequency of interrupt processing can be adjusted by changing the value to be rewritten in the interrupt processing program to an arbitrary value other than H'00.

  FIG. 2 is a block diagram showing an example of the overall configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 2 is, for example, a microcomputer or a system LSI, and includes a central processing unit CPU, an interrupt controller INT, a watchdog timer WDT, a WDT oscillator WDT_OSC, a volatile memory RAM, A nonvolatile memory ROM and other various functional units PERI are provided. The CPU, INT, WDT, RAM, ROM, and PERI are connected by an address bus BUS (ADD) and a data bus BUS (DAT), respectively, and can communicate with each other. For example, although not shown, the CPU or the like operates with an internal clock different from the output of WDT_OSC.

  When the configuration example in FIG. 1A is applied to such a semiconductor integrated circuit device, CUNT, OF, and WG_BLK1 in FIG. 1A are mounted on the WDT in FIG. 2, and INT_BLK in FIG. 2 is mounted on the INT of FIG. 2, and INT_PRG of FIG. 1A is mounted on the CPU and RAM / ROM of FIG. FIG. 3 is a circuit block diagram showing a more detailed configuration example around the WDT when the configuration example of FIG. 1 is applied to the semiconductor integrated circuit device of FIG.

  The semiconductor integrated circuit device of FIG. 3 includes the above-described WDT oscillator WDT_OSC, interrupt controller INT and central processing unit CPU, prescaler PSS, count source selector CK_SEL, timer counter TCWD, comparison circuit CMPa, and various registers. Is done. The various registers include a timer mode register TMWD, a timer warning register TWWD, an interrupt control register WDTIC, a timer control / status register TCSRWD, and the like.

  The count source selector CK_SEL receives an internal clock set in a desired cycle by the prescaler PSS, a count source clock from the WDT_OSC, and the like, and selects one of these clocks to supply to the timer counter TCWD. The clock is selected at this time by setting the timer mode register TMWD. The timer counter TCWD performs a count operation in synchronization with a clock from CK_SEL (for example, a count source clock from WDT_OSC), and generates an internal reset signal when it overflows. When an internal reset signal is generated, the CPU and the like are forcibly reset.

  Further, the most significant bit (b7) and its lower bit (b6) of the timer counter TCWD and a value (first value) preset by the timer warning register TWWD corresponding to these bits are input to the comparison circuit CMPa. And compared. The comparison circuit CMPa is composed of various logic circuits including a composite gate and the like. The values (b7, b6) set in the TWWD match the count values (b7, b6) of the TCWD, and the interrupt enable signal is activated. A warning (WARNING) signal is generated. This warning signal is input to the interrupt controller INT.

  INT compares the priorities of the warning signal and other interrupt request signals (not shown), outputs an interrupt signal to the CPU, and notifies the signal with the highest priority. The interrupt priority order of the warning signal at this time is set by the interrupt control register WDTIC. For practical use, it is desirable to set the warning signal to a higher priority. Upon receiving the interrupt signal corresponding to the warning signal, the CPU executes the interrupt processing program stored in the RAM or ROM, and controls the timer control / status register TCSRWD or the timer counter TCWD in the interrupt processing program. To the desired value. Here, TCWD is in a write enable state under the control of TCSRWD, and is rewritable in this state.

  As described above, by using the semiconductor integrated circuit device according to the first embodiment, as described with reference to FIG. 1, the user's labor and human error are reduced, and the system can be easily monitored. In addition, since an unintended reset does not occur, reliability when monitoring the system is improved. Furthermore, since the timing for generating an interrupt (warning signal) can be selected, various system conditions can be flexibly handled. In addition, when the present embodiment is applied to a general microcomputer or the like, it is only necessary to add a comparison circuit CMPa and a timer warning register TWWD as shown in FIG. 3 to an existing circuit, which can be realized with a small area overhead. It becomes. In particular, since the comparison circuit CMPa is configured to compare some bits, a comparison operation is possible with a small circuit scale.

(Embodiment 2)
FIG. 4 is a conceptual diagram showing a configuration example of the main part of the semiconductor integrated circuit device according to the second embodiment of the present invention. As in the configuration example of FIG. 1, the semiconductor integrated circuit device of FIG. 4 includes a counter CUNT, an overflow detection unit OF, a warning signal generation unit (first circuit) WG_BLK2, and an interrupt signal generation unit (second circuit) INT_BLK. And an interrupt processing unit (third circuit) INT_PRG. However, the configuration in the warning signal generation unit WG_BLK2 is different from that in FIG. Since other functions are similar to those in FIG. 1, detailed description thereof is omitted.

  The warning signal generation unit WG_BLK2 is configured by hardware, and generates a warning (WARNING) signal when the values of all the bits of the CUNT are equal to preset values unlike the WG_BLK1 of FIG. Specifically, WG_BLK2 includes a timer warning register TWWD that can set an arbitrary value (first value) corresponding to all the bits of CUNT in advance, and compares each bit of TWWD and CUNT. When all the bits match, a warning signal (second signal) is output to the interrupt processing unit INT_BLK.

  After the warning signal is output, the priority processing and the generation of the interrupt signal for INT_PRG are performed by INT_BLK as in the configuration example of FIG. 1, and the CUNT is rewritten in the interrupt processing program in INT_PRG. Done. When such a configuration is used, in addition to the effects described in FIG. 1, the timing for generating an interrupt (warning signal) can be arbitrarily set, so that it is possible to flexibly respond to various system conditions. Become.

  When such a configuration is applied to a microcomputer or the like, for example, a circuit as shown in FIG. 5 may be used. FIG. 5 is a circuit block diagram showing a more detailed configuration example around the WDT when the configuration example of FIG. 4 is applied to the semiconductor integrated circuit device of FIG. 2 described above. As in the configuration example of FIG. 3, the semiconductor integrated circuit device of FIG. 5 includes a WDT oscillator WDT_OSC, an interrupt controller INT, a central processing unit CPU, a prescaler PSS, a count source selector CK_SEL, a timer counter TCWD, a comparison circuit CMPb, and various registers. Consists of. The various registers also include a timer mode register TMWD, a timer warning register TWWD, an interrupt control register WDTIC, a timer control / status register TCSRWD, and the like, as in the configuration example of FIG.

  However, the configuration of the semiconductor integrated circuit device of FIG. 5 is different from that of FIG. 3 in the comparison circuit CMPb. Since other functions are the same as those in FIG. 3, detailed description thereof is omitted. The comparison circuit CMPb in FIG. 5 has a logic such that, for example, each bit (b0 to b7) of TCWD and TWWD is subjected to an EXOR operation, and all the operation results are ANDed. The AND operation result is output as a warning signal by setting the interrupt enable signal to a valid state (here, “H” level). By setting the interrupt enable signal to an invalid state (here, “L” level), the warning signal can be used as a general WDT without causing an interrupt factor.

  As described above, by using the semiconductor integrated circuit device of the second embodiment, the user's labor and human error are reduced as in the first embodiment, and the system can be easily monitored. In addition, since an unintended reset does not occur, reliability when monitoring the system is improved. Furthermore, since the timing for generating an interrupt (warning signal) can be arbitrarily set, it is possible to flexibly cope with various system conditions.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The semiconductor integrated circuit device according to the present invention is particularly effective when applied to a microcomputer equipped with a watchdog timer, an interrupt controller or the like, and is not limited to this, but for any system including a watchdog timer. Widely applicable.

BRIEF DESCRIPTION OF THE DRAWINGS The semiconductor integrated circuit device by Embodiment 1 of this invention shows the outline | summary of the principal part, (a) is a conceptual diagram which shows the structural example, (b) is the operation example of (a). It is explanatory drawing shown. 1 is a block diagram showing an example of the overall configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. 3 is a circuit block diagram showing a more detailed configuration example around the WDT when the configuration example of FIG. 1 is applied to the semiconductor integrated circuit device of FIG. In the semiconductor integrated circuit device by Embodiment 2 of this invention, it is a conceptual diagram which shows the outline | summary which shows the structural example of the principal part. 5 is a circuit block diagram showing a more detailed configuration example around the WDT when the configuration example of FIG. 4 is applied to the semiconductor integrated circuit device of FIG. The watchdog timer examined as a premise of the present invention is shown, (a) is a conceptual diagram showing a configuration example and a usage example, and (b) is an explanatory diagram showing an operation example thereof.

Explanation of symbols

CUNT counter CLK count source clock OF overflow detection unit WG_BLK warning signal generation unit INT_BLK interrupt signal generation unit INT_PRG interrupt processing unit CPU central processing unit INT interrupt controller WDT watchdog timer WDT_OSC oscillator for WDT BUS bus RAM nonvolatile memory ROM non-volatile memory ROM Various functional units PSS Prescaler CK_SEL Count source selector TMWD Timer mode register TCSRWD Timer control / status register TCWD Timer counter TWWD Timer warning register WDTIC Interrupt control register CMP comparison circuit

Claims (5)

A counter circuit that performs a counting operation in synchronization with the first clock signal and outputs the first signal when an overflow occurs;
A first circuit that can set a first value in advance, compares the first value with the value of the counter circuit, and outputs a second signal when the comparison result matches;
A second circuit that receives the second signal as an interrupt factor and outputs an interrupt signal corresponding to the second signal;
A semiconductor integrated circuit device comprising: a third circuit that receives the interrupt signal, operates an interrupt processing program corresponding to the interrupt signal, and rewrites the value of the counter circuit using the interrupt processing program. The semiconductor integrated circuit device according to claim 1.
The semiconductor integrated circuit device according to claim 1, wherein the first value is a value corresponding to a part of bits of the counter circuit. The semiconductor integrated circuit device according to claim 1.
The semiconductor integrated circuit device according to claim 1, wherein the first value is a value corresponding to all bits of the counter circuit. The semiconductor integrated circuit device according to claim 1.
The semiconductor integrated circuit device, wherein the input of the second signal to the second circuit can be disabled by setting. The semiconductor integrated circuit device according to claim 1.
The third circuit includes a CPU and a memory,
2. The semiconductor integrated circuit device according to claim 1, wherein an operation clock signal of the CPU is different from the first clock signal.

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