JP2005055726A - El display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an EL display device capable of suppressing the occurrence of color irregularity, and reducing electric power consumption, size and weight. <P>SOLUTION: An anode voltage Vdd is generated from the voltage Vin of a battery cell by a DC-DC converter 3941a. A reference voltage Vdw is also generated by a DC-DC converter 3941b using the voltage Vin. A cathode voltage Vss is generated from the anode voltage Vdd and the reference voltage Vdw by a regulator 3943. The P channel transistors of the pixels formed in a matrix form of the EL display panel operate with the anode voltage Vdd as a reference. When the current flowing to the EL display panel is large, the anode voltage Vdd is made higher. When the anode voltage Vdd is to be changed, the cathode voltage Vss is also cooperatively shifted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a self-luminous display panel such as an EL display panel using an organic or inorganic electroluminescence (EL) element. The present invention also relates to a drive circuit (IC) such as these display panels. The present invention relates to a driving method and a driving circuit for an EL display panel and the like, an information display device using them, and the like.

In general, in an active matrix display device, an image is displayed by arranging a large number of pixels in a matrix and controlling the light intensity for each pixel in accordance with a given video signal. For example, when liquid crystal is used as the electro-optical material, the transmittance of the pixel changes according to the voltage written to each pixel. In an active matrix image display device using an organic electroluminescence (EL) material as an electro-optic conversion substance, light emission luminance changes according to a current written to a pixel.

  In the liquid crystal display panel, each pixel operates as a shutter, and an image is displayed by turning on and off light from a backlight with a shutter that is a pixel. The organic EL display panel is a self-luminous type having a light emitting element in each pixel. Therefore, the organic EL display panel has advantages such as higher image visibility than the liquid crystal display panel, no backlight, and high response speed.

  In the organic EL display panel, the luminance of each light emitting element (pixel) is controlled by the amount of current. That is, it is greatly different from the liquid crystal display panel in that the light emitting element is a current drive type or a current control type.

  The organic EL display panel can also be configured in a simple matrix system and an active matrix system. Although the former has a simple structure, it is difficult to realize a large and high-definition display panel. However, it is cheap. The latter can realize a large, high-definition display panel. However, there is a problem that the control method is technically difficult and relatively expensive. At present, active matrix systems are actively developed. In the active matrix system, a current flowing through a light emitting element provided in each pixel is controlled by a thin film transistor (transistor) provided in the pixel.

  An equivalent circuit for one pixel of this active matrix organic EL display panel is shown in FIG. 46 (see, for example, Patent Document 1). The pixel 16 includes an EL element 15 that is a light emitting element, a first transistor 11 a, a second transistor 11 b, and a storage capacitor 19. The light emitting element 15 is an organic electroluminescence (EL) element. In the present invention, the transistor 11 a that supplies (controls) current to the EL element 15 is referred to as a driving transistor 11. A transistor that operates as a switch, such as the transistor 11b in FIG. 46, is referred to as a switching transistor 11.

  Since the organic EL element 15 often has a rectifying property, it is sometimes called an OLED (organic light emitting diode). In FIG. 46 and the like, a diode symbol is used as the light emitting element 15.

  However, the light emitting element 15 in the present invention is not limited to the OLED, and may be any element whose luminance is controlled by the amount of current flowing through the element 15. For example, an inorganic EL element is illustrated. In addition, a white light emitting diode made of a semiconductor is exemplified. Moreover, a common light emitting diode is illustrated. In addition, a light emitting transistor may be used. In addition, the light emitting element 15 is not necessarily required to have rectification. A bidirectional diode may also be used. Any of these may be sufficient as the EL element 15 of this invention.

  In the example of FIG. 46, the source terminal (S) of the P-channel transistor 11a is set to Vdd (power supply potential), and the cathode (cathode) of the EL element 15 is connected to the ground potential (Vss). On the other hand, the anode (anode) is connected to the drain terminal (D) of the transistor 11b. On the other hand, the gate terminal of the P-channel transistor 11a is connected to the gate signal line 17a, the source terminal is connected to the source signal line 18, and the drain terminal is connected to the storage capacitor 19 and the gate terminal (G) of the transistor 11a. Yes.

In order to operate the pixel 16, first, the gate signal line 17 a is selected, and a video signal representing luminance information is applied to the source signal line 18. Then, the transistor 11a becomes conductive, the storage capacitor 19 is charged or discharged, and the gate potential of the transistor 11b matches the potential of the video signal. When the gate signal line 17a is not selected, the transistor 11a is turned off and the transistor 11b is electrically disconnected from the source signal line 18. However, the gate potential of the transistor 11 a is stably held by the storage capacitor (capacitor) 19. The current flowing to the light emitting element 15 through the transistor 11a has a value corresponding to the gate / source terminal voltage Vgs of the transistor 11a, and the light emitting element 15 emits light with luminance corresponding to the amount of current supplied through the transistor 11a. to continue.
JP-A-8-234683

  Since the liquid crystal display panel is not a self-luminous device, there is a problem that an image cannot be displayed unless a backlight is used. Since a predetermined thickness is required to configure the backlight, there is a problem that the thickness of the display panel is increased. In order to perform color display on the liquid crystal display panel, it is necessary to use a color filter. Therefore, there is a problem that the light utilization efficiency is low. There is also a problem that the color reproduction range is narrow.

  The organic EL display panel is configured by using a low-temperature polysilicon transistor array. However, since the organic EL element emits light by current, there is a problem that display unevenness occurs when the transistor characteristics vary.

  Display unevenness can be reduced by adopting a current programming system for the pixels. In order to implement the current program, a current drive type driver circuit is required. However, variation also occurs in the transistor elements constituting the current output stage in the current drive type driver circuit. For this reason, there is a problem in that the gradation output current from each output terminal varies and a good image display cannot be performed.

In order to achieve this object, the driver circuit of the EL display panel (EL display device) of the present invention includes a plurality of transistors that output unit current, and outputs output current by changing the number of transistors. It is. Further, it is characterized by being composed of a multi-stage current mirror circuit. A transistor group in which signal transfer is voltage transfer is formed densely, and signal transfer with the current mirror circuit group adopts a current transfer configuration. The reference current is performed by a plurality of transistors.

Since the source driver circuit of the present invention is formed so that the transistors constituting the cant mirror circuit are adjacent to each other, variation in output current due to a shift in threshold value is small. Therefore, it is possible to suppress the occurrence of luminance unevenness in the EL display panel, and its practical effect is great.

  In addition, the display panel, the display device, and the like of the present invention exhibit distinctive effects according to their respective configurations such as high image quality, good moving image display performance, low power consumption, low cost, and high luminance.

  Note that if the present invention is used, a low power consumption information display device or the like can be configured, so that power is not consumed. Moreover, since it can be reduced in size and weight, resources are not consumed. Further, even a high-definition display panel can be sufficiently handled. Therefore, it is friendly to the global environment and space environment.

  In the present specification, each drawing is omitted or / and enlarged or reduced for easy understanding and / or drawing. For example, in the cross-sectional view of the display panel shown in FIG. 11, the thin film sealing film 111 and the like are shown to be sufficiently thick. On the other hand, in FIG. 10, the sealing lid 85 is shown thinly. Also, there are some omitted parts. For example, in the display panel of the present invention, a phase film such as a circularly polarizing plate is necessary for preventing reflection. However, it is omitted in each drawing of this specification. The same applies to the following drawings. Moreover, the part which attached | subjected the same number or the symbol etc. has the same or similar form, material, function, or operation | movement.

  Note that the contents described in the drawings and the like can be combined with other embodiments and the like without particular notice. For example, a touch panel or the like is added to the display panel of FIG. 8, and the information display device illustrated in FIGS. 157 and 159 to 161 can be obtained. Further, a viewfinder (see FIG. 58) used for a video camera (see FIG. 159, etc.) can be configured by attaching a magnifying lens 1582.

  4, 15, 18, 21, 23, 29, 30, 35, 36, 40, 41, 44, 100 to 110, 125 to 131, 133 to 146, 197 to 205, 234 to 244, 255 to 264, 276 to 302, 327 to 336, 355 to 358, 362 to 373, and 381 The driving method of the present invention described in FIGS. 384, 386, 396 to 398, and 404 to 406 can be applied to any display device or display panel of the present invention.

  Note that in this specification, the driving transistor 11 and the switching transistor 11 are described as thin film transistors, but the present invention is not limited thereto. A thin film diode (TFD), a ring diode, or the like can also be used. The transistor is not limited to a thin film element, and may be a transistor formed on a silicon wafer. The substrate 71 may be formed of a silicon wafer. Of course, an FET, a MOS-FET, a MOS transistor, or a bipolar transistor may be used. These are also basically thin film transistors. In addition, it goes without saying that varistors, thyristors, ring diodes, photodiodes, phototransistors, PLZT elements may be used. That is, any of these can be used for the transistor element 11, the gate driver circuit 12, the source driver circuit 14, and the like of the present invention.

  Hereinafter, the EL panel of the present invention will be described with reference to the drawings. As shown in FIG. 10, the organic EL display panel includes at least one of an electron transport layer, a light emitting layer, a hole transport layer, and the like on a glass plate 71 (array substrate) on which a transparent electrode 105 as a pixel electrode is formed. An organic functional layer (EL layer) 15 and a metal electrode (reflection film) (cathode) 106 are laminated. A positive voltage is applied to the anode (anode), which is the transparent electrode (pixel electrode) 105, and a negative voltage is applied to the cathode (cathode) of the metal electrode (reflection electrode) 106, that is, a direct current is applied between the transparent electrode 105 and the metal electrode 106. As a result, the organic functional layer (EL layer) 15 emits light.

  The metal electrode 106 is preferably made of a material having a small work function such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy thereof. In particular, for example, an Al—Li alloy is preferably used. The transparent electrode 105 can be made of a conductive material having a high work function such as ITO or gold. When gold is used as an electrode material, the electrode is in a semitransparent state. ITO may be other materials such as IZO. The same applies to the other pixel electrodes 105.

  A desiccant 107 is disposed in the space between the sealing lid 85 and the array substrate 71. This is because the organic EL film 15 is vulnerable to humidity. The desiccant 107 absorbs moisture penetrating the sealant and prevents the organic EL film 15 from deteriorating.

  A problem of an EL display panel (EL display device) is a reduction in contrast caused by halation occurring inside the panel. This occurs because light generated from the EL element 15 (pixel 16) is confined within the panel and diffusely reflected.

  In order to solve this problem, in the present invention, as shown in FIG. 388, a light absorption film 3881 is formed or arranged in a display area (ineffective area) ineffective for image display. By forming the light absorption film 3881, light (indicated by a light locus 3882) generated from the pixel 16 is diffusely reflected by the substrate 71 or the like, and display contrast deterioration due to generated halation can be suppressed.

  Note that the invalid area includes the side surface of the substrate 71 or the lid 85, the substrate 71 other than the display area (for example, an area where the gate driver 12 is formed, etc.), the entire surface of the lid 85 (in the case of lower extraction), and the like.

  As illustrated in FIG. 388, light 3883 that is irregularly reflected in the substrate 71 is absorbed by the light absorption film 3881. It is also effective to form the sealing lid 85 with a black material or the like.

  In FIG. 388 (a), the end of the panel is formed or configured in an oblique shape. The formation area of the light absorption film 3881 can be widened by forming or configuring in an oblique shape. Therefore, light (light locus 3882) that halates in the substrate 71 of the panel can be absorbed more efficiently, and display contrast can be improved.

  Substances that make up the light absorption film include organic materials such as acrylic resins containing carbon, black pigments or pigments dispersed in organic resins, and gelatin or casein as a color filter. What was dye | stained with the acid dye is illustrated. In addition, a single black fluoran dye may be used, and a color scheme black obtained by mixing a green dye and a red dye may also be used. Examples thereof include a PrMnO3 film formed by sputtering and a phthalocyanine film formed by plasma polymerization.

  The above materials are all black materials, but as the light absorption film, a material having a complementary color with respect to the light color generated by the display element may be used. For example, a light-absorbing material for a color filter may be used so as to obtain desired light absorption characteristics. Basically, a material obtained by dyeing a natural resin with a pigment may be used in the same manner as the black absorbing material described above. Further, a material in which a pigment is dispersed in a synthetic resin can be used. The selection range of the pigment is wider than the black pigment, and may be one suitable from azo dye, anthraquinone dye, phthalocyanine dye, triphenylmethane dye, or a combination of two or more thereof.

  Further, a metal material may be used as the light absorption film. For example, hexavalent chromium is exemplified. Hexavalent chromium is black and functions as a light absorbing film. In addition, light scattering materials such as opal glass and titanium oxide may be used. This is because scattering the light is equivalent to absorbing the light as a result.

  Needless to say, the above items can also be applied to the configuration of FIG.

  FIG. 10 shows a configuration in which sealing is performed using a glass lid 85, but sealing may be performed using a film (which may be a thin film, that is, a thin film sealing film) 111 as illustrated in FIG. For example, as the sealing film (thin film sealing film) 111, it is exemplified to use a film of an electrolytic capacitor obtained by vapor-depositing DLC (diamond-like carbon). This film has extremely poor moisture permeability (high moisture resistance). This film is used as the sealing film 111. Needless to say, a structure in which a DLC (diamond-like carbon) film or the like is directly deposited on the surface of the electrode 106 is preferable. In addition, a thin film sealing film may be configured by laminating a resin thin film and a metal thin film in multiple layers.

  The film thickness of the thin film is calculated by n · d (where n is the refractive index of the thin film, and when a plurality of thin films are stacked, the refractive indexes thereof are combined (calculate n · d of each thin film)). When the plurality of thin films are laminated, their refractive indexes are calculated together.) Is preferably equal to or less than the emission main wavelength λ of the EL element 15. By satisfying this condition, the light extraction efficiency from the EL element 15 becomes twice or more as compared with the case of sealing with a glass substrate. Further, an alloy or a mixture or a laminate of aluminum and silver may be formed.

  A configuration in which sealing is performed with the sealing film 111 without using the lid 85 as described above is referred to as thin film sealing. Thin film encapsulation in the case of “lower extraction (see FIG. 10, the light extraction direction is the arrow direction in FIG. 10)” for extracting light from the substrate 71 side becomes a cathode on the EL film after forming the EL film. An aluminum electrode is formed. Next, a resin layer as a buffer layer is formed on the aluminum film. Examples of the buffer layer include organic materials such as acrylic and epoxy. Further, the film thickness is suitably 1 μm or more and 10 μm or less. More preferably, the film thickness is 2 μm or more and 6 μm or less. A sealing film 74 on the buffer film is formed. Without the buffer film, the structure of the EL film collapses due to the stress, and a line-like defect occurs. As described above, the sealing film 111 is exemplified by DLC (Diamond Like Carbon) or a layer structure of an electric field capacitor (a structure in which dielectric thin films and aluminum thin films are alternately deposited).

  In the case of extracting light from the EL layer 15 side, see “Upper extraction see FIG. 11, the light extraction direction is the direction of the arrow in FIG. 11”, thin film encapsulation is performed after the EL film 15 is formed and then the cathode ( An Ag—Mg film to be an anode is formed with a film thickness of 20 Å or more and 300 Å. A transparent electrode such as ITO is formed thereon to reduce the resistance. Next, a resin layer as a buffer layer is formed on the electrode film. A sealing film 111 is formed on the buffer film.

  Half of the light generated from the organic EL layer 15 is reflected by the reflective film 106 and transmitted through the array substrate 71 to be emitted. However, external light is reflected on the reflective film 106 and a reflection occurs to reduce the display contrast. For this measure, a λ / 4 plate 108 and a polarizing plate (polarizing film) 109 are arranged on the array substrate 71. These are generally called circularly polarizing plates (circularly polarizing sheets).

  When the pixel is a reflective electrode, the light generated from the EL layer 15 is emitted upward. Therefore, it goes without saying that the phase plate 108 and the polarizing plate 109 are arranged on the light emitting side. The reflective pixel is obtained by forming the pixel electrode 105 with aluminum, chromium, silver, or the like. Further, by providing a convex portion (or a concave-convex portion) on the surface of the pixel electrode 105, the interface with the organic EL layer 15 is widened, the light emitting area is increased, and the luminous efficiency is improved. Note that the circularly polarizing plate is not necessary when the reflective film to be the cathode 106 (anode 105) is formed on the transparent electrode or when the reflectance can be reduced to 30% or less. This is because the reflection is greatly reduced. It is also desirable to reduce light interference.

  The transistor 11 preferably employs an LDD (lightly doped drain) structure. In this specification, an organic EL element (described by various abbreviations such as OEL, PEL, PLED, and OLED) 15 is described as an example of the EL element, but the present invention is not limited to this. Needless to say, this also applies.

First, the active matrix method used for organic EL display panels is:
A specific pixel can be selected and given display information can be given.
Two conditions must be satisfied that current can flow through the EL element throughout one frame period.

  In order to satisfy these two conditions, in the conventional organic EL pixel configuration shown in FIG. 46, the first transistor 11b is a switching transistor for selecting a pixel, and the second transistor 11a is an EL element (EL film). ) A driving transistor for supplying current to 15.

  In the case of displaying gradation using this configuration, it is necessary to apply a voltage corresponding to the gradation as the gate voltage of the driving transistor 11a. Therefore, the variation in the on-state current of the driving transistor 11a appears in the display as it is.

  The on-current of a transistor is very uniform if it is a transistor formed of a single crystal, but in a low-temperature polycrystalline transistor formed by low-temperature polysilicon technology that can be formed on an inexpensive glass substrate with a formation temperature of 450 degrees or less. The threshold value varies in the range of ± 0.2V to 0.5V. For this reason, the on-current flowing through the driving transistor 11a varies correspondingly, and the display is uneven. These irregularities are caused not only by variations in threshold voltage, but also by transistor mobility, gate insulating film thickness, and the like. The characteristics also change due to deterioration of the transistor 11.

  This phenomenon is not limited to low-temperature polysilicon technology, and transistors and the like are formed using solid-phase (CGS) grown semiconductor films even in high-temperature polysilicon technology with a process temperature of 450 degrees Celsius or higher. Even things can occur. In addition, it occurs in organic transistors. It also occurs in amorphous silicon transistors.

  The present invention described below is a configuration or method that can cope with these techniques. In this specification, a transistor formed by low-temperature polysilicon technology will be mainly described.

  Therefore, as shown in FIG. 46, in the method of displaying gradation by writing a voltage, it is necessary to strictly control the device characteristics in order to obtain a uniform display. However, the current low-temperature polycrystalline polysilicon transistor and the like cannot satisfy the specification of suppressing this variation within a predetermined range.

  Specifically, the pixel structure of the EL display device of the present invention is formed by a plurality of transistors 11 and EL elements each having at least four unit pixels as shown in FIG. The pixel electrode is configured to overlap the source signal line. That is, an insulating film or a planarizing film made of an acrylic material is formed on the source signal line 18 for insulation, and the pixel electrode 105 is formed on the insulating film. Such a configuration in which the pixel electrode is overlaid on at least a part on the source signal line 18 is referred to as a high aperture (HA) structure. Unnecessary interference light and the like are reduced, and a good light emission state can be expected.

  By activating the gate signal line (first scanning line) 17a (applying an ON voltage), the current value to be passed through the EL element 15 through the driving transistor 11a and the switching transistor 11c of the EL element 15 is sourced. It flows from the driver circuit 14. In addition, the transistor 11b opens when the gate signal line 17a becomes active (applies an ON voltage) so as to short-circuit between the gate and drain of the transistor 11a, and a capacitor (capacitor, capacitor) connected between the gate and source of the transistor 11a. The gate voltage (or drain voltage) of the transistor 11a is stored in the storage capacitor (additional capacitor) 19 (see FIG. 3A).

  Note that the size of the capacitor (storage capacitor) 19 is preferably 0.2 pF or more and 2 pF or less, and in particular, the size of the capacitor (storage capacitor) 19 is preferably 0.4 pF or more and 1.2 pF or less. . The capacitance of the capacitor 19 is determined in consideration of the pixel size. If the capacity required for one pixel is Cs (pF) and the area occupied by one pixel (not the aperture ratio) is Sp (square μm), then 500 / S ≦ Cs ≦ 20000 / S, more preferably 1000 / Sp ≦ Cs ≦ 10000 / Sp. Since the gate capacity of the transistor is small, Q here is the capacity of the storage capacitor (capacitor) 19 alone.

  The gate signal line 17a is inactive (OFF voltage is applied), the gate signal line 17b is active, and the current flow path includes the transistor 11d and the EL element 15 connected to the first transistor 11a and the EL element 15. The operation is switched to the path so that the stored current flows through the EL element 15 (see FIG. 3B).

  This circuit has four transistors 11 in one pixel, and the gate of the transistor 11a is connected to the source of the transistor 11b. The gates of the transistors 11b and 11c are connected to the gate signal line 17a. The drain of the transistor 11 b is connected to the source of the transistor 11 c and the source of the transistor 11 d, and the drain of the transistor 11 c is connected to the source signal line 18. The gate of the transistor 11d is connected to the gate signal line 17b, and the drain of the transistor 11d is connected to the anode electrode of the EL element 15.

  In FIG. 1, all the transistors are P-channel. The P channel has a lower mobility than an N channel transistor, but is preferable because it has a high breakdown voltage and is less likely to deteriorate. However, the present invention is not limited to the configuration of the EL element with the P channel. You may comprise only N channel. Moreover, you may comprise using both N channel and P channel.

  Optimally, it is preferable that all the transistors 11 constituting the pixel are formed by the P channel, and the built-in gate driver 12 is also formed by the P channel. By forming the array with only P-channel transistors in this way, the number of masks becomes five, and cost reduction and high yield can be realized.

  Hereinafter, in order to facilitate the understanding of the present invention, the EL element configuration of the present invention will be described with reference to FIG. The EL device configuration of the present invention is controlled by two timings. The first timing is a timing for storing a necessary current value. When the transistor 11b and the transistor 11c are turned on at this timing, an equivalent circuit is shown in FIG. Here, a predetermined current Iw is written from the signal line. As a result, the gate and drain of the transistor 11a are connected, and a current Iw flows through the transistor 11a and the transistor 11c. Therefore, the gate-source voltage of the transistor 11a is a voltage at which I1 flows.

  The second timing is a timing at which the transistor 11a and the transistor 11c are closed and the transistor 11d is opened, and the equivalent circuit at that time is shown in FIG. The voltage between the source and gate of the transistor 11a remains held. In this case, since the transistor 11a always operates in the saturation region, the current Iw is constant.

  When operated in this way, it is as shown in FIG. That is, 51a in FIG. 5A indicates a pixel (row) (write pixel row) in the display screen 50 that is current-programmed at a certain time. This pixel (row) 51a is not lit (non-display pixel (row)) as shown in FIG. The other pixel (row) is a display pixel (row) 53 (current flows through the EL element 15 of the pixel 16 in the display area 53, and the EL element 15 emits light).

  In the case of the pixel configuration of FIG. 1, as shown in FIG. 3A, the program current Iw flows through the source signal line 18 during current programming. The voltage is set (programmed) in the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing through Iw is maintained. At this time, the transistor 11d is in an open state (off state).

  Next, during a period in which a current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d is operated as shown in FIG. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d is turned on.

  This timing chart is shown in FIG. In FIG. 4 and the like, subscripts in parentheses (for example, (1) and the like) indicate pixel row numbers. That is, the gate signal line 17a (1) indicates the gate signal line 17a of the pixel row (1). Also, * H in the upper part of FIG. 4 (an arbitrary symbol or numerical value is applied to “*” and indicates a horizontal scanning line number) indicates a horizontal scanning period. That is, 1H is the first horizontal scanning period. The above items are for ease of explanation and are not limited (1H number, 1H cycle, order of pixel row numbers, etc.).

  As can be seen from FIG. 4, when a turn-on voltage is applied to the gate signal line 17a in each selected pixel row (selection period is 1H), a turn-off voltage is applied to the gate signal line 17b. Yes. During this period, no current flows through the EL element 15 (non-lighting state). In an unselected pixel row, an off voltage is applied to the gate signal line 17a, and an on voltage is applied to the gate signal line 17b. Further, during this period, a current flows through the EL element 15 (lighting state).

  Note that the gate of the transistor 11a and the gate of the transistor 11c are connected to the same gate signal line 11a. However, the gate of the transistor 11a and the gate of the transistor 11c may be connected to different gate signal lines 11 (see FIG. 32). One pixel has three gate signal lines (the configuration in FIG. 1 is two). By individually controlling the ON / OFF timing of the gate of the transistor 11b and the ON / OFF timing of the gate of the transistor 11c, variation in the current value of the EL element 15 due to variations in the transistor 11a can be further reduced.

  When the gate signal line 17a and the gate signal line 17b are made common and the transistors 11c and 11d have different conductivity types (N channel and P channel), the drive circuit can be simplified and the aperture ratio of the pixel can be improved. .

  With this configuration, the write path from the signal line is turned off as the operation timing of the present invention. That is, when a predetermined current is stored, if there is a branch in the current flow path, an accurate current value is not stored in the capacitance (capacitor) between the source (S) and the gate (G) of the transistor 11a. By making the transistors 11c and 11d have different conductivity types, the transistor 11d can be turned on after the transistor 11c is always turned off at the timing of switching of the scanning lines by controlling the threshold values of the transistors 11c and 11d.

  In this case, however, it is necessary to carefully control each other's thresholds, so care must be taken in the process. Although the circuit described above can be realized with at least four transistors, the transistor 11e is cascade-connected as shown in FIG. 2 to control the timing more accurately or to reduce the mirror effect as described later. The operation principle is the same even when the total number of transistors is 4 or more. With the configuration in which the transistor 11e is added as described above, the current programmed through the transistor 11c can be supplied to the EL element 15 with higher accuracy.

  Note that the pixel configuration of the present invention is not limited to the configurations of FIGS. For example, it may be configured as shown in FIG. 113 does not have the switch element 11d as compared with the configuration of FIG. Instead, a changeover switch 1131 is formed or arranged. The switch 11d in FIG. 1 has a function of controlling on / off (flow or not flow) of a current flowing from the driving transistor 11a to the EL element 15. As will be described in the following embodiments, the on / off control function of the transistor 11d is an important component of the present invention. The configuration in FIG. 113 realizes an on / off function without forming the transistor 11d.

  In FIG. 113, the terminal a of the changeover switch 1131 is connected to the anode voltage Vdd. The voltage applied to the terminal a is not limited to the anode voltage Vdd, and any voltage that can turn off the current flowing through the EL element 15 may be used.

  The b terminal of the changeover switch 1131 is connected to the cathode voltage (shown as ground in FIG. 113). The voltage applied to the b terminal is not limited to the cathode voltage, and any voltage that can turn on the current flowing through the EL element 15 may be used.

  The cathode terminal of the EL element 15 is connected to the c terminal of the changeover switch 1131. Note that the change-over switch 1131 may be any as long as it has a function of turning on and off the current flowing through the EL element 15. Therefore, it is not limited to the formation position in FIG. 113, and any path may be used as long as the current of the EL element 15 flows. Further, the function of the switch is not limited, and any function may be used as long as the current flowing through the EL element 15 can be turned on and off. In other words, in the present invention, any pixel configuration may be used as long as switching means capable of turning on and off the current flowing through the EL element 15 is provided in the current path of the EL element 15.

  Further, “off” does not mean a state in which no current flows completely. Any current can be used as long as the current flowing through the EL element 15 can be reduced more than usual. The above matters are the same in other configurations of the present invention.

  Since the change-over switch 1131 can be easily realized by combining a P-channel transistor and an N-channel transistor, description thereof will not be required. For example, two analog switches may be formed. Of course, since the switch 1131 only turns on and off the current flowing through the EL element 15, it is needless to say that the switch 1131 can be formed of a P-channel transistor or an N-channel transistor.

  When the switch 1131 is connected to the a terminal, the Vdd voltage is applied to the cathode terminal of the EL element 15. Therefore, no current flows through the EL element 15 regardless of the voltage holding state of the gate terminal G of the driving transistor 11a. Therefore, the EL element 15 is not turned on.

  When the switch 1131 is connected to the b terminal, the GND voltage is applied to the cathode terminal of the EL element 15. Therefore, a current flows through the EL element 15 in accordance with the voltage state held at the gate terminal G of the driving transistor 11a. Therefore, the EL element 15 is turned on.

  From the above, in the pixel configuration of FIG. 113, the switching transistor 11 d is not formed between the driving transistor 11 a and the EL element 15. However, the lighting control of the EL element 15 can be performed by controlling the switch 1131.

  In the pixel configuration shown in FIGS. 1 and 2, the number of driving transistors 11a is one per pixel. The present invention is not limited to this, and a plurality of driving transistors 11a may be formed or arranged in one pixel. FIG. 116 shows an example. In FIG. 116, two driving transistor elements 11 a 1 and 11 a 2 are formed in one pixel, and the gate terminals of the two driving transistors 11 a 1 and 11 a 2 are connected to a common capacitor 19. By forming a plurality of driving transistors 11a, there is an effect that variation in programmed current is reduced. Other configurations are the same as those in FIG.

  1 and 2, the current output from the driving transistor 11a is supplied to the EL element 15, and the current is on / off controlled by the switching element 11d disposed between the driving transistor 11a and the EL element 15. In FIG. However, the present invention is not limited to this. For example, the configuration of FIG. 117 is illustrated.

  In the embodiment of FIG. 117, the current flowing through the EL element 15 is controlled by the driving transistor 11a. Switching on and off the current flowing through the EL element 15 is controlled by the switching element 11 d disposed between the Vdd terminal and the EL element 15. Therefore, in the present invention, the arrangement of the switching element 11d may be anywhere, and any arrangement can be used as long as the current flowing through the EL element 15 can be controlled. The operation and the like are similar to those in FIG.

  Further, in the pixel configuration in FIG. 387, all the transistors are configured by N channels. However, the present invention is not limited to the configuration of the EL element composed of N channels. You may comprise using both N channel and P channel.

  Hereinafter, the pixel configuration in FIG. 387 is controlled by two timings. The first timing is a timing for storing a necessary current value.

  At this timing, an ON voltage (Vgh) is applied to the gate signal line 17a, whereby the transistor 11b and the transistor 11c are turned on. Further, an off voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d is turned off. Therefore, a predetermined current Iw is written from the source signal line 18. As a result, the gate of the transistor 11a is connected to the drain, and a program current flows through the transistor 11a and the transistor 11c.

  In the second timing, an off voltage is applied to the gate signal line 17a, and an on voltage is applied to the gate signal line 17b. Therefore, the transistors 11a and 11c are closed and the transistor 11d is opened. In this case, since the transistor 11a always operates in the saturation region, the current Iw is constant.

  The variation in the characteristics of the transistor 11a has a correlation with the transistor size. In order to reduce the characteristic variation, the channel length of the first transistor 11a is preferably 5 μm or more and 100 μm or less. More preferably, the channel length of the first transistor 11a is 10 μm or more and 50 μm or less. This is considered to be because when the channel length L is increased, the grain boundary included in the channel increases, the electric field is relaxed, and the kink effect is suppressed to a low level.

  As described above, the present invention controls the current flowing through the EL element 15 in the path through which current flows into the EL element 15 or the path through which current flows from the EL element 15 (that is, the current path of the EL element 15). The circuit means is configured, formed or arranged.

  Even in the current mirror system which is one of current programming systems, as shown in FIG. 114, an EL element is formed by arranging or arranging a transistor 11g as a switching element between the driving transistor 11b and the EL element 15. The current flowing through 15 can be turned on and off (can be controlled). Of course, the transistor 11g may be replaced with the switch 1131 in FIG.

  114 are connected to one gate signal line 17a. However, as shown in FIG. 115, the transistor 11c is controlled by the gate signal line 17a1, and the transistor 11d has a gate signal. You may comprise so that it may control by the line 17a2. 115 is more versatile in controlling the pixel 16.

  Further, as illustrated in FIG. 42A, the transistors 11b and 11c may be formed of N-channel transistors. Further, as shown in FIG. 42B, the transistors 11c, 11d and the like may be formed of P-channel transistors.

  In the configuration of the pixel 16 described above, the number of transistors constituting the pixel 16 is 4 or 5 or more. However, the present invention is not limited to this. As shown in FIG. 261, it may be composed of five or more transistors. In FIG. 261, by using the driving transistors 11a1 and 11a2, it is possible to perform current programming without insufficient writing even in a low gradation region.

  Hereinafter, a driving method of the pixel configuration illustrated in FIG. 261 will be described. The pixel configuration in FIG. 261 includes three driving states as shown in FIG. The first state is shown in FIG. The second state is shown in FIG. The third state is shown in FIG. The first state and the second state are states in which current programming is performed, and the third state is a state in which a current is passed through the EL element 15 and the EL element 15 emits light. It is to be noted that performing the duty control by opening or closing the switching transistor 11d1 is the same as in the other embodiments of the present invention, and thus the description thereof is omitted.

  The pixel configuration in FIG. 261 includes a source signal line 18a and a source signal line 18b. Basically, the current is programmed so that the difference between the program current applied to the source signal line 18a and the program current applied to the source signal line 18b flows to the driving transistor 11a1, and this current flows to the EL element 15. For ease of explanation, it is assumed that the program current I1 = 10 μA flows through the source signal line 18a, the program current I3 = 10.1 μA flows through the source signal line 18b, and I2 = the difference between I1 and I3 flows through the driving transistor 11a1. Let us write 0.1 μA.

  In the first state, as illustrated in FIG. 265, the transistor 11c2 and the transistor 11b2 are closed, and the transistor d2, the transistor 11b1, the transistor 11d1, and the transistor 11c1 are opened.

  As shown in FIG. 262, the program current I1 flows from the anode terminal to the source signal line 18a via the driving transistor 11a2. The program current I1 is generated by the source driver IC14. The program current I1 is held by the capacitor 19b (a voltage is held at the gate terminal of the drive transistor 11a2 so that the drive transistor 11a2 can pass the program current I1). The other switching transistors 11 are off. With the first state described above, the driving transistor 11a2 is programmed so that the program current I1 flows.

  In the second state, as illustrated in FIG. 265, the transistor 11d2, the transistor 11b1, and the transistor 11c1 are closed, and the transistor 11c2, the transistor 11b2, and the transistor 11d1 are opened.

  As shown in FIG. 263, the program current I3 flows from the anode terminal to the source signal line 18b via the driving transistor 11a1. Program current I3 is generated by source driver IC14.

  Of the program current I3 = 10.1 μA, the program current I1 = 10 μA is supplied by the driving transistor 11a2. Therefore, the driving transistor 11a1 supplies a current of I2 = 0.1 μA, which is the difference between the program currents I1 and I3. The program current I2 flows from the anode terminal to the source signal line 18b through the driving transistor 11a1.

  The program current I2 is held by the capacitor 19a (a voltage is held at the gate terminal of the drive transistor 11a1 so that the drive transistor 11a1 can pass the program current I2). Therefore, the current that flows through the EL element 15 is programmed in the driving transistor 11a1. The current flowing through the EL element 15 is as small as 0.1 μA. However, the current flowing through the source signal lines 18a and 18b is as large as 10 μA. Therefore, it is possible to current-program a minute current flowing through the EL element 15 without being affected by the parasitic capacitance of the source signal line 18.

  The third state is a state in which the EL element current is supplied and the EL element 15 emits light. In the third state, as shown in FIG. 265, the transistor 11d1 is closed and the other switching transistors 11 are opened. As shown in FIG. 264, due to the voltage held at the gate terminal of the driving transistor 11a1, a current I2 flows through the driving transistor 11a1, and the EL element 15 emits light. By performing on / off control of the switching transistor 11d1, duty control can be performed as in FIG.

  The object of the invention of this patent is to propose a circuit configuration in which variations in transistor characteristics do not affect display, and for that purpose four or more transistors are required. When circuit constants are determined based on these transistor characteristics, it is difficult to obtain appropriate circuit constants if the characteristics of the four transistors do not match. When the channel direction is horizontal and vertical with respect to the major axis direction of laser irradiation, the threshold value and mobility of transistor characteristics are different. In both cases, the degree of variation is the same. The average value of mobility and threshold value differs between the horizontal direction and the vertical direction. Therefore, it is desirable that the channel directions of all the transistors constituting the pixel are the same.

  Further, when the capacitance value of the storage capacitor 19 is Cs and the off-current value of the second transistor 11b is Ioff, it is preferable to satisfy the following equation.

3 <Cs / Ioff <24
More preferably, it is preferable to satisfy the following formula.

6 <Cs / Ioff <18
By setting the off-state current of the transistor 11b to 5 pA or less, the change in the current value flowing through the EL can be suppressed to 2% or less. This is because when the leakage current increases, the electric charge stored between the gate and the source (both ends of the capacitor) cannot be held for one field in the voltage non-writing state. Therefore, if the storage capacity of the capacitor 19 is large, the allowable amount of off-current is also large. By satisfying the above equation, the fluctuation of the current value between adjacent pixels can be suppressed to 2% or less.

  In addition, it is preferable to adopt a multi-gate structure in which the transistors constituting the active matrix are configured as p-channel polysilicon thin film transistors and the transistor 11b is a dual gate or higher. Since the transistor 11b functions as a switch between the source and drain of the transistor 11a, the transistor 11b is required to have as high a ON / OFF ratio as possible. By setting the gate structure of the transistor 11b to a multi-gate structure that is equal to or higher than the dual gate structure, a characteristic with a high ON / OFF ratio can be realized.

  The semiconductor film constituting the transistor 11 of the pixel 16 is generally formed by laser annealing in the low temperature polysilicon technology. Variations in the laser annealing conditions result in variations in transistor 11 characteristics. However, if the characteristics of the transistors 11 in one pixel 16 match, the current programming method shown in FIG. 1 can be driven so that a predetermined current flows through the EL element 15. This is an advantage not found in voltage programming. An excimer laser is preferably used as the laser.

  In the present invention, the formation of the semiconductor film is not limited to the laser annealing method, but may be a thermal annealing method or a method by solid phase (CGS) growth. In addition, the present invention is not limited to the low temperature polysilicon technology, and it goes without saying that the high temperature polysilicon technology may be used. Further, it may be a semiconductor film formed using amorphous silicon technology.

  To deal with this problem, in the present invention, as shown in FIG. 7, a laser irradiation spot (laser irradiation range) 72 at the time of annealing is irradiated in parallel to the source signal line 18. Further, the laser irradiation spot 72 is moved so as to coincide with one pixel column. Of course, the present invention is not limited to one pixel column. For example, RGB in FIG. 55 may be irradiated with laser in units of one pixel 16 (in this case, it is a three pixel column). In addition, a plurality of pixels may be irradiated simultaneously. It goes without saying that the movement of the laser irradiation range may overlap (usually, the irradiation range of the moving laser light is usually overlapped).

  The pixels are made of three pixels of RGB and have a square shape. Accordingly, each of the R, G, and B pixels has a vertically long pixel shape. Therefore, by annealing the laser irradiation spot 72 in a vertically long shape, the characteristic variation of the transistor 11 can be prevented from occurring within one pixel. Further, the characteristics (mobility, Vt, S value, etc.) of the transistor 11 connected to one source signal line 18 can be made uniform (that is, the characteristics are different from those of the transistor 11 of the adjacent source signal line 18). However, the characteristics of the transistor 11 connected to one source signal line can be made substantially equal).

  In the configuration of FIG. 7, three panels are formed vertically within the range of the length of the laser irradiation spot 72. The annealing apparatus that irradiates the laser irradiation spot 72 recognizes the positioning markers 73a and 73b of the glass substrate 74 (automatic positioning by pattern recognition) and moves the laser irradiation spot 72. The positioning marker 73 is recognized by a pattern recognition device. An annealing apparatus (not shown) recognizes the positioning marker 73 and extracts the position of the pixel column (makes the laser irradiation range 72 parallel to the source signal line 18). The laser irradiation spot 72 is irradiated so as to overlap the pixel column position, and annealing is sequentially performed.

  The laser annealing method described in FIG. 7 (method of irradiating a line-shaped laser spot in parallel with the source signal line 18) is preferably employed particularly in the current programming method of the organic EL display panel. This is because the characteristics of the transistor 11 match in the direction parallel to the source signal line (the characteristics of the pixel transistors adjacent in the vertical direction are approximate). Therefore, there is little change in the voltage level of the source signal line at the time of current driving, and current writing shortage hardly occurs.

  For example, in the case of white raster display, the current flowing through the transistor 11a of each adjacent pixel is almost the same, so the change in the current amplitude output from the source driver IC 14 is small. If the characteristics of the transistor 11a in FIG. 1 are the same and the current values to be programmed in each pixel are the same in the pixel columns, the potential of the source signal line 18 at the time of current programming is constant. Therefore, the potential fluctuation of the source signal line 18 does not occur. If the characteristics of the transistors 11a connected to one source signal line 18 are almost the same, the potential fluctuation of the source signal line 18 is small. This is the same for other current-programmed pixel configurations such as FIG. 38 (that is, it is preferable to apply the manufacturing method of FIG. 7).

  In addition, uniform image display (since display unevenness due to variations in transistor characteristics is unlikely to occur) can be realized by a method of simultaneously writing a plurality of pixel rows described with reference to FIGS. In FIG. 27 and the like, a plurality of pixel rows are selected at the same time. Therefore, if the transistors in adjacent pixel rows are uniform, the transistor circuit unevenness in the vertical direction can be absorbed by the driver circuit.

  In FIG. 7, the source driver circuit 14 is illustrated as having an IC chip mounted thereon; however, the present invention is not limited to this, and the source driver circuit 14 may be formed in the same process as the pixel 16. Needless to say.

  The characteristic distribution of the driving transistor 11a of the array 71 also occurs in the doping process. As shown in FIG. 346 (a), the doping head 3461 has holes for doping at equal intervals. Therefore, as shown in FIG. 346 (a), the characteristic distribution due to doping occurs in a streak shape. In the manufacturing method of the present invention, as shown in FIG. 346, the characteristic distribution direction by doping (FIG. 346 (a)), the characteristic distribution direction by laser annealing direction (FIG. 346 (b)), and the source signal line 18 The formation direction (FIG. 346 (c)) is made to coincide. By configuring (forming) as described above, it is possible to satisfactorily realize the characteristic compensation of the driving transistor 11a in the current driving method.

  In the present invention, in particular, the threshold voltage Vth2 of the driving transistor 11b is set not to be lower than the threshold voltage Vth1 of the corresponding driving transistor 11a in the pixel. For example, the gate length L2 of the transistor 11b is made longer than the gate length L1 of the transistor 11a so that Vth2 does not become lower than Vth1 even if the process parameters of these thin film transistors vary. Thereby, a minute current leak can be suppressed.

  The above items can also be applied to the pixel configuration of the current mirror shown in FIG. In FIG. 38, the pixel circuit and the data line data are controlled by controlling the gate signal line 17a1 in addition to the driving transistor 11b for controlling the driving current flowing in the light emitting element including the driving transistor 11a and the EL element 15 through which the signal current flows. The switching transistor 11d that short-circuits the gate and drain of the transistor 11a during the writing period and the gate-source voltage of the transistor 11a are held even after the writing is finished, by controlling the take-in transistor 11c to be connected or cut off and the gate signal line 17a2. For example, a capacitor C19 and an EL element 15 as a light emitting element.

  In FIG. 38, the transistors 11c and 11d are N-channel transistors, and the other transistors are P-channel transistors. However, this is an example, and this is not necessarily the case. The capacitor Cs has one terminal connected to the gate of the transistor 11a and the other terminal connected to Vdd (power supply potential). However, the capacitor Cs is not limited to Vdd, and may be any constant potential. The cathode (cathode) of the EL element 15 is connected to the ground potential.

  Next, the EL display panel or EL display device of the present invention will be described. FIG. 6 is an explanatory diagram focusing on the circuit of the EL display device. Pixels 16 are arranged or formed in a matrix. Each pixel 16 is connected to a source driver circuit 14 that outputs a current for current programming of each pixel. A current mirror circuit corresponding to the number of bits of the video signal is formed at the output stage of the source driver circuit 14 (described later). For example, in the case of 64 gradations, 63 current mirror circuits are formed in each source signal line, and a desired current can be applied to the source signal line 18 by selecting the number of these current mirror circuits. (See FIG. 48).

  The minimum output current of one current mirror circuit is 10 nA or more and 50 nA. In particular, the minimum output current of the current mirror circuit is preferably 15 nA or more and 35 nA. This is to ensure the accuracy of the transistors constituting the current mirror circuit in the driver IC 14.

  A precharge or discharge circuit for forcibly releasing or charging the source signal line 18 is incorporated. The voltage (current) output value of the precharge or discharge circuit that forcibly releases or charges the source signal line 18 is preferably configured to be set independently by R, G, and B. This is because the threshold value of the EL element 15 is different between RGB (refer to FIGS. 65 and 67 and the description of the precharge circuit).

  It is known that an organic EL element has a large temperature dependency characteristic (temperature characteristic). In order to adjust the light emission luminance change due to the temperature characteristics, a non-linear element such as a thermistor or a posistor that changes the output current is added to the current mirror circuit, and the temperature characteristics change is adjusted by the thermistor as an analog reference. Adjust (change) the current.

  In the present invention, the source driver 14 is formed of a semiconductor silicon chip, and is connected to the terminal of the source signal line 18 of the substrate 71 by glass-on-chip (COG) technology. The mounting of the source driver 14 is not limited to the COG technology, and the source driver IC 14 described above may be mounted on the chip on film (COF) technology and connected to the signal line of the display panel. Further, the drive IC may have a three-chip configuration by separately producing a power supply IC 82.

  On the other hand, the gate driver circuit 12 is formed by low-temperature polysilicon technology. That is, it is formed by the same process as the pixel transistor. This is because the internal structure is easier and the operating frequency is lower than that of the source driver circuit 14. Therefore, it can be formed easily even if it is formed by a low temperature polysilicon technique, and a narrow frame can be realized. Of course, it goes without saying that the gate driver 12 may be formed of a silicon chip and mounted on the substrate 71 using COG technology or the like. In addition, switching elements such as pixel transistors, gate drivers, and the like may be formed by high-temperature polysilicon technology or organic materials (organic transistors).

  The gate driver 12 includes a shift register circuit 61a for the gate signal line 17a and a shift register circuit 61b for the gate signal line 17b. Each shift register circuit 61 is controlled by positive-phase and negative-phase clock signals (CLKxP, CLKxN) and a start pulse (STx) (see FIG. 6). In addition, it is preferable to add an enable (ENABL) signal for controlling the output and non-output of the gate signal line and an up / down (UPDWM) signal for reversing the shift direction up and down. In addition, it is preferable to provide an output terminal for confirming that the start pulse is shifted to the shift register and output. Note that the shift timing of the shift register is controlled by a control signal from the control IC 81. A level shift circuit for shifting the level of external data is incorporated.

  Since the buffer capacity of the shift register circuit 61 is small, the gate signal line 17 cannot be driven directly. For this reason, at least two or more inverter circuits 62 are formed between the output of the shift register circuit 61 and the output gate 63 that drives the gate signal line 17.

  The same applies to the case where the source driver 14 is directly formed on the substrate 71 by a polysilicon technique such as low-temperature polysilicon. Between the gate of an analog switch such as a transfer gate that drives the source signal line 18 and the shift register of the source driver circuit 14. A plurality of inverter circuits are formed. The following items (the output of the shift register and the output stage that drives the signal line (the matter related to the inverter circuit arranged between the output stage such as the output gate or the transfer gate)) are common to the source drive and the gate drive circuit. is there.

  For example, FIG. 6 shows that the output of the source driver 14 is directly connected to the source signal line 18, but actually, the output of the shift register of the source driver is connected to a multi-stage inverter circuit, The output is connected to the gate of an analog switch such as a transfer gate.

  The inverter circuit 62 includes a P-channel MOS transistor and an N-channel MOS transistor. As described above, the inverter circuit 62 is connected in multiple stages to the output terminal of the shift register circuit 61 of the gate driver circuit 12, and its final output is connected to the output gate circuit 63. Note that the inverter circuit 62 may be composed of only the P channel. However, in this case, it may be configured as a simple gate circuit instead of an inverter.

  FIG. 8 is a configuration diagram of signal and voltage supply of the display device of the present invention or a configuration diagram of the display device. Signals (power supply wiring, data wiring, etc.) supplied from the control IC 81 to the source driver circuit 14 a are supplied via the flexible substrate 84.

  In FIG. 8, the control signal for the gate driver 12 is generated by the control IC, and after the level shift is performed by the source driver 14, it is applied to the gate driver 12. Since the drive voltage of the source driver 14 is 4 to 8 (V), the 3.3 (V) amplitude control signal output from the control IC 81 can be converted to 5 (V) amplitude that the gate driver 12 can receive. it can.

  8 is described as a source driver in FIG. 8 and the like, but not only a driver, but also a power supply circuit, a buffer circuit (including a circuit such as a shift register), a data conversion circuit, a latch circuit, a command decoder, a shift circuit, an address A conversion circuit, an image memory, or the like may be incorporated. Needless to say, the three-side free configuration or configuration described in FIG. 9 or the like, the driving method, or the like can be applied to the configuration described in FIG. 8 or the like.

  As shown in FIG. 361, the substrate 83 on which the control IC 81 and the power supply IC 82 are mounted is arranged so that components and the like are inserted into the recesses formed in the sealing substrate 85 (sealing lid 85). By configuring as in FIG. 361, the panel module can be made compact.

  When the display panel is used for an information display device such as a mobile phone, as shown in FIG. 9, the source driver IC (circuit) 14 and the gate driver IC (circuit) 12 are mounted (formed) on one side of the display panel. (A configuration in which the driver IC (circuit) is mounted (formed) on one side in this way is called a three-side free configuration (structure). Conventionally, the gate driver IC 12 is mounted on the X side of the display area, and Y The source driver IC 14 was mounted on the side). This is because it is easy to design the center line of the screen 50 to be the center of the display device, and it is easy to mount the driver IC. Note that the gate driver circuit may be fabricated with a three-side free configuration using high-temperature polysilicon or low-temperature polysilicon technology (that is, at least one of the source driver circuit 14 and the gate driver circuit 12 in FIG. 9 is polysilicon). Directly formed on the substrate 71 by technology).

  The three-side free configuration is not only a configuration in which an IC is directly stacked or formed on the substrate 71, but also a film (TCP, TAB technology, etc.) on which a source driver IC (circuit) 14, a gate driver IC (circuit) 12, etc. are attached ) Is attached to one side (or almost one side) of the substrate 71. In other words, this means a configuration, arrangement, or all similar to that where no IC is mounted or attached to two sides.

  When the gate driver circuit 12 is arranged beside the source driver circuit 14 as shown in FIG. 9, the gate signal line 17 needs to be formed along the side C.

  In FIG. 9 and the like, a portion indicated by a thick solid line indicates a portion where the gate signal lines 17 are formed in parallel. Therefore, the gate signal lines 17 corresponding to the number of scanning signal lines are formed in parallel in the portion b (lower screen), and one gate signal line 17 is formed in the portion a (upper screen).

  The pitch of the gate signal lines 17 formed on the C side is 5 μm or more and 12 μm or less. If it is less than 5 μm, noise will be applied to the adjacent gate signal line due to the influence of parasitic capacitance. According to the experiment, the influence of the parasitic capacitance is remarkably generated at 7 μm or less. Furthermore, if it is less than 5 μm, image noise such as a beat is generated violently on the display screen. In particular, noise generation differs between the left and right sides of the screen, and it is difficult to reduce image noise such as a beat. On the other hand, if the reduction exceeds 12 μm, the frame width D of the display panel becomes too large to be practical.

  In order to reduce the image noise described above, a grant pattern (a conductive pattern whose voltage is fixed to a constant voltage or set to a stable potential as a whole) is disposed in the lower layer or upper layer of the portion where the gate signal line 17 is formed. Can be reduced. Further, a separately provided shield plate (shield foil (conductive pattern fixed to a constant voltage or set to a stable potential as a whole)) may be disposed on the gate signal line 17.

  Although the gate signal line 17 on the C side in FIG. 9 may be formed of an ITO electrode, it is preferably formed by laminating ITO and a metal thin film in order to reduce resistance. Moreover, it is preferable to form with a metal film. When laminating with ITO, a titanium film is formed on ITO, and an aluminum or aluminum / molybdenum alloy thin film is formed thereon. Alternatively, a chromium film is formed on ITO. In the case of a metal film, it is formed of an aluminum thin film or a chromium thin film. The above matters are the same in other embodiments of the present invention.

  In FIG. 9 and the like, the gate signal lines 17 and the like are arranged on one side of the display area. However, the present invention is not limited to this and may be arranged on both sides. For example, the gate signal line 17a may be disposed (formed) on the right side of the display area 50, and the gate signal line 17b may be disposed (formed) on the left side of the display area 50. The above matters are the same in other embodiments.

  Further, the source driver IC 14 and the gate driver IC 12 may be integrated into one chip. If one chip is used, only one IC chip needs to be mounted on the display panel. Therefore, the mounting cost can be reduced. Various voltages used in the one-chip driver IC can be generated simultaneously.

  The source driver IC 14 and the gate driver IC 12 are made of a semiconductor wafer such as silicon and mounted on the display panel. However, the present invention is not limited to this, and the source driver IC 14 and the gate driver IC 12 are directly formed on the display panel 82 by low-temperature polysilicon technology or high-temperature polysilicon technology. Needless to say.

  The pixels are R, G, and B primary colors. However, the present invention is not limited to this, and may be cyan, yellow, and magenta. Also, two colors of B and yellow may be used. Of course, it may be a single color. Also, six colors of R, G, B, cyan, yellow, and magenta may be used. Five colors of R, G, B, cyan, and magenta may be used. These are natural colors, and the color reproduction range is expanded to achieve a good display. As described above, the EL display device of the present invention is not limited to one that performs color display with the three primary colors RGB.

  There are mainly three methods for colorizing an organic EL display panel, and one of them is a color conversion method. It is only necessary to form a blue-only single layer as the light emitting layer, and the remaining green and red colors necessary for full color are generated from blue light by color conversion. Therefore, there is an advantage that it is not necessary to separately coat each layer of RGB, and it is not necessary to prepare organic EL materials of each color of RGB. The color conversion method does not cause a decrease in yield unlike the color separation method. The EL display panel of the present invention can be applied to any of these methods.

  In addition to the three primary colors, white light emitting pixels may be formed. A white light emitting pixel can be realized by forming (forming or configuring) by stacking R, G, and B light emitting structures. One set of pixels includes three primary colors of RGB and a pixel 16W that emits white light. By forming a pixel emitting white light, white peak luminance can be easily expressed. Accordingly, it is possible to realize a bright image display.

  Even in the case of forming a set of pixels for three primary colors such as RGB, it is preferable that the areas of the pixel electrodes of the respective colors are different. Of course, if the luminous efficiency of each color is well balanced and the color purity is well balanced, the same area may be used. However, if the balance of one or more colors is bad, it is preferable to adjust the pixel electrode (light emitting area). The electrode area of each color may be determined based on the current density. That is, when the white balance is adjusted within a color temperature range of 7000 K (Kelvin) to 12000 K, the difference in current density of each color is within ± 30%. More preferably, it is within ± 15%. For example, if the current density is 100 A / square meter, the three primary colors are all set to 70 A / square meter or more and 130 A / square meter or less. More preferably, the three primary colors are all set to 85 A / square meter or more and 115 A / square meter or less.

  The organic EL element 15 is a self-light emitting element. When light emitted by this light emission enters a transistor as a switching element, a photoconductor phenomenon (photoconversion) occurs. “Photocon” refers to a phenomenon in which leakage (off leak) increases when a switching element such as a transistor is turned off by photoexcitation.

  In order to cope with this problem, in the present invention, a light shielding film under the gate driver 12 (in some cases, the source driver 14) and under the pixel transistor 11 is formed. The light shielding film is formed of a metal thin film such as chromium, and the film thickness is set to 50 nm or more and 150 nm or less. If the film thickness is thin, the light shielding effect is poor, and if it is thick, irregularities are generated, making it difficult to pattern the upper transistor 11A1.

  The driver circuit 12 and the like should suppress light from not only the back surface but also the front surface. This is because malfunction occurs due to the influence of the photocon. Therefore, in the present invention, when the cathode electrode is a metal film, the cathode electrode is also formed on the surface of the driver 12 and the like, and this electrode is used as a light shielding film.

  However, when a cathode electrode is formed on the driver 12, there is a possibility that a malfunction of the driver due to an electric field from the cathode electrode or an electrical contact between the cathode electrode and the driver circuit may occur. In order to cope with this problem, in the present invention, an organic EL film of at least one layer, preferably a plurality of layers, is formed simultaneously with the formation of the organic EL film on the pixel electrode on the driver circuit 12 or the like.

  When the terminals of one or more transistors 11 of the pixel or the transistor 11 and the signal line are short-circuited, the EL element 15 may be a bright spot that is always lit. This bright spot is visually conspicuous and needs to be turned into black (not lit). For the bright spot, the corresponding pixel 16 is detected, and the capacitor 19 is irradiated with laser light to short-circuit the terminals of the capacitor. Therefore, since the capacitor 19 cannot hold the electric charge, the transistor 11a can be prevented from flowing current. It is desirable to remove the cathode film corresponding to the position where the laser beam is irradiated. This is to prevent the terminal electrode of the capacitor 19 and the cathode film from being short-circuited by laser irradiation.

  The defect of the transistor 11 of the pixel 16 also affects the driver IC 14 and the like. For example, in FIG. 45, when a source-drain (SD) short 452 is generated in the driving transistor 11a, the Vdd voltage of the panel is applied to the source driver IC. Therefore, the power supply voltage of the source driver IC 14 is preferably the same as or higher than the power supply voltage Vdd of the panel. It should be noted that the reference current used in the source driver IC is preferably configured so that it can be adjusted by the electronic volume 451.

  When the SD short 452 is generated in the transistor 11a, an excessive current flows in the EL element 15. That is, the EL element 15 is always lit (bright spot). Bright spots are easily noticeable as defects. For example, in FIG. 45, when the source-drain (SD) short of the transistor 11a occurs, a current always flows from the Vdd voltage to the EL element 15 regardless of the gate (G) terminal potential of the transistor 11a ( When the transistor 11d is on). Therefore, it becomes a bright spot.

  On the other hand, when an SD short occurs in the transistor 11a, the Vdd voltage is applied to the source signal line 18 and the Vdd voltage is applied to the source driver 14 when the transistor 11c is in the on state. If the power supply voltage of the source driver 14 is equal to or lower than Vdd, the source driver 14 may be destroyed beyond the breakdown voltage. Therefore, it is preferable that the power supply voltage of the source driver 14 be equal to or higher than the Vdd voltage (the higher voltage of the panel).

  The SD short of the transistor 11a is not limited to a point defect, and may cause destruction of the source driver circuit of the panel. Further, since the bright spot is conspicuous, the panel becomes defective. Therefore, it is necessary to cut the wiring connecting the transistor 11a and the EL element 15 to make the bright spot a black spot defect. For this cutting, it is preferable to use an optical means such as a laser beam.

  Hereinafter, the driving method of the present invention will be described. As shown in FIG. 1, the gate signal line 17a becomes conductive during the row selection period (here, since the transistor 11 of FIG. 1 is a p-channel transistor, it becomes conductive at a low level), and the gate signal line 17b remains in the non-selection period. Sometimes conductive.

  The source signal line 18 has a parasitic capacitance (not shown). The parasitic capacitance is generated by the capacitance of the cross portion between the source signal line 18 and the gate signal line 17, the channel capacitance of the transistors 11b and 11c, and the like.

  Parasitic capacitance is generated not only in the source signal line 18 but also in the source driver IC 14. As shown in FIG. 273, the protection diode 2731 is the main cause. The protective diode 2731 has a purpose of protecting the IC 14 from static electricity, but also serves as a capacitor. The capacity of a general protection diode is 3 to 5 pF.

  In the source driver IC of the present invention (which will be described in detail later), a surge reduction resistor 2732 is formed or disposed between the terminal 681 and the output stage 654 as shown in FIG. The resistor 2732 is formed of polysilicon or a diffused resistor. The resistance value is 1 KΩ or more and 1 MΩ or less. Static electricity from the outside is suppressed by this resistance. Therefore, the size of the protection diode 2731 may be small. If the protective diode 2731 is small, the parasitic capacitance due to the protective diode is also small. In FIG. 273, a resistor 2732 is formed or arranged in the source driver IC 14, but the present invention is not limited to this, and the resistor 2732 may be formed or arranged in the array 71. Needless to say. The same applies to the diode 2731 (including a transistor having a diode configuration).

  The time t required to change the current value of the source signal line 18 is t = C · V / I, where C is the size of the stray capacitance, V is the voltage of the source signal line, and I is the current flowing through the source signal line. The fact that the value can be increased 10 times can shorten the time required for the current value change to nearly 1/10. Or, it shows that even if the parasitic capacitance of the source signal line 18 is increased 10 times, it can be changed to a predetermined current value. Therefore, it is effective to increase the current value in order to write a predetermined current value within a short horizontal scanning period.

  When the input current is increased 10 times, the output current is also increased 10 times, and the luminance of EL is increased 10 times. Therefore, in order to obtain a predetermined luminance, the conduction period of the transistor 17d in FIG. By setting the value to 1/10, a predetermined luminance is displayed. Note that the explanation is given by exemplifying 10 times for easy understanding. Needless to say, it is not limited to 10 times.

  That is, it is necessary to output a relatively large current from the source driver 14 in order to sufficiently charge and discharge the parasitic capacitance of the source signal line 18 and to program a predetermined current value in the transistor 11 a of the pixel 16. However, when such a large current flows through the source signal line 18, this current value is programmed in the pixel, and a large current flows through the EL element 15 with respect to a predetermined current. For example, if programming is performed with 10 times the current, naturally, 10 times the current flows through the EL element 15, and the EL element 15 emits light with 10 times the luminance. In order to obtain a predetermined light emission luminance, the time required to flow through the EL element 15 may be reduced to 1/10. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained.

  It should be noted that although 10 times the current value is written in the pixel transistor 11a (more precisely, the terminal voltage of the capacitor 19 is set) and the on-time of the EL element 15 is reduced to 1/10, this is merely an example. In some cases, a 10 times larger current value may be written in the pixel transistor 11a, and the on-time of the EL element 15 may be reduced to 1/5. On the contrary, there may be a case where a 10 times larger current value is written in the pixel transistor 11a and the on-time of the EL element 15 is halved.

  The present invention is characterized in that the pixel write current is set to a value other than a predetermined value and the current flowing through the EL element 15 is driven intermittently. In this specification, for ease of explanation, it is assumed that N times the current value is written in the transistor 11 of the pixel and the on-time of the EL element 15 is 1 / N times. However, the present invention is not limited to this, and it goes without saying that a current value of N1 times is written in the transistor 11 of the pixel, and the ON time of the EL element 15 may be 1 / (N2) times (different from N1 and N2). .

  In the white raster display, it is assumed that the average luminance in one field (frame) period of the display screen 50 is B0. At this time, the current (voltage) program is performed so that the luminance B1 of each pixel 16 is higher than the average luminance B0. The non-display area 53 is generated in at least one field (frame) period. Therefore, in the driving method of the present invention, the average luminance in one field (frame) period is lower than B1.

  The intermittent interval (non-display area 52 / display area 53) is not limited to an equal interval. For example, it may be random (as a whole, the display period or the non-display period may be a predetermined value (a constant ratio)). Also, it may be different for RGB. That is, it is only necessary to adjust (set) the R, G, B display period or the non-display period to a predetermined value (a constant ratio) so that the white balance is optimal.

  In order to facilitate the description of the driving method of the present invention, 1 / N is described on the assumption that 1F is set to 1 / N on the basis of 1F (one field or one frame). However, there is a time during which one pixel row is selected and the current value is programmed (usually, one horizontal scanning period (1H)), and it goes without saying that an error may occur depending on the scanning state.

  For example, the pixel 16 may be current-programmed with a current N = 10 times, and the EL element 15 may be turned on for a period of 1/5. The EL element 15 is lit with 10/5 = 2 times the luminance. The pixel 16 may be current-programmed with N = 2 times the current, and the EL element 15 may be turned on for a quarter period. The EL element 15 is lit with a brightness of 2/4 = 0.5 times. In other words, the present invention performs programming with a current that is not N = 1 times and performs a display other than the always-on (1/1, ie, not intermittent display) state. Further, this is a driving method in which the current supplied to the EL element 15 is turned off at least once in one frame (or one field) period. Further, it is a driving method in which the pixel 16 is programmed with a current larger than a predetermined value and at least intermittent display is performed.

  The organic (inorganic) EL display device also has a problem in that the display method is basically different from a display that displays an image as a set of line displays with an electron gun, such as a CRT. That is, in the EL display device, the current (voltage) written to the pixel is held for a period of 1F (1 field or 1 frame). For this reason, when a moving image is displayed, there is a problem that the outline of the display image is blurred.

  In the present invention, a current is passed through the EL element 15 only during the period of 1F / N, and no current is passed during the other period (1F (N-1) / N). Consider the case where this driving method is implemented and one point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is intermittently displayed over time. When the moving image data display is viewed in the intermittent display state, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized.

  In the driving method of the present invention, intermittent display is realized. However, the intermittent display only needs to be turned on / off for the transistor 11d in a cycle of 1H. Therefore, the main clock of the circuit is not different from the conventional one, and the power consumption of the circuit does not increase. In the liquid crystal display panel, an image memory is necessary to realize intermittent display. In the present invention, image data is held in each pixel 16. Therefore, an image memory for performing intermittent display is unnecessary.

  In the present invention, the current supplied to the EL element 15 is controlled only by turning on or off the switching transistor 11d or the transistor 11e. That is, even when the current Iw flowing through the EL element 15 is turned off, the image data is held in the capacitor 19 as it is. Therefore, if the switching element 11d and the like are turned on at the next timing and a current flows through the EL element 15, the flowing current is the same as the previously flowing current value. In the present invention, it is not necessary to increase the main clock of the circuit even when black insertion (intermittent display such as black display) is realized. Further, there is no need for an image memory because it is not necessary to perform time axis expansion. Further, the organic EL element 15 has a short time from application of current to light emission, and responds at high speed. Therefore, it is suitable for moving image display and can solve the problem of moving image display, which is a problem of conventional data retention type display panels (liquid crystal display panel, EL display panel, etc.) by performing intermittent display.

  Further, when the wiring length of the source signal line 18 is increased and the parasitic capacitance of the source signal line 18 is increased in a large display device, it is possible to cope with the problem by increasing the N value. When the program current value applied to the source signal line 18 is increased N times, the conduction period of the gate signal line 17b (transistor 11d) may be set to 1 F / N. Accordingly, the present invention can be applied to large display devices such as televisions and monitors.

  Hereinafter, the driving method of the present invention will be described in more detail with reference to the drawings. The parasitic capacitance of the source signal line 18 is generated by a coupling capacitance between adjacent source signal lines 18, a buffer output capacitance of the source drive IC (circuit) 14, a cross capacitance between the gate signal line 17 and the source signal line 18, and the like. This parasitic capacitance is usually 10 pF or more. In the case of voltage driving, a voltage is applied from the driver IC 14 to the source signal line 18 with a low impedance, so that there is no problem in driving even if the parasitic capacitance is somewhat large.

  However, current driving requires that the pixel capacitor 19 be programmed with a very small current of 20 nA or less, particularly for black level image display. Accordingly, when the parasitic capacitance is generated with a magnitude greater than or equal to a predetermined value, the time for programming to one pixel row (usually within 1H, however, it is not limited to within 1H because two pixel rows may be written simultaneously. ) Can not charge and discharge the parasitic capacitance. If charging / discharging is not possible in the 1H period, writing into the pixel is insufficient and the resolution is not high.

  In the case of the pixel configuration of FIG. 1, as shown in FIG. 3A, the program current Iw flows through the source signal line 18 during current programming. The voltage is set (programmed) in the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing through Iw is maintained. At this time, the transistor 11d is in an open state (off state).

  Next, during a period in which a current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d is operated as shown in FIG. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d is turned on.

  Assuming that the current I1 is N times the current (predetermined value) that flows originally, the current flowing through the EL element 15 in FIG. 3B is also Iw. Therefore, the EL element 15 emits light with a luminance 10 times the predetermined value. That is, as shown in FIG. 12, the display brightness B of the pixel 16 increases as the magnification N increases. Therefore, the magnification and the luminance of the pixel 16 are in a proportional relationship.

  Therefore, if the transistor 11d is turned on only for a period of 1 / N of the time for which the transistor 11d is originally turned on (about 1F) and is turned off for the other periods (N-1) / N, the average brightness of the entire 1F becomes a predetermined brightness. Become. This display state approximates that the CRT is scanning the screen with an electron gun. The difference is that the range in which the image is displayed is 1 / N of the entire screen (the whole screen is 1) is lit (in CRT, the lit range is one pixel row (strictly Is one pixel).

  In the present invention, the 1F / N image display area 53 moves from the top to the bottom of the screen 50 as shown in FIG. In the present invention, current flows through the EL element 15 only during the period of 1F / N, and no current flows during the other period (1F · (N−1) / N). Accordingly, each pixel 16 is intermittently displayed. However, since the image is retained by the afterimage to the human eye, the entire screen appears to be displayed uniformly.

  As shown in FIG. 13, the writing pixel row 51a is a non-lighting display 52a. However, this is the case of the pixel configuration shown in FIGS. In the pixel configuration of the current mirror illustrated in FIG. 38 and the like, the writing pixel row 51a may be lit. However, in this specification, for ease of explanation, the pixel configuration in FIG. A driving method in which programming is performed with a current larger than the predetermined driving current Iw, such as FIGS. 13 and 16, and intermittent driving is referred to as N-fold pulse driving.

  In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. In a liquid crystal display panel (an EL display panel other than the present invention), since data is held in pixels for a period of 1F, even if image data changes in the case of moving image display, the change cannot be followed. The video was blurred (outline blur in the image). However, since the image is intermittently displayed in the present invention, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized.

  As shown in FIG. 13, in order to drive, the current program period of the pixel 16 (in the pixel configuration of FIG. 1, the period during which the ON voltage Vgl of the gate signal line 17a is applied), the EL element It is necessary to be able to control independently the period during which 15 is turned off or on (in the pixel configuration of FIG. 1, the period during which the on voltage Vgl or the off voltage Vgh of the gate signal line 17b is applied). Therefore, the gate signal line 17a and the gate signal line 17b need to be separated.

  For example, when there is one gate signal line 17 wired from the gate driver circuit 12 to the pixel 16, the logic (Vgh or Vgl) applied to the gate signal line 17 is applied to the transistor 11 b, and the gate signal line 17 is applied. The driving method of the present invention cannot be implemented in a configuration in which the applied logic is converted (Vgl or Vgh) by an inverter and applied to the transistor 11d. Therefore, the present invention requires the gate driver circuit 12a for operating the gate signal line 17a and the gate driver circuit 12b for operating the gate signal line 17b.

  In addition, the driving method of the present invention is a driving method for non-lighting display in the pixel configuration of FIG. 1 and in a period other than the current program period (1H).

  FIG. 14 shows a timing chart of the driving method of FIG. In the present invention and the like, the pixel configuration when there is no particular notice is assumed to be FIG. As can be seen from FIG. 14, when an on-voltage (Vgl) is applied to the gate signal line 17a in each selected pixel row (selection period is 1H) (see FIG. 14A). In FIG. 14, an off voltage (Vgh) is applied to the gate signal line 17b (see FIG. 14B). During this period, no current flows through the EL element 15 (non-lighting state). In an unselected pixel row, an off voltage (Vgh) is applied to the gate signal line 17a, and an on voltage (Vgl) is applied to the gate signal line 17b. Further, during this period, a current flows through the EL element 15 (lighting state). In the lighting state, the EL element 15 is lit with a predetermined N times luminance (N · B), and the lighting period is 1 F / N. Therefore, the display luminance of the display panel that averages 1F is (N · B) × (1 / N) = B (predetermined luminance).

  FIG. 15 shows an embodiment in which the operation of FIG. 14 is applied to each pixel row. A voltage waveform applied to the gate signal line 17 is shown. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level). Subscripts such as (1) and (2) indicate the selected pixel row number.

  In FIG. 15, the gate signal line 17 a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11 a of the selected pixel row toward the source driver 14. This program current is N times a predetermined value (for ease of explanation, it is assumed that N = 10. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. .) Therefore, the capacitor 19 is programmed so that 10 times the current flows through the transistor 11a. When the pixel row (1) is selected, in the pixel configuration of FIG. 1, the gate signal line 17b (1) is applied with the off voltage (Vgh), and no current flows through the EL element 15.

  After 1H, the gate signal line 17a (2) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11a in the selected pixel row toward the source driver. This program current is N times a predetermined value (in order to facilitate explanation, explanation will be made assuming that N = 10). Therefore, the capacitor 19 is programmed so that 10 times the current flows through the transistor 11a. When the pixel row (2) is selected, the gate signal line 17b (2) is applied with the off voltage (Vgh) in the pixel configuration of FIG. 1, and no current flows through the EL element 15. However, the off voltage (Vgh) is applied to the gate signal line 17a (1) of the previous pixel row (1), and the on voltage (Vgl) is applied to the gate signal line 17b (1). It has become.

  After the next 1H, the gate signal line 17a (3) is selected, the off voltage (Vgh) is applied to the gate signal line 17b (3), and no current flows through the EL elements 15 in the pixel row (3). However, the off voltage (Vgh) is applied to the gate signal lines 17a (1) (2) of the previous pixel rows (1) (2), and the on voltage (Vgl) is applied to the gate signal lines 17b (1) (2). ) Is applied, and is in a lighting state.

  The above operation is displayed in synchronization with the 1H synchronization signal. However, in the driving method of FIG. 15, 10 times of current flows through the EL element 15. Therefore, the display screen 50 is displayed with about 10 times the luminance. Of course, in order to perform a predetermined luminance display in this state, it goes without saying that the program current may be set to 1/10. However, if the current is 1/10, insufficient writing occurs due to parasitic capacitance or the like. Therefore, programming at a high current and obtaining a predetermined luminance by inserting the black screen 52 is the basic gist of the present invention.

  In the driving method of the present invention, the concept is that a current higher than a predetermined current flows in the EL element 15 and the parasitic capacitance of the source signal line 18 is sufficiently charged and discharged. That is, it is not necessary to flow N times the current through the EL element 15. For example, a current path is formed in parallel with the EL element 15 (a dummy EL element is formed, a light shielding film is not formed on the EL element to emit light, etc.), and the current is shunted between the dummy EL element and the EL element 15. May be flushed. For example, when the signal current is 0.2 μA, the program current is set to 2.2 μA, and 2.2 μA is passed through the transistor 11a. Of these currents, a system is exemplified in which a signal current of 0.2 μA is passed through the EL element 15 and 2 μA is passed through a dummy EL element. That is, the dummy pixel row 271 in FIG. 27 is always selected. Note that the dummy pixel rows are configured not to emit light or to form a light-shielding film or the like so that they cannot be visually seen even if they emit light.

  With the above configuration, by increasing the current flowing through the source signal line 18 by N times, it is possible to program the driving transistor 11a so that N times the current flows, and the current EL element 15 Therefore, a current sufficiently smaller than N times can be achieved. In the above method, as shown in FIG. 5, the entire display area 50 can be used as the image display area 53 without providing the non-lighting area 52.

  FIG. 13A illustrates a writing state on the display image 50. In FIG. 13A, reference numeral 51a denotes a writing pixel row. A program current is supplied from the source driver IC 14 to each source signal line 18. In FIG. 13 and the like, one pixel row is written in the 1H period. However, it is not limited to 1H at all, and it may be 0.5H period or 2H period. In addition, although the program current is written to the source signal line 18, the present invention is not limited to the current program method, and a voltage program method (such as FIG. 46) in which the voltage is written to the source signal line 18 may be used. .

  In FIG. 13A, when the gate signal line 17a is selected, the current flowing through the source signal line 18 is programmed into the transistor 11a. At this time, an off voltage is applied to the gate signal line 17 b and no current flows through the EL element 15. This is because, when the transistor 11d is in the ON state on the EL element 15 side, the capacitance component of the EL element 15 can be seen from the source signal line 18, and the capacitor 19 cannot be sufficiently accurately programmed due to the capacitance. It is. Therefore, taking the configuration of FIG. 1 as an example, a pixel row in which a current is written becomes a non-lighting region 52 as shown in FIG.

  Now, if the current is programmed with N times (N = 10 as described above), the screen brightness will be 10 times. Therefore, a 90% range of the display area 50 may be set as the non-lighting area 52. Therefore, if the horizontal scanning lines of the image display area are 220 QCIF (S = 220), 22 lines and the display area 53 may be used, and 220-22 = 198 may be the non-display area 52. Generally speaking, if the horizontal scanning line (number of pixel rows) is S, the S / N area is set as the display area 53, and the display area 53 is caused to emit light with N times the luminance. Then, the display area 53 is scanned in the vertical direction of the screen. Accordingly, the S (N−1) / N region is a non-lighting region 52. This non-lighting area is black display (non-light emitting). The non-light emitting portion 52 is realized by turning off the transistor 11d. Although it is assumed that the light is lit at N times the luminance, it goes without saying that the value is adjusted to N times by brightness adjustment and gamma adjustment.

  Further, in the previous embodiment, if programming was performed with 10 times the current, the brightness of the screen would be 10 times, and 90% of the display area 50 could be the non-lighting area 52. However, this is not limited to the common use of the RGB pixels as the non-lighting region 52. For example, for the R pixel, 1/8 is the non-lighting area 52, for the G pixel, 1/6 is the non-lighting area 52, and for the B pixel, 1/10 is the non-lighting area 52. You may change by. Further, the non-lighting area 52 (or the lighting area 53) may be individually adjusted with RGB colors. In order to realize these, separate gate signal lines 17b are required for R, G, and B. However, by allowing individual adjustment of RGB as described above, it is possible to adjust white balance, and color balance adjustment is facilitated at each gradation (see FIG. 41).

  As shown in FIG. 13B, the pixel row including the writing pixel row 51a is a non-lighting region 52, and the S / N (1F / N in terms of time) range of the upper screen from the writing pixel row 51a is set. The display area 53 is set (if the writing scan is from the top to the bottom of the screen, the opposite is true when the screen is scanned from the bottom to the top). In the image display state, the display area 53 is strip-shaped and moves from the top to the bottom of the screen.

  In the display of FIG. 13, one display area 53 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the display area 53 moves. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.

  For this problem, the display area 53 may be divided into a plurality of parts as shown in FIG. If the divided sum is an area of S (N-1) / N, it is equivalent to the brightness of FIG. The divided display areas 53 do not have to be equal (equally divided). Further, the divided non-display areas 52 need not be equal.

  As described above, screen flickering is reduced by dividing display area 53 into a plurality of parts. Therefore, no flicker occurs and a good image display can be realized. The division may be made finer. However, the moving image display performance decreases as it is divided.

  FIG. 17 shows the voltage waveform of the gate signal line 17 and the light emission luminance of EL. As is apparent from FIG. 17, the period (1F / N) during which the gate signal line 17b is set to Vgl is divided into a plurality of numbers (the number of divisions K). That is, a period of 1 gl / (K · N) is performed K times for the period of Vgl. By controlling in this way, the occurrence of flicker can be suppressed and an image display with a low frame rate can be realized. Further, it is preferable that the number of divisions of the image is variable. For example, this change may be detected and the value of K may be changed by the user pressing a brightness adjustment switch or turning the brightness adjustment volume. Moreover, you may comprise so that a user may adjust a brightness | luminance. You may comprise so that it may change manually or automatically by the content and data of the image to display.

  In FIG. 17 and the like, the period (1F / N) for setting the gate signal line 17b to Vgl is divided into a plurality (number of divisions K), and the period for setting the Vgl is 1F / (K · N) K times. However, this is not a limitation. The period of 1F / (K · N) may be performed L (L ≠ K) times. In other words, the present invention displays the image 50 by controlling the period (time) flowing through the EL element 15. Therefore, it is included in the technical idea of the present invention to execute the period of 1F / (K · N) L (L ≠ K) times. Further, by changing the value of L, the brightness of the image 50 can be changed digitally. For example, when L = 2 and L = 3, the luminance (contrast) changes by 50%. Further, when the image display area 53 is divided, the period during which the gate signal line 17b is set to Vgl is not limited to the same period.

  In the above embodiment, the current flowing through the EL element 15 is cut off, and the current flowing through the EL element is connected to turn on and off the display screen 50 (lighting or non-lighting). That is, substantially the same current is caused to flow through the transistor 11a a plurality of times by the charge held in the capacitor 19. The present invention is not limited to this. For example, the display screen 50 may be turned on / off (lighted or not lighted) by charging / discharging the charge held in the capacitor 19.

  FIG. 18 shows voltage waveforms applied to the gate signal line 17 for realizing the image display state of FIG. The difference between FIG. 18 and FIG. 15 is the operation of the gate signal line 17b. The gate signal lines 17b are turned on / off (Vgl and Vgh) corresponding to the number of divided screens. The other points are the same as in FIG.

  In the EL display device, since the black display is completely unlit, there is no reduction in contrast as in the case where the liquid crystal display panel is intermittently displayed. In the configurations of FIGS. 1, 2, 32, 43, and 117, intermittent display can be realized only by turning on and off the transistor 11d. In the configurations of FIGS. 38, 51, and 115, intermittent display can be realized simply by turning on and off the transistor element 11e. In FIG. 113, intermittent display can be realized by controlling the switching circuit 1131. In FIG. 114, intermittent display can be realized by on / off controlling the transistor 11g. This is because the image data is stored in the capacitor 19 (the number of gradations is infinite because it is an analog value). That is, the image data is held in each pixel 16 during the period of 1F. Whether or not a current corresponding to the stored image data is supplied to the EL element 15 is realized by controlling the transistors 11d and 11e.

  Therefore, the above driving method is not limited to the current driving method, but can also be applied to the voltage driving method. That is, in the configuration in which the current flowing through the EL element 15 is stored in each pixel, the driving transistor 11 is intermittently driven by turning on and off the current path between the EL elements 15.

  Maintaining the terminal voltage of the capacitor 19 is important for reducing flicker and reducing power consumption. This is because if the terminal voltage of the capacitor 19 changes (charges / discharges) in one field (frame) period, the screen brightness changes, and flickering (flicker or the like) occurs when the frame rate decreases. It is necessary that the current that the transistor 11a passes through the EL element 15 in one frame (one field) period does not decrease to at least 65% or less. This 65% means that when the current written to the pixel 16 and the current flowing to the EL element 15 is 100%, the current flowing to the EL element 15 immediately before writing to the pixel 16 in the next frame (field) is 65% or more. It is to do.

  In the pixel configuration of FIG. 1, there is no change in the number of transistors 11 that constitute one pixel, in the case where intermittent display is realized or not. That is, the current configuration is realized by removing the influence of the parasitic capacitance of the source signal line 18 without changing the pixel configuration. In addition, a moving image display close to a CRT is realized.

  Further, since the operation clock of the gate driver circuit 12 is sufficiently slower than the operation clock of the source driver circuit 14, the main clock of the circuit does not increase. Further, it is easy to change the value of N.

  The image display direction (image writing direction) may be from the top to the bottom in the first field (one frame) and from the bottom to the top in the second field (frame). In other words, the top-to-bottom direction and the bottom-to-top direction are alternately repeated.

  In the first field (one frame), the screen is displayed from the top to the bottom. Once the entire screen is displayed in black (not displayed), the second field (frame) is displayed from the bottom to the top. Also good. Alternatively, the entire screen may be displayed black (not displayed) once.

  In the above description of the driving method, the screen writing method is set from the top to the bottom or from the bottom to the top, but the present invention is not limited to this. The screen writing direction is constantly fixed from top to bottom or from bottom to top, and the non-display area 52 operation direction is from top to bottom in the first field, and from the bottom in the second field. It is good also as an upward direction. Further, one frame may be divided into three fields, and R is formed in the first field, G is formed in the second field, and B is formed in the third field. Further, R, G, and B may be switched and displayed for each horizontal scanning period (1H) (see FIGS. 125 to 132 and the description thereof). The above matters are the same in other embodiments of the present invention.

  The non-display area 52 does not have to be completely unlit. Even if there is weak light emission or low luminance image display, there is no practical problem. That is, it should be interpreted as an area having a lower display luminance than the image display area 53. Further, the non-display area 52 includes a case where only one or two colors of the R, G, and B image displays are in a non-display state. In addition, the case where only one or two colors of the R, G, and B image displays are in a low luminance image display state is also included.

  Basically, when the brightness (brightness) of the display area 53 is maintained at a predetermined value, the brightness of the screen 50 increases as the area of the display area 53 increases. For example, when the luminance of the display area 53 is 100 (nt), if the ratio of the display area 53 to the entire screen 50 is changed from 10% to 20%, the luminance of the screen is doubled. Therefore, the display brightness of the screen can be changed by changing the area of the display area 53 occupying the entire screen 50. The display brightness of the screen 50 is proportional to the ratio of the display area 53 occupying the screen 50.

  The area of the display area 53 can be arbitrarily set by controlling the data pulse (ST2) to the shift register 61. Also, the display state of FIG. 16 and the display state of FIG. 13 can be switched by changing the input timing and period of the data pulse. If the number of data pulses in the 1F cycle is increased, the screen 50 becomes brighter, and if it is decreased, the screen 50 becomes darker. If the data pulse is continuously applied, the display state shown in FIG. 13 is obtained, and if the data pulse is input intermittently, the display state shown in FIG. 16 is obtained.

  FIG. 19A shows a brightness adjustment method when the display area 53 is continuous as shown in FIG. The display brightness of the screen 50 in FIG. 19 (a1) is the brightest. The display brightness of the screen 50 in FIG. 19 (a2) is the next brightest, and the display brightness of the screen 50 in FIG. 19 (a3) is the darkest. FIG. 19A is most suitable for moving image display.

  The change from FIG. 19 (a1) to FIG. 19 (a3) (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. At this time, it is not necessary to change the Vdd voltage in FIG. That is, it is possible to change the luminance of the display screen 50 without changing the power supply voltage. In addition, the gamma characteristic of the screen does not change at all during the change from FIG. 19 (a1) to FIG. 19 (a3). Therefore, the contrast and gradation characteristics of the display image are maintained regardless of the brightness of the screen 50. This is an effective feature of the present invention.

  In the conventional screen brightness adjustment, when the brightness of the screen 50 is low, the gradation performance deteriorates. That is, even when 64 gradation display can be realized during high brightness display, only half or less of the number of gradations can be displayed during low brightness display. Compared to this, the driving method of the present invention can realize the highest 64 gradation display without depending on the display brightness of the screen.

  FIG. 19B shows a brightness adjustment method when the display area 53 is dispersed as shown in FIG. The display brightness of the screen 50 in FIG. 19 (b1) is the brightest. The display brightness of the screen 50 in FIG. 19 (b2) is the next brightest, and the display brightness of the screen 50 in FIG. 19 (b3) is the darkest. The change from FIG. 19 (b1) to FIG. 19 (b3) (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. If the display area 53 is dispersed as shown in FIG. 19B, flicker does not occur even at a low frame rate.

  In order to prevent flicker from occurring even at a lower frame rate, the display area 53 may be finely dispersed as shown in FIG. However, the display performance of moving images decreases. Therefore, the driving method shown in FIG. 19A is suitable for displaying a moving image. When a still image is displayed and low power consumption is desired, the driving method shown in FIG. 19C is suitable. Switching of the driving method from FIG. 19A to FIG. 19C can be easily realized by controlling the shift register 61.

  The above embodiments are mainly embodiments in which N = 2 times, 4 times, and the like. However, it goes without saying that the present invention is not limited to integer multiples. Moreover, it is not limited to N = 2 or more. For example, an area less than half of the display area 50 at a certain time may be set as the non-lighting area 52. If the current is programmed with a current Iw that is 5/4 times the predetermined value and the light is turned on for 4/5 of 1F, a predetermined luminance can be realized.

  The present invention is not limited to this. As an example, there is a method in which current programming is performed with a current Iw that is 10/4 times, and lighting is performed for a 4/5 period of 1F. In this case, it is lit at twice the predetermined luminance. There is also a method in which current programming is performed with a current Iw that is 5/4 times, and lighting is performed for a period of 2/5 of 1F. In this case, the light is lit at half the predetermined luminance. There is also a method in which current programming is performed with a current Iw that is 5/4 times, and lighting is performed for a 1/1 period of 1F. In this case, it is lit at 5/4 times the predetermined luminance.

  That is, the present invention is a method for controlling the luminance of the display screen by controlling the magnitude of the program current and the lighting period of 1F. Further, by turning on the light for a period shorter than the 1F period, the black screen 52 can be inserted, and the moving image display performance can be improved. A bright screen can be displayed by always lighting it for the period of 1F.

When the pixel size is A square mm and the white raster display predetermined luminance is B (nt), the current written into the pixel (program current output from the source driver circuit 14) is:
(A * B) / 20 <= I <= (A * B)
It is preferable to set it as the range. Luminous efficiency is improved and insufficient current writing is eliminated.

Further preferably, the program current I (μA) is
(A * B) / 10 <= I <= (A * B)
It is preferable to set it as the range.

  In FIGS. 14 and 17, the operation timing of the gate signal line 17a and the write timing of the gate signal line 17b are not mentioned. However, when a certain pixel is selected (when a turn-on voltage is applied to the gate signal line 17a to which the pixel is connected), the 1H period (one horizontal scanning period) before and after that is the gate signal line. An off voltage is applied to 17b (a gate signal line for controlling the EL-side transistor 11d). By setting the off voltage to the gate signal line 17b during the 1H period before and after, a crosstalk does not occur in the panel, and a stable image display can be realized.

  A timing chart of this driving method is shown in FIG. An ON voltage (Vgl) is applied to the gate signal line 17a during 1H (selection period). The off voltage (Vgh) is applied to the gate signal line 17b during the 1H period (total 3H period) before and after the 1H period.

  In the above embodiment, the off voltage is applied to the gate signal line 17b during the 1H period before and after the selection period. However, the present invention is not limited to this. For example, as illustrated in FIG. 382, an off voltage may be applied to the gate signal line 17b in the 1H period before the selection period and the 2H period after the selection period. It goes without saying that the above embodiment can be applied to other embodiments of the present invention.

  FIG. 20 is an explanatory diagram of another embodiment in which the current flowing through the source signal line 18 is increased. Basically, a plurality of pixel rows are selected simultaneously, and a parasitic capacitance of the source signal line 18 is charged / discharged with a current obtained by combining the plurality of pixel rows, thereby greatly improving current writing shortage. However, since a plurality of pixel rows are selected at the same time, the driving current per pixel can be reduced. Therefore, the current flowing through the EL element 15 can be reduced. Here, for ease of explanation, as an example, N = 10 will be described (the current flowing through the source signal line 18 is multiplied by 10).

  The present invention described with reference to FIG. 20 selects M pixel rows at the same time as the pixel rows. From the source driver IC 14, a current N times the predetermined current is applied to the source signal line 18. Each pixel is programmed with a current N / M times the current flowing through the EL element 15. As an example, in order to set the EL element 15 to a predetermined light emission luminance, the time flowing through the EL element 15 is set to M / N time of one frame (one field) (however, it is not limited to M / N). / N is for ease of understanding, as described above, needless to say, it can be set freely depending on the brightness of the screen 50 to be displayed.) By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained with good resolution.

  Display is performed so that current flows through the EL element 15 only during the M / N period of one frame (one field) and no current flows during the other period (1F (N−1) M / N). In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. Accordingly, the outline blurring of the image is eliminated and a good moving image display can be realized. Further, since the source signal line 18 is driven with N times the current, it is not affected by the parasitic capacitance and can be applied to a high-definition display panel.

  FIG. 21 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. The signal waveform has an off voltage of Vgh (H level) and an on voltage of Vgl (L level). The subscript of each signal line describes the number of the pixel row ((1) (2) (3) etc.). The number of rows is 220 for the QCIF display panel and 480 for the VGA panel.

  In FIG. 21, the gate signal line 17 a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11 a of the selected pixel row toward the source driver 14. Here, for ease of explanation, first, it is assumed that the writing pixel row 51a is the pixel row (1) -th.

  The program current flowing through the source signal line 18 is N times a predetermined value (for ease of explanation, N = 10 will be described. Of course, since the predetermined value is a data current for displaying an image, white raster display is performed. It is not a fixed value unless it is). Further, description will be made assuming that five pixel rows are selected simultaneously (M = 5). Therefore, ideally, the capacitor 19 of one pixel is programmed so that the current flows through the transistor 11a twice (N / M = 10/5 = 2).

  When the writing pixel row is the (1) pixel row, as shown in FIG. 21, (1), (2), (3), (4), and (5) are selected for the gate signal line 17a. That is, the switching transistors 11b and the transistors 11c in the pixel rows (1), (2), (3), (4), and (5) are on. Further, the gate signal line 17b has an opposite phase to the gate signal line 17a. Therefore, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52.

  Ideally, each of the five-pixel transistors 11a passes an Iw × 2 current to the source signal line 18 (that is, Iw × 2 × N = Iw × 2 × 5 = Iw × 10 in the source signal line 18). Therefore, when the N-times pulse driving according to the present invention is not performed and the predetermined current Iw is used, a current 10 times as large as Iw flows in the source signal line 18).

  With the above operation (driving method), a double current is programmed in the capacitor 19 of each pixel 16. Here, in order to facilitate understanding, description will be made assuming that the characteristics (Vt, S value) of the transistors 11a are the same.

  Since five pixel rows (M = 5) are selected at the same time, the five driving transistors 11a operate. That is, 10/5 = 2 times the current flows through the transistor 11a per pixel. A current obtained by adding the program currents of the five transistors 11a flows through the source signal line 18. For example, the write current Iw is originally set to the write pixel row 51a, and a current of Iw × 10 is supplied to the source signal line 18. This is a pixel row used as an auxiliary to increase the amount of current to the writing pixel row 51b to which the image data is written after the writing pixel row (1). However, there is no problem in the writing pixel row 51b because normal image data is written later.

  Accordingly, the same display as 51a is performed in the four pixel row 51b during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected to increase the current. However, in the current mirror pixel configuration as shown in FIG. 38 and other voltage programming pixel configurations, the display state may be used.

  After 1H, the gate signal line 17a (1) is not selected, and an ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (6) is selected (Vgl voltage), and a program current flows from the transistor 11a of the selected pixel row (6) to the source driver 14 to the source signal line 18. By operating in this way, regular image data is held in the pixel row (1).

  After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17 a (7) is selected (Vgl voltage), and a program current flows from the transistor 11 a of the selected pixel row (7) toward the source driver 14 through the source signal line 18. By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by performing the above operation and scanning while shifting one pixel row at a time.

  In the driving method of FIG. 20, since each pixel is programmed with twice the current (voltage), the light emission luminance of the EL element 15 of each pixel is ideally doubled. Therefore, the brightness of the display screen is twice the predetermined value. In order to obtain a predetermined luminance, as shown in FIG. 16, a non-display area 52 may be included that includes the writing pixel row 51 and is ½ of the display area 50.

  As in FIG. 13, when one display area 53 moves downward from the top of the screen as shown in FIG. 20, it is visually recognized that the display area 53 moves when the frame rate is low. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.

  For this problem, the display area 53 may be divided into a plurality of parts as shown in FIG. When the divided non-display area 52 is added to have an area of S (N-1) / N, it is the same as when not divided.

  FIG. 23 shows voltage waveforms applied to the gate signal line 17. The difference between FIG. 21 and FIG. 23 is basically the operation of the gate signal line 17b. The gate signal lines 17b are turned on / off (Vgl and Vgh) corresponding to the number of divided screens. The other points are almost the same as those in FIG.

  As described above, screen flickering is reduced by dividing display area 53 into a plurality of parts. Therefore, no flicker occurs and a good image display can be realized. The division may be made finer. However, the more divided, the less flicker. In particular, since the responsiveness of the EL element 15 is fast, even if it is turned on / off in a time shorter than 5 μsec, the display luminance does not decrease.

  In the driving method of the present invention, ON / OFF of the EL element 15 can be controlled by ON / OFF of a signal applied to the gate signal line 17b. Therefore, in the driving method of the present invention, control is possible at a low frequency on the order of KHz. Further, an image memory or the like is not required to realize black screen insertion (non-display area 52 insertion). Therefore, the drive circuit or method of the present invention can be realized at low cost.

  FIG. 24 shows a case where two pixel rows are selected simultaneously. According to the examination result, in the display panel formed by the low-temperature polysilicon technology, the method of selecting two pixel rows at the same time has practical display uniformity. This is presumably because the characteristics of the driving transistors 11a of the adjacent pixels are very consistent. In addition, when laser annealing was performed, a good result was obtained by irradiating the stripe laser beam in parallel with the source signal line 18.

  This is because the characteristics of the semiconductor film that is annealed in the same time are uniform. That is, the semiconductor film is uniformly formed within the stripe-shaped laser irradiation range, and the Vt and mobility of the transistor using the semiconductor film are almost equal. Therefore, by irradiating a striped laser shot parallel to the formation direction of the source signal line 18 and moving the irradiation position, pixels (pixel columns, pixels in the vertical direction of the screen) along the source signal line 18 are moved. The characteristics are made approximately equal. Therefore, when current programming is performed by simultaneously turning on a plurality of pixel rows, the programming current is selected at the same time, and the current obtained by dividing the programming current by the number of selected pixels is substantially the same for the plurality of pixels. Is done. Therefore, a current program close to the target value can be implemented, and uniform display can be realized. Therefore, there is a synergistic effect between the laser shot direction and the driving method described in FIG.

  As described above, by making the laser shot direction substantially coincide with the formation direction of the source signal line 18 (see FIG. 7), the characteristics of the transistors 11a in the vertical direction of the pixel become substantially the same, and a good current can be obtained. The program can be executed (even if the characteristics of the transistors 11a in the horizontal direction of the pixel do not match). The above operation is performed by shifting the position of the selected pixel row by one pixel row or a plurality of pixel rows in synchronization with 1H (one horizontal scanning period).

  As described with reference to FIG. 8, the laser shot direction is made parallel to the source signal line 18, but it is not necessarily parallel. This is because even if the source signal line 18 is irradiated with a laser shot in an oblique direction, the characteristics of the transistors 11a in the vertical direction of the pixels along one source signal line 18 are formed substantially coincident with each other. Therefore, irradiating a laser shot in parallel with the source signal line means that adjacent pixels above or below any pixel along the source signal line 18 are formed so as to fall within one laser irradiation range. . The source signal line 18 is generally a wiring for transmitting a program current or voltage that becomes a video signal.

  In the embodiment of the present invention, the writing pixel row position is shifted every 1H. However, the present invention is not limited to this, and the writing pixel row position may be shifted every 2H (every 2 pixel rows). The pixel rows may be shifted one by one. Moreover, you may shift by arbitrary time units. Further, it may be shifted by one pixel row.

  Depending on the screen position, the shift time may be changed. For example, the shift time at the center of the screen may be shortened and the shift time may be lengthened at the top and bottom of the screen. For example, the center portion of the screen 50 shifts one pixel row every 200 μsec, and the upper and lower portions of the screen 50 shift one pixel row every 100 μsec. By shifting in this way, the light emission luminance at the center of the screen 50 is increased, and the periphery (upper and lower portions of the screen 50) can be decreased). Needless to say, the shift time between the central portion of the screen 50 and the upper portion of the screen, and the shift time between the central portion of the screen 50 and the lower portion of the screen are changed smoothly so as not to have a luminance contour.

  Note that the reference current of the source driver circuit 14 may be changed corresponding to the scanning position of the screen 50 (see FIG. 146 and the like). For example, the reference current at the center of the screen 50 is 10 μA, and the reference current at the top and bottom of the screen 50 is 5 μA. Thus, by changing the reference current corresponding to the position of the screen 50, the light emission luminance at the center of the screen 50 is increased, and the periphery (upper and lower portions of the screen 50) can be decreased). The values of the reference current between the center portion of the screen 50 and the upper portion of the screen and the reference current values between the center portion of the screen 50 and the lower portion of the screen are changed with time so that the luminance contour is not present. Needless to say, control.

  It goes without saying that image display may be performed by combining a driving method for controlling the time for shifting the pixel rows in accordance with the screen position and a driving method for changing the reference current in accordance with the position of the screen 50.

  The shift time may be changed for each frame. Further, the present invention is not limited to selecting a plurality of continuous pixel rows. For example, a pixel row extending to one pixel row may be selected.

  That is, the first pixel row and the third pixel row are selected in the first horizontal scanning period, and the second pixel row and the fourth pixel row are selected in the second horizontal scanning period. The third pixel row and the fifth pixel row are selected during the third horizontal scanning period, and the fourth pixel row and the sixth pixel row are selected during the fourth horizontal scanning period. This is a driving method. Of course, a driving method of selecting the first pixel row, the third pixel row, and the fifth pixel row in the first horizontal scanning period is also a technical category. Of course, even if a pixel row position extending to a plurality of pixel rows is selected.

  Note that the combination of the laser shot direction and the selection of a plurality of pixel rows at the same time is not limited to the pixel configurations of FIGS. 1, 2, and 32, and is a pixel configuration of a current mirror. Needless to say, the present invention can be applied to other current-driven pixel configurations such as 38, 42, and 50. Further, the present invention can also be applied to voltage-driven pixel configurations such as FIGS. 43, 51, 54, and 46. That is, if the characteristics of the transistors on the upper and lower sides of the pixel match, the voltage program can be satisfactorily performed with the voltage value applied to the same source signal line 18.

  In FIG. 24, when the writing pixel row is (1) pixel row, (1) and (2) are selected for the gate signal line 17a (see FIG. 25). That is, the switching transistors 11b and 11c in the pixel rows (1) and (2) are in the on state. Accordingly, at least the switching transistors 11d in the pixel rows (1) and (2) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52. In FIG. 24, the display area 53 is divided into five parts in order to reduce the occurrence of flicker.

  Ideally, the transistors 11a of two pixels (rows) each have Iw × 5 (N = 10. That is, since K = 2, the current flowing through the source signal line 18 is Iw × K × 5 = Iw. A current of × 10) is passed through the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with 5 times the current.

  Since two pixel rows (K = 2) are selected at the same time, the two driving transistors 11a operate. That is, a current of 10/2 = 5 times flows through the transistor 11a per pixel. A current obtained by adding the program currents of the two transistors 11a flows through the source signal line 18.

  For example, the write current Id is originally written in the write pixel row 51 a, and a current of Iw × 10 is passed through the source signal line 18. There is no problem in the writing pixel row 51b because normal image data is written later. The pixel row 51b has the same display as 51a during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected to increase the current.

  After the next 1H, the gate signal line 17a (1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17 a (3) is selected (Vgl voltage), and a program current flows from the transistor 11 a of the selected pixel row (3) toward the source driver 14 through the source signal line 18. By operating in this way, regular image data is held in the pixel row (1).

  After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17 a (4) is selected (Vgl voltage), and a program current flows from the transistor 11 a of the selected pixel row (4) toward the source driver 14 through the source signal line 18. By operating in this way, regular image data is held in the pixel row (2). The above operation and shift by one pixel row (of course, multiple pixel rows may be shifted. For example, if pseudo-interlace driving is used, the shift will be performed by two rows. One screen is rewritten by scanning while the same image may be written in the pixel row.

  Although it is the same as FIG. 16, in the driving method of FIG. 24, since each pixel is programmed with a current (voltage) 5 times, the emission luminance of the EL element 15 of each pixel is ideally 5 times. . Therefore, the luminance of the display area 53 is five times higher than the predetermined value. In order to obtain a predetermined luminance, as shown in FIG. 16 and the like, a non-display area 52 may be included that includes a writing pixel row 51 and that is 1/5 of the display screen 1.

  As shown in FIG. 27, two write pixel rows 51 (51a, 51b) are selected and sequentially selected from the upper side to the lower side of the screen 50 (see also FIG. 26. In FIG. 26, the pixel row 16a). And 16b are selected). However, as shown in FIG. 27B, when it reaches the lower side of the screen, the writing pixel row 51a exists, but the 51b disappears. That is, only one pixel row is selected. Therefore, all the current applied to the source signal line 18 is written to the pixel row 51a. Therefore, twice as much current is programmed in the pixel as compared with the pixel row 51a.

  In response to this problem, the present invention forms (arranges) a dummy pixel row 271 on the lower side of the screen 50 as shown in FIG. Therefore, when the selected pixel row is selected up to the lower side of the screen 50, the last pixel row and the dummy pixel row 271 on the screen 50 are selected. Therefore, a prescribed current is written into the write pixel row in FIG.

  Although the dummy pixel row 271 is illustrated as being formed adjacent to the upper end or the lower end of the display area 50, the present invention is not limited to this. It may be formed at a position away from the display area 50. Further, it is not necessary to form the switching transistor 11d, the EL element 15 and the like in FIG. By not forming, the size of the dummy pixel row 271 is reduced.

  FIG. 28 shows the state of FIG. As is apparent from FIG. 28, when the selected pixel rows are selected up to the pixel 16c row on the lower side of the screen 50, the last pixel row (dummy pixel row) 271 of the screen 50 is selected. The dummy pixel row 271 is arranged outside the display area 50. That is, the dummy pixel row (dummy pixel) 271 is configured not to be lit, not to be lit, or not to be seen as a display even when lit. For example, the contact hole between the pixel electrode 105 and the transistor 11 is eliminated, or the EL film 15 is not formed in the dummy pixel row 271. Further, a configuration in which an insulating film is formed over the pixel electrode 105 in the dummy pixel row is exemplified.

  In FIG. 27, the dummy pixels (rows) 271 are provided (formed or arranged) on the lower side of the screen 50, but the present invention is not limited to this. For example, as shown in FIG. 29A, when scanning from the lower side to the upper side of the screen (upside down scanning), the dummy pixel row 271 is also formed on the upper side of the screen 50 as shown in FIG. Should be formed. That is, the dummy pixel rows 271 are formed (arranged) on the upper side and the lower side of the screen 50, respectively. With the configuration described above, it is possible to cope with upside down scanning of the screen. In the above embodiment, two pixel rows are selected simultaneously.

  The present invention is not limited to this. For example, a method of simultaneously selecting five pixel rows (see FIG. 23) may be used. That is, in the case of simultaneous driving of five pixel rows, the dummy pixel rows 271 may be formed for four rows. Therefore, the dummy pixel rows 271 may be formed by the number of pixels of the pixel row-1 selected at the same time. However, this is a case where pixel rows to be selected are shifted one pixel row at a time. In the case of shifting by a plurality of pixel rows, it is sufficient to form (M-1) × L pixel rows, where M is the number of selected pixels and L is the number of pixel rows to be shifted.

  The dummy pixel row configuration or dummy pixel row driving according to the present invention is a method using at least one dummy pixel row. Of course, it is preferable to use a combination of the dummy pixel row driving method and N-times pulse driving.

  In the driving method of selecting a plurality of pixel rows at the same time, it becomes more difficult to absorb the characteristic variation of the transistor 11a as the number of pixel rows to be selected simultaneously increases. However, when the number M of simultaneously selected pixel rows decreases, the current programmed to one pixel increases, and a large current flows through the EL element 15. If the current passed through the EL element 15 is large, the EL element 15 is likely to deteriorate.

  FIG. 30 solves this problem. The basic concept of FIG. 30 is a method of simultaneously selecting a plurality of pixel rows in 1 / 2H (1/2 of the horizontal scanning period) as described in FIGS. Subsequent (1/2) H (1/2 of the horizontal scanning period) is a combination of methods for selecting one pixel row as described with reference to FIGS. By combining in this way, it is possible to absorb the characteristic variation of the transistor 11a, and to improve the in-plane uniformity at a higher speed. In addition, in order to make an understanding easy, although it demonstrates as operating by (1/2) H, it is not limited to this. The first period may be (1/4) H and the latter period may be (3/4) H.

  In FIG. 30, for ease of explanation, it is assumed that five pixel rows are simultaneously selected in the first period and one pixel row is selected in the second period. First, in the first period (1 / 2H in the first half), as shown in FIG. 30A1, five pixel rows are selected simultaneously. Since this operation has been described with reference to FIG. As an example, the current flowing through the source signal line 18 is 25 times the predetermined value. Accordingly, the transistor 11a of each pixel 16 (in the case of the pixel configuration in FIG. 1) is programmed with a current that is five times (25/5 pixel row = 5). Since the current is 25 times, the parasitic capacitance generated in the source signal line 18 and the like is charged and discharged in a very short time. Therefore, the potential of the source signal line 18 becomes the target potential in a short time, and the terminal voltage of the capacitor 19 of each pixel 16 is also programmed to flow 5 times the current. The application time of the 25 times current is set to 1 / 2H in the first half (1/2 of one horizontal scanning period).

  As a matter of course, since the same image data is written in the five pixel rows of the writing pixel row, the transistors 11d in the five pixel rows are turned off so as not to be displayed. Therefore, the display state is as shown in FIG.

  In the next ½H period of the second half, one pixel row is selected and current (voltage) programming is performed. This state is shown in FIG. 30 (b1). The write pixel row 51a is programmed with a current (voltage) so as to pass a current that is five times the current as before. 30A1 and FIG. 30B1 have the same current flowing through each pixel so that the change in the terminal voltage of the programmed capacitor 19 can be reduced so that the target current can flow faster. It is to do.

  That is, in FIG. 30 (a1), a current is passed through a plurality of pixels and is brought close to a value at which an approximate current flows at a high speed. In this first stage, since programming is performed by the plurality of transistors 11a, an error due to transistor variation occurs with respect to the target value. In the next second stage, only a pixel row in which data is written and held is selected, and a complete program is executed from a rough target value to a predetermined target value.

  The scanning of the non-lighting area 52 from the top to the bottom of the screen and the scanning of the writing pixel row 51a from the top to the bottom of the screen are the same as in the embodiment of FIG. .

  FIG. 31 shows drive waveforms for realizing the drive method of FIG. As can be seen in FIG. 31, 1H (one horizontal scanning period) is composed of two phases. These two phases are switched by the ISEL signal. The ISEL signal is illustrated in FIG.

  First, the ISEL signal will be described. The driver circuit 14 implementing FIG. 30 includes a current output circuit A and a current output circuit B. Each current output circuit includes a DA circuit for DA-converting 8-bit gradation data, an operational amplifier, and the like. In the embodiment of FIG. 30, the current output circuit A is configured to output a current 25 times larger. On the other hand, the current output circuit B is configured to output five times the current. The outputs of the current output circuit A and the current output circuit B are applied to the source signal line 18 by controlling the switch circuit formed (arranged) in the current output unit by the ISEL signal. This current output circuit is disposed on each source signal line.

  When the ISEL signal is at the L level, the current output circuit A that outputs a current 25 times larger is selected, and the current from the source signal line 18 is absorbed by the source driver IC 14 (more suitably, formed in the source driver circuit 14). Absorbed by the current output circuit A). It is easy to adjust the magnitude of the current output circuit current such as 25 times or 5 times. This is because it can be easily configured with a plurality of resistors and analog switches.

  As shown in FIG. 30, when the writing pixel row is the (1) pixel row (see the column 1H in FIG. 30), the gate signal line 17a is (1) (2) (3) (4) (5) Is selected (in the case of the pixel configuration in FIG. 1). That is, the switching transistors 11b and the transistors 11c in the pixel rows (1), (2), (3), (4), and (5) are on. Further, since ISEL is at the L level, the current output circuit A that outputs a 25-fold current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b. Therefore, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52.

  Ideally, each of the five-pixel transistors 11 a allows a current of Iw × 2 to flow through the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with 5 times the current. Here, in order to facilitate understanding, description will be made assuming that the characteristics (Vt, S value) of the transistors 11a are the same.

  Since five pixel rows (K = 5) are selected at the same time, the five driving transistors 11a operate. That is, a current of 25/5 = 5 times flows to the transistor 11a per pixel. A current obtained by adding the program currents of the five transistors 11a flows through the source signal line 18. For example, when the current Iw to be written to the pixel by the conventional driving method is set in the write pixel row 51a, a current of Iw × 25 is passed through the source signal line 18. This is a pixel row used as an auxiliary to increase the amount of current to the writing pixel row 51b to which the image data is written after the writing pixel row (1). However, there is no problem in the writing pixel row 51b because normal image data is written later.

  Therefore, the pixel row 51b has the same display as 51a during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected to increase the current.

  In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 51a is selected. That is, (1) only the pixel row is selected. As apparent from FIG. 31, only the gate signal line 17a (1) is applied with the ON voltage (Vgl), and the gate signal lines 17a (2), (3), (4), and (5) are applied with OFF (Vgh). Has been. Therefore, the transistor 11a in the pixel row (1) is in an operating state (a state in which current is supplied to the source signal line 18), but the switching transistor 11b in the pixel rows (2), (3), (4), and (5). The transistor 11c is off. That is, it is a non-selection state.

  Further, since ISEL is at the H level, the current output circuit B that outputs a 5-fold current is selected, and the current output circuit B and the source signal line 18 are connected. Further, the state of the gate signal line 17b is not changed from the previous state of 1 / 2H, and an off voltage (Vgh) is applied. Therefore, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52.

  From the above, the transistors 11a in the pixel row (1) flow Iw × 5 current to the source signal line 18, respectively. Then, the capacitor 19 in each pixel row (1) is programmed with 5 times the current.

  In the next horizontal scanning period, one pixel row and a writing pixel row are shifted. That is, the writing pixel row is (2) this time. In the first ½H period, when the writing pixel row is the (2) pixel row as shown in FIG. 31, the gate signal line 17a is (2) (3) (4) (5) (6). Is selected. That is, the switching transistors 11b and the transistors 11c in the pixel rows (2), (3), (4), (5), and (6) are on. Further, since ISEL is at the L level, the current output circuit A that outputs a 25-fold current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b.

  Therefore, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are in the off state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52. On the other hand, since the Vgl voltage is applied to the gate signal line 17b (1) of the pixel row (1), the transistor 11d is on, and the EL element 15 of the pixel row (1) is lit.

  Since five pixel rows (K = 5) are selected at the same time, the five driving transistors 11a operate. That is, a current of 25/5 = 5 times flows to the transistor 11a per pixel. A current obtained by adding the program currents of the five transistors 11a flows through the source signal line 18.

  In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 51a is selected. That is, (2) only the pixel row is selected. As apparent from FIG. 31, only the gate signal line 17a (2) is applied with the ON voltage (Vgl), and the gate signal lines 17a (3), (4), (5), and (6) are applied with OFF (Vgh). Has been.

  Therefore, the transistors 11a in the pixel rows (1) and (2) are in an operating state (the pixel row (1) supplies current to the EL element 15 and the pixel row (2) supplies current to the source signal line 18). However, the switching transistors 11b and 11c in the pixel rows (3), (4), (5), and (6) are off. That is, it is a non-selection state.

  In addition, since ISEL is at the H level, the current output circuit B that outputs a 5-fold current is selected, and the current output circuit 1222b and the source signal line 18 are connected. Further, the state of the gate signal line 17b is not changed from the previous state of 1 / 2H, and an off voltage (Vgh) is applied. Therefore, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are in the off state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52.

  From the above, the transistors 11 a in the pixel row (2) flow a current of Iw × 5 to the source signal line 18. Then, the capacitor 19 in each pixel row (2) is programmed with 5 times the current. One screen can be displayed by sequentially performing the above operations.

  The driving method described with reference to FIG. 30 selects G pixel rows (G is 2 or more) in the first period, and performs programming so that N times the current flows in each pixel row. In the second period after the first period, a B pixel row (B is smaller than G and 1 or more) is selected, and the pixel is programmed to flow N times as much current.

  However, there are other strategies. In the first period, G pixel rows (G is 2 or more) are selected and programmed so that the total current of each pixel row is N times the current. In the second period after the first period, a B pixel row (B is smaller than G and is 1 or more) is selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, In this method, the current of one pixel row is programmed to be N times. For example, in FIG. 30 (a1), five pixel rows are selected simultaneously, and twice the current flows through the transistor 11a of each pixel. Therefore, the current of 5 × 2 = 10 times flows through the source signal line 18. In the next second period, one pixel row is selected in FIG. A 10-fold current flows through the transistor 11a of one pixel.

  In FIG. 31, the period for simultaneously selecting a plurality of pixel rows is set to 1 / 2H and the period for selecting one pixel row is set to 1 / 2H. However, the present invention is not limited to this. The period for selecting a plurality of pixel rows at the same time may be 1 / 4H, and the period for selecting one pixel row may be 3 / 4H. In addition, the period including the period for simultaneously selecting a plurality of pixel rows and the period for selecting one pixel row is set to 1H, but the present invention is not limited to this. For example, it may be a 2H period or a 1.5H period.

  In FIG. 30, the period for simultaneously selecting five pixel rows may be set to 1 / 2H, and two pixel rows may be simultaneously selected in the next second period. Even in this case, it is possible to realize an image display that is practically satisfactory.

  In FIG. 30, the first period for selecting five pixel rows at the same time is ½H, and the second period for selecting one pixel row is ½H. However, the present invention is not limited to this. Absent. For example, the first stage may select three pixel rows at the same time, the second period may select three pixel rows among the five pixel rows, and finally select one pixel row. . That is, the image data may be written in the pixel row at a plurality of stages.

  In the above-described embodiments, one pixel row is sequentially selected and current programming is performed on the pixels, or a plurality of pixel rows are sequentially selected and current programming is performed on the pixels. However, the present invention is not limited to this. A method in which one pixel row is sequentially selected according to image data and current programming is performed on the pixel may be combined with a method in which a plurality of pixel rows are sequentially selected and current programming is performed on the pixel.

  Hereinafter, the interlace drive of the present invention will be described. FIG. 133 shows the structure of the display panel of the present invention which performs interlace driving. In FIG. 133, the gate signal lines 17a in the odd-numbered pixel rows are connected to the gate driver circuit 12a1. The gate signal lines 17a in the even pixel rows are connected to the gate driver circuit 12a2. On the other hand, the gate signal lines 17b in the odd-numbered pixel rows are connected to the gate driver circuit 12b1. The gate signal lines 17b in the even pixel rows are connected to the gate driver circuit 12b2.

  Therefore, the image data of the odd-numbered pixel rows is sequentially rewritten by the operation (control) of the gate driver circuit 12a1. In the odd-numbered pixel row, lighting / non-lighting control of the EL element is performed by the operation (control) of the gate driver circuit 12b1. In addition, the image data of the even pixel rows is sequentially rewritten by the operation (control) of the gate driver circuit 12a2. In the even-numbered pixel row, lighting / non-lighting control of the EL element is performed by the operation (control) of the gate driver circuit 12b2.

  FIG. 134A shows the operating state of the display panel in the first field. FIG. 134B shows the operation state of the display panel in the second field. For ease of explanation, it is assumed that one frame is composed of two fields. In FIG. 134, the hatched gate driver 12 indicates that no data scanning operation is performed. That is, in the first field of FIG. 134A, the gate driver circuit 12a1 operates as program current write control, and the gate driver circuit 12b2 operates as lighting control of the EL element 15. In the second field of FIG. 134 (b), the gate driver circuit 12a2 operates as the program current write control, and the gate driver circuit 12b1 operates as the EL element 15 lighting control. The above operation is repeated in the frame.

  FIG. 135 shows an image display state in the first field. 135 (a) illustrates the write pixel row (odd pixel row position where current (voltage) programming is performed. FIG. 135 (a1) → (a2) → (a3) and the write pixel row position are sequentially shifted. In the first field, the odd-numbered pixel rows are sequentially rewritten (the image data of the even-numbered pixel rows are retained), and Fig. 135 (b) illustrates the display state of the odd-numbered pixel rows. 135 (b) illustrates only odd pixel rows, and even pixel rows are illustrated in Fig. 135 (c), as can be seen in Fig. 135 (b), EL of pixels corresponding to odd pixel rows. On the other hand, the even-numbered pixel rows scan the display area 53 and the non-display area 52 (N-fold pulse driving) as shown in FIG.

  FIG. 136 shows the image display state in the second field. 136 (a) illustrates the write pixel row (odd pixel row position where current (voltage) programming is performed. The write pixel row position is sequentially shifted in FIG. 136 (a1) → (a2) → (a3). In the second field, even-numbered pixel rows are sequentially rewritten (image data of odd-numbered pixel rows is retained), and Fig. 136 (b) illustrates the display state of odd-numbered pixel rows. 136 (b) illustrates only odd pixel rows, and even pixel rows are illustrated in Fig. 136 (c), as can be seen in Fig. 136 (b), EL of pixels corresponding to even pixel rows. On the other hand, the odd-numbered pixel rows scan the display area 53 and the non-display area 52 (N-fold pulse drive) as shown in FIG.

  By driving as described above, interlaced driving can be easily realized with an EL display panel. In addition, by performing N-fold pulse driving, writing shortage does not occur and moving image blur does not occur. In addition, the control of the current (voltage) program and the lighting control of the EL element 15 are easy, and the circuit can be easily realized.

  Note that the driving method of the present invention is not limited to the driving method shown in FIGS. 135 and 136. For example, the driving method of FIG. 137 is also exemplified. 135 and 136, the odd-numbered pixel row or the even-numbered pixel row for which the current (voltage) program is performed is the non-display area 52 (non-lit, black display). In the embodiment of FIG. 137, both the gate driver circuits 12b1 and 12b2 for controlling the lighting of the EL element 15 are operated in synchronization. However, it goes without saying that the pixel row 51 on which current (voltage) programming is performed is controlled to be a non-display area (the current mirror pixel configuration in FIG. 38 does not need to do so). In FIG. 137, since the lighting control of the odd-numbered pixel row and the even-numbered pixel row is the same, it is not necessary to provide two gate driver circuits 12b1 and 12b2. One gate driver circuit 12b can be controlled for lighting.

  FIG. 137 shows a driving method in which the lighting control is the same for odd-numbered pixel rows and even-numbered pixel rows. However, the present invention is not limited to this. FIG. 138 shows an embodiment in which the lighting control for odd-numbered pixel rows and even-numbered pixel rows is different. In particular, FIG. 138 is an example in which the reverse pattern of the lighting state of the odd-numbered pixel rows (display area 53, non-display area 52) is changed to the lighting state of even-numbered pixel rows. Therefore, the area of the display area 53 and the area of the non-display area 52 are made the same. Of course, the area of the display area 53 and the area of the non-display area 52 are not limited to be the same.

  In FIG. 136 and FIG. 135, the pixel rows are not limited to the non-lighting state in the odd pixel rows or the even pixel rows.

  The above embodiment is a driving method for executing a current (voltage) program for each pixel row. However, the driving method of the present invention is not limited to this, and it goes without saying that two pixel rows (multiple pixel rows) may be simultaneously programmed with current (voltage) as shown in FIG. 139 (FIG. 27). And its description). FIG. 139 (a) shows an example of an odd field, and FIG. 139 (b) shows an example of an even field. In the odd field, (1,2) pixel rows, (3,4) pixel rows, (5,6) pixel rows, (7,8) pixel rows, (9,10) pixel rows, (11,12) pixels ... (N, n + 1) Two pixel rows are sequentially selected from a set of (n, n + 1) pixel rows (n is an integer of 1 or more), and current programming is performed. In the even field, (2, 3) pixel rows, (4, 5) pixel rows, (6, 7) pixel rows, (8, 9) pixel rows, (10, 11) pixel rows, (12, 13) pixels ... (N + 1, n + 2) Two pixel rows are sequentially selected from a set of (n + 1, n + 2) pixel rows (n is an integer of 1 or more), and current programming is performed.

  As described above, by selecting a plurality of pixel rows in each field and performing current programming, the current flowing through the source signal line 18 can be increased, and black writing can be improved. Further, the resolution of the image can be improved by shifting a set of a plurality of pixel rows selected in the odd field and the even field by at least one pixel row.

  In the embodiment of FIG. 139, the pixel rows selected in each field are two pixel rows. However, the pixel row is not limited to this, and may be three pixel rows. In this case, it is possible to select two methods, ie, a method of shifting one pixel and a method of shifting two pixels by a set of three pixel rows selected in the odd field and the even field. The pixel rows selected in each field may be four or more pixel rows. Further, as shown in FIGS. 125 to 132, one frame may be composed of three or more fields.

  In the embodiment of FIG. 139, two pixel rows are selected at the same time. However, the present invention is not limited to this, and 1H is set to the first half 1 / 2H and the second half 1 / 2H, and in the odd field, the first half of the first H period. In the 1 / 2H period, the first pixel row is selected and current programming is performed, and in the latter half of the 1 / 2H period, the second pixel row is selected and current programming is performed. In the first half of the next 2H period, the third pixel row is selected and current programming is performed, and in the second half of the H period, the fourth pixel row is selected and current programming is performed. The fifth pixel row is selected and current programming is performed in the first 1 / 2H period of the first H period of the next 3H period, and the sixth pixel row is selected and current programming is performed in the second 1 / 2H period. Do.・ ・ ・ ・ It may be driven.

  In the even field, the second pixel row is selected and current programming is performed in the first 1 / 2H period of the first H period, and the third pixel row is selected and current programming is performed in the second half of the H period. In the first half of the next 2H period, the fourth pixel row is selected for current programming, and in the second half of the H period, the fifth pixel row is selected for current programming. Further, the sixth pixel row is selected and current programming is performed in the first 1 / 2H period of the first H period of the next 3H period, and the seventh pixel row is selected and current programming is performed in the second half of the H period. Do.・ ・ ・ ・ It may be driven.

  Also in the above embodiment, the pixel rows selected in each field are two pixel rows. However, the pixel rows are not limited to this and may be three pixel rows. In this case, it is possible to select two methods, ie, a method of shifting one pixel and a method of shifting two pixels by a set of three pixel rows selected in the odd field and the even field. The pixel rows selected in each field may be four or more pixel rows.

  In the N-fold pulse driving method of the present invention, the waveform of the gate signal line 17b is made the same in each pixel row, and the application is performed by shifting at an interval of 1H. By scanning in this way, it is possible to sequentially shift the pixel rows to be lit while prescribing the time during which the EL element 15 is lit to 1 F / N. Thus, it is easy to realize that the waveform of the gate signal line 17b is the same and shifted in each pixel row. This is because it is only necessary to control ST1 and ST2 which are data applied to the shift register circuits 61a and 61b in FIG. For example, if Vgl is output to the gate signal line 17b when the input ST2 is at L level, and Vgh is output to the gate signal line 17b when the input ST2 is at H level, ST2 applied to the shift register 17b is output. Input is made at the L level only for the period of 1F / N, and is set to the H level for the other periods. The input ST2 is simply shifted by the clock CLK2 synchronized with 1H.

  Note that the cycle of turning on and off the EL element 15 needs to be 0.5 msec or more. When this period is short, the image is not completely displayed due to the afterimage characteristics of the human eye, and the image becomes blurred, as if the resolution is lowered. Further, the display state of the data holding type display panel is set. However, when the on / off cycle is 100 msec or more, it appears to blink. Therefore, the on / off cycle of the EL element should be 0.5 μsec or more and 100 msec or less. More preferably, the on / off cycle should be 2 msec or more and 30 msec or less. More preferably, the on / off cycle should be 3 msec or more and 20 msec or less.

  As described above, if the number of divisions of the black screen 52 is one, a satisfactory moving image display can be realized, but the flickering of the screen can be easily seen. Therefore, it is preferable to divide the black insertion portion into a plurality. However, if the number of divisions is too large, motion blur will occur. The number of divisions should be between 1 and 8. More preferably, it is 1 or more and 5 or less.

  It should be noted that the number of black screen divisions is preferably configured so that it can be changed between a still image and a moving image. With N = 4, 75% is a black screen and 25% is an image display. At this time, the division number is 1 to scan the 75% black display portion in the vertical direction of the screen in the 75% black belt state. The number of divisions is 3 for scanning with 3 blocks of a 25% black screen and a 25/3% display screen. Increase the number of divisions for still images. Reduce the number of divisions for movies. Switching may be performed automatically (moving image detection or the like) according to the input image, or may be performed manually by the user. Further, it may be configured to switch the video of the display device in accordance with the input outlet.

  For example, in a mobile phone or the like, the number of divisions is set to 10 or more on the wallpaper display and input screen (extremely, it may be turned on / off every 1H). When displaying NTSC moving images, the number of divisions is set to 1 or more and 5 or less. It should be noted that the number of divisions is preferably configured so that it can be switched to multiple stages of 3 or more. For example, no division number, 2, 4, 8, etc.

  The ratio of the black screen to the total display screen is preferably 0.2 or more and 0.9 or less (1.2 or more and 9 or less if displayed in N) when the area of the entire screen is 1. In particular, it is preferably 0.25 or more and 0.6 or less (in the case of N, it is 1.25 or more and 6 or less). If it is 0.20 or less, the improvement effect in moving image display is low. If it is 0.9 or more, the luminance of the display portion increases, and it is easy to visually recognize that the display portion moves up and down.

  The number of frames per second is preferably 10 or more and 100 or less (10 Hz or more and 100 Hz or less). Furthermore, 12 or more and 65 or less (12 Hz or more and 65 Hz or less) are preferable. If the number of frames is small, the flickering of the screen becomes conspicuous. If the number of frames is too large, writing from the source driver circuit 14 becomes difficult and the resolution deteriorates.

  Needless to say, the above items can be applied to the pixel configuration of the current program shown in FIG. 38 and the pixel configuration of the voltage program shown in FIGS. 43, 51, and 54. In FIG. 38, the transistor 11d, the transistor 11d in FIG. 43, and the transistor 11e in FIG. In this way, by turning on and off the wiring for supplying current to the EL element 15, the N-fold pulse driving of the present invention can be easily realized.

  Further, the time to set Vgl only during the period of 1F / N of the gate signal line 17b may be any time in the period of 1F (not limited to 1F; it may be a unit period). This is because a predetermined average luminance is obtained by turning on the EL element 15 for a predetermined period of time in the unit time. However, it is better to set the gate signal line 17b to Vgl immediately after the current program period (1H) and cause the EL element 15 to emit light. This is because it is less susceptible to the retention characteristics of the capacitor 19 of FIG.

  Further, it is preferable that the number of divisions of the image is variable. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, this change is detected and the value of K is changed. You may comprise so that it may change manually or automatically by the content and data of the image to display.

  In this way, it is possible to easily change the value of K (the number of divisions of the image display unit 53). This is because the timing of data to be applied to ST in FIG. 6 (when it is set to L level at 1F) can be adjusted or varied.

  In FIG. 16 and the like, the period (1F / N) in which the gate signal line 17b is set to Vgl is divided into a plurality (number of divisions M), and the period of 1F / (K · N) is performed K times for the period to set Vgl. However, this is not a limitation. The period of 1F / (K · N) may be performed L (L ≠ K) times. In other words, the present invention displays the image 50 by controlling the period (time) flowing through the EL element 15. Therefore, it is included in the technical idea of the present invention to execute the period of 1F / (K · N) L (L ≠ K) times. Further, by changing the value of L, the brightness of the image 50 can be changed digitally. For example, when L = 2 and L = 3, the luminance (contrast) change is 50%. It goes without saying that these controls can also be applied to other embodiments of the present invention (of course, the present invention described later can also be applied). These are also the N-fold pulse drive of the present invention.

  In the above embodiment, the transistor 11d as a switching element is disposed (formed) between the EL element 15 and the driving transistor 11a, and the screen 11 is displayed on and off by controlling the transistor 11d. . By this driving method, current writing shortage in the black display state of the current programming method is eliminated, and a good resolution or black display is realized. That is, in the current program method, it is important to realize a good black display. The driving method described below is to reset the driving transistor 11a to realize good black display. Hereinafter, the embodiment will be described with reference to FIG.

  FIG. 32 basically shows the pixel configuration of FIG. In the pixel configuration of FIG. 32, the programmed Iw current flows through the EL element 15, and the EL element 15 emits light. That is, the driving transistor 11a retains the ability to flow current by being programmed. A method of resetting (turning off) the transistor 11a using this current flowing capability is the driving method of FIG. Hereinafter, this driving method is referred to as reset driving.

  In order to realize reset driving with the pixel configuration of FIG. 1, it is necessary to configure the transistor 11b and the transistor 11c so that they can be controlled on and off independently. That is, as shown in FIG. 32, the gate signal line 17a (gate signal line WR) for controlling on / off of the transistor 11b and the gate signal line 17c (gate signal line EL) for controlling on / off of the transistor 11c can be controlled independently. To do. The gate signal line 17a and the gate signal line 17c may be controlled by two independent shift registers 61 as shown in FIG.

  The drive voltage of the gate signal line 17a for driving the transistor 11b and the gate signal line 17b for driving the transistor 11d may be changed (in the case of the pixel configuration in FIG. 1). The amplitude value of the gate signal line 17a (difference between the on voltage and the off voltage) is made smaller than the amplitude value of the gate signal line 17b.

  If the amplitude value of the gate signal line 17 is large, the punch-through voltage between the gate signal line 17 and the pixel 16 increases, and black floating occurs. The amplitude of the gate signal line 17a may be controlled so that the potential of the source signal line 18 is not applied to the pixel 16 (applied (when selected)). Since the potential fluctuation of the source signal line 18 is small, the amplitude value of the gate signal line 17a can be reduced.

  On the other hand, the gate signal line 17b needs to perform EL on / off control. Therefore, the amplitude value becomes large. In order to cope with this, the output voltages of the shift registers 61a and 61b are changed. When the pixel is formed of a P-channel transistor, the Vgh (off voltage) of the shift registers 61a and 61b is substantially the same, and the Vgl (on voltage) of the shift register 61a is greater than the Vgl (on voltage) of the shift register 61b. make low.

  Hereinafter, the reset driving method will be described with reference to FIG. FIG. 33 is a diagram for explaining the principle of reset driving. First, as illustrated in FIG. 33A, the transistors 11c and 11d are turned off and the transistor 11b is turned on. Then, the drain (D) terminal and the gate (G) terminal of the driving transistor 11a are short-circuited, and an Ib current flows. Generally, the transistor 11a is current-programmed in the previous field (frame). In this state, when the transistor 11d is turned off and the transistor 11b is turned on, the drive current Ib flows to the gate (G) terminal of the transistor 11a. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the transistor 11a is reset (a state in which no current flows).

  Note that before the operation in FIG. 33A, it is preferable to perform an operation in which the transistor 11b and the transistor 11c are turned off, the transistor 11d is turned on, and a current is supplied to the driving transistor 11a. This operation is preferably completed in as short a time as possible. This is because a current flows through the EL element 15 and the EL element 15 is lit, which may reduce the display contrast. This operation time is preferably 0.1% or more and 10% or less of 1H (one horizontal scanning period). More preferably, it is preferably 0.2% or more and 2% or less. Alternatively, it is preferable to be 0.2 μsec or more and 5 μsec or less. Further, the above-described operation (operation performed before FIG. 33A) may be performed collectively on the pixels 16 of the entire screen. By performing the above operation, the drain (D) terminal voltage of the driving transistor 11a is lowered, and a smooth Ib current can flow in the state of FIG. The above matters also apply to other reset driving methods of the present invention.

  As the execution time of FIG. 33A is made longer, the Ib current flows and the terminal voltage of the capacitor 19 tends to decrease. Therefore, the execution time of FIG. 33 (a) needs to be a fixed value. According to experiments and examinations, it is preferable that the execution time of FIG. 33 (a) be 1H or more and 5H or less.

  Note that this period is preferably different for R, G, and B pixels. This is because the EL material is different for each color pixel, and the rising voltage of the EL material is different. For each pixel of RGB, the most optimal period is set according to the EL material. In the embodiment, this period is set to 1H or more and 5H or less, but it goes without saying that it may be 5H or more in a driving method mainly for black insertion (writing a black screen). Note that the longer the period, the better the black display state of the pixel.

  After performing FIG. 33A, the state shown in FIG. 33B is obtained in a period of 1H to 5H. FIG. 33B shows a state in which the transistors 11c and 11b are turned on and the transistor 11d is turned off. The state shown in FIG. 33B is a state in which current programming is performed as described above. That is, the program current Iw is output (or absorbed) from the source driver circuit 14, and this program current Iw is supplied to the driving transistor 11a. The potential of the gate (G) terminal of the driving transistor 11a is set so that the program current Iw flows (the set potential is held in the capacitor 19).

  If the program current Iw is 0 (A), the transistor 11a remains in a state where no current flows as shown in FIG. 33A, so that a good black display can be realized. In addition, even when white display current programming is performed in FIG. 33B, even if there is a variation in the characteristics of the driving transistors of each pixel, the current programming is performed from the offset voltage in the black display state completely. . Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a, and a good image display can be realized.

  After current programming in FIG. 33B, as shown in FIG. 33C, the transistors 11b and 11c are turned off, the transistor 11d is turned on, and the program current Iw (= Ie) from the driving transistor 11a is turned on. Is caused to flow through the EL element 15 to cause the EL element 15 to emit light. Since FIG. 33 (c) has been described previously with reference to FIG.

  That is, in the driving method (reset driving) described in FIG. 33, the driving transistor 11a and the EL element 15 are disconnected (the current does not flow), and the drain (D) terminal and the gate (G) ) Terminal (or source (S) terminal and gate (G) terminal, more generally, two terminals including the gate (G) terminal of the driving transistor), Thereafter, a second operation of performing current (voltage) programming on the driving transistor is performed. In addition, at least the second operation is performed after the first operation. In order to perform reset driving, the transistor 11b and the transistor 11c must be configured to be independently controlled as in the configuration of FIG.

  The image display state (if an instantaneous change can be observed), first, the pixel row for which current programming is performed is in the reset state (black display state), and current programming is performed after 1H (at this time) Is also in a black display state because the transistor 11d is off.) Next, a current is supplied to the EL element 15, and the pixel row emits light with a predetermined luminance (programmed current). That is, it should appear that the black pixel row moves from the top to the bottom of the screen, and the image is rewritten at the position where the pixel row passes.

  Although current programming is performed 1H after reset, this period may be within about 5H. This is because it takes a relatively long time for the reset of FIG. If this period is 5H, 5 pixel rows should be displayed in black (6 pixel rows if a current program pixel row is included).

  In addition, the reset state is not limited to performing one pixel row at a time, and the reset state may be simultaneously performed for a plurality of pixel rows. Alternatively, the scanning may be performed while simultaneously resetting and overlapping each pixel row. For example, if four pixel rows are simultaneously reset, the pixel rows (1), (2), (3), and (4) are reset in the first horizontal scanning period (one unit), and the next second horizontal scan is performed. In the scanning period, the pixel rows (3), (4), (5), and (6) are reset, and in the next third horizontal scanning period, the pixel rows (5), (6), (7), and (8) are reset. Put it in a state. In addition, a driving state in which the pixel rows (7), (8), (9), and (10) are reset in the next fourth horizontal scanning period is exemplified. Of course, the drive states of FIGS. 33B and 33C are also performed in synchronization with the drive state of FIG.

  Further, it goes without saying that the driving shown in FIGS. 33B and 33C may be carried out after all the pixels of one screen are reset at the same time or in the scanning state. Needless to say, the interlace drive state (interlaced scanning of one pixel row or a plurality of pixel rows) may be set to the reset state (interlace of one pixel row or a plurality of pixel rows). Moreover, you may implement a random reset state. Further, the description of the reset driving according to the present invention is a method of manipulating pixel rows (that is, controlling the vertical direction of the screen). However, the concept of reset driving does not limit the control direction to pixel rows. For example, it goes without saying that reset driving may be performed in the pixel column direction.

  Note that the reset driving in FIG. 33 can be combined with the N-fold pulse driving of the present invention or with interlaced driving to realize better image display. In particular, the configuration of FIG. 22 is an intermittent N / K-fold pulse drive (a drive method in which a plurality of lighting regions are provided on one screen. This drive method is easy by controlling the gate signal line 17b and turning on / off the transistor 11d. (This has been described before.) Can be easily realized, so that a good image display can be realized without occurrence of flicker.

  It goes without saying that a better image display can be realized by combining with other driving methods, for example, a precharge driving method described below. As described above, it is needless to say that reset driving can be performed in combination with other embodiments of the present specification as in the present invention.

  FIG. 34 is a configuration diagram of a display device that realizes reset driving. The gate driver circuit 12a controls the gate signal line 17a and the gate signal line 17b in FIG. The transistor 11b is on / off controlled by applying an on / off voltage to the gate signal line 17a. Further, the transistor 11d is on / off controlled by applying an on / off voltage to the gate signal line 17b. The gate driver circuit 12b controls the gate signal line 17c in FIG. The transistor 11c is on / off controlled by applying an on / off voltage to the gate signal line 17c.

  Therefore, the gate signal line 17a is operated by the gate driver circuit 12a, and the gate signal line 17c is operated by the gate driver circuit 12b. Therefore, the timing at which the transistor 11b is turned on to reset the driving transistor 11a and the timing at which the transistor 111c is turned on to perform current programming on the driving transistor 11a can be freely set. Other configurations are the same as or similar to those previously described, and thus description thereof is omitted.

  FIG. 35 is a timing chart of reset driving. When a turn-on voltage is applied to the gate signal line 17a to turn on the transistor 11b and the driving transistor 11a is reset, a turn-off voltage is applied to the gate signal line 17b and the transistor 11d is turned off. Therefore, the state shown in FIG. During this period, an Ib current flows.

  In the timing chart of FIG. 35, the reset time is 2H (the on-voltage is applied to the gate signal line 17a and the transistor 11b is turned on), but the invention is not limited to this. It may be 2H or more. If the reset can be performed at a very high speed, the reset time may be less than 1H.

  The number of reset periods can be easily changed by the DATA (ST) pulse period input to the gate driver circuit 12. For example, if DATA input to the ST terminal is set to H level for 2H period, the reset period output from each gate signal line 17a becomes 2H period. Similarly, if DATA input to the ST terminal is set to the H level during the 5H period, the reset period output from each gate signal line 17a becomes the 5H period.

  After the reset of the 1H period, the ON voltage is applied to the gate signal line 17c (1) of the pixel row (1). When the transistor 11c is turned on, the program current Iw applied to the source signal line 18 is written to the driving transistor 11a via the transistor 11c.

  After current programming, a turn-off voltage is applied to the gate signal line 17c of the pixel (1), the transistor 11c is turned off, and the pixel is disconnected from the source signal line. At the same time, a turn-off voltage is applied to the gate signal line 17a, and the reset state of the driving transistor 11a is canceled (in this period, it is more appropriate to express the current program state than the reset state). is there). Further, an on-voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and a current programmed in the driving transistor 11a flows through the EL element 15. The pixel row (2) and subsequent pixels are the same as the pixel row (1), and the operation is obvious from FIG.

  In FIG. 35, the reset period is a 1H period. FIG. 36 shows an embodiment in which the reset period is 5H. The number of reset periods can be easily changed by the DATA (ST) pulse period input to the gate driver circuit 12. FIG. 36 shows an embodiment in which DATA input to the ST1 terminal of the gate driver circuit 12a is set to H level for 5H periods, and the reset period output from each gate signal line 17a is 5H periods. The longer the reset period, the more complete the reset and the better black display can be realized. However, the display luminance is reduced for the ratio of the reset period.

  FIG. 36 shows an example in which the reset period is 5H. Moreover, this reset state was a continuous state. However, the reset state is not limited to being performed continuously. For example, the signal output from each gate signal line 17a may be turned on / off every 1H. Such an on / off operation can be easily realized by operating an enable circuit (not shown) formed in the output stage of the shift register. Further, it can be easily realized by controlling the DATA (ST) pulse input to the gate driver circuit 12.

  In the circuit configuration of FIG. 34, the gate driver circuit 12a requires at least two shift register circuits (one for controlling the gate signal line 17a and the other for controlling the gate signal line 17b). Therefore, there is a problem that the circuit scale of the gate driver circuit 12a is increased. FIG. 37 shows an embodiment in which the gate driver circuit 12a has one shift register. A timing chart of an output signal obtained by operating the circuit of FIG. 37 is as shown in FIG. Note that FIG. 35 and FIG. 37 are different in the symbol of the gate signal line 17 output from the gate driver circuits 12a and 12b.

  As is apparent from the addition of the OR circuit 371 in FIG. 37, the output of each gate signal line 17a is ORed with the preceding stage output of the shift register circuit 61a. That is, the ON voltage is output from the gate signal line 17a during the 2H period. On the other hand, the output of the shift register circuit 61a is output as it is to the gate signal line 17c. Therefore, the on-voltage is applied during the 1H period.

  For example, when the second H level signal is output from the shift register circuit 61a, an ON voltage is output to the gate signal line 17c of the pixel 16 (1), and the pixel 16 (1) is in a current (voltage) program state. It is. At the same time, an on-voltage is output to the gate signal line 17a of the pixel 16 (2), the transistor 11b of the pixel 16 (2) is turned on, and the driving transistor 11a of the pixel 16 (2) is reset.

  Similarly, when the third H level signal is output from the shift register circuit 61a, an on-voltage is output to the gate signal line 17c of the pixel 16 (2), and the pixel 16 (2) is subjected to the current (voltage) program. State. At the same time, an ON voltage is also output to the pixel 16 (3 gate signal line 17a, the pixel 16 (3) transistor 11b is turned on, and the pixel 16 (3) driving transistor 11a is reset. An on-voltage is output from the gate signal line 17a, and an on-voltage is output to the gate signal line 17c for 1H period.

  In the programmed state, when the transistor 11b and the transistor 11c are turned on at the same time (FIG. 33 (b)), the transistor 11c is preceded by the transistor 11b when shifting to the non-programmed state (FIG. 33 (c)). When it is turned off, the reset state shown in FIG. In order to prevent this, the transistor 11c needs to be turned off after the transistor 11b. For this purpose, it is necessary to control the gate signal line 17a so that the ON voltage is applied before the gate signal line 17c.

  The above example is an example related to the pixel configuration of FIG. 32 (basically, FIG. 1). However, the present invention is not limited to this. For example, the pixel configuration of a current mirror as shown in FIG. 38 can be implemented. In FIG. 38, the N-fold pulse driving illustrated in FIGS. 13 and 15 can be realized by on / off controlling the transistor 11e. FIG. 39 is an explanatory diagram of an embodiment in the pixel configuration of the current mirror of FIG. Hereinafter, the reset driving method in the pixel configuration of the current mirror will be described with reference to FIG.

  As illustrated in FIG. 39A, the transistor 11c and the transistor 11e are turned off, and the transistor 11d is turned on. Then, the drain (D) terminal and the gate (G) terminal of the current programming transistor 11b are short-circuited, and an Ib current flows as shown in the figure. In general, the transistor 11b is current-programmed in the previous field (frame) and has a capability of flowing current (the gate potential is held in the capacitor 19 for 1F period and is naturally displayed. , Current does not flow when a complete black display is performed). In this state, when the transistor 11e is turned off and the transistor 11d is turned on, the drive current Ib flows in the direction of the gate (G) terminal of the transistor 11a (the gate (G) terminal and the drain (D) terminal are short-circuited). ) Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the transistor 11a is reset (a state in which no current flows). Further, since the gate (G) terminal of the driving transistor 11b is common with the gate (G) terminal of the current programming transistor 11a, the driving transistor 11b is also reset.

  The reset state (state in which no current flows) of the transistors 11a and 11b is equivalent to the state in which the offset voltage of the voltage offset canceller system described in FIG. That is, in the state of FIG. 39 (a), an offset voltage (starting voltage at which current starts to flow) is applied between the terminals of the capacitor 19. By applying a voltage higher than the absolute value of this voltage, current flows through the transistor 11. Will be held. This offset voltage has a different voltage value depending on the characteristics of the transistors 11a and 11b. Therefore, by performing the operation of FIG. 39A, the capacitor 19 of each pixel is maintained in a state in which no current flows through the transistor 11a and the transistor 11b (that is, a black display current (almost equal to 0)). (Reset to the starting voltage at which current begins to flow).

  39A, as in FIG. 33A, the Ib current flows and the terminal voltage of the capacitor 19 tends to decrease as the reset execution time increases. Therefore, the execution time of FIG. 39A needs to be a fixed value. According to experiments and examinations, it is preferable that the execution time of FIG. 39A is 1H or more and 10H (10 horizontal scanning periods) or less. Furthermore, it is preferable to set it to 1H or more and 5H or less. Alternatively, it is preferably 20 μsec or more and 2 msec or less. The same applies to the driving method shown in FIG.

  The same applies to FIG. 33A, but when the reset state of FIG. 39A and the current program state of FIG. 39B are performed in synchronization, the reset state of FIG. Since the period until the current programming state in FIG. 39B is a fixed value (constant value), there is no problem (the value is fixed). That is, the period from the reset state of FIG. 33A or FIG. 39A to the current program state of FIG. 33B or FIG. 39B is set to 1H or more and 10H (10 horizontal scanning periods) or less. It is preferable. Furthermore, it is preferable to set it to 1H or more and 5H or less. Alternatively, it is preferably 20 μsec or more and 2 msec or less. If this period is short, the driving transistor 11 is not completely reset. If it is too long, the driving transistor 11 is completely turned off, and this time, it takes a long time to program the current. In addition, the brightness of the screen 50 also decreases.

  After performing FIG. 39A, the state shown in FIG. FIG. 39B shows a state where the transistors 11c and 11d are turned on and the transistor 11e is turned off. The state shown in FIG. 39B is a state where current programming is performed. That is, the program current Iw is output (or absorbed) from the source driver circuit 14, and this program current Iw is supplied to the current programming transistor 11a. The potential of the gate (G) terminal of the driving transistor 11b is set in the capacitor 19 so that the program current Iw flows.

  If the program current Iw is 0 (A) (black display), the transistor 11b remains in a state where no current flows as shown in FIG. 33A, so that a good black display can be realized. . Further, in the case of performing white display current programming in FIG. 39B, even if there is a variation in the characteristics of the driving transistors in each pixel, the offset voltage in the completely black display state (in the characteristics of each driving transistor). A current program is performed from the start voltage at which the set current flows accordingly. Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a or the transistor 11b, and a good image display can be realized.

  After the current programming of FIG. 39B, as shown in FIG. 39C, the transistors 11c and 11d are turned off, the transistor 11e is turned on, and the program current Iw (= Ie) from the driving transistor 11b is turned on. Is caused to flow through the EL element 15 to cause the EL element 15 to emit light. Also with respect to FIG. 39 (c), since it has been described previously, details are omitted.

  In the driving method (reset driving) described with reference to FIGS. 33 and 39, the driving transistor 11a or 11b and the EL element 15 are disconnected (the current does not flow. Performed by the transistor 11e or the transistor 11d) and the driving is performed. Between a drain (D) terminal and a gate (G) terminal of a transistor for driving (or a source (S) terminal and a gate (G) terminal, more generally two terminals including a gate (G) terminal of a driving transistor)) A first operation for short-circuiting and a second operation for performing a current (voltage) program on the driving transistor after the operation are performed.

  At least the second operation is performed after the first operation. Note that the operation of disconnecting the driving transistor 11a or the transistor 11b and the EL element 15 in the first operation is not necessarily an essential condition. If the driving transistor 11a or the transistor 11b and the EL element 15 in the first operation are not disconnected, the first operation of shorting between the drain (D) terminal and the gate (G) terminal of the driving transistor is performed. This is because there may be a case where a slight variation in the reset state may occur. This is determined by examining the transistor characteristics of the fabricated array.

  The pixel configuration of the current mirror in FIG. 39 is a driving method in which the current transistor transistor 11b is reset as a result by resetting the current program transistor 11a.

  In the pixel configuration of the current mirror in FIG. 39, it is not always necessary to disconnect the driving transistor 11b and the EL element 15 in the reset state. Accordingly, the drain (D) terminal and the gate (G) terminal (or the source (S) terminal and the gate (G) terminal) of the current programming transistor a, or more generally, the gate (G) terminal of the current programming transistor. A first operation for short-circuiting between the two terminals including the first terminal and the second terminal including the gate (G) terminal of the driving transistor), and a second program for performing current (voltage) programming on the current programming transistor after the first operation. Operation. At least the second operation is performed after the first operation.

  In the image display state (if an instantaneous change can be observed), first, the pixel row for which current programming is performed is in a reset state (black display state), and current programming is performed after a predetermined H. From the top to the bottom of the screen, the black pixel row should move, and the image should appear to be rewritten at the position where this pixel row has passed.

  Although the above embodiments have been described with a focus on the pixel configuration of the current program, the reset driving of the present invention can also be applied to the pixel configuration of the voltage program. FIG. 43 is an explanatory diagram of the pixel configuration (panel configuration) of the present invention for performing reset driving in the pixel configuration of the voltage program.

  In the pixel configuration of FIG. 43, a transistor 11e for resetting the driving transistor 11a is formed. When a turn-on voltage is applied to the gate signal line 17e, the transistor 11e is turned on, and the gate (G) terminal and the drain (D) terminal of the driving transistor 11a are short-circuited. In addition, a transistor 11d that cuts off a current path between the EL element 15 and the driving transistor 11a is formed. Hereinafter, the reset driving method of the present invention in the pixel configuration of the voltage program will be described with reference to FIG.

  As illustrated in FIG. 44A, the transistor 11b and the transistor 11d are turned off, and the transistor 11e is turned on. The drain (D) terminal and the gate (G) terminal of the driving transistor 11a are short-circuited, and an Ib current flows as shown in the figure. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the driving transistor 11a is reset (a state in which no current flows). Before resetting the transistor 11a, as described in FIG. 33 or FIG. 39, in synchronization with the HD synchronization signal, the transistor 11d is first turned on, the transistor 11e is turned off, and a current flows through the transistor 11a. Keep it. Thereafter, the operation shown in FIG.

  In the voltage-programmed pixel configuration, as in the current-programmed pixel configuration, the Ib current flows and the terminal voltage of the capacitor 19 tends to decrease as the reset execution time in FIG. . Therefore, the execution time of FIG. 44 (a) needs to be a fixed value. The implementation time is preferably 0.2H or more and 5H (5 horizontal scanning periods) or less. Furthermore, it is preferable to set it to 0.5H or more and 4H or less. Or it is preferable to set it as 2 to 400 microseconds.

  The gate signal line 17e is preferably shared with the gate signal line 17a in the previous pixel row. That is, the gate signal line 17e and the gate signal line 17a of the previous pixel row are formed in a short state. This configuration is called a pre-stage gate control system. Note that the pre-stage gate control method uses a gate signal line waveform of a pixel row selected at least 1H before the target pixel row. Therefore, it is not limited to one pixel row before. For example, the driving transistor 11a of the pixel of interest may be reset using the signal waveform of the gate signal line two rows before.

  A more specific description of the pre-stage gate control method is as follows. A pixel row of interest is an (N) pixel row, and its gate signal lines are a gate signal line 17e (N) and a gate signal line 17a (N). The pixel row in the previous stage selected 1H before is the (N-1) pixel row, and the gate signal lines are the gate signal line 17e (N-1) and the gate signal line 17a (N-1). . A pixel row selected after 1H after the pixel row of interest is an (N + 1) pixel row, and its gate signal lines are a gate signal line 17e (N + 1) and a gate signal line 17a (N + 1).

  In the (N−1) H period, when the ON voltage is applied to the gate signal line 17a (N−1) of the (N−1) th pixel row, the gate signal line 17e (N) of the (N) th pixel row. ) Is also applied with an ON voltage. This is because the gate signal line 17e (N) and the gate signal line 17a (N-1) in the previous pixel row are formed in a short state. Therefore, the transistor 11b (N-1) of the pixel in the (N-1) th pixel row is turned on, and the voltage of the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N-1). At the same time, the transistors 11e (N) of the pixels in the (N) th pixel row are turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N) are short-circuited, and the driving transistor 11a (N ) Is reset.

  In the (N) period following the (N−1) H period, when the ON voltage is applied to the gate signal line 17a (N) of the (N) pixel row, the gate signal of the (N + 1) pixel row. The on-voltage is also applied to the line 17e (N + 1). Accordingly, the transistor 11b (N) of the pixel in the (N) th pixel row is turned on, and the voltage applied to the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N). At the same time, the transistor 11e (N + 1) of the pixel in the (N + 1) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N + 1) are short-circuited, and the driving transistor 11a (N + 1) ) Is reset.

  Similarly, in the (N + 1) period subsequent to the (N) H period, when the ON voltage is applied to the gate signal line 17a (N + 1) in the (N + 1) th pixel row, the (N + 2) th pixel row. The on-voltage is also applied to the gate signal line 17e (N + 2). Accordingly, the transistor 11b (N + 1) of the pixel in the (N + 1) th pixel row is turned on, and the voltage applied to the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N + 1). At the same time, the transistor 11e (N + 2) of the pixel in the (N + 2) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N + 2) are short-circuited, and the driving transistor 11a (N + 2) ) Is reset.

  In the above-described pre-stage gate control system of the present invention, the driving transistor 11a is reset for 1H period, and then the voltage (current) program is executed.

  The same applies to FIG. 33A, but when the reset state of FIG. 44A and the voltage program state of FIG. 44B are performed in synchronization, the reset state of FIG. There is no problem because the period until the current programming state in FIG. 44 (b) is a fixed value (constant value). If this period is short, the driving transistor 11 is not completely reset. If the length is too long, the driving transistor 11a is completely turned off, and this time, it takes a long time to program the current. In addition, the brightness of the screen 12 is also reduced.

  After implementing FIG. 44A, the state shown in FIG. 44B is obtained. FIG. 44B shows a state in which the transistor 11b is turned on and the transistors 11e and 11d are turned off. The state shown in FIG. 44B is a state where voltage programming is performed. That is, a program voltage is output from the source driver circuit 14, and this program voltage is written to the gate (G) terminal of the driving transistor 11a (the potential of the gate (G) terminal of the driving transistor 11a is set in the capacitor 19). In the case of the voltage programming method, it is not always necessary to turn off the transistor 11d during voltage programming. Further, it is a combination of the N-fold pulse drive shown in FIGS. 13 and 15 or the like, or the intermittent N / K-fold pulse drive as described above (a drive method in which a plurality of lighting regions are provided on one screen. The transistor 11e is not necessary if it is not necessary to implement (by easily turning on and off the transistor 11e). Since this has been described before, the description is omitted.

  When the voltage program for white display is performed by the configuration of FIG. 43 or the driving method of FIG. 44, the offset voltage of each black display state (each driving transistor is completely different even if the characteristics of the driving transistor for each pixel vary. The voltage program is performed from the starting voltage at which a current set according to the characteristics of the current flows. Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a, and a good image display can be realized.

  After the current programming of FIG. 44B, as shown in FIG. 44C, the transistor 11b is turned off, the transistor 11d is turned on, and the program current from the driving transistor 11a is supplied to the EL element 15, and the EL The element 15 is caused to emit light.

  As described above, in the reset driving of the present invention in the voltage program of FIG. 43, first, in synchronization with the HD synchronization signal, the transistor 11d is first turned on, the transistor 11e is turned off, and the current flows through the transistor 11a. 1, the transistor 11 a and the EL element 15 are disconnected, and the drain (D) terminal and the gate (G) terminal (or the source (S) terminal and the gate (G) terminal of the driving transistor 11 a, In other words, a second operation for short-circuiting between the gate (G) terminals of the driving transistor) and a third operation for performing voltage programming on the driving transistor 11a after the above operation are performed. Is.

  In the above embodiment, the transistor 11d is turned on and off to control the current flowing from the driving transistor element 11a (in the pixel configuration of FIG. 1) to the EL element 15. In order to turn on and off the transistor 11d, it is necessary to scan the gate signal line 17b, and the shift register 61 (gate circuit 12) is necessary for scanning. However, the shift register 61 is large in scale and cannot be narrowed by using the shift register 61 for controlling the gate signal line 17b. The method described in FIG. 40 solves this problem.

  Although the present invention will be described mainly by exemplifying the pixel configuration of the current program illustrated in FIG. 1 and the like, the present invention is not limited to this, and other current program configurations described in FIG. Needless to say, the present invention can be applied to a pixel configuration. Needless to say, the technical concept of turning on / off in a block can be applied to the pixel configuration of the voltage program shown in FIG.

  FIG. 40 shows an embodiment of the block drive system. First, for ease of explanation, the description will be made assuming that the gate driver circuit 12 is formed directly on the substrate 71 or the gate driver IC 12 of a silicon chip is mounted on the substrate 71. Further, the source driver 14 and the source signal line 18 are omitted because the drawing becomes complicated.

  In FIG. 40, the gate signal line 17a is connected to the gate driver circuit 12. On the other hand, the gate signal line 17 b of each pixel is connected to the lighting control line 401. In FIG. 40, four gate signal lines 17b are connected to one lighting control line 401.

  Needless to say, blocking with the four gate signal lines 17b is not limited to this, and may be more than that. In general, the display area 50 is preferably divided into at least five or more. More preferably, it is preferably divided into 10 or more. Furthermore, it is preferable to divide into 20 or more. When the number of divisions is small, flicker is easy to see. If the number of divisions is too large, the number of lighting control lines 401 increases, and the layout of the control lines 401 becomes difficult.

  Therefore, in the case of the QCIF display panel, since the number of vertical scanning lines is 220, it is necessary to block at least 220/5 = 44 or more, and preferably block at 220/10 = 11 or more. There is a need to. However, when two blocks are formed on the odd and even lines, the occurrence of flicker is relatively small even at a low frame rate, and thus two blocks may be sufficient.

  In the embodiment of FIG. 40, an ON voltage (Vgl) or an OFF voltage (Vgh) is sequentially applied to the lighting control lines 401a, 401b, 401c, 401d. The current that flows is turned on and off.

  In the embodiment of FIG. 40, the gate signal line 17b and the lighting control line 401 do not cross each other. Therefore, a short defect between the gate signal line 17b and the lighting control line 401 does not occur. Further, since the gate signal line 17b and the lighting control line 401 are not capacitively coupled, the capacitance addition when the gate signal line 17b side is viewed from the lighting control line 401 is extremely small. Therefore, it is easy to drive the lighting control line 401.

  A gate signal line 17 a is connected to the gate driver 12. By applying an on voltage to the gate signal line 17a, a pixel row is selected, the transistors 11b and 11c of each selected pixel are turned on, and the current (voltage) applied to the source signal line 18 is supplied to each pixel. Program the capacitor 19. On the other hand, the gate signal line 17b is connected to the gate (G) terminal of the transistor 11d of each pixel. Therefore, when a turn-on voltage (Vgl) is applied to the lighting control line 401, a current path is formed between the driving transistor 11a and the EL element 15, and conversely, when a turn-off voltage (Vgh) is applied, the EL element Fifteen anode terminals are opened.

  Note that the control timing of the on / off voltage applied to the lighting control line 401 and the timing of the pixel row selection voltage (Vgl) output from the gate driver circuit 12 to the gate signal line 17a are synchronized with one horizontal scanning clock (1H). It is preferable. However, the present invention is not limited to this.

  The signal applied to the lighting control line 401 simply turns on and off the current to the EL element 15. Further, it is not necessary to be synchronized with the image data output from the source driver 14. This is because the signal applied to the lighting control line 401 controls the current programmed in the capacitor 19 of each pixel 16. Therefore, it is not necessarily required to be synchronized with the pixel row selection signal. Even in the case of synchronization, the clock is not limited to the 1H signal, and may be 1 / 2H or 1 / 4H.

  Even in the pixel configuration of the current mirror shown in FIG. 38, the transistor 11e can be controlled to be turned on / off by connecting the gate signal line 17b to the lighting control line 401. Therefore, block driving can be realized.

  In FIG. 32, if the gate signal line 17a is connected to the lighting control line 401 and resetting is performed, the block driving can be realized. That is, the block driving of the present invention is a driving method in which a plurality of pixel rows are simultaneously not lit (or black display) with one control line.

  In the above embodiment, one selected pixel row is arranged (formed) for each pixel row. The present invention is not limited to this, and one selection gate signal line may be arranged (formed) in a plurality of pixel rows.

  FIG. 41 shows an example. In order to facilitate the description, the pixel configuration will be described mainly using the case of FIG. In FIG. 41, the pixel row selection gate signal line 17a simultaneously selects three pixels (16R, 16G, 16B). The symbol “R” means a red pixel relationship, the symbol “G” means a green pixel relationship, and the symbol “B” means a blue pixel relationship.

  Therefore, by selecting the gate signal line 17a, the pixel 16R, the pixel 16G, and the pixel 16B are simultaneously selected to enter a data writing state. The pixel 16R writes data from the source signal line 18R to the capacitor 19R, and the pixel 16G writes data from the source signal line 18G to the capacitor 19G. The pixel 16B writes data from the source signal line 18B to the capacitor 19B.

  The transistor 11d of the pixel 16R is connected to the gate signal line 17bR. The transistor 11d of the pixel 16G is connected to the gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to the gate signal line 17bB. Accordingly, the EL element 15R of the pixel 16R, the EL element 15G of the pixel 16G, and the EL element 15B of the pixel 16B can be separately controlled on and off. That is, the EL element 15R, the EL element 15G, and the EL element 15B can individually control the lighting time and the lighting cycle by controlling the gate signal lines 17bR, 17bG, and 17bB.

  In order to realize this operation, in the configuration of FIG. 6, the shift register circuit 61 that scans the gate signal line 17a, the shift register circuit 61 that scans the gate signal line 17bR, and the shift register that scans the gate signal line 17bG. It is appropriate to form (place) four circuits 61 and shift register circuit 61 that scans gate signal line 17bB.

  Although a current N times the predetermined current is supplied to the source signal line 18 and a current N times the predetermined current is supplied to the EL element 15 for a period of 1 / N, this cannot be realized in practice. This is because the signal pulse applied to the gate signal line 17 actually penetrates the capacitor 19 and a desired voltage value (current value) cannot be set in the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set for the capacitor 19. For example, even if it is driven to set a current value 10 times, only about 5 times the current is set in the capacitor 19. For example, even when N = 10, the current that actually flows through the EL element 15 is the same as when N = 5. Therefore, the present invention is a method of setting the current value N times and driving the EL element 15 so that a current proportional to or corresponding to the N times flows through the EL element 15. Alternatively, it is a driving method in which a current larger than a desired value is applied to the EL element 15 in a pulse shape.

  Further, a current (voltage) program is applied to the driving transistor 11a (in the case of FIG. 1) by supplying a current (a current that is higher than the desired luminance when a current is continuously passed through the EL element 15 as it is) from a desired value. In this way, the light emission luminance of the desired EL element is obtained by making the current flowing through the EL element 15 intermittent.

  Further, the switching transistors 11b, 11c and the like shown in FIG. 1 are preferably formed of an N channel. This is because the penetration voltage to the capacitor 19 is reduced. Further, since the off-leakage of the capacitor 19 is also reduced, it can be applied to a low frame rate of 10 Hz or less.

  Further, depending on the pixel configuration, when the punch-through voltage acts in the direction of increasing the current flowing through the EL element 15, the white peak current increases and the contrast of the image display increases. Therefore, a good image display can be realized.

  On the other hand, it is also effective to make the black display better by causing the penetration transistors of the switching transistors 11b and 11c of FIG. When the P-channel transistor 11b is turned off, the voltage becomes Vgh. Therefore, the terminal voltage of the capacitor 19 is slightly shifted to the Vdd side. For this reason, the gate (G) terminal voltage of the transistor 11a rises, resulting in a black display. In addition, since the current value for the first gradation display can be increased (a constant base current can be made to flow until gradation 1), a shortage of write current can be reduced by the current programming method.

  The transistor 11b in FIG. 1 operates to hold the current flowing in the driving transistor 11a in the capacitor 19. That is, it has a function of shorting between the gate terminal (G) and the drain terminal (D) or the source terminal (S) of the driving transistor 11a at the time of programming. A switching transistor having a function like the transistor 11b is referred to as a short-circuit transistor. The short-circuit transistor has a source terminal or drain terminal connected to the holding capacitor 19. The short-circuit transistor is on / off controlled by the voltage applied to the gate signal line 17a. The problem is that the voltage of the gate signal line 17a penetrates the capacitor 19 when the off-voltage is applied. Due to this punch-through voltage, the potential of the capacitor 19 (= the potential of the gate terminal (G) of the driving transistor 11a) fluctuates, and a good current program cannot be performed, causing laser shot unevenness and the like. Therefore, it is necessary to reduce the punch-through voltage.

  In order to reduce the punch-through voltage, it is preferable to reduce the size of the short-circuit transistor 11b. Now, the size Scc of the short-circuit transistor is defined as channel width W (μm) and channel length L (μm), and Scc = W · L (square μm). When a plurality of short-circuit transistors are connected in series, Scc is the sum of the connected transistor sizes. For example, if W = 5 (μm) and L = 6 (μm) of one short-circuit transistor and the number (n = 4) is connected, Scc = 5 × 6 × 4 = 120 (square μm) ).

  There is a correlation between the size of the short-circuit transistor and the punch-through voltage. This relationship is shown in FIG. Note that the short-circuit transistor is a P-channel transistor. However, even an N-channel transistor can be applied.

  In FIG. 194, the horizontal axis is Scc / n. As described above, Scc is the sum of the sizes of the short-circuit transistors. n is the number of connected short-circuit transistors. In FIG. 194, the horizontal axis represents n pieces of Scc. That is, the size of one short-circuit transistor is one.

  In the first embodiment, when the size Scc of the short-circuit transistor is the channel width W (μm) and the channel length L (μm), and the number of short-circuit transistors is n = 4, Scc / n = 5 × 6 × 4/4 = 30 (square μm). In FIG. 194, the vertical axis represents the penetration voltage (V).

  If the punch-through voltage is not within 0.3 (V), laser shot unevenness occurs and is not visually acceptable. Therefore, the size of one short-circuited transistor needs to be 25 (square μm) or less. On the other hand, unless the short-circuit transistor is set to 5 (square μm) or more, the processing accuracy of the transistor cannot be achieved and the variation becomes large. There is also a problem with drive capability. From the above, the short-circuit transistor 11b needs to be 5 (square μm) or more and 25 (square μm) or less. More preferably, the short-circuit transistor 11b needs to be 5 (square μm) or more and 20 (square μm) or less.

  The punch-through voltage due to the short-circuit transistor is also correlated with the amplitude value (Vgh−Vgl) of the voltage (Vgh, Vgl) for driving the short-circuit transistor. The larger the amplitude value, the larger the punch-through voltage. This relationship is illustrated in FIG. In FIG. 196, the horizontal axis represents the amplitude value (Vgh−Vhl) (V). The vertical axis represents the penetration voltage. As described with reference to FIG. 194, the punch-through voltage needs to be 0.3 (V) or less.

  In other words, the permissible voltage 0.3 (V) of the penetration voltage is 1/5 or less (20% or less) of the amplitude value of the source signal line 18. The source signal line 18 is 1.5 (V) when the program current is white, and 3.0 (V) when the program current is black. Therefore, (3.0−1.5) /5=0.3 (V).

  On the other hand, if the amplitude value (Vgh−Vhl) of the gate signal line is 4 (V) or more, the pixel 16 cannot be sufficiently written. From the above, the amplitude value (Vgh−Vgl) of the gate signal line needs to satisfy the condition of 4 (V) or more and 15 (V) or less. More preferably, the amplitude value (Vgh−Vgl) of the gate signal line needs to satisfy the condition of 5 (V) or more and 12 (V) or less.

  In the configuration of the pixel 16 such as FIG. 1, the driving transistor 11 a has one configuration for each pixel 16. However, in the present invention, the driving transistor 11a is not limited to one. For example, the pixel configuration in FIG. 315 is illustrated.

  FIG. 315 shows an embodiment in which five driving transistors 11a are configured. Other configurations are the same as those of the embodiment of FIG. In FIG. 315 and the like, it goes without saying that the transistor 11e may be added as shown in FIG. Needless to say, the above matters also apply to other embodiments of the present invention.

  In the embodiment of FIG. 1, there is a relationship of program current Iw = current flowing in the EL element 15. Therefore, when the EL element 15 emits light with low luminance, the program current Iw is also reduced, and the source signal line 18 is easily affected by the parasitic capacitance (it takes a long time to charge and discharge the parasitic capacitance, and the 1H period In the meantime, it becomes difficult to change the gate terminal potential of the driving transistor 11a to a predetermined potential).

  In the embodiment of FIG. 315, when the gate signal line 17a is selected, the transistors 11e, 11b, and 11c are activated, and a current path between the driving transistor 11a and the source signal line 18 is formed. The program current Iw is a combination of the currents of the driving transistors 11a, 11a2, 11a3, 11a4, and 11a5. For ease of explanation, it is assumed that the currents flowing through the driving transistors 11a are equal. For ease of explanation, the transistor 11a that supplies current to the EL element 15 is referred to as a driving transistor, and the transistor 11a2 that operates during current programming is referred to as a programming transistor 11a.

  In FIG. 315, the drive transistor 11a and each program transistor 11a have the same output current (when the voltages applied to the gate terminals are the same). In order to make the output currents equal, the WL (channel width W and channel length L) of each transistor 11a may be the same. It is preferable to form a plurality of transistors 11a having the same WL because output variations of the transistors 11a are reduced and variations between the pixels 16 are reduced. This is the same reason that the source driver IC 14 shown in FIG. However, the present invention is not limited to this, and the plurality of programming transistors 11a may be formed or configured as one programming transistor 11a. Also in this case, the configuration is easy. This is because the programming transistor 11a may be formed with a large W.

  When a selection voltage (ON voltage) is applied to the gate signal line 17a, a combination of currents from the driving transistor 11a and the programming transistor 11a becomes the programming current Iw. The program current Iw is set to a predetermined magnification of the current Ie flowing through the EL element 15.

Iw = n · Ie (n is a natural number greater than 1)
In the above equation, the display brightness B (nt) at the maximum white raster of the display panel, the pixel area S (square millimeter) of the display panel (the pixel area is handled with RGB as one unit. If 0.1 mm and 0.05 mm in width, S = 0.1 × (0.05 × 3) (square millimeter)), one pixel row selection period (one horizontal scanning (1H) period) of the display panel When H is H (milliseconds), the following conditions are satisfied. Note that the display brightness B is the maximum displayable brightness specified in the panel specification.

5 <= (B.S) / (n.H) <= 150
More preferably, the following conditions are satisfied.

10 <= (B.S) / (n.H) <= 100
In addition, A <= B means B is more than A.

  The above items also apply to n, B, H and the assumed pixel size S described in FIGS. 13, 14, 15, 16, and 17. In this case, n is driven so as to satisfy Iw = n · Ie. The above relational expression is also applied to other embodiments of the present invention such as FIGS. 323 and 325.

  Iw is a program current output from the source driver IC (circuit) 14, and a voltage corresponding to this program current is held in the capacitor 19 of the pixel 16. Ie is a current that the driving transistor 11a passes through the EL element 15. However, errors due to punch-through voltage are not considered.

  Therefore, the WL, size, and output current of the programming transistor 11a are configured or formed so as to satisfy the above relational expression. In the configuration of FIG. 315, assuming that the size or supply current of the driving transistor 11a is equal to the size or supply current of the programming transistor 11a, the n-1 programming transistors 11a are formed. The relation of the formula can be satisfied. In particular, in the pixel configuration of FIG. 315, the current of the driving transistor 11a can also be set to the program current, and the aperture ratio of the pixel 16 can be made higher than the pixel configuration of the current mirror.

  By configuring the pixel 16 as described above, the program current Iw becomes n times as large as Ie. Therefore, even if parasitic capacitance exists in the source signal line 18, there is no shortage of writing.

  In FIG. 1, the program current Iw and the current Ie flowing through the EL element 15 are the same, and no variation occurs. However, in the configuration of FIG. 315, a part of the program current Iw becomes the current Ie that flows through the EL element 15. Therefore, variation may occur.

  In order to prevent this problem, the programming transistor 11a and the driving transistor 11a are formed or arranged close to each other (see FIG. 316). In FIG. 316, the driving transistor 11a and the programming transistor 11a are formed in the same WL. Further, the left and right sides of the driving transistor 11a are formed or arranged so as to be surrounded by the programming transistor 11a. With the configuration as described above, variations in the transistor 11a can be reduced, and a highly accurate relationship of Iw = n · Ie can be maintained.

  In the embodiment of FIG. 315, there is one drive transistor 11a, but the present invention is not limited to this. As shown in FIG. 317, a plurality of driving transistors may be formed (11aa, 11ab).

  The characteristics of the transistor 11a may vary depending on the formation direction. Therefore, as shown in FIG. 316, the output variation can be reduced by forming one driving transistor 11aa in the horizontal direction and forming the other driving transistor 11ab in the vertical direction. The same applies to FIG. 116). In addition, as shown in FIG. 316, the programming transistors 11a are also preferably arranged in the vertical direction and the horizontal direction.

  In the EL display panel, the RGB EL elements are made of different materials. Therefore, the luminous efficiency is often different for each color. Therefore, each RGB program current Iw is also different. The parasitic capacitance of the source signal line 18 generally does not change with respect to RGB and is often the same. If the RGB program currents Iw are different and the parasitic capacitances of the source signal lines 18 are the same in RGB, the program current write time constants are different.

  To deal with this problem, the present invention changes the number of RGB programming transistors 11a as shown in FIG. As an example, the number of programming transistors 11a in the R pixel 16 is two, the number of programming transistors 11a in the G pixel 16 is four, and the number of programming transistors 11a in the B pixel 16 is one.

  In the embodiment shown in FIG. 319, the number of RGB programming transistors 11a is changed. However, the present invention is not limited to this. For example, it goes without saying that the size (WL or the like) of each RGB programming transistor 11an or the magnitude of the supply current may be changed. Needless to say, if the RGB program currents Iw are the same or similar, the number of programming transistors 11an may be the same for RGB.

  The embodiment of FIG. 319 is an embodiment in which the number of programming transistors 11an and the like are changed in RGB, but the present invention is not limited to this. For example, as shown in FIG. 320, the number or size of the driving transistors 11a may be changed. In FIG. 320, it is formed or configured such that the size of the driving transistor 11a for the B pixel> the size of the driving transistor 11a for the G pixel> the size of the driving transistor 11a for the R pixel.

  In the embodiment of FIG. 315 and the like, during current programming, the current Ie of the driving transistor 11a is output to the source signal line 18 via the transistor 11e and the transistor 11c. On the other hand, the output current Iw-Ie of the programming transistor 11a is output to the source signal line 18 via only one transistor 11c. In the transistors 11e and 11c, a potential difference between the source and the drain is generated even in the on state. For this reason, the output current of the driving transistor 11a may be smaller than the output current per one of the programming transistors 11a.

  For this problem, it is preferable to configure or form as shown in FIG. In the configuration of FIG. 321, the current Ie of the driving transistor 11a1 is output to the source signal line 18 via the transistor 11c1 during current programming. On the other hand, the output current Iw-Ie of the programming transistor 11an is output to the source signal line 18 via the transistor 11c2. Therefore, the number of transistors passing through the source signal line 18 is equal between the driving transistor 11a1 and the programming transistor 11an. Therefore, since the influence of the potential difference between the source and drain of the transistor does not occur, the output current per one programming transistor 11an is equal to the output current of the driving transistor 11a1. In FIG. 321, a driving transistor 11a is formed or arranged with a gate-drain short-circuit transistor 11b1. Similarly, a gate-drain short transistor 11b2 is formed or arranged in the program transistor 11an.

  FIG. 322 is a pixel configuration diagram in which a transistor 11e that connects the drain terminal of the programming transistor 11a1 and the drain terminal of the programming transistor 11an is formed. However, in the pixel configuration in FIG. 322, since the number of transistors constituting the pixel 16 is as large as seven, the pixel aperture ratio decreases.

  In FIG. 323, the number of transistors constituting the pixel 16 is six, and the program transistor 11an is configured to be connected to the source signal line 18 via the two transistors 11b2 and 11c. 11a1 is an embodiment configured to be connected to the source signal line 18 via two transistors 11b1 and 11c.

  In FIG. 323, the gate terminal of the driving transistor 11a1 and the gate terminal of the programming transistor 11an are made common. The transistor 11b1 operates so as to short-circuit the drain terminal and the gate terminal of the driving transistor 11a1 during current programming. The transistor 11b2 operates so as to short-circuit the drain terminal and the gate terminal of the programming transistor 11an during current programming. The transistor 11c is connected to the gate terminal of the driving transistor 11a1, and the transistor 11d is formed or arranged between the driving transistor 11a1 and the EL element 15, and controls the current flowing through the EL element 15. An additional capacitor 19 is formed or disposed between the gate terminal and the anode (Vdd) terminal of the driving transistor 11a1, and the source terminals of the driving transistor 11a1 and the programming transistor 11an are connected to the anode (Vdd) terminal. ing.

  As described above, by configuring the driving transistor 11a1 and the programming transistor 11an to pass through the same number of transistors, the accuracy can be improved. That is, the current flowing through the driving transistor 11a1 flows to the source signal line 18 through the transistors 11b1 and 11c. The current flowing through the programming transistor 11an flows to the source signal line 18 through the transistor 11b2 and the transistor 11c. Therefore, the current of the driving transistor 11a1 and the current of the programming transistor 11an pass through the same number of two transistors and flow to the source signal line 18.

  When the gate signal line 17a is selected, both the driving transistor 11a1 and the programming transistor 11an are turned on. It is preferable that the current Iw1 flowing through the driving transistor 11a1 and the current Iw2 flowing through the programming transistor 11a1 are substantially matched. Most preferably, the sizes (W, L) of the programming transistor 11an and the driving transistor 11a1 are matched. That is, it is preferable to satisfy the relationship of Iw1 = Iw2 and Iw = 2Ie. Of course, satisfying the relationship of Iw1 = Iw2 is not limited to matching the transistor sizes (W, L), but may be matched by changing the size. This can be easily realized by adjusting the WL of the transistor. If approximately Iw2 / Iw1 = 1, the sizes of the transistors 11b1 and 11b1 can be configured or formed to be substantially the same.

  It should be noted that Iw2 / Iw1 preferably satisfies the relationship of 1 or more and 10 or less. Iw2 / Iw1 preferably satisfies a relationship of 1 or more and 10 or less. More preferably, the relationship of 1.5 to 5 is preferably satisfied.

  When Iw2 / Iw1 is 1 or less, the effect of improving the influence of the parasitic capacitance of the source signal line 18 is hardly expected. On the other hand, if Iw2 / Iw is 10 or more, the relationship between Ie and Iw varies from pixel to pixel, and a uniform image display cannot be realized. In addition, the transistor 11b is greatly affected by the on-resistance, and pixel design becomes difficult.

  When the current Iw2 flowing through the programming transistor 11an is larger than the current Iw1 flowing through the driving transistor 11a1 (Iw2> Iw1), the on-resistance of the switching transistor 11b2 is set higher than the on-resistance of the switching transistor 11b1. Need to be smaller. This is because the switching transistor 11b2 needs to be configured so that a current larger than that of the transistor 11b1 flows to the voltage of the same gate signal line 17a.

  That is, it is necessary to match the magnitude of the transistor 11b1 with respect to the magnitude of the output current of the driving transistor 11a1 and the magnitude of the transistor 11b2 with respect to the magnitude of the output current of the programming transistor 11an.

  In other words, it is necessary to change the on-resistance of the transistor 11b with respect to the program current Iw2 and the program current Iw1. Further, it is necessary to change the sizes of the transistors 11b1 and 11b2 with respect to the program current Iw2 and the program current Iw1.

  If the program current Iw2 is larger than the program current Iw1, the on-resistance of the transistor 11b2 needs to be smaller than the on-resistance of the transistor 11b1 (in the case where the gate terminal voltages of the transistor 11b1 and the transistor 11b2 are the same). If the program current Iw2 is larger than the program current Iw1, the on-current (Iw2) of the transistor 11b2 needs to be larger than the on-current (Iw1) of the transistor 11b1 (when the gate terminal voltages of the transistor 11b1 and the transistor 11b2 are the same) Is).

  When Iw2: Iw1 = n: 1, an on-voltage is applied to the gate signal line 17a, and when the transistor 11b1 and the transistor 11b2 are turned on, the on-resistance of the transistor 11b2 is R2, and the on-resistance of the transistor 11b1 is R1. At this time, R2 is configured to satisfy the relationship of R1 / (n + 5) or more and R1 / (n) or less. To configure means to form, arrange or operate the transistor 11b in a predetermined size. However, n is a value larger than 1.

  Note that the above item is an explanation of the on-resistance R or the program current Iw of the transistors 11b1 and 11b2. Accordingly, any configuration is possible as long as the pixel configuration is realized so as to satisfy the above-described conditions. For example, when the gate signal line 17 connected to the gate terminal of the transistor 11b1 and the gate signal line 17 connected to the gate terminal of the transistor 11b2 are different signal lines, the voltage applied to each gate signal line is changed. As a result, the on-resistance and the like can be changed, and the conditions of the present invention can be satisfied.

  FIG. 324 is an explanatory diagram of the operation of the pixel configuration of FIG. FIG. 323 (a) shows a current program state, and FIG. 323 (b) shows a state where current is supplied to the EL element 15. Needless to say, intermittent display may be performed by turning on and off the transistor 11d in the state of FIG.

  In FIG. 324 (a), an on-voltage is applied to the gate signal line 17a, and the transistors 11b1, 11b2, and 11c are turned on. The transistor 11a1 supplies a current Ie, the transistor 11an supplies a current Iw-Ie, and the combined current Iw becomes a program current for the source driver Ic. With the above operation, a voltage corresponding to the program current Iw is held in the capacitor 19. During current programming, the transistor 11d is held in the off state (the off voltage is applied to the gate signal line 17b).

  The case where a current is passed through the EL element 15 is set to the operation state shown in FIG. An off voltage is applied to the gate signal line 17a, and an on voltage is applied to the gate signal line 17b. In this state, the transistors 11b1, 11b2, and 11c are turned off, and the transistor 11d is turned on. An Ie current is supplied to the EL element 15.

  FIG. 325 is a modification of FIG. In FIG. 325, the transistor 11c is arranged between the source signal line 18 and the drain terminal of the transistor 11a1. As described above, a number of modified examples can be illustrated in FIG. 323.

  In FIG. 323, the transistors 11b1, 11b2, and 11c are controlled by applying an on / off voltage to the gate signal line 17a. However, when the transistors 11b1 and 11b2 and the transistor 11c are turned off at the same time when changing from the current programming state to a state other than the current programming state, if the transistor 11c is turned off earlier than the transistors 11b1 and 11b2, the capacitor 19 holds it. The applied voltage may change from a specified value. Due to the change, an error occurs in the current Ie supplied from the driving transistor 11a to the EL element 15.

  For this problem, a configuration as shown in FIG. 376 is preferable. In FIG. 376, the gate terminals of the transistors 11b1 and 11b2 of the gate signal line 17a1 are connected. The gate terminal of the transistor 11c is connected to the gate signal line 17a2. Therefore, the transistors 11b1 and 11b2 are on / off controlled by applying an on / off voltage to the gate signal line 17a1. Further, the transistor 11c is on / off controlled by applying an on / off voltage to the gate signal line 17a2.

  When changing from the current programming state to a state other than the current programming state (when changing from the state in which the on-voltage is applied to the gate signal lines 17a1 and 17a2 to the state in which the off-voltage is applied to the gate signal lines 17a1 and 17a2) The applied voltage of the gate signal line 17a1 is changed from the on voltage to the off voltage. Accordingly, the transistors 11b1 and 11b2 are turned off. Next, the gate signal line 17a2 is changed from the on-voltage applied state to the off-voltage applied state. Accordingly, the transistor 11c is turned off.

  As described above, by turning off the transistors 11b1 and 11b2 and then turning off the transistor 11c, the influence of the punch-through voltage is reduced and the amount of leakage current is also reduced. The voltage is as specified. Note that it is preferable that the difference in timing of applying the off voltage to the gate signal line 17a1 and the gate signal line 17a2 is 0.1 μsec or more and 5 μsec or less.

  The above embodiment is a modification of FIG. The present invention is not limited to this, and can also be applied to the pixel configuration of the current mirror of FIG.

  FIG. 377 shows an embodiment of the present invention. FIG. 377 shows an embodiment in which a pixel is configured with one driving transistor 11b and four programming transistors 11an. Other configurations are the same as those of the embodiment of FIG.

  In the embodiment of FIG. 377, when the gate signal lines 17a1 and 17a2 are selected, the transistors 11c and 11d are activated, and a current path between the programming transistor 11an and the source signal line 18 is formed. The four programming transistors 11an are preferably formed with the same size (the same WL). However, in the present invention, the programming transistor 11an may be composed of one. In this case, it is preferable to realize a predetermined program current Iw in consideration of the shape or WL ratio of one program transistor 11an.

  In the embodiment of FIG. 377, the program current Iw is the sum of the currents of the four program transistors 11an. For ease of explanation, it is assumed that the currents flowing through the programming transistors 11a are equal. For ease of explanation, the transistor 11a that supplies current to the EL element 15 is referred to as a driving transistor 11b, and the transistor 11an that operates during current programming is referred to as a programming transistor 11an.

  In FIG. 377, the driving transistor 11b and one programming transistor 11an have the same output current (when the voltages applied to the gate terminals of the driving transistor and the programming transistor are the same). In order to make the output currents equal, the transistors 11an and 11b have the same WL (channel width W and channel length L). It is preferable to form a plurality of transistors 11a having the same WL because output variations of the transistors 11a are reduced and variations between the pixels 16 are reduced.

  When a selection voltage (ON voltage) is applied to the gate signal lines 17a1 and 17a2, a combination of currents from the plurality of programming transistors 11an becomes the programming current Iw. The program current Iw is set to a predetermined magnification of the current Ie flowing from the driving transistor 11b to the EL element 15.

Iw = n · Ie (n is a natural number greater than 1)
In the above equation, the display brightness B (nt) at the maximum white raster of the display panel, the pixel area S (square millimeter) of the display panel (the pixel area is handled with RGB as one unit. If 0.1 mm and 0.05 mm in width, S = 0.1 × (0.05 × 3) (square millimeter)), one pixel row selection period (one horizontal scanning (1H) period) of the display panel When H is H (milliseconds), the following conditions are satisfied. Note that the display brightness B is the maximum displayable brightness specified in the panel specification.

5 <= (B.S) / (n.H) <= 150
More preferably, the following conditions are satisfied.

10 <= (B.S) / (n.H) <= 100
Iw is a program current output from the source driver IC (circuit) 14, and a voltage corresponding to this program current is held in the capacitor 19 of the pixel 16. Ie is a current that the driving transistor 11a passes through the EL element 15.

  Therefore, the WL, size (shape), and output current of the driving transistor 11b and the programming transistor 11a are configured or formed so as to satisfy the above relational expression. For ease of explanation, in the configuration of FIG. 377, assuming that the size or supply current of the driving transistor 11b is equal to the size (shape) of the programming transistor 11an or supply current per one, n−1. The relationship of the above equation can be satisfied by forming the programming transistors 11a. In particular, in the pixel configuration of FIG. 315, the current of the driving transistor 11a can also be set to the program current, and the aperture ratio of the pixel 16 can be made higher than the pixel configuration of the current mirror.

  By configuring the pixel 16 as described above, the program current Iw becomes n times as large as Ie. Therefore, even if parasitic capacitance exists in the source signal line 18, there is no shortage of writing.

  Regarding the output variations of the transistors 11b and 11an, the programming transistor 11an and the driving transistor 11b are formed or arranged close to each other as in FIG. 315 (the description is omitted because it is similar to FIG. 316). Further, the characteristics of the transistors 11an and 11b may differ depending on the formation direction. Therefore, it is preferable to form in the horizontal direction or the vertical direction as shown in FIG.

  In the EL display panel, the RGB EL elements are made of different materials. Therefore, the luminous efficiency is often different for each color. Therefore, each RGB program current Iw is also different. The parasitic capacitance of the source signal line 18 generally does not change with respect to RGB and is often the same. If the RGB program currents Iw are different and the parasitic capacitances of the source signal lines 18 are the same in RGB, the program current write time constants are different.

  With respect to the pixel configuration of FIG. 377 as well as FIG. 319, the number of RGB programming transistors 11an may be changed. Needless to say, the size (WL or the like) or the magnitude of the supply current of each of the RGB programming transistors 11an may be changed. Further, as described in FIG. 320, the number or size of the driving transistor 11a may be changed.

  FIG. 378 shows a configuration in which the transistor 11c and the transistor 11d can be controlled by a voltage applied to the gate signal line 17a. In the configuration of FIG. 378, only two gate signal lines 17 are required to drive the pixels 16, so that the number of wiring signal lines can be reduced. However, in FIG. 378, the transistors 11c and 11d are controlled by applying an on / off voltage to the gate signal line 17a.

  However, when the transistor 11c and the transistor 11d are turned off at the same time or when the transistor 11d is turned off before the transistor 11c when the current programming state changes to a state other than the current programming state, the voltage held in the capacitor 19 is reduced. It may change from the specified value. Due to the change, an error occurs in the current Ie supplied from the driving transistor 11b to the EL element 15.

  For this problem, it is preferable to configure as shown in FIG. In FIG. 377, the transistor 11c is controlled by the gate signal line 17a1. The transistor 11d is controlled by the gate signal line 17a2. Therefore, the transistor 11c is controlled to be turned on / off by applying an on / off voltage to the gate signal line 17a1. Further, the transistor 11d is on / off controlled by applying an on / off voltage to the gate signal line 17a2.

  When changing from the current programming state to a state other than the current programming state (when changing from the state in which the on-voltage is applied to the gate signal lines 17a1 and 17a2 to the state in which the off-voltage is applied to the gate signal lines 17a1 and 17a2) The applied voltage of the gate signal line 17a2 is changed from the on voltage to the off voltage. Accordingly, the transistor 11d is turned off. Next, the gate signal line 17a1 is changed from the on-voltage applied state to the off-voltage applied state. Accordingly, the transistor 11c is turned off.

  As described above, when the transistor 11d is turned off and then the transistor 11c is turned off, the influence of the punch-through voltage is reduced and the amount of leakage current is also reduced. Is as specified. Note that it is preferable that the difference in timing of applying the off voltage to the gate signal line 17a1 and the gate signal line 17a2 is 0.1 μsec or more and 5 μsec or less.

  In the embodiments shown in FIGS. 377 and 378, the driving transistor 11b and the programming transistor 11an are described as having the same size. However, the present invention is not limited to this, and the driving transistor as shown in FIG. The size or shape of 11b and the size or shape of the programming transistor 11an may be changed.

  In FIGS. 315 to 325 and FIGS. 376 to 379, an example of a pixel configuration in which Iw and Ie are mainly different or a pixel configuration having a program transistor and a drive transistor is shown. It is effective to combine this pixel configuration (panel configuration) with another embodiment of the present invention. For example, combinations with driving methods such as FIGS. 13, 16, 17, 19, 24, 29, 30, 30, 100, 101, 102, and 288 to 302 are exemplified. Further, combinations with driving methods such as FIGS. 34, 40, and 41 are exemplified. 48, 65, 169 to 172, 185 to 223, 255 to 260, 274, 305 to 314, 327 to 337, 350 to 357, and 386. A combination with the source driver circuit 14 such as FIG. 392 is illustrated. In addition, combinations of the driving methods shown in FIGS. 85 to 96 and 108 are exemplified. A combination with the driving method or configuration shown in FIGS. 127 to 132 is also effective. A combination with the apparatus of FIGS. 147 to 156 is also effective. Combinations with the pixel configurations of FIGS. 261 to 265 are also effective. Further, combinations with panel configurations such as FIGS. 268 to 272, 360, 361, and 388 are also effective. Combinations with power supply circuit configurations such as FIGS. 112, 177 to 183, and 394 to 398 are also effective. Needless to say, the present invention can be implemented by mutually adopting or combining the matters described in the specification as in the above example.

  Hereinafter, another driving method of the present invention will be described with reference to the drawings. FIG. 125 is an explanatory diagram of a display panel for carrying out the sequence driving of the present invention. The source driver circuit 14 switches the R, G, B data to the connection terminal 681 and outputs it. Therefore, the number of output terminals of the source driver circuit 14 can be reduced to 1/3 as compared with the case of FIG.

  A signal output from the source driver circuit 14 to the connection terminal 681 is distributed to the source signal lines 18R, 18G, and 18B by the output switching circuit 1251. The output switching circuit 1251 is directly formed on the substrate 71 by polysilicon technology or amorphous silicon technology. The output switching circuit 1251 may be formed of a silicon chip and mounted on the substrate 71 by COG technology, TAB technology, or COF technology. Further, the output switching circuit 1251 may incorporate the changeover switch 1251 in the source driver circuit 14 as a circuit of the source driver circuit 14.

  When the changeover switch 1252 is connected to the R terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18R. When the changeover switch 1252 is connected to the G terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18G. When the changeover switch 1252 is connected to the B terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18B.

  In the configuration of FIG. 126, when the changeover switch 1252 is connected to the R terminal, the G terminal and B terminal of the changeover switch are open. Therefore, the current input to the source signal lines 18G and 18B is 0A. Therefore, the pixels 16 connected to the source signal lines 18G and 18B display black.

  When the changeover switch 1252 is connected to the G terminal, the R terminal and the B terminal of the changeover switch are open. Therefore, the current input to the source signal lines 18R and 18B is 0A. Therefore, the pixels 16 connected to the source signal lines 18R and 18B display black.

  In the configuration of FIG. 126, when the changeover switch 1252 is connected to the B terminal, the R terminal and the G terminal of the changeover switch are open. Therefore, the current input to the source signal lines 18R and 18G is 0A. Therefore, the pixels 16 connected to the source signal lines 18R and 18G display black.

  Basically, when one frame is composed of three fields, R image data is sequentially written in the pixels 16 of the display area 50 in the first field. In the second field, G image data is sequentially written to the pixels 16 in the display area 50. In the third field, B images are sequentially written in the pixels 16 of the display area 50.

  As described above, R data → G data → B data → R data → G data → B data → R data →. As described with reference to FIGS. 5, 13, and 16, the switching transistor 11 d is turned on / off as shown in FIG. 1 to realize N-fold pulse driving. Needless to say, these driving methods can be combined with sequence driving. Of course, it goes without saying that other driving methods of the present invention and sequence driving can be combined.

  In the embodiment described above, when image data is written to the R pixel 16, black data is written to the G pixel and the B pixel. When image data is written to the G pixel 16, black data is written to the R pixel and the B pixel. When image data is written to the B pixel 16, black data is written to the R pixel and the G pixel. The present invention is not limited to this.

  For example, when image data is written to the R pixel 16, the image data of the G pixel and the B pixel may hold the image data rewritten in the previous field. By driving in this way, the brightness of the screen 50 can be increased. When the image data is written to the G pixel 16, the image data of the R pixel and the B pixel is retained as the image data rewritten in the previous field. When writing image data to the B pixel 16, the image data of the G pixel and the R pixel holds the image data rewritten in the previous field.

  As described above, in order to hold image data of pixels other than the color pixel being rewritten, the gate signal line 17a may be controlled independently by RGB pixels. For example, as shown in FIG. 125, the gate signal line 17aR is a signal line for controlling on / off of the transistors 11b and 11c of the R pixel. The gate signal line 17aG is a signal line for controlling on / off of the transistors 11b and 11c of the G pixel. The gate signal line 17aB is a signal line for controlling on / off of the transistors 11b and 11c of the B pixel. On the other hand, the gate signal line 17b is a signal line that turns on and off the transistors 11d of the R pixel, the G pixel, and the B pixel in common.

  With the above configuration, when the source driver circuit 14 outputs R image data and the switch 1252 is switched to the R contact, an ON voltage is applied to the gate signal line 17aR, and the gate signal line aG and gate An off voltage can be applied to the signal line aB. Accordingly, R image data can be written to the R pixel 16, and the G pixel 16 and the B pixel 16 can retain the image data of the field before.

  In the second field, when the source driver circuit 14 outputs G image data and the switch 1252 is switched to the G contact, an ON voltage is applied to the gate signal line 17aG, and the gate signal line aR, the gate signal line aB, An off-voltage can be applied to. Therefore, the G image data can be written into the G pixel 16, and the R pixel 16 and the B pixel 16 can retain the image data of the field before.

  When the source driver circuit 14 outputs B image data and the switch 1252 is switched to the B contact in the third field, an ON voltage is applied to the gate signal line 17aB, and the gate signal line aR, the gate signal line aG, An off-voltage can be applied to. Therefore, the B image data can be written to the B pixel 16, and the R pixel 16 and the G pixel 16 can retain the image data of the field before.

  In the embodiment of FIG. 125, the gate signal line 17a for turning on and off the transistor 11b of the pixel 16 is formed or arranged for each of RGB. However, the present invention is not limited to this. For example, as shown in FIG. 126, a configuration in which a gate signal line 17a common to the RGB pixels 16 is formed or arranged may be employed.

  In the configuration of FIG. 125 and the like, it has been described that the G source signal line and the B source signal line are opened when the changeover switch 1252 selects the R source signal line. However, the open state is an electrically floating state, which is not preferable.

  FIG. 126 shows a configuration in which measures are taken to eliminate this floating state. The a terminal of the switch 1252 of the output switching circuit 1251 is connected to the Vaa voltage (voltage for black display). The b terminal is connected to the output terminal of the source driver circuit 14. The switch 1252 is provided for each of RGB.

  In the state of FIG. 126, the switch 1252R is connected to the Vaa terminal. Therefore, Vaa voltage (black voltage) is applied to the source signal line 18R. The switch 1252G is connected to the Vaa terminal. Therefore, Vaa voltage (black voltage) is applied to the source signal line 18G. The switch 1252B is connected to the output terminal of the source driver circuit 14. Therefore, the B video signal is applied to the source signal line 18B.

  In the above state, the B pixel is rewritten, and the black display voltage is applied to the R pixel and the G pixel. By controlling the switch 1252 as described above, the image of the pixel 16 is rewritten. Note that the control of the gate signal line 17b and the like are the same as those in the previously described embodiment, and thus the description thereof is omitted.

  In the above embodiment, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel that is rewritten for each field changes. The present invention is not limited to this. The color of the pixel to be rewritten may be changed every horizontal scanning period (1H). For example, the R pixel is rewritten in the 1H, the G pixel is rewritten in the 2Hth, the B pixel is rewritten in the 3Hth, the R pixel is rewritten in the 4Hth, and so on. Of course, the color of the pixel to be rewritten may be changed every 2H or more horizontal scanning periods, or the color of the pixel to be rewritten may be changed every 1/3 field.

  FIG. 127 shows an embodiment in which the color of the pixel to be rewritten is changed every 1H. In FIG. 127 to FIG. 129, the pixel 16 shown by hatching indicates that the image data of the previous field is held without rewriting the pixel, or is displayed in black. Of course, it may be repeatedly performed such that the pixel is displayed in black or the data of the previous field is retained.

  Needless to say, in the driving methods shown in FIGS. 125 to 129, N-fold pulse driving or M-row simultaneous driving as shown in FIG. 125 to 129 and the like illustrate the writing state of the pixel 16. Although the lighting control of the EL element 15 will not be described, it goes without saying that the embodiments described before or after can be combined. Of course, the configuration in which the dummy pixel row 271 described in FIG. 27 is formed and the driving method using the dummy pixel row may be combined.

  Further, one frame is not limited to being composed of three fields. Two fields or four or more fields may be used. In the case where one frame has two fields and the three primary colors of RGB, an example in which R and G pixels are rewritten in the first field and B pixels are rewritten in the second field is exemplified. In addition, when one frame has four fields and three primary colors of RGB, the R pixel is rewritten in the first field, the G pixel is rewritten in the second field, and the B pixel is rewritten in the third field and the fourth field. An example is illustrated. These sequences can achieve white balance more efficiently by considering the light emission efficiency of the RGB EL elements 15.

  In the above embodiment, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel that is rewritten for each field changes.

  In the embodiment of FIG. 127, the R pixel is rewritten in the 1H of the first field, the G pixel is rewritten in the 2Hth, the B pixel is rewritten in the 3Hth, the R pixel is rewritten in the 4Hth, and so on. It is a method of driving. Of course, the color of the pixel to be rewritten may be changed every 2H or more horizontal scanning periods, or the color of the pixel to be rewritten may be changed every 1/3 field.

  In the embodiment of FIG. 127, the R pixel is rewritten in the 1H of the first field, the G pixel is rewritten in the 2Hth, the B pixel is rewritten in the 3Hth, and the R pixel is rewritten in the 4Hth. The G pixel is rewritten in the 1H of the second field, the B pixel is rewritten in the 2Hth, the R pixel is rewritten in the 3Hth, and the G pixel is rewritten in the 4Hth. The B pixel is rewritten in 1H of the third field, the R pixel is rewritten in the 2Hth, the G pixel is rewritten in the 3Hth, and the B pixel is rewritten in the 4Hth.

  As described above, R, G, and B color separation can be prevented by rewriting R, G, and B pixels arbitrarily or with a predetermined regularity in each field. In addition, occurrence of flicker can be suppressed.

  In FIG. 128, the number of colors of pixels 16 rewritten every 1H is plural. In FIG. 127, in the first field, the 1H-th pixel 16 to be rewritten is an R pixel, and the 2H-th pixel 16 to be rewritten is a G pixel. Further, the 3H-th pixel 16 to be rewritten is a B pixel, and the 4H-th pixel 16 to be rewritten is an R pixel.

  In FIG. 128, the color position of the pixel to be rewritten is different for each 1H. R, G, and B color separation can be prevented by making R, G, and B pixels different in each field (it goes without saying that they may have a predetermined regularity) and sequentially rewriting them. In addition, occurrence of flicker can be suppressed.

  In the embodiment of FIG. 128 as well, each pixel (a set of RGB pixels) has the same RGB lighting time or light emission intensity. Needless to say, this is also implemented in the embodiments of FIG. 126, FIG. 127, and the like. This is because the color becomes uneven.

  As shown in FIG. 128, the number of pixels to be rewritten every 1H (in the 1H field of FIG. 128, the three colors R, G, and B are rewritten) is plural in FIG. The source driver circuit 14 is configured to output a video signal of any color (may have a certain regularity) to each output terminal, and the switch 1252 can arbitrarily connect the contacts R, G, and B (a certain rule) It may be configured so that it can be connected.

  The display panel of the embodiment of FIG. 129 has W (white) pixels 16W in addition to the three primary colors RGB. By forming or arranging the pixel 16W, the color peak luminance can be satisfactorily realized. In addition, high luminance display can be realized. FIG. 129 (a) shows an embodiment in which R, G, B, and W pixels 16 are formed in one pixel row. FIG. 129 (b) shows a configuration in which RGBW pixels 16 are arranged for each pixel row.

  It goes without saying that the driving method shown in FIGS. 127 and 128 can also be implemented in the driving method shown in FIG. It goes without saying that N-fold pulse driving, M pixel row simultaneous driving, and the like can be performed. Those matters can be easily realized by those skilled in the art according to the present specification, and the description thereof will be omitted.

  In order to facilitate the description of the present invention, the display panel of the present invention is described as having three primary colors of RGB, but the present invention is not limited to this. In addition to RGB, cyan, yellow, and magenta may be added, or a display panel using any one of R, G, and B, and any two colors of R, G, and B may be used.

  In the above sequence driving method, although RGB is operated for each field, it goes without saying that the present invention is not limited to this. Further, the embodiments of FIGS. 125 to 129 describe a method of writing image data to the pixels 16. It does not describe a method of operating the transistor 11d in FIG. 1 or the like and causing an electric current to flow through the EL element 15 to display an image (which is of course relevant). The current flowing through the EL element 15 is controlled by controlling the transistor 11d in the pixel configuration of FIG.

  In the driving method shown in FIGS. 127 and 128, RGB images can be sequentially displayed by controlling the transistor 11d (in the case of FIG. 1). For example, in FIG. 130A, the R display area 53R, the G display area 53G, and the B display area 53B are scanned from the top to the bottom of the screen (or from the bottom to the top) in one frame (one field) period. An area other than the RGB display area is a non-display area 52. That is, intermittent driving is performed.

  FIG. 130 (b) shows an embodiment in which a plurality of RGB display areas 53 are generated in one field (one frame) period. This driving method is similar to the driving method of FIG. Therefore, no explanation will be required. By dividing the display area 53 into a plurality of parts in FIG. 130B, the occurrence of flicker is eliminated even at a lower frame rate.

  FIG. 131A shows an RGB display area 53 in which the area of the display area 53 is different (it goes without saying that the area of the display area 53 is proportional to the lighting period). In FIG. 131A, the R display area 53R and the G display area 53G have the same area. The area of the B display area 53B is larger than that of the G display area 53G. In the organic EL display panel, the light emission efficiency of B is often poor. As shown in FIG. 131 (a), the B display area 53B is made larger than the display area 53 of other colors, so that white balance can be achieved efficiently. Will be able to.

  FIG. 131 (b) is an example in which there are a plurality of B display periods 53B (53B1, 53B2) in one field (frame) period. FIG. 131A shows a method of changing one B display area 53B. By changing it, the white balance can be adjusted well. In FIG. 131B, white balance is improved by displaying a plurality of B display regions 53B having the same area.

  The drive system of the present invention is not limited to either FIG. 131 (a) or FIG. 131 (b). An object is to generate display areas 53 for R, G, and B, and to intermittently display them, thereby preventing motion blur and improving insufficient writing to the pixels 16. In the driving method of FIG. 16, the display area 53 in which R, G, and B are independent does not occur. RGB is displayed at the same time (should be expressed when the W display area 53 is displayed). Needless to say, FIG. 131 (a) and FIG. 131 (b) may be combined. For example, there is an implementation of a driving method that changes the RGB display area 53 of FIG. 131A and generates a plurality of RGB display areas 53 of FIG. 131B.

  130 to 131 is not limited to the drive system of the present invention shown in FIGS. 125 to 129. As shown in FIG. 41, if the current flowing through the EL element 15 (EL element 15R, EL element 15G, EL element 15B) can be controlled for each of RGB, the driving method shown in FIGS. 130 and 131 can be easily implemented. But not. By applying an on / off voltage to the gate signal line 17bR, the R pixel 16R can be on / off controlled. By applying an on / off voltage to the gate signal line 17bG, the G pixel 16G can be on / off controlled. By applying an on / off voltage to the gate signal line 17bB, the B pixel 16B can be on / off controlled.

  In order to realize the above driving, as shown in FIG. 132, the gate driver circuit 12bR for controlling the gate signal line 17bR, the gate driver circuit 12bG for controlling the gate signal line 17bG, and the gate signal line 17bB are controlled. The gate driver circuit 12bB to be formed may be formed or arranged. The gate driver 12bR, 12bG, 12bB in FIG. 132 is driven by the method described with reference to FIG. 6 and the like, whereby the driving method in FIGS. 130 and 131 can be realized. Of course, it is needless to say that the driving method of FIG. 16 can be realized with the configuration of the display panel of FIG.

  If the black image data is rewritten to the pixels 16 other than the pixel 16 whose image data is to be rewritten with the configuration shown in FIGS. 125 to 128, the gate signal line 17bR for controlling the EL element 15R and the EL element 15G are controlled. Needless to say, the gate signal line 17bG and the gate signal line bB for controlling the EL element 15B are not separated, and the drive system shown in FIGS. 130 and 131 can be realized even if the gate signal line 17b is common to the RGB pixels. .

  In FIG. 15, FIG. 18, FIG. 21, etc., it is assumed that the gate signal line 17b (EL-side selection signal line) applies ON voltage (Vgl) and OFF voltage (Vgh) in units of one horizontal scanning period (1H). Did. However, the light emission amount of the EL element 15 is proportional to the flow time when the flow current is a constant current. Therefore, it is not necessary to limit the flowing time to 1H unit.

  In order to introduce the concept of output enable (OEV), it is defined as follows. By performing the OEV control, an on / off voltage (Vgl voltage, Vgh voltage) can be applied to the pixel 16 to the gate signal lines 17a and 17b within one horizontal scanning period (1H).

  For ease of explanation, the display panel of the present invention will be described on the assumption that it is the gate signal line 17a (in the case of FIG. 1) for selecting a pixel row for current programming. The output of the gate driver circuit 12a that controls the gate signal line 17a is called a WR-side selection signal line. The description will be made assuming that the gate signal line 17b (in the case of FIG. 1) for selecting the EL element 15 is used. The output of the gate driver circuit 12b that controls the gate signal line 17b is called an EL-side selection signal line.

  The gate driver circuit 12 receives a start pulse, and the input start pulse sequentially shifts in the shift register as retained data. Data held in the shift register of the gate driver circuit 12a determines whether the voltage output to the WR side selection signal line is the on voltage (Vgl) or the off voltage (Vgh). Further, an OEV1 circuit (not shown) that forcibly turns off the output is formed or arranged at the output stage of the gate driver circuit 12a. When the OEV1 circuit is at the L level, the WR side selection signal that is the output of the gate driver circuit 12a is output to the gate signal line 17a as it is. If the above relationship is illustrated logically, the relationship shown in FIG. 224 (a) is obtained (an OR circuit). The on-voltage is a logic level L (0), and the off-voltage is a logic voltage H (1).

  That is, when the gate driver circuit 12a outputs an off voltage, the off voltage is applied to the gate signal line 17a. When the gate driver circuit 12a outputs an on-voltage (logic L level), the OR circuit takes an OR with the output of the OEV1 circuit and outputs it to the gate signal line 17a. That is, when the OEV1 circuit is at the H level, the voltage output to the gate driver signal line 17a is set to the off voltage (Vgh) (see the timing chart example in FIG. 176).

  Data held in the shift register of the gate driver circuit 12b determines whether the voltage output to the gate signal line 17b (EL-side selection signal line) is the on voltage (Vgl) or the off voltage (Vgh). Further, an OEV2 circuit (not shown) for forcibly turning off the output is formed or arranged at the output stage of the gate driver circuit 12b. When the OEV2 circuit is at L level, the output of the gate driver circuit 12b is output as it is to the gate signal line 17b. If the above relationship is illustrated logically, the relationship shown in FIG. 176 (a) is obtained. The on-voltage is a logic level L (0), and the off-voltage is a logic voltage H (1).

  That is, when the gate driver circuit 12b outputs the off voltage (the EL side selection signal is the off voltage), the off voltage is applied to the gate signal line 17b. When the gate driver circuit 12b outputs an ON voltage (logic L level), the OR circuit takes an OR with the output of the OEV2 circuit and outputs it to the gate signal line 17b. That is, the OEV2 circuit sets the voltage output to the gate driver signal line 17b to the off voltage (Vgh) when the input signal is at the H level. Therefore, even if the EL side selection signal of the OEV2 circuit is in the ON voltage output state, the signal forcibly output to the gate signal line 17b becomes the OFF voltage (Vgh). If the input of the OEV2 circuit is L, the EL side selection signal is output through to the gate signal line 17b (see the timing chart example in FIG. 176).

  The screen brightness is adjusted by the control of OEV2. There is a permissible range of brightness that can change depending on the screen brightness. FIG. 175 illustrates the relationship between the allowable change (%) and the screen brightness (nt). As can be seen from FIG. 175, the allowable change amount is relatively small in a relatively dark image. Therefore, the brightness adjustment of the screen 50 by the control by the OEV2 or the duty ratio control is controlled in consideration of the screen 50 brightness. The permissible change due to control is shortened when the screen is darker than when the screen is bright.

  FIG. 140 shows the 1/4 duty ratio drive. During the 1H period in the 4H period, the ON voltage is applied to the gate signal line 17b (EL-side selection signal line), and the position where the ON voltage is applied in synchronization with the horizontal synchronizing signal (HD) is scanned. Therefore, the on-time is 1H unit.

  However, the present invention is not limited to this, and may be less than 1H as shown in FIG. 143 (1 / 2H in FIG. 143), or may be 1H or less. That is, it is not limited to 1H units, and generation other than 1H units is easy. An OEV2 circuit formed or arranged at the output stage of the gate driver circuit 12b (a circuit for controlling the gate signal line 17b) may be used. Since the OEV2 circuit is the same as the OEV1 circuit described above, description thereof is omitted.

  In FIG. 141, the ON time of the gate signal line 17b (EL-side selection signal line) does not have 1H as a unit. The on-voltage is applied to the gate signal line 17b (EL-side selection signal line) in the odd pixel row for a period of less than 1H. The on-voltage is applied to the gate signal line 17b (EL-side selection signal line) in the even pixel row for an extremely short period. Further, an on-voltage time T1 applied to the gate signal line 17b (EL-side selection signal line) of the odd-numbered pixel row and an on-voltage time T2 applied to the gate signal line 17b (EL-side selection signal line) of the even-numbered pixel row. The added time is set to be 1H period. FIG. 141 shows the state of the first field.

  In the second field next to the first field, the ON voltage is applied to the gate signal line 17b (EL-side selection signal line) of the even-numbered pixel row for a period of less than 1H. The ON voltage is applied to the gate signal line 17b (EL-side selection signal line) in the odd-numbered pixel row for an extremely short period. Further, an on-voltage time T1 applied to the gate signal line 17b (EL-side selection signal line) of the even-numbered pixel row and an on-voltage time T2 applied to the gate signal line 17b (EL-side selection signal line) of the odd-numbered pixel row. The added time is set to be 1H period.

  As described above, the sum of the ON times applied to the gate signal lines 17b (EL-side selection signal lines) in a plurality of pixel rows is made constant, and the lighting time of the EL elements 15 in each pixel row in a plurality of fields. May be constant.

  In FIG. 142, the on time of the gate signal line 17b (EL-side selection signal line) is 1.5H. Further, the rising and falling of the gate signal line 17b (EL-side selection signal line) at the point A overlap each other. The gate signal line 17b (EL-side selection signal line) and the source signal line 18 are coupled. Therefore, when the waveform of the gate signal line 17b (EL-side selection signal line) changes, the change in waveform penetrates to the source signal line 18. When potential fluctuation occurs in the source signal line 18 due to this penetration, the accuracy of current (voltage) programming is lowered, and the characteristic unevenness of the driving transistor 11a is displayed.

  142, at point A, the gate signal line 17B (EL-side selection signal line) (1) changes from the on-voltage (Vgl) application state to the off-voltage (Vgh) application state. The gate signal line 17B (EL-side selection signal line) (2) changes from the off voltage (Vgh) application state to the on voltage (Vgl) application state. Therefore, at point A, the signal waveform of the gate signal line 17B (EL-side selection signal line) (1) and the signal waveform of the gate signal line 17B (EL-side selection signal line) (2) cancel each other. Therefore, even if the source signal line 18 and the gate signal line 17B (EL-side selection signal line) are coupled, the waveform change of the gate signal line 17B (EL-side selection signal line) does not penetrate into the source signal line 18. Absent. Therefore, good current (voltage) programming accuracy can be obtained, and uniform image display can be realized.

  FIG. 142 shows an example in which the on-time is 1.5H. However, the present invention is not limited to this, and it goes without saying that the ON voltage application time may be 1H or less as shown in FIG.

  The brightness of the display screen 50 can be linearly adjusted by adjusting the period during which the ON voltage is applied to the gate signal line 17B (EL-side selection signal line). This can be easily realized by controlling the OEV2 circuit. For example, in FIG. 145, the display brightness is lower in FIG. 145 (b) than in FIG. 145 (a). In addition, the display luminance is lower in FIG. 145 (c) than in FIG. 145 (b).

  FIG. 109 illustrates the relationship between the signal waveforms of OEV2 and the gate signal line 17b. In FIG. 109, FIG. 109 (a) has the shortest period during which OEV2 is at the L level. Therefore, since the period during which the on-voltage is applied to the gate signal line 17b is short, the current period flowing through the EL element 15 is shortened. This state is a state where the duty ratio is small as a result. In FIG. 109 (b), the period during which OEV2 next becomes L level is long. Further, FIG. 109 (c) has a longer period during which OEV2 is at the L level than FIG. 109 (b). Therefore, the duty ratio in FIG. 109 (c) is larger than the duty ratio in FIG. 109 (b).

  Note that the embodiments shown in FIGS. 109A, 109B, and 109C perform duty ratio control in a period shorter than 1H. However, the present invention is not limited to this, and duty ratio control may be performed in units of 1H as illustrated in FIG. 109 (d). FIG. 109 (d) shows an example with a duty ratio of 1/2.

  In FIG. 109 (a), the period during which OEV2 is at the L level is the shortest. Therefore, since the period during which the on-voltage is applied to the gate signal line 17b is short, the current period flowing through the EL element 15 is shortened. This state is a state where the duty ratio is small as a result.

  In FIG. 109 (a), the period during which OEV2 is at the L level is the shortest. Therefore, since the period during which the on-voltage is applied to the gate signal line 17b is short, the current period flowing through the EL element 15 is shortened. This state is a state where the duty ratio is small as a result.

  In addition, as illustrated in FIG. 146, a set of a period in which the on-voltage is applied and a period in which the off-voltage is applied in the 1H period may be provided a plurality of times. FIG. 146 (a) shows an embodiment provided six times. FIG. 146 (b) shows an embodiment provided three times. FIG. 146 (c) shows an embodiment provided once. In FIG. 146, the display brightness is lower in FIG. 146 (b) than in FIG. 146 (a). In addition, the display luminance is lower in FIG. 146 (c) than in FIG. 146 (b). Therefore, the display luminance can be easily adjusted (controlled) by controlling the number of ON periods.

  Hereinafter, the current driver type source driver IC (circuit) 14 of the present invention will be described. The source driver IC of the present invention is used to realize the driving method and driving circuit of the present invention described above. Further, it is used in combination with the driving method, driving circuit, and display device of the present invention. Although the description will be made with reference to an IC chip, the present invention is not limited to this, and it goes without saying that it may be produced on the substrate 71 of the display panel using a low-temperature polysilicon technique, an amorphous silicon technique, or the like.

  First, FIG. 55 shows an example of a conventional current-driven driver circuit. However, FIG. 55 is a principle for explaining the current driver type source driver IC (source driver circuit) 14 of the present invention.

  In FIG. 55, reference numeral 551 denotes a D / A converter. An n-bit data signal is input to the D / A converter 551, and an analog signal is output from the D / A converter based on the input data. This analog signal is input to the operational amplifier 552. The operational amplifier 552 is input to the N-channel transistor 471a, and the current flowing through the transistor 471a flows through the resistor 531. The terminal voltage of the resistor R becomes the negative input of the operational amplifier 552, and the negative terminal voltage and the positive terminal of the operational amplifier 552 become the same voltage. Therefore, the output voltage of the D / A converter 551 becomes the terminal voltage of the resistor 531.

  If the resistance value of the resistor 531 is 1 MΩ and the output of the D / A converter 551 is 1 (V), a current of 1 (V) / 1 MΩ = 1 (μA) flows through the resistor 531. This is a constant current circuit. Therefore, the analog output of the D / A converter 551 changes according to the value of the data signal, and a predetermined current flows through the resistor 531 based on the value of the analog output, and becomes the program current Iw.

  However, the circuit scale of the DA conversion circuit 551 is large. The circuit scale of the operational amplifier 552 is also large. If the DA converter circuit 551 and the operational amplifier 552 are formed in one output circuit, the size of the source driver IC 14 becomes enormous. Therefore, it is impossible to produce practically.

  The present invention has been made in view of this point. The source driver circuit 14 of the present invention has a circuit configuration and a layout configuration for reducing the scale of the current output circuit and minimizing variations in output current between the current output terminals as much as possible.

  FIG. 47 shows a configuration diagram of one embodiment of the current-driven source driver IC (circuit) 14 of the present invention. FIG. 47 shows a multistage current mirror circuit when the current source has a three-stage configuration (471, 472, 473) as an example.

  In FIG. 47, the current value of the first-stage current source 471 is copied to N (where N is an arbitrary integer) second-stage current sources 472 by a current mirror circuit. Further, the current value of the second stage current source 472 is copied to M (where M is an arbitrary integer) third stage current sources 473 by a current mirror circuit. With this configuration, as a result, the current value of the first stage current source 471 is copied to N × M third stage current sources 473.

  For example, when the driver signal 14 is used to drive the source signal line 18 of the QCIF format display panel, the output is 176 (because the source signal line needs 176 outputs for each RGB). In this case, N is 16 and M = 11. Therefore, 16 × 11 = 176, which corresponds to 176 outputs. In this way, by setting one of N or M to 8 or 16, or a multiple thereof, the layout design of the current source of the driver IC is facilitated.

  In the current driver type source driver IC (circuit) 14 using the multistage current mirror circuit of the present invention, the current value of the first stage current source 471 is directly applied to the N × M third stage current sources 473 as described above. Instead of copying with the current mirror circuit, the second-stage current source 472 is provided in the middle, so that variations in transistor characteristics can be absorbed there.

  In particular, the present invention is characterized in that the first stage current mirror circuit (current source 471) and the second stage current mirror circuit (current source 472) are closely arranged. If the first-stage current source 471 to the third-stage current source 473 (that is, the two-stage configuration of the current mirror circuit), the number of second-stage current sources 473 connected to the first-stage current source is In many cases, the first-stage current source 471 and the third-stage current source 473 cannot be arranged closely.

  Like the source driver circuit 14 of the present invention, the current of the first stage current mirror circuit (current source 471) is copied to the second stage current mirror circuit (current source 472), and the second stage current mirror circuit ( In this configuration, the current of the current source 472) is copied to the current mirror circuit (current source 472) in the third stage. In this configuration, the number of second-stage current mirror circuits (current sources 472) connected to the first-stage current mirror circuits (current sources 471) is small. Therefore, the first-stage current mirror circuit (current source 471) and the second-stage current mirror circuit (current source 472) can be closely arranged.

  If the transistors constituting the current mirror circuit can be arranged in close proximity, naturally, the variation of the transistors is reduced, so that the variation in the copied current value is also reduced. Further, the number of third-stage current mirror circuits (current sources 473) connected to the second-stage current mirror circuits (current sources 472) is also reduced. Therefore, the second-stage current mirror circuit (current source 472) and the third-stage current mirror circuit (current source 473) can be closely arranged.

  That is, as a whole, the transistors in the current receiving section of the first-stage current mirror circuit (current source 471), the second-stage current mirror circuit (current source 472), and the third-stage current mirror circuit (current source 473) Can be placed closely. Accordingly, since the transistors constituting the current mirror circuit can be closely arranged, the variation of the transistors is reduced, and the variation of the current signal from the output terminal is extremely reduced (high accuracy).

  In the present invention, they are expressed as current sources 471, 472, and 473, or as current mirror circuits. These are used synonymously. That is, the current source is a basic configuration concept of the present invention, and when the current source is specifically configured, it becomes a current mirror circuit. Therefore, the current source is not limited only to the current mirror circuit, and may be a constant current circuit including a combination of the operational amplifier 552, the transistor 471, and the resistor R.

  FIG. 48 is a structural diagram of a more specific source driver IC (circuit) 14. FIG. 48 illustrates a portion of the third current source 473. That is, the output unit is connected to one source signal line 18. As a final stage current mirror configuration, a plurality of current mirror circuits of the same size (unit transistors 484 (one unit)) are configured, and the number of bits is weighted corresponding to the bits of the image data.

  The transistors constituting the source driver IC (circuit) 14 of the present invention are not limited to the MOS type but may be a bipolar type. Moreover, it is not limited to a silicon semiconductor, and a gallium arsenide semiconductor may be used. Further, a germanium semiconductor may be used. Further, the substrate may be formed directly by polysilicon technology such as low-temperature polysilicon or amorphous silicon technology.

  As is apparent from FIG. 48, a case of 6-bit digital input is shown as one embodiment of the present invention. That is, since it is 2 6, it is a 64 gradation display. By mounting this source driver IC 14 on the array substrate, red (R), green (G), and blue (B) have 64 gradations, so that 64 × 64 × 64 = about 260,000 colors can be displayed. Become.

  In the case of 64 gradations, there are one D0 bit unit transistor 484, two D1 bit unit transistors 484, four D2 bit unit transistors 484, eight D3 bit unit transistors 484, and D4 bit units. Since there are 16 unit transistors 484 and 32 D5-bit unit transistors 484, the total number of unit transistors 484 is 63. In other words, the present invention configures (forms) one unit transistor 484 with one output number of gradations (in this example, 64 gradations) minus one unit transistor 484. Even when one unit transistor is divided into a plurality of sub-unit transistors, the unit transistor is simply divided into sub-unit transistors. Therefore, there is no difference (synonymous) in that the present invention is composed of unit transistors with the number of grayscale representations minus one.

  In FIG. 48, D0 indicates the LSB input, and D5 indicates the MSB input. When the D0 input terminal is at the H level (positive logic), the switch 481a (on / off means. Of course, it may be constituted by a single transistor or an analog switch in which a P channel transistor and an N channel transistor are combined). ) Turns on. Then, a current flows toward a current source (1 unit) 484 constituting the current mirror. This current flows through the internal wiring 483 in the IC 14. Since the internal wiring 483 is connected to the source signal line 18 via the terminal electrode of the IC 14, the current flowing through the internal wiring 483 becomes the program current of the pixel 16.

  For example, when the D1 input terminal is at the H level (positive logic), the switch 481b is turned on. Then, current flows toward the two current sources (1 unit) 484 constituting the current mirror. This current flows through the internal wiring 483 in the IC 14. Since the internal wiring 483 is connected to the source signal line 18 via the terminal electrode of the IC 14, the current flowing through the internal wiring 483 becomes the program current of the pixel 16.

  The same applies to the other switches 481. When the D2 input terminal is at the H level (positive logic), the switch 481c is turned on. Then, current flows toward the four current sources (1 unit) 484 constituting the current mirror. When the D5 input terminal is at the H level (positive logic), the switch 481f is turned on. Then, current flows toward 32 current sources (1 unit) 484 constituting the current mirror.

  As described above, according to data (D0 to D5) from the outside, a current flows toward the corresponding current source (1 unit). Therefore, the current flows from 0 to 63 current sources (one unit) according to the data.

  In the present invention, for ease of explanation, the number of current sources is 63, which is 6 bits. However, the present invention is not limited to this. In the case of 8 bits, 255 unit transistors 484 may be formed (arranged). In the case of 4 bits, 15 unit transistors 484 may be formed (arranged). The transistors 484 constituting the unit current source have the same channel width W and channel width L. By configuring with the same transistor in this way, an output stage with little variation can be configured.

  Further, all the unit transistors 484 are not limited to flowing the same current. For example, each unit transistor 484 may be weighted. For example, the current output circuit may be configured by mixing one unit unit transistor 484, a double unit transistor 484, a quadruple unit transistor 484, and the like. However, if the unit transistors 484 are weighted, the weighted current sources do not have a weighted ratio, and there is a possibility of variation. Therefore, even in the case of weighting, each current source is preferably configured by forming a plurality of transistors serving as one unit of current source.

  The size of the transistor constituting the unit transistor 484 needs to be a certain size or more. The smaller the transistor size, the greater the variation in output current. The size of the transistor 484 is a size obtained by multiplying the channel length L by the channel width W. For example, if W = 3 μm and L = 4 μm, the size of the transistor 484 constituting one unit current source is W × L = 12 square μm. The reason why the variation increases as the transistor size decreases is considered to be due to the influence of the crystal interface state of the silicon wafer. Therefore, when one transistor is formed across a plurality of crystal interfaces, the output current variation of the transistor is reduced.

  FIG. 119 shows the relationship between transistor size and output current variation. The horizontal axis of the graph in FIG. 119 is the transistor size (square μm). The vertical axis shows the variation in output current in%. However, the variation% of the output current is that the unit current source (one unit transistor) 484 is formed of 63 groups (63 units are formed), and a large number of these groups are formed on the wafer, and the variation of the output current is reduced. I have found it. Therefore, although the horizontal axis of the graph is shown as the size of a transistor constituting one unit current source (the size of the unit transistor 484), the area is 63 times because there are 63 actual transistors in parallel. However, in FIG. 119, the size of the unit transistor 484 is considered as a unit. Therefore, in FIG. 119, when 63 unit transistors 484 of 30 square μm are formed, the variation in output current at that time is 0.5%.

  In the case of 64 gradations, 100/64 = 1.5%. Therefore, the output current variation needs to be within 1.5%. In order to make it 1.5% or less from FIG. 119, the size of the unit transistor needs to be 2 square μm or more (63 unit transistors of 2 square μm operate in 64 gradations). On the other hand, the transistor size is limited. This is because the IC chip size increases and the lateral width per output is limited. From this point, the upper limit of the size of the unit transistor 484 is 300 square μm. Therefore, in the 64 gradation display, the size of the unit transistor 484 needs to be 2 square μm or more and 300 square μm or less.

  In the case of 128 gradations, 100/128 = 1%. Therefore, the output current variation needs to be within 1%. In order to obtain 1% or less from FIG. 119, the size of the unit transistor needs to be 8 square μm or more. Therefore, in 128 gradation display, the size of the unit transistor 484 needs to be 8 square μm or more and 300 square μm or less.

Generally, when the number of gradations is K and the size of the unit transistor 484 is St (square μm),
The relationship of 40 ≦ K / √ (St) and St ≦ 300 is satisfied.
More preferably, it is preferable to satisfy the relationship of 120 ≦ K / √ (St) and St ≦ 300.

  The above example is a case where 63 transistors are formed with 64 gradations. In the case of configuring 64 gradations with 127 unit transistors 484, the size of the unit transistor 484 is a size obtained by adding two unit transistors 484. For example, if there are 64 gradations, the size of the unit transistor 484 is 10 square μm, and 127 are formed, the size of the unit transistor needs to be in the column of 10 × 2 = 20 in FIG. Similarly, in 64 gradations, if the size of the unit transistor 484 is 10 square μm and 255 are formed, it is necessary to see the column of 10 × 4 = 40 for the size of the unit transistor in FIG.

  The unit transistor 484 needs to consider not only the size but also the shape. This is to reduce the influence of kink. Kink is a phenomenon in which the current flowing through the unit transistor 484 changes when the source (S) -drain (D) voltage of the unit transistor 484 is changed while the gate voltage of the unit transistor 484 is kept constant. say. When there is no kink effect (ideal state), the current flowing through the unit transistor 484 does not change even when the voltage applied between the source (S) and the drain (D) is changed.

  The influence of the kink occurs when the source signal line 18 differs due to variations in Vt of the driving transistor 11a shown in FIG. The driver circuit 14 supplies a program current to the source signal line 18 so that the program current flows through the pixel driving transistor 11a. With this program current, the gate terminal voltage of the drive transistor 11a changes, and the program current flows through the drive transistor 11a. As can be seen from FIG. 3, when the selected pixel 16 is in the programmed state, the gate terminal voltage of the driving transistor 11a is equal to the potential of the source signal line 18.

  Therefore, the potential of the source signal line 18 varies depending on the Vt variation of the driving transistor 11a of each pixel 16. The potential of the source signal line 18 becomes the source-drain voltage of the unit transistor 484 of the driver circuit 14. That is, the source-drain voltage applied to the unit transistor 484 varies depending on the Vt variation of the driving transistor 11a of the pixel 16, and the source-drain voltage causes variation in the output current due to the kink in the unit transistor 484.

  FIG. 123 is a graph of deviation (variation) from the unit transistor L / W and the target value. When the L / W ratio of the unit transistor is 2 or less, the deviation from the target value is large (the slope of the straight line is large). However, as L / W increases, the deviation of the target value tends to decrease. When the unit transistor L / W is 2 or more, the change in deviation from the target value is small. The deviation (variation) from the target value is L / W = 2 or more and 0.5% or less. Therefore, it can be adopted in the source driver circuit 14 as transistor accuracy. Note that L is the channel length of the unit transistor 484, and W is the channel width of the unit transistor.

  However, the channel length L of the unit transistor 484 cannot be increased as much as possible. This is because the longer L is, the larger IC chip 14 is. Further, the gate terminal voltage of the unit transistor 484 increases, and the power supply voltage required for the IC 14 increases. When the power supply voltage increases, it is necessary to adopt a high breakdown voltage IC process. The source driver IC 14 formed by the high breakdown voltage IC process has a large output variation of the unit transistor 484 (see FIG. 121 and its description). According to the results of the study, L / W is preferably set to 100 or less. More preferably, L / W is preferably 50 or less.

  From the above, the unit transistor L / W is preferably set to 2 or more. L / W is preferably 100 or less. More preferably, L / W is preferably 40 or less.

  The magnitude of L / W also depends on the number of gradations. When the number of gradations is small, there is no problem even if the output current of the unit transistor 484 varies due to the kink because the difference between the gradations is large. However, in a display panel with a large number of gradations, the difference between the gradations is small, so that the number of gradations is reduced if the output current of the unit transistor 484 varies even slightly due to the influence of kink.

In consideration of the above, the driver circuit 14 according to the present invention has the number of gradations as K and L / W of the unit transistor 484 (L is the channel length of the unit transistor 484 and W is the channel width of the unit transistor). ,
(√ (K / 16)) ≦ L / W ≦ and (√ (K / 16)) × 20
It is configured (formed) to satisfy this relationship. This relationship is illustrated in FIG. The upper side of the straight line in FIG. 120 is an implementation range of the present invention.

  The variation in the output current of the unit transistor 484 also depends on the withstand voltage of the source driver IC 14. The breakdown voltage of the source driver IC generally means the power supply voltage of the IC. For example, with a 5 (V) breakdown voltage, the power supply voltage is used at a standard voltage of 5 (V). The IC withstand voltage may be read as the maximum usable voltage. These breakdown voltages are standardized and held by semiconductor IC manufacturers as a 5 (V) breakdown voltage process and a 10 (V) breakdown voltage process.

  It is considered that the IC withstand voltage affects the output variation of the unit transistor 484 due to the film quality and film thickness of the gate insulating film of the transistor 484. A transistor 484 manufactured by a process with high IC breakdown voltage has a thick gate insulating film. This is to prevent dielectric breakdown even when a high voltage is applied. When the insulating film is thick, it becomes difficult to control the gate insulating film thickness, and the film quality variation of the gate insulating film also increases. As a result, the variation of the transistors increases. In addition, the mobility of a transistor manufactured by a high breakdown voltage process is low. If the mobility is low, the characteristics differ only by a small change in the electrons injected into the gate of the transistor. Therefore, the variation of the transistors increases. Therefore, in order to reduce the variation of the unit transistors 484, it is preferable to employ an IC process having a low IC withstand voltage.

  FIG. 121 illustrates the relationship between the IC breakdown voltage and the output variation of the unit transistor 484. With respect to the variation ratio of the vertical axis, the variation of the unit transistor 484 is set to 1 by the 1.8 (V) breakdown voltage process. FIG. 121 shows the output variation of the unit transistor 484 manufactured by each withstand voltage process when the shape L / W of the unit transistor 484 is 12 (μm) / 6 (μm). In addition, a plurality of unit transistors are formed in each IC withstand voltage process, and output current variation is obtained. However, the breakdown voltage process is 1.8 (V) breakdown voltage, 2.5 (V) breakdown voltage, 3.3 (V) breakdown voltage, 5 (V) breakdown voltage, 8 (V) breakdown voltage, 10 (V) breakdown voltage, 15 ( V) A discrete value such as a withstand voltage. However, for ease of explanation, the variation of the transistors formed at each breakdown voltage is entered in a graph and connected by a straight line.

As can be seen from FIG. 121, the increase rate of the variation ratio (the output current variation of the unit transistor 484) with respect to the IC process is small until the IC breakdown voltage is about 13 (V). However, when the IC breakdown voltage is 15 (V) or more, the slope of the variation ratio with respect to the IC breakdown voltage increases.
In FIG. 121, the variation ratio within 3 is a variation allowable range in 64 gradation to 256 gradation display. However, this variation ratio varies depending on the area of the unit transistor 484 and L / W. However, even if the shape of the unit transistor 484 is changed, there is almost no difference in the variation tendency of the variation ratio with respect to the IC breakdown voltage. When the IC withstand voltage is 12 to 15 (V) or more, the variation ratio tends to increase.

  On the other hand, the potential of the output terminal 681 in FIG. 48 changes depending on the program current of the driving transistor 11 a of the pixel 16. The gate terminal voltage of the driving transistor 11a is almost equal to the potential of the source signal line 18. Further, the potential of the source signal line 18 becomes the potential of the output terminal 681 of the source driver IC (circuit) 14. The gate terminal potential Vw when the driving transistor 11a of the pixel 16 passes white raster (maximum white display) current is used. A gate terminal potential Vb when the driving transistor 11a of the pixel 16 passes a black raster (full black display) current is used. The absolute value of Vw−Vb needs to be 2 (V) or more. Further, when the Vw voltage is applied to the terminal 681, the channel-to-channel voltage of the unit transistor 484 needs to be 0.5 (V).

  Therefore, the output terminal 681 (the terminal 681 is connected to the source signal line 18 and the gate terminal voltage of the driving transistor 11a of the pixel 16 is applied during current programming) from 0.5 (V) to ((Vw A voltage of −Vb) +0.5) (V) is applied. Since Vw−Vb is 2 (V), a maximum of 2 (V) +0.5 (V) = 2.5 (V) is applied to the terminal 681. Therefore, even if the output voltage (current) of the source driver IC 14 has a rail-to-rail circuit configuration (a circuit configuration capable of outputting a voltage up to the IC power supply potential), an IC withstand voltage of 2.5 (V) is required. . The required amplitude range of the terminal 741 is 2.5 (V) or more.

  From the above, it is preferable to use a process with a breakdown voltage of the source driver IC 14 of 2.5 (V) to 15 (V). More preferably, the source driver IC 14 has a withstand voltage of 3 (V) to 13 (V).

  In the above explanation, the withstand voltage process of the source driver IC 12 is assumed to be a process of 2.5 (V) or more and 13 (V) or less. However, this withstand voltage is also applied to an embodiment in which the source driver circuit 14 is formed directly on the substrate 71 (low temperature polysilicon process or the like). The use withstand voltage of the source driver circuit 14 formed on the substrate 71 may be as high as 15 (V) or more. In this case, the power supply voltage used for the source driver circuit 14 may be replaced with the IC withstand voltage shown in FIG. Even in the source driver IC 14, the IC withstand voltage may be replaced with the power supply voltage to be used.

  The area of the unit transistor 484 is correlated with variations in output current. FIG. 122 is a graph when the area of the unit transistor 484 is constant and the transistor width W of the unit transistor 484 is changed. In FIG. 121, the variation of the channel width W = 2 (μm) of the unit transistor 484 is 1. The vertical axis of the graph represents the relative ratio when the variation of the channel width W = 2 (μm) is 1.

  As shown in FIG. 122, the variation ratio of the unit transistor gradually increases from 2 (μm) to 9 to 10 (μm), and the variation ratio tends to increase when the unit transistor exceeds 10 (μm). Also, the variation ratio tends to increase when the channel width W = 2 (μm) or less.

  In FIG. 122, the variation ratio within 3 is a variation allowable range in 64 gradation to 256 gradation display. However, this variation ratio varies depending on the area of the unit transistor 484. However, even if the area of the unit transistor 484 is changed, there is almost no difference in the variation tendency of the variation ratio with respect to the IC breakdown voltage.

  From the above, the channel width W of the unit transistor 484 is preferably 2 (μm) or more and 10 (μm) or less. More preferably, the channel width W of the unit transistor 484 is preferably 2 (μm) or more and 9 (μm) or less. However, when the number of gradations is 64, there is no practical problem even if the channel width W is 2 (μm) or more and 15 (μm) or less.

  As shown in FIG. 52, the current flowing through the second-stage current mirror circuit 472b is copied to the transistor 473a constituting the third-stage current mirror circuit. When the current mirror magnification is 1, this current is It flows to the transistor 473b. This current is copied to the unit transistor 484 in the final stage.

  Since the portion corresponding to D0 is composed of one unit transistor 484, it is a current value flowing through the unit transistor 473 of the final stage current source. Since the portion corresponding to D1 is composed of two unit transistors 484, the current value is twice that of the final stage current source. Since D2 is composed of four unit transistors 484, the current value is four times that of the final stage current source, and the portion corresponding to D5 is composed of 32 transistors. The current value is 32 times that of the stage current source. However, this is a case where the mirror ratio of the last stage current mirror circuit is 1.

  The program current Iw is output to the source signal line through the switch controlled by the 6-bit image data D0, D1, D2,..., D5 (current is drawn). Therefore, according to the ON / OFF of the 6-bit image data D0, D1, D2,..., D5, the output line is 1 time, 2 times, 4 times,. A current of 32 times is added and output. That is, a current value 0 to 63 times that of the final stage current source 473 is output from the output line by 6-bit image data D0, D1, D2,..., D5 (current is drawn from the source signal line 18).

  Actually, as shown in FIG. 76, FIG. 77, FIG. 78, and FIG. 118, the reference current (IaR, IaG, IaB) for each of R, G, and B in the source driver IC 14 is a resistor 491 (491R). 491G, 491B) and the like. The white balance can be easily adjusted by adjusting the reference current Ia.

  In order to realize full color display on an EL display panel, it is necessary to form (create) a reference current for each of RGB. White balance can be adjusted by the ratio of RGB reference currents. In the case of the current driving method, the present invention also determines the current value that the unit transistor 484 flows from one reference current. Therefore, if the magnitude of the reference current is determined, the current that the unit transistor 484 flows can be determined. For this reason, if R, G, and B reference currents are set, white balance can be obtained in all gradations. The above items are the effects that are exhibited because the source driver circuit 14 has a current step output (current drive). Therefore, the point is how the reference current can be set for each RGB.

  The luminous efficiency of the EL element is determined by the thickness of the EL material deposited or applied. Or it is the dominant factor. The film thickness is almost constant from lot to lot. Therefore, if the formed film thickness of the EL element 15 is managed as a lot, the relationship between the current passed through the EL element 15 and the light emission luminance is determined. That is, the current value for white balance is fixed for each lot.

  FIG. 49 shows an example of a circuit diagram of 176 outputs (N × M = 176) by a three-stage current mirror circuit. In FIG. 49, the current source 471 based on the first stage current mirror circuit is referred to as a parent current source, the current source 472 based on the second stage current mirror circuit is referred to as a child current source, and the current source 473 based on the third stage current mirror circuit is referred to as a grandchild current source. ing. With a configuration of an integral multiple of the current source by the third stage current mirror circuit which is the final stage current mirror circuit, variation in 176 outputs is suppressed as much as possible, and highly accurate current output is possible.

  Note that the dense arrangement means that the first current source 471 and the second current source 472 are arranged at a distance of at least 8 mm (current or voltage output side and current or voltage input side). . Furthermore, it is preferable to arrange within 5 mm. This is because, if it is within this range, it is arranged in the silicon chip by examination, and the difference in transistor characteristics (Vt, mobility (μ)) hardly occurs. Similarly, the second current source 472 and the third current source 473 (current output side and current input side) are also arranged at a distance of at least 8 mm. More preferably, it is preferable to arrange at a position within 5 mm. Needless to say, the above matters also apply to other embodiments of the present invention.

  The current or voltage output side and the current or voltage input side mean the following relationship. In the case of the voltage delivery in FIG. 50, the relation is that the transistors 471 (output side) of the (I) -th current source and the transistors 472a (input side) of the (I + 1) -th current source are closely arranged. In the case of the current delivery in FIG. 51, the relationship is that the transistors 471a (output side) of the (I) -th current source and the transistors 472b (input side) of the (I + 1) -th current source are closely arranged.

  Note that although the number of transistors 471 is one in FIGS. 49 and 50, the present invention is not limited to this. For example, the unit transistor 484 may be configured by forming a plurality of small sub-transistors 471 and connecting the source or drain terminals of the plurality of sub-transistors to the resistor 491. By connecting a plurality of small sub-transistors in parallel, variations in the unit transistors 484 can be reduced.

  Similarly, although the number of transistors 472a is one, it is not limited to this. For example, a plurality of small transistors 472a may be formed, and a plurality of gate terminals of the transistor 472a may be connected to a gate terminal of the transistor 471. By connecting a plurality of small transistors 472a in parallel, variation in the transistors 472a can be reduced.

  Therefore, the structure of the present invention includes a structure in which one transistor 471 and a plurality of transistors 472a are connected, a structure in which a plurality of transistors 471 and one transistor 472a are connected, and a plurality of transistors 471 and a plurality of transistors. A configuration in which the transistor 472a is connected is exemplified. The above embodiment will be described in detail later.

  The above items also apply to the structures of the transistor 473a and the transistor 473b in FIG. A configuration in which one transistor 473a and a plurality of transistors 473ba are connected, a configuration in which a plurality of transistors 473a and one transistor 473b are connected, and a configuration in which a plurality of transistors 473a and a plurality of transistors 473b are connected Illustrated. This is because variation of the transistors 473 can be reduced by connecting a plurality of small transistors 473 in parallel.

  The above items can also be applied to the relationship with the transistors 472a and 472b in FIG. In addition, the transistor 473b in FIG. 48 is preferably formed using a plurality of transistors. Similarly, the transistor 473 in FIGS. 56 and 57 is preferably formed using a plurality of transistors.

  Here, the source driver IC 14 is described as being formed of a silicon chip, but the present invention is not limited to this. The source driver IC 14 may be another semiconductor chip formed such as a gallium substrate or a germanium substrate. The unit transistor 484 may be a bipolar transistor, a CMOS transistor, an FET, a bi-CMOS transistor, or a DMOS transistor. However, from the viewpoint of reducing the output variation of the unit transistor 484, the unit transistor 484 is preferably composed of a CMOS transistor.

  The unit transistor 484 is preferably composed of an N channel. The unit transistor composed of P-channel transistors has an output variation of 1.5 times that of a unit transistor composed of N-channel transistors.

  Since the unit transistor 484 of the source driver IC 14 is preferably composed of an N-channel transistor, the program current of the source driver IC 14 is a drawing current from the pixel 16 to the source driver IC. Therefore, the driving transistor 11a of the pixel 16 is formed of a P channel. The switching transistor 11d shown in FIG. 1 is also a P-channel transistor.

  From the above, the configuration in which the unit transistor 484 in the output stage of the source driver IC (circuit) 14 is configured by an N-channel transistor, and the driving transistor 11a of the pixel 16 is configured by a P-channel transistor is characteristic of the present invention. It is a configuration. Note that all of the transistors 11 (transistors 11a, 11b, 11c, and 11d) included in the pixel 16 may be formed as a P channel. Since the process for forming the N-channel transistor can be eliminated, cost reduction and high yield can be realized.

  Although the unit transistor 484 is formed in the IC 14, it is not limited to this. The source driver circuit 14 may be formed by low-temperature polysilicon technology. Also in this case, the unit transistor 484 in the source driver circuit 14 is preferably composed of an N-channel transistor.

  FIG. 51 shows an embodiment of a current delivery configuration. FIG. 50 shows an example of a voltage delivery configuration. 50 and 51 are the same as the circuit diagrams, and the layout configuration, that is, the way of wiring is different. In FIG. 50, 471 is a first-stage current source N-channel transistor, 472a is a second-stage current source N-channel transistor, and 472b is a second-stage current source P-channel transistor.

  In FIG. 51, 471a is a first-stage current source N-channel transistor, 472a is a second-stage current source N-channel transistor, and 472b is a second-stage current source P-channel transistor.

  In FIG. 50, the gate voltage of the first-stage current source composed of the variable resistor 491 (used to change the current) and the N-channel transistor 471 is the gate voltage of the N-channel transistor 472a of the second-stage current source. Therefore, the layout configuration is a voltage delivery system.

  On the other hand, in FIG. 51, the gate voltage of the first-stage current source composed of the variable resistor 491 and the N-channel transistor 471a is applied to the gate of the N-channel transistor 472a of the adjacent second-stage current source, and as a result, Since the flowing current value is transferred to the P-channel transistor 472b of the second-stage current source, the layout configuration is a current transfer method.

  In the embodiment of the present invention, the relationship between the first current source and the second current source is mainly described for the sake of easy explanation or easy understanding. However, the present invention is not limited to this. Needless to say, the present invention can also be applied (applicable) in the relationship between the second current source and the third current source, or in the relationship with other current sources.

  In the layout configuration of the voltage transfer type current mirror circuit shown in FIG. 50, the N-channel transistor 471 of the first-stage current source and the N-channel transistor 472a of the second-stage current source that constitute the current mirror circuit are separated from each other. (It should be easy to get away from each other.) Therefore, the transistor characteristics of the two are likely to be different. Therefore, the current value of the first stage current source is not accurately transmitted to the second stage current source, and variations tend to occur.

  On the other hand, in the layout configuration of the current transfer type current mirror circuit shown in FIG. 51, the N-channel transistor 471a of the first-stage current source and the N-channel transistor 472a of the second-stage current source that constitute the current mirror circuit are adjacent to each other. Therefore, the transistor characteristics of the two are hardly different, the current value of the first stage current source is accurately transmitted to the second stage current source, and variations are less likely to occur.

  From the above, the circuit configuration of the multi-stage current mirror circuit of the present invention (the current-driven source driver IC (circuit) 14 of the present invention has a layout configuration that does not pass voltage but passes current). Of course, the above embodiments can be applied to other embodiments of the present invention.

  For convenience of explanation, the case of the first stage current source to the second stage current source is shown, but the second stage current source to the third stage current source, the third stage current source to the fourth stage current source,. Needless to say, the same applies to multi-stages such as. Needless to say, the present invention may employ a single-stage current source configuration (see FIGS. 48, 164, 165, 166, etc.).

  FIG. 52 shows an example in which the current mirror circuit (three-stage current source) having the three-stage configuration shown in FIG. 49 is configured as a current delivery system (therefore, FIG. 49 shows a circuit configuration of the voltage delivery system). ).

  In FIG. 52, first, a reference current is created by the variable resistor 491 and the N-channel transistor 471. Although the reference current is adjusted by the variable resistor 491, the source voltage of the transistor 471 is actually set by an electronic volume circuit formed (or arranged) in the source driver IC (circuit) 14. Configured to be adjusted. Alternatively, the reference current is adjusted by supplying the current output from the current-type electronic volume composed of a large number of current sources (one unit) 484 as shown in FIG. 48 directly to the source terminal of the transistor 471. (See FIG. 53).

  The gate voltage of the first-stage current source by the transistor 471 is applied to the gate of the N-channel transistor 472a of the adjacent second-stage current source, and as a result, the current value flowing through the transistor is the P-channel transistor 472b of the second-stage current source. Is passed on. In addition, the gate voltage of the second current source transistor 472b is applied to the gate of the N-channel transistor 473a of the adjacent third-stage current source, and as a result, the current value flowing through the transistor is the N-channel of the third-stage current source. Passed to the transistor 473b. A large number of unit transistors 484 shown in FIG. 48 are formed (arranged) on the gate of the N-channel transistor 473b of the third stage current source according to the required number of bits.

  In FIG. 53, the first-stage current source 471 of the multistage current mirror circuit includes a current value adjusting element. With this configuration, the output current can be controlled by changing the current value of the first stage current source 471.

  The Vt variation (characteristic variation) of the transistors varies about 100 (mV) within one wafer. However, the Vt variation of transistors formed close to each other within 100 μm is at least 10 (mV) or less (actual measurement). That is, by forming transistors in close proximity to form a current mirror circuit, output current variation of the current mirror circuit can be reduced. Therefore, variations in output current at each terminal of the source driver IC can be reduced.

  Note that the transistor variation is described as Vt, but the transistor variation is not limited to Vt. However, since Vt variation is a main factor of transistor characteristic variation, Vt variation = transistor variation will be described for easy understanding.

  FIG. 118 shows measurement results of the transistor formation area (square millimeters) and the output current variation of the single transistor 484. The output current variation is a current variation at the Vt voltage. Black spots are transistor output current variations of evaluation samples (10 to 200) produced within a predetermined formation area. The transistor formed in the region A (formation area within 0.5 square millimeter) in FIG. 118 has almost no output current variation (almost only an output current variation in an error range. That is, a constant output current is Output). Conversely, in the C region (formation area of 2.4 square millimeters or more), the variation in output current with respect to the formation area tends to increase rapidly. In the region B (formation area of 0.5 square millimeters or greater and 2.4 square millimeters or less), the variation in output current with respect to the formation area is in a substantially proportional relationship.

  However, the absolute value of the output current varies from wafer to wafer. However, this problem can be addressed by adjusting the reference current or setting it to a predetermined value in the source driver IC (circuit) 14 of the present invention. Moreover, it can respond (solve) by circuit devices, such as a current mirror circuit.

  The present invention changes (controls) the amount of current flowing through the source signal line 18 by switching the number of currents flowing through the unit transistor 484 according to the input digital data (D). If the number of gradations is 64 gradations or more, 1/64 = 0.015, so theoretically, it is necessary to make the output current variation within 1-2%. In addition, it is difficult to visually discriminate output variations within 1%, and it is almost impossible to discriminate below 0.5% (appears uniform).

  In order to make the output current variation (%) within 1%, it is necessary to make the formation area of the transistor group (transistor for which the occurrence of variation is suppressed) within 2 square millimeters as shown in the result of FIG. . More preferably, output current variation (that is, transistor Vt variation) is preferably within 0.5%. As shown in the result of FIG. 118, the formation area of the transistor group 521 may be set within 1.2 square millimeters. The formation area is an area of length × width. For example, as an example, 1.2 mm2 is 1 mm × 1.2 mm.

  The same applies to the set of unit transistors 484 (for 64 gradations, a set of 63 transistors 484 (see FIG. 48, etc.). The formation area of the set of unit transistors 484 is within 2 square millimeters. More preferably, the formation area of the unit transistor set 484 should be within 1.2 square millimeters.

  The above is particularly the case of 8 bits (256 gradations) or more. In the case of 256 gradations or less, for example, in the case of 6 bits (64 gradations), the variation in output current may be about 2% (the actual state is not problematic in image display). In this case, the transistor group 521 may be formed within 5 square millimeters. Further, both of the transistor groups 521 (two transistor groups 521a and 521b are illustrated in FIG. 52) do not need to satisfy this condition. If at least one (one or more transistor groups 521 when there are three or more) is configured to satisfy this condition, the effect of the present invention is exhibited. In particular, it is preferable to satisfy this condition with respect to the lower-order transistor group 521 (the relationship in which 521a is the higher order and 521b is the lower order). This is because a problem in image display is less likely to occur.

  In the source driver IC (circuit) 14 of the present invention, as shown in FIG. 52, a plurality of current sources such as a parent, a child, and a grandchild are connected in multiple stages, and each current source is arranged densely (of course, A two-stage connection of a parent and a child may be used). In addition, current is passed between the current sources (between the transistor groups 521). Specifically, a range (transistor group 521) surrounded by a dotted line in FIG. 52 is densely arranged. The transistor group 521 is in a voltage transfer relationship. Further, the parent current source 471 and the child current source 472a are formed or arranged at substantially the center of the source driver IC 14 chip. This is because the distance between the transistor 472a constituting the child current source arranged on the left and right of the chip and the transistor 472b constituting the child current source can be made relatively short. That is, the uppermost transistor group 521a is arranged at the substantially central portion of the IC chip. Then, lower transistor groups 521b are arranged on the left and right sides of the IC chip 14. Preferably, the lower transistor group 521b is arranged, formed, or manufactured so that the number of the lower transistor groups 521b is substantially equal on the left and right of the IC chip. Note that the above items are not limited to the IC chip 14, but also apply to the source driver circuit 14 formed directly on the substrate 71 by the low temperature polysilicon technique or the high temperature polysilicon technique. The same applies to other matters.

  In the present invention, one transistor group 521a is configured, arranged, formed, or manufactured at a substantially central portion of the IC chip 14, and eight transistor groups 521b are formed on the left and right sides of the chip (N = 8 + 8, FIG. 47). The child transistor group 521b is equal to the left and right of the chip, or the number of transistor groups 521b formed or arranged on the left side and the position formed or arranged on the right side of the chip with respect to the position where the parent at the center of the chip is formed. It is preferable that the difference between the number of the transistor groups 521b formed is 4 or less. Furthermore, it is preferable that the difference between the number of transistor groups 521b formed or arranged on the left side of the chip and the number of transistor groups 521b formed or arranged on the right side of the chip be within one. . The above matters are the same for the transistor group (not shown in FIG. 52) as the grandchild.

  Voltage transfer (voltage connection) is performed between the parent current source 471 and the child current source 472a. Therefore, it is easily affected by the Vt variation of the transistor. Therefore, the transistor group 521a is densely arranged. The formation area of the transistor group 521a is formed within an area of 2 square millimeters as shown in FIG. More preferably, it is formed within 1.2 mm 2. Of course, when the number of gradations is 64 gradations or less, it may be within 5 square millimeters.

  Since data is transferred (current transfer) between the transistor group 521a and the child transistor 472b, a distance may flow. This distance range (for example, the distance from the output terminal of the upper transistor group 521a to the input terminal of the lower transistor 521b) is the same as that of the transistor 472a constituting the second current source (child) as described above. The transistor 472b constituting the second current source (child) is arranged at a distance of at least 10 mm. This is preferably arranged or formed within 8 mm. Furthermore, it is preferable to arrange within 5 mm.

  This is because the difference in the characteristics (Vt, mobility (μ)) of the transistors arranged in the silicon chip by examination will hardly affect the current delivery. In particular, this relationship is preferably implemented by a lower-order transistor group. For example, if the transistor group 521a is higher, the lower is the transistor group 521b, and the lower is the transistor group 521c, the current transfer between the transistor group 521b and the transistor group 521c is satisfied. Therefore, the present invention is not limited to all the transistor groups 521 satisfying this relationship. It is only necessary that at least one transistor group 521 satisfies this relationship. This is because the number of transistor groups 521 increases especially in the lower order.

  The same applies to the transistor 473a constituting the third current source (grandchild) and the transistor 473b constituting the third current source. Needless to say, the present invention can also be applied to voltage transfer.

  The transistor group 521b is formed, fabricated, or arranged in the left-right direction of the chip (longitudinal direction, that is, at a position facing the output terminal 681). The transistor group 521b is formed, fabricated, or arranged in the left-right direction of the chip (longitudinal direction, that is, at a position facing the output terminal 681). The number M of the transistor groups 521b is 11 in the present invention (see FIG. 47).

  A voltage is passed (voltage connected) between the child current source 472b and the grandchild current source 473a. Therefore, as in the transistor group 521a, the transistor group 521b is densely arranged. The formation area of this transistor group 521b is formed within an area of 2 square millimeters as shown in FIG. More preferably, it is formed within 1.2 mm 2. However, if the Vt of the transistor group 521b varies slightly, it is easily recognized as an image. Therefore, it is preferable that the formation area be an A region (within 0.5 square millimeters) in FIG. 118 so that the variation hardly occurs.

  Since data is exchanged (current exchange) between the grandchild transistor 473a and the transistor 473b in the transistor group 521b, a slight distance may flow. This distance range is the same as described above. The transistor 473a constituting the third current source (grandchild) and the transistor 473b constituting the second current source (grandchild) are arranged at a distance of at least 8 mm. Furthermore, it is preferable to arrange within 5 mm.

  FIG. 53 shows a case where the current value control element is composed of an electronic regulator. The electronic volume includes a resistor 531 (which generates a current limit and each reference voltage. The resistor 531 is formed of polysilicon), a decoder 532, a level shifter 533, and the like. The electronic volume outputs a current. The transistor 481 functions as an analog switch circuit.

  In the source driver IC (circuit) 14, the transistor may be described as a current source. This is because a current mirror circuit composed of transistors functions as a current source.

  The electronic volume circuit is formed (or arranged) according to the number of colors of the EL display panel. For example, in the case of three primary colors of RGB, it is preferable to form (or arrange) three electronic volume circuits corresponding to each color so that each color can be adjusted independently. However, when one color is used as a reference (fixed), an electronic volume circuit of −1 number of colors is formed (or arranged).

  FIG. 68 shows a configuration in which a resistance element 491 that controls the reference current independently for the three primary colors RGB is formed (arranged). Of course, it goes without saying that the resistance element 491 may be replaced with an electronic regulator. The resistance element 491 may be built in the source driver IC (circuit) 14. Basic current sources such as a parent current source and a child current source such as the current source 471 and the current source 472 are densely arranged in the current output circuit 654 in an area shown in FIG. By arranging them densely, output variations from the source signal lines 18 are reduced. As shown in FIG. 68, a current output circuit 654 (not limited to a current output circuit at the center of the IC chip (circuit) 14 may be a reference current generation circuit unit or a controller unit. (The area where no circuit is formed) makes it easy to evenly distribute current from the current sources 471 and 472 to the left and right of the IC chip (circuit) 14. Therefore, left and right output variations are unlikely to occur.

  However, the present invention is not limited to being arranged in the current output circuit 654 at the center. You may form in the one end or both ends of an IC chip. Further, it may be formed or arranged in parallel with the output current circuit 654.

  Forming the controller or output current circuit 654 at the center of the IC chip 14 is not very preferable because it is easily affected by the Vt distribution of the unit transistors 484 of the IC chip 14 (the Vt of the wafer is within the wafer). This is because a smooth distribution occurs).

  In the circuit configuration of FIG. 52, one transistor 473a and one transistor 473b are connected in a one-to-one relationship. Also in FIG. 51, one transistor 472a and one transistor 472b are connected in a one-to-one completion. The same applies to FIG. 49 and the like.

  However, if one transistor and one transistor are connected in a one-to-one relationship, the characteristics of the corresponding transistors (such as Vt) vary, and the output of the transistor connected to this transistor varies. End up.

  An example of a configuration for solving this problem is the configuration of FIG. In the configuration of FIG. 58, for example, a transmission transistor group 521b (521b1, 521b2, 521b3) including four transistors 473a and a transmission transistor group 521c (521c1, 521c2, 521c3) including four transistors 473b are connected. However, although the transfer transistor group 521b and the transfer transistor group 521c are each configured by four transistors 473, the present invention is not limited to this, and it goes without saying that it may be 3 or less or 5 or more. That is, the reference current Ib flowing through the transistor 473a is output by the plurality of transistors 473 that form a current mirror circuit with the transistor 473a, and the output current is received by the plurality of transistors 473b.

  It is preferable that the plurality of transistors 473a and the plurality of transistors 473b have substantially the same size and the same number. Further, the number of unit transistors 484 constituting one output (63 in the case of 64 gradations as shown in FIG. 48) and the number of unit transistors 484 and transistors 473b constituting the current mirror are substantially the same size and the same. It is preferable to use a number. Specifically, the difference between the size of the unit transistor 484 and the size of the transistor 473b is preferably within ± 25%. With the above configuration, the current magnification can be set with high accuracy, and variations in output current are reduced. Note that the area of the transistor is an area obtained by multiplying the channel length L of the transistor by the channel width W of the transistor.

  Note that the current Ib flowing through the transistor 473b is preferably set so that the current Ib flowing through the transistor 473b is five times or more. This is because the gate potential of the transistor 473a is stabilized and the occurrence of a transient phenomenon due to the output current can be suppressed.

  In addition, four transistors 473a are arranged adjacent to the transfer transistor group 521b1, the transfer transistor group 521b2 is arranged adjacent to the transfer transistor group 521b1, and the four transistors 473a are adjacent to the transfer transistor group 521b2. However, the present invention is not limited to this. For example, the transistor 473a of the transfer transistor group 521b1 and the transistor 473a of the transfer transistor group 521b2 may be arranged or formed so that their positional relationships are interlaced with each other. By varying the positional relationship (the arrangement of the transistors 473 is exchanged between the transmission transistor groups 521), the variation in output current (program current) at each terminal can be further reduced.

  By configuring the current passing transistor with a plurality of transistors in this way, variations in output current as a whole transistor group are reduced, and variations in output current (program current) at each terminal can be further reduced.

  The total formation area of the transistors 473 constituting the transmission transistor group 521 is an important item. Basically, the larger the total formation area of the transistors 473, the smaller the variation of the output current (program current flowing from the source signal line 18). That is, the variation decreases as the formation area of the transfer transistor group 521 (the total formation area of the transistors 473) increases. However, if the formation area of the transistor 473 increases, the chip area increases and the price of the IC chip 14 increases.

  Note that the formation area of the transfer transistor group 521 is the total area of the transistors 473 constituting the transfer transistor group 521. The area of the transistor 473 is an area obtained by multiplying the channel length L of the transistor 473 and the channel width W of the transistor 473. Therefore, if the transistor 521 is composed of 10 transistors 473, the channel length L of the transistor 473 is 10 μm, and the channel width W of the transistor 473 is 5 μm, the formation area Tm (square μm) of the transfer transistor group 521 is 10 μm × 5 μm × 10 = 500 (square μm).

  The formation area of the transmission transistor group 521 needs to maintain a predetermined relationship with the unit transistor 484. Further, it is necessary to maintain a predetermined relationship between the transfer transistor group 521a and the transfer transistor group 521b.

  The relation between the formation area of the transistor group 521 and the unit transistor 484 will be described. As shown in FIG. 50, a plurality of unit transistors 484 are connected corresponding to one transistor 473b. In the case of 64 gradations, there are 63 unit transistors 484 corresponding to one transistor 473b (in the case of the configuration in FIG. 48). The formation area Ts (square μm) of this unit transistor group (63 unit transistors 484 in this example) is 10 μm × when the channel length L of the unit transistor 473 is 10 μm and the channel width W of the transistor 473 is 10 μm. 10 μm × 63 = 6300 square μm.

  The transistor 473b in FIG. 48 corresponds to the transfer transistor group 521c in FIG. The formation area Ts of the unit transistor group and the formation area Tm of the transfer transistor group 521c are set as follows.

1/4 ≦ Tm / Ts ≦ 6
More preferably, the formation area Ts of the unit transistor group and the formation area Tm of the transmission transistor group 521c have the following relationship.

1/2 ≦ Tm / Ts ≦ 4
By satisfying the above relationship, variations in output current (program current) at each terminal can be reduced.

  The formation area Tmm of the transmission transistor group 521b is set to have the following relationship with the formation area Tms of the transmission transistor group 521c.

1/2 ≦ Tmm / Tms ≦ 8
More preferably, the formation area Ts of the unit transistor group and the formation area Tm of the transmission transistor group 521c have the following relationship.

1 ≦ Tmm / Tms ≦ 4
By satisfying the above relationship, variations in output current (program current) at each terminal can be reduced.

  When the output current Ic1 from the transistor group 521b1, the output current Ic2 from the transistor group 521b2, and the output current Ic3 from the transistor group 521b2, it is necessary to match the output current Ic1, the output current Ic2, and the output current Ic3. In the present invention, since the transistor group 521 includes a plurality of transistors 473, even if the individual transistors 473 vary, the transistor group 521 does not vary in output current Ic.

  The above embodiment is not limited to the configuration of the three-stage current mirror connection (multi-stage current mirror connection) as shown in FIG. Needless to say, this can also be applied to a one-stage current mirror connection. 52, the transistor group 521b (521b1, 521b2, 521b3,...) Composed of a plurality of transistors 473a and the transistor group 521c (521c1, 521c2, 521c3,...) Composed of a plurality of transistors 473b. ..)). However, the present invention is not limited to this, and a transistor group 521c (521c1, 521c2, 521c3,...) Including one transistor 473a and a plurality of transistors 473b may be connected. Further, a transistor group 521b (521b1, 521b2, 521b3,...) Including a plurality of transistors 473a may be connected to one transistor group 473b.

  48, switch 481a corresponds to the 0th bit, switch 481b corresponds to the 1st bit, switch 481c corresponds to the 2nd bit,... Switch 481f corresponds to the 5th bit. The 0th bit is composed of one unit transistor, the 1st bit is composed of 2 unit transistors, the 2nd bit is composed of 4 unit transistors, the 5th bit is composed of 32 unit transistors. . In order to facilitate the description, the driver circuit 14 is described as being 6-bit compatible with 64-gradation display.

  In the configuration of the source driver IC (circuit) 14 of the present invention, the first bit outputs a program current twice as large as the 0th bit. The second bit outputs a program current twice that of the first bit. The third bit outputs a program current twice that of the second bit. The fourth bit outputs a program current twice that of the third bit. The fifth bit outputs a program current twice that of the fourth bit. Conversely, each adjacent bit needs to be configured to output exactly twice the program current.

  The configuration of FIG. 58 reduces the variation in the output current of each terminal by receiving the output currents of the plurality of transistors 473a by the plurality of transistors 473b. FIG. 60 shows a configuration in which variations in output current are reduced by supplying a reference current from both sides of a transistor group. That is, a plurality of current Ib supply sources are provided. In the present invention, the current Ib1 and the current Ib2 have the same current value, and a transistor that generates the current Ib1, a transistor that generates the current Ib2, and a pair of transistors constitute a current mirror circuit.

  Therefore, the present invention has a configuration in which a plurality of transistors (current generating means) for generating a reference current that defines the output current of the unit transistor 484 are formed or arranged. More preferably, the output current from the plurality of transistors is connected to a current receiving circuit such as a transistor constituting a current mirror circuit, and the output current of the unit transistor 484 is controlled by the gate voltage generated by the plurality of transistors. is there. That is, the present invention has a configuration in which a plurality of unit transistors 484 and a plurality of transistors 473b forming a current mirror circuit are formed. In FIG. 58, five transistors 473b forming a current mirror circuit are arranged (formed) for a transistor group in which 63 unit transistors 484 are formed.

  When the IC chip is a silicon chip, the gate terminal voltage of the unit transistor 484 is preferably set in the range of 0.52 to 0.68 (V). Within this range, the variation in the output current of the unit transistor 484 is reduced. The above matters also apply to other embodiments of the present invention such as FIGS. 163, 164, and 165.

  In FIG. 60, if the reference current Ib1 and the reference current Ib2 can be individually adjusted, the voltage at the point a and the voltage at the point b of the gate terminal 581 can be freely set. By adjusting the reference currents Ib1 and Ib2, the unit transistors Vt are different between the left and right sides of the IC chip 14, so that even when the output current is tilted, it can be corrected.

  The current generated by the transistors constituting the current mirror circuit is preferably transferred by a plurality of transistors. The transistors formed in the IC chip 14 have characteristic variations. In order to suppress variations in transistor characteristics, there is a method of increasing the transistor size. However, even if the transistor size is increased, the current mirror magnification of the current mirror circuit may be greatly shifted. In order to solve this problem, it is preferable to use a plurality of transistors to exchange current or voltage. If a plurality of transistors are used, even if the characteristics of the transistors vary, the overall characteristic variation becomes small. Also, the accuracy of the current mirror magnification is improved. In total, the IC chip area is also reduced.

  In FIG. 58, a transistor group 521a and a transistor group 521b constitute a current mirror circuit. The transistor 521a includes a plurality of transistors 472b. On the other hand, the transistor group 521b includes a transistor 473a. Similarly, the transistor group 521c includes a plurality of transistors 473b.

  The transistor groups 521b1, transistor groups 521b2, transistor groups 521b3, transistor groups 521b4,... Are formed in the same number. Further, the total area of the transistors 473a in each transistor group 521b (WL size of the transistors 473a in the transistor group 521b × number of transistors 473a) is formed to be (substantially) equal. The same applies to the transistor group 521c.

  The total area of the transistor 473b of the transistor 521c (WL size of the transistor 473b in the transistor group 521c × number of transistors 473b) is Sc. Further, the total area of the transistors 473a in the transistor 521b (WL size of the transistors 473a in the transistor group 521b × the number of transistors 473a) is defined as Sb. The total area of the transistors 472b in the transistor 521a (WL size of the transistors 472b in the transistor group 521a × number of transistors 472b) is Sa. Further, the total area of one output unit transistor 484 is Sd (in the embodiment of FIG. 48, WL area of unit transistor 484 × 63).

  The total area Sc and the total area Sb are preferably formed to be substantially equal. The number of transistors 473a included in the transistor group 521b is preferably the same as the number of transistors 473b in the transistor group 521c. However, the number of transistors 473a included in the transistor group 521b is smaller than the number of transistors 473b included in the transistor group 521c due to restrictions on the layout of the IC chip 14, and the size of the transistor 473a included in the transistor group 521b is reduced to the transistor group. It may be larger than the size of the transistor 473b of 521c.

  This embodiment is illustrated in FIG. The transistor group 521a includes a plurality of transistors 472b. The transistor group 521a and the transistor 473a constitute a current mirror circuit. Transistor 473a generates current Ic. One transistor 473a drives a plurality of transistors 473b of a transistor group 521c (current Ic from one transistor 473a is shunted to a plurality of transistors 473b. Generally, the number of transistors 473a is equal to the number of output circuits. For example, in the case of a QCIF + panel, 176 transistors 473a are formed or arranged in R, G, and B circuits.

  The relationship between the total area Sd and the total area Sc correlates with output variations. This relationship is illustrated in FIG. Refer to FIG. 121 for the variation ratio and the like. The variation ratio is 1 when the total area Sd: total area Sc = 2: 1 (Sc / Sd = 1/2). As can be seen from FIG. 124, when Sc / Sd is small, the variation ratio sharply deteriorates. In particular, there is a tendency for Sc / Sd = 1/2 or less to deteriorate. When Sc / Sd is ½ or more, output variation is reduced. The reduction effect is moderate. Further, when Sc / Sd = 1/2, the output variation is within the allowable range. In view of the above, it is preferable to form such that 1/2 <= Sc / Sd. However, as Sc increases, the IC chip size also increases. Therefore, the upper limit is preferably Sc / Sd = 4. That is, the relationship of 1/2 <= Sc / Sd <= 4 is satisfied.

  A> = B means that A is B or more. A> B means that A is larger than B. A << = B means A is B or less. A <B means that A is smaller than B.

  Furthermore, it is preferable that the total area Sd and the total area Sc are substantially equal. Furthermore, it is preferable that the number of unit transistors 484 with one output and the number of transistors 473b in the transistor group 521c be the same. That is, in the case of 64 gradation display, 63 unit transistors 484 of 1 output are formed. Accordingly, 63 transistors 473b are included in the transistor group 521c.

  Preferably, the transistor group 521a, the transistor group 521b, the transistor 521c, and the unit transistor 484 are each formed using a transistor having a WL area ratio of 4 times or less. More preferably, a transistor with a WL area ratio of 2 times or less is preferable. Furthermore, it is preferable that all the transistors be the same size. That is, it is preferable that the current mirror circuit and the output current circuit 654 are configured by transistors having substantially the same shape.

  The total area Sa is set to be larger than the total area Sb. Preferably, it is configured to satisfy the relationship of 200Sb> = Sa> = 4Sb. Further, the total area of the transistors 473a configuring all the transistor groups 521b and Sa are configured to be substantially equal.

  In FIG. 60 and the like, transistors or transistor groups are arranged at both ends of the gate wiring 581. Therefore, two transistors are arranged on both sides of the gate wiring 581 or two sets of transistors are included. However, the present invention is not limited to this. As shown in FIG. 61, a transistor or a transistor group may be arranged or formed in the central portion of the gate wiring 581 or the like. In FIG. 61, three transistor groups 521a are formed. The present invention is characterized in that a plurality of transistors or transistor groups 521 are formed in the gate wiring 581. By forming a plurality of gate wirings 581, the impedance of the gate wiring 581 can be reduced, and stability is improved.

  In order to further improve the stability, it is preferable to form or place a capacitor 661 on the gate wiring 581 as shown in FIG. The capacitor 661 may be formed in the IC chip 14 or the source driver circuit 14, or may be arranged or stacked outside the chip as an external capacitor of the IC 14. When the capacitor 661 is externally attached, a capacitor connection terminal is arranged on the terminal of the IC chip.

  In the above embodiment, a reference current is supplied, the reference current is copied by a current mirror circuit, and is transmitted to the unit transistor 484 at the final stage. When the image display is black display (complete black raster), no current flows through any of the unit transistors 484. This is because any switch 481 is open. Therefore, since the current flowing through the source signal line 18 is 0 (A), no power is consumed.

  However, the reference current flows even in black raster display. For example, the current Ib and the current Ic in FIG. This current becomes a reactive current. It is efficient if the reference current is configured to flow during current programming. Therefore, the reference current is restricted from flowing during the vertical blanking period and the horizontal blanking period of the image. Further, the flow of the reference current is also restricted during the wait period.

  To prevent the reference current from flowing, the sleep switch 631 may be opened as shown in FIG. The sleep switch 631 is an analog switch. The analog switch is formed in the source driver circuit or the source driver IC 14. Of course, the sleep switch 631 may be disposed outside the IC 14 and the sleep switch 631 may be controlled.

  By turning off the sleep switch 631, the reference current Ib does not flow. Therefore, since no current flows through the transistor 473a in the transistor group 521a1, the reference current Ic is also 0 (A). Accordingly, no current flows through the transistor 473b of the transistor group 521c. Therefore, power efficiency is improved.

  FIG. 64 is a timing chart. A blanking signal is generated in synchronization with the horizontal synchronizing signal HD. When the blanking signal is at the H level, it is a blanking period, and when it is at the L level, it is a period during which the video signal is applied. The sleep switch 631 is off (open) when at the L level, and is on when at the H level.

  Therefore, during the blanking period A, the sleep switch 631 is off, so that the reference current does not flow. During the period D, the sleep switch 631 is on and a reference current is generated.

  Note that on / off control of the sleep switch 631 may be performed according to the image data. For example, when the image data of one pixel row is all black image data (the program current output to all the source signal lines 18 is 0 during the 1H period), the sleep switch 631 is turned off and the reference current (Ic , Ib, etc.). Further, a sleep switch may be formed or arranged so as to correspond to each source signal line, and on / off control may be performed. For example, when the odd-numbered source signal line 18 is in black display (vertical black stripe display), the sleep switch corresponding to the odd-numbered is turned off.

  52 and 77 are configuration diagrams of the source driver IC (circuit) 14 having a multi-stage connection current mirror configuration. The present invention is not limited to the multi-stage connection configuration shown in FIG. A one-stage source driver circuit 14 may be used. FIGS. 166 to 172, 190, 191, 208, 211, 213, and 214 are configuration diagrams of a one-stage connection source driver IC (circuit). The one-stage configuration has a simple circuit configuration and small output current variation. Also in this case, the unit transistor 484 is composed of an N-channel transistor. Therefore, the program current from the source signal line 18 becomes a sink current. The gate terminal of the unit transistor 484 and the gate terminal of the transistor 473b are connected by a common gate wiring 581. FIG. 166 shows the unit transistor group 521c. It is arranged or formed within a dotted line showing the unit transistor 521c in each drawing.

  In FIGS. 213 and 214, the reference current source 521b is illustrated as being disposed on both sides of the unit transistor group 521b (for example, both ends of the chip 14), but the present invention is not limited to this. Needless to say, the reference current source 521b may be provided at one position (one or one side).

  Consider a case where a plurality of source driver ICs (14a, 14b) are arranged adjacent to each other as shown in FIGS. 207, 210, and 228. In the white raster display, it is preferable that the output currents of all the terminals (Iout) coincide with each other without variation. Even if the output current varies, if the output current difference between adjacent output terminals is small, it is not visually recognized as a variation. Note that the variation between adjacent output terminals needs to be within 1%.

  When the display screen 50 is driven by one source driver IC 14, it is sufficient that the variation between adjacent output terminals is small. However, as shown in FIG. 228, driving a single screen 50 with a plurality of source driver ICs 14 is a problem. This is because there is a difference between the absolute values of the output currents of the source driver IC 14a and the source driver IC 14b.

  This is because if the absolute value of the output current of Ioutn of the unit transistor group 521 of the source driver IC 14a and the output current of Iout (n + 1) of the unit transistor group 521 of the source driver IC 14b are different, a boundary occurs on the screen 50 due to the adjacent output difference. Hereinafter, a method for solving this problem will be described.

  In FIG. 167, the transistor 472b and the two transistors 473a constitute a current mirror circuit. The transistors 473a1 and 473a2 are the same size. Accordingly, the current Ic flowing through the transistor 473a1 and the current Ic flowing through the transistor 473a2 are the same.

  The transistor group 521c and the transistor 473b1 including the unit transistor 484 and the transistor group 521c and the transistor 473b2 including the unit transistor 484 form a current mirror circuit in FIG. Variations occur in the output current of the transistor group 521c. However, the current of the output of the transistor group 521 that forms a current mirror circuit in close proximity is accurately defined.

  In the source driver IC 14a, the transistor 473b1 and the transistor group 521c1 are arranged close to each other to form a current mirror circuit. In addition, the transistor 473b2 and the transistor group 521cn are arranged close to each other to form a current mirror circuit. Therefore, if the current flowing through the transistor 473b1 is equal to the current flowing through the transistor 473b2, the output current of the transistor group 521c1 and the output current of the transistor group 521cn become equal.

  Similarly, in the source driver IC 14b, the transistor 473b1 and the transistor group 521c (n + 1) are arranged close to each other to form a current mirror circuit. In addition, the transistor 473b2 and the transistor group 521c (2n) are also arranged close to each other to form a current mirror circuit. Therefore, if the current flowing through the transistor 473b1 is equal to the current flowing through the transistor 473b2, the output current of the transistor group 521c (n + 1) and the output current of the transistor group 521c (2n) are equal.

  In FIG. 228, the reference voltage Vs is applied to the positive terminal of the operational amplifier 522. An external resistor R1 is connected to the negative terminal of the operational amplifier 522. One terminal of the resistor R1 is connected to a stable voltage Vp. Therefore, the resistor R1, the operational amplifier 522, and the transistor 473 constitute a constant current circuit. The current Ic flowing through the transistor 473 is Ic = (Vs−Vp) / R1. The resistor R1 is an external resistor. However, the resistor R1 is not limited to this and may be incorporated in the source driver IC (circuit) 14. For example, diffused resistors and polysilicon resistors formed in the IC chip are exemplified. Of course, the resistor may be formed by low temperature polysilicon technology. Further, the reference voltages Vs, Vp, etc. may be shared with the power supply voltage Vcc of the source driver IC (circuit) 14. Further, it may be shared with the anode voltage Vdd of the panel.

  The same reference voltage Vs is applied to the source driver IC 14a and the source driver IC 14b, and a reference current Ic is generated by a constant current circuit including the operational amplifier 552 by the reference voltage Vs (see also FIG. 170 and the like). For ease of explanation, the resistor R1 is an external resistor of the IC 14 and will be described assuming that one having an accuracy of 1% or less is used.

  With the above configuration, the current Ic flowing through the transistor 473b1 and the transistor 473b2 of the source driver IC 14a and the current Ic flowing through the transistor 473b1 and the transistor 473b2 of the source driver IC 14b can be made equal. Therefore, the current Ic flowing through the transistor 473b2 of the source driver IC 14a and the transistor 473b1 of the source driver IC 14b can be made equal.

  In the source driver IC 14a, the transistor 473b2 and the transistor group 521cn are arranged close to each other, so that a highly accurate current mirror circuit is configured. In the source driver IC 14b, the transistor 473b1 and the transistor group 521c (n + 1) are arranged close to each other, so that a highly accurate current mirror circuit is configured. From the above, the output current of the unit transistor group 521cn of the source driver IC 14a and the output current of the unit transistor 521c (n + 1) of the source driver IC 14b are substantially the same. Therefore, the boundary between the source driver IC 14a and the source driver IC 14b on the screen 50 does not occur.

  As described above, the source driver IC 14 according to the present invention is characterized in that it includes the transistor 473b that allows the reference current to flow to the left and right of the chip. For example, as shown in FIG. 207, it is obvious when the source driver IC 14 includes a transistor 473b on only one side. In the configuration of FIG. 207, as shown in FIG. 208, the unit transistor group 521c1 is close to the transistor 473b, so that an accurate current mirror circuit is configured. However, the unit transistor group 521cn and the transistor 473b which are D distance away from the transistor 473b (D is a distance close to the lateral width of the IC chip size) do not have the accuracy of the current mirror circuit.

  When a plurality of source driver ICs 14 having the configuration of FIG. 208 are arranged as shown in FIG. 207, even when a plurality of transistors 4 of the source driver IC 14a are arranged as shown in FIG. 207, the transistors 473b of the source driver IC 14a and the source drivers are arranged. Even if the same reference current Ic is supplied to the transistor 473b of the IC 14b, as shown in FIG. 209, the output currents at the terminals 681a and 681n are inclined. Therefore, a boundary is generated between the screen 50a driven by the source driver IC 14a and the screen 50b driven by the source driver IC 14b.

  In the present invention, as shown in FIG. 210, the source driver IC 14 is formed or arranged with transistors 473b (473b1, 473b2) that flow a reference current to the left and right of the chip. A specific circuit configuration is shown in FIG.

  In the embodiment of FIG. 228, the currents Ic1 and Ic2 flowing through the transistors 473a and 473b of the IC 14 can be made equal by increasing the degree of the external resistor and the accuracy of the reference voltage Vs. Therefore, the output currents in the same gradation of the transistor 473b and the transistor groups 521c1, 521cn, 521c (n + 1), and 521c (2n) that form the current mirror circuit can be made the same with high accuracy. Therefore, even when the screen 50 is driven by a plurality of source driver ICs (circuits) 14, the boundary between the source driver ICs (circuits) 14 is not visible. Needless to say, the currents Ic1 and Ic2 may be generated by a reference current circuit configured outside the IC chip and supplied to the transistor 473b.

  The resistors R11a and R12a are formed (designed) with a resistance value of a predetermined ratio or preferably with the same resistance value. Similarly, the resistor R21a and the resistor R22a are formed (designed) with a predetermined ratio of resistance values or preferably with the same resistance value. The same applies to the combination of the resistors R11b and R12b and the resistors R21b and R22b. Here, for ease of explanation, it is assumed that the resistors R11a, R12a, R21a, R22a, R11b, R12b, R21b, and R22b are designed (formed) to have the same resistance value. .

  The resistors R11a and R12a are formed or arranged close to each other. Similarly, the resistors R21a and R22a are formed or arranged close to each other, and the resistors R11b and R12b are formed or arranged close to each other. Similarly, the resistors R21b and R22b are formed or arranged close to each other. Each resistor is a polysilicon resistor or a diffused resistor. The value of the resistor formed (configured) in the IC chip has a characteristic that the relative ratio of the resistors arranged close to each other can be formed with high accuracy. However, absolute values often do not have accuracy.

  In many cases, the reference current source of the IC 14 is formed at both ends of the IC chip. However, the distance between the two reference current sources is at most about 20 mm. Therefore, the resistance value difference between the resistor R11a and the resistor R21a of the source driver IC 14a is often small. However, the absolute values of the resistors R11a and R21a and the source driver IC14b resistors R11b and R21b of the source driver IC14a having different IC chips are often different. This is because even if the source driver ICs 14a and 14b are formed on the same wafer, the IC formation positions are often greatly different.

  In order to facilitate the description, as an example, it is assumed that the resistance values of the resistor 11a, the resistor 12a, the resistor 21a, and the resistor 22a of the source driver IC 14a are equal to 50 (KΩ). Further, description will be made assuming that the resistance values of the resistor 11b, the resistor 12b, the resistor 21b, and the resistor 22b of the source driver IC 14b are equal to 75 (KΩ). That is, it is assumed that the built-in resistance of the source driver IC 14a and the built-in resistance of the source driver IC 14b have different absolute values, and the relative resistance value of the built-in resistance of each source driver IC is equal.

  In FIG. 229, one terminal of the resistor R11a, the resistor R21a, the resistor R11b, and the resistor R21b is connected to the voltage Vp. A reference voltage Vs is applied to the operational amplifier 522. In this respect, the configuration is the same as that of FIG. The difference between FIG. 229 and FIG. 228 is that in FIG. 228, the resistor R1 is an external resistor. In addition, the built-in resistors of adjacent source driver ICs in FIG. 229 are cascade-connected by the connection wiring 2291.

  The resistor R22a of the source driver IC 14a and the resistor R11b of the source driver IC 14b are electrically connected by a connection wiring 2291. The connection wiring 2291c is exemplified by a wiring pattern formed on the substrate 71. Therefore, the resistance connected to the operational amplifier 522b of the source driver IC 14a is R11b + R22a = 75 (KΩ) +50 (KΩ) = 125 (KΩ). The resistor R21a of the source driver IC 14a and the resistor R12b of the source driver IC 14b are electrically connected by a connection wiring 2291b. Therefore, the resistance connected to the operational amplifier 522a of the source driver IC 14b is R11b + R22a = 75 (KΩ) +50 (KΩ) = 125 (KΩ).

  The resistance connected to the operational amplifier 522b of the source driver IC 14a and the operational amplifier 522a of the source driver IC 14b is equal to 125 (KΩ), and the applied reference voltages Vs and Vp are also the same. Therefore, the current Ic2 flowing through the transistor 473b2 of the source driver IC 14a in FIG. 229 is equal to the current Ic1 flowing through the transistor 473b1 of the source driver IC 14b. Therefore, the program current flowing through the transistor group 521cn of the source driver IC 14a is equal to the program current flowing through the transistor group 521c (n + 1) of the source driver IC 14b.

  With the configuration of FIG. 229, the program output current between adjacent source driver ICs 14 can be made equal without an external resistor as shown in FIG. That is, even if the absolute value of the resistor R in the source driver IC 14 varies, the reference current can be made equal by self-alignment. Therefore, even when a plurality of source driver ICs 14 of the present invention are mounted on the substrate 71, there is no need for adjustment at all, and the cascade connection of the source driver ICs can be realized only by mounting.

Note that the resistance R in the source driver IC 14 may be adjusted to a predetermined absolute value by trimming. Further, the relative resistance value of a set of resistors R11a and R12a, resistors R21a and R22a, etc. may be adjusted to be a predetermined relative value.
As shown in FIG. 229, the internal resistor 11a and the resistor 12a at the end of the source driver 14a are short-circuited by a wiring 2291a. The internal resistor 21b and the resistor 22b at the end of the source driver 14b are short-circuited by the wiring 2291d.

  The built-in resistor 11a and the resistor 12a at the end of the source driver 14a are connected by a connection wiring 2291a. The resistance connected to the operational amplifier 522a of the source driver IC 14a is resistance 11a + resistance 12a = 50 (KΩ) +50 (KΩ) = 100 (KΩ). The resistance connected to the operational amplifier 522b of the source driver IC 14a is R21b + R22a = 75 (KΩ) +50 (KΩ) = 125 (KΩ). Therefore, the reference current Ic1 and the reference current Ic2 of the source driver IC 14a have different values. For this reason, the Iout1 program output current of the source driver IC 14a and the Ioutn program output current of the source driver IC 14a have different values. However, since Iout1 is located at the end of the screen 50, it is not visually recognized even if the brightness of the end of the screen 50 is different from the central portion of the screen 50. However, the brightness needs to change smoothly from the center to the end of the screen 50.

  Similarly, the internal resistor 21b and the resistor 22b at the end of the source driver 14b are connected by a connection wiring 2291d. The resistance connected to the operational amplifier 522b of the source driver IC 14b is resistance 21b + resistance 22b = 75 (KΩ) +75 (KΩ) = 150 (KΩ). The resistance connected to the operational amplifier 522a of the source driver IC 14b is R11b + R12b = 75 (KΩ) +50 (KΩ) = 125 (KΩ). Therefore, the reference current Ic1 and the reference current Ic2 of the source driver IC 14b have different values. Therefore, the program output current of Iout (n + 1) of the source driver IC 14b is different from the program output current of Iout (2n) of the source driver IC 14b. However, since Iout (2n) is located at the end of the screen 50, it is not visually recognized even if the brightness of the end of the screen 50 is different from the central portion of the screen 50.

  230, the program current from the transistor group 521c can be adjusted by connecting a volume 491a to the resistor R12a and by connecting the volume 491b to the resistor R22b. Good. Further, the resistor R12a, the resistor R22a, etc. may be an electronic volume. It goes without saying that the above matters may be applied to the resistor R22a and the resistor 12b.

  228, FIG. 229, and FIG. 230 have a configuration in which each source driver circuit 14 has a built-in resistor. The present invention is not limited to this. For example, as shown in FIG. 231, the same resistance value R (R1, R2, R3, R4) may be built in the source driver IC 14a. The resistors R (R1, R2, R3, R4) are arranged close to each other. By arranging them close to each other, the relative value of the resistance value can be accurately formed. The resistors (R1, R2, R3, R4) may be adjusted so that the absolute values are equal by performing laser trimming. Further, the relative values of the resistors may be adjusted to be equal by trimming.

  The resistors R3 and R4 of the source driver IC 14a are output via the terminals a2 and a4. This output is input to the source driver IC 14b from the terminals b2 and b3 of the source driver IV14b. With the above configuration, the resistor R3 in the source driver IC 14a is connected to the operational amplifier 522a of the source driver IC 14b, and a constant current circuit is configured. In addition, the resistor R4 in the source driver IC 14a is connected to the operational amplifier 522b of the source driver IC 14b to constitute a constant current circuit.

  The reference voltage Vs is also input to the source driver IC 14a, and is output to the source driver IC 14b via the terminal a1 of the source driver IC 14a. The output reference voltage Vs is input to the source driver IC 14b from the terminal b1 of the source driver IC 14b.

  In FIG. 229 and FIG. 230, the connection wiring 2291 intersects on the array substrate 71. It is necessary to form an insulating film at the intersection. However, in order to form an insulating film, it is necessary to increase the number of masks. The increase in the number of masks increases the panel manufacturing cost.

  In order to deal with this problem, an intersection is formed in the IC chip 14 as shown in FIG. In the IC chip, since the two-layer metal wiring is used, the intersection can be formed without an increase in cost. The resistor R21a of the source driver 14a is connected to the terminal b2, and the resistor R22b is connected to the terminal a2. Therefore, an intersection is formed. The same applies to the source driver 14b. The resistor R11a of the source driver 14b is connected to the terminal a1, and the resistor R12b is connected to the terminal b1. In FIG. 246, no intersection occurs. The same applies to the source driver 14a.

  With the above configuration, the connection wiring 2291 for connecting the source driver IC 14a and the source driver IC 14b can be linearly formed (formed) as shown in FIG.

  In order to perform the cascade connection, as an example, the leftmost terminals (a1, b1) of the IC 14 do not form an intersection. Intersections are formed or arranged at the terminals (a2, b2) on the right side of the IC. That is, an intersection is formed on one of the left and right terminals of the IC 14, and no intersection is formed on the other. Alternatively, the configuration of the left and right output wirings (output terminal positions) of the IC 14 is changed.

  In the above embodiments, 14a and 14b are source driver ICs. However, the present invention is not limited to this, and a source driver circuit formed by a low-temperature polysilicon technique or the like may be used. Needless to say, this technical idea can be applied to cascade connection of circuits having other functions such as the gate driver circuit (IC) 12.

  In the previous embodiment, the currents flowing through the transistors 473b1 and 473b2 are the same. However, for ease of explanation in FIG. 211, the reference current Ic1 is passed through the transistor 473b1 and the reference current Ic2 is passed through the transistor 473b2. Explain.

  In the configuration of FIG. 210, since the unit transistor group 521cn of the source driver IC 14a is close to the transistor 473b2, a highly accurate current mirror circuit is configured. Further, since the unit transistor group 521c1 of the source driver IC 14b is close to the transistor 473b1, an accurate current mirror circuit is configured. Therefore, by adjusting the reference current Ic2 of the source driver IC 14a and the reference current Ic1 of the source driver IC 14b, the output current of the unit transistor group 521cn of the source driver IC 14a and the output current of the unit transistor group 521c1 of the source driver IC 14b are adjusted. be able to.

  Therefore, even when the output currents of the source driver IC 14a and the source driver IC 14b are inclined as shown in FIG. 209, by adjusting the reference current Ic2 of the source driver IC 14a and / or the reference current Ic1 of the source driver IC 14b, FIG. As shown, the output current can be adjusted to be continuous on the screens 50a and 50b. Of course, it goes without saying that the boundary between the screen 50a and the screen 50b can be prevented by making the reference current Ic1 and the reference current Ic2 the same.

  That is, in the present invention, by configuring so that the reference current Ic1 of the transistor 473b1 and the reference current Ic2 of the transistor 473b2 can be adjusted, the boundary between the screen 50a and the screen 50b can be further prevented.

  Note that in the above description, the number of transistors 473b is one. However, it is preferable that a plurality of transistors 473b be formed to form the transistor group 521b. The transistor 521b includes a plurality of transistors 473b. The transistor size and shape of the transistor 473b in the transistor group 521b are preferably the same shape and size as the unit transistor 484. The number of transistors 473b in the transistor group 521b is preferably the same as the number of unit transistors 484 in the transistor 521c. Further, it is preferable to form a plurality of blocks of the transistor group 521b.

  Alternatively, the total area of the transistors 473b in the transistor group 521b is preferably substantially equal to the total area of the unit transistors 484 included in the unit transistor group 521c. Further, it is preferable to form a plurality of blocks of the transistor group 521b.

  In the above description, the source driver IC is described as an example. However, the present invention is not limited to this, and it goes without saying that the present invention can also be applied to a source driver circuit formed by a low-temperature polysilicon technique. Needless to say, the above matters are the same for the following embodiments.

  Note that in FIG. 211, the transistor 473b through which the reference current flows is disposed outside the IC chip. However, the present invention is not limited to this. For example, as illustrated in FIG. 247, the transistor 473b3 may be formed or disposed in the center of the gate wiring 581 or the like. The stability of the gate wiring 581 increases and there is no occurrence of lateral crosstalk. Therefore, it is preferable to form the transistor 473b through which a plurality of reference currents flow in the gate wiring 581. Needless to say, the stability of the gate wiring 581 is improved by reducing the resistance.

  As described with reference to FIG. 62, the potential of the gate wiring 581 is stabilized by connecting the capacitor 621 to the gate wiring 581. The capacitor 621 may be externally connected to the terminal of the IC chip 14. Needless to say, even if the driver circuit 14 is formed directly on the substrate 71 by a low-temperature polysilicon technique or the like, the stability of the gate wiring 581 is improved by forming the capacitor 621.

  FIG. 215 shows an arrangement configuration of the transistor 483b of the transistor group 521b. In one transistor group 521b, 63 transistors 473b having the same number as the unit transistors 484 of the unit transistor group 521c are formed. Of course, the number of transistors 473b in one transistor group 521b is not limited to 63. When the number of unit transistors 484 in the unit transistor group 521c is configured with the number of gradations −1, the number of transistors 473b in the transistor group 521b is also the number of gradations −1 or the same or similar number. Further, the configuration is not limited to the configuration shown in FIG. 215, and may be formed or arranged in a matrix as shown in FIG.

  The above configuration is schematically shown in FIG. The unit transistor groups 521c are arranged in parallel by the number of output terminals. A plurality of transistor groups 521b are formed on both sides of the unit transistor group 521c. A gate wiring 581 connects the gate terminal of the transistor 473b of the transistor group 521b and the gate terminal of the unit transistor 484 of the unit transistor group 521c.

  In the above description, for the sake of simplicity, the description has been made as a single-color source driver IC 14, but it is originally configured as shown in FIG. 214. That is, in the transistor group 521b and the unit transistor group 521c, red (R), green (G), and blue (B) transistor groups are alternately arranged (in FIG. 214, the transistor group to which the subscript R is added is red. (R) is shown, the transistor group to which the subscript G is added indicates green (G), and the transistor group to which the subscript B is added indicates blue (B)). As described above, output variations between RGB are reduced by alternately arranging RGB transistor groups. This configuration is also an important requirement for the layout in the source driver IC 14.

  In FIG. 228, the reference current Ic is generated by the operational amplifier 552 or the like, but is not limited to this. Instead of the volume, the reference current Ic may be adjusted by this volume. Similarly to FIG. 62, the transistor 473b may be formed using a plurality of transistors to form the transistor group 521b1 and the transistor 521b2. Also, a fixed resistor may be used.

  In FIG. 228 and the like, a plurality of source driver ICs 14 are cascade-connected by configuring (forming) the gate wiring 581 to have a relatively high resistance value. However, when two source driver ICs are cascade-connected, the gate wiring 581 may be formed with a low resistance value. This configuration is shown in FIG.

  In FIG. 248, the source driver IC 14a is configured such that the transistor 473b2 for passing the reference current is configured at the right end, and the left end is in an open state (see also FIG. 208 and the like). Therefore, the reference current Ic2 flows through the transistor 473b2 (only the current flowing into the gate terminal of the unit transistor 484 flows through the gate wiring 581a). The description will be made assuming that the reference currents Ic1 and Ic2 are equal. The output terminal 681a1 and the transistor 473b2 constituting the current mirror circuit and a current with high current mirror accuracy are output.

  In the source driver IC 14b, a transistor 473b1 for supplying a reference current is configured at the left end, and the right end is in an open state. Therefore, the reference current Ic1 flows through the transistor 473b1 (only the current flowing into the gate terminal of the unit transistor 484 flows through the gate wiring 581b). The output terminal 681a2 and the transistor 473b1 forming the current mirror circuit and a current with high current mirror accuracy are output. Therefore, if the reference currents Ic1 and Ic2 are equal, the gradation current output from the output terminal 681a1 of the source driver IC 14a and the gradation current output from the output terminal 681a2 of the source driver IC 14b are the same. For the above reasons, the two source driver ICs 14a and 14b are cascade-connected.

  In FIG. 248, the gradation current output from the right end terminal 681a3 of the source driver IC 14a does not always match the gradation current output from the left end terminal 681a1 of the source driver IC 14a. This is because the characteristics of the unit transistor 484 in the IC chip 14a change more. Further, the gradation current output from the right end terminal 681a2 of the source driver IC 14b does not necessarily match the gradation current output from the left end terminal 681a3 of the source driver IC 14b. This is because the characteristics of the unit transistor 484 in the IC chip 14b change more. However, since the source driver ICs 14 to be cascaded are two chips, there is no problem as long as the gradation current from the output terminal 681a1 of the source driver IC 14a matches the gradation current from the output terminal 681a2 of the source driver IC 14b. . Therefore, the gate wiring 581 may be formed of a low resistance wiring.

  FIG. 228, FIG. 211, FIG. 213, and the like are structures in which a transistor 473b3 for supplying a reference current is arranged or formed at both ends of the gate wiring 581. In this configuration, in order to realize the configuration in FIG. 248, one of the transistors 473b located at both ends of the gate wiring 581 of the IC chip 14a needs to be in an open state (a state in which no current flows through the transistor 473b). That is, it is necessary to configure as shown in FIG. In FIG. 249, the transistor 473b1 of the source drive IC 14a is open except for the gate terminal. Therefore, no current flows from the gate wiring 581a into the transistor 473b1. The transistor 473b2 of the source drive IC 14b is open except for the gate terminal. Therefore, no current flows from the gate wiring 581b into the transistor 473b2.

  In order to realize the configurations of FIGS. 248 and 249 in the configurations of FIGS. 228, 211, and 213, the configurations of FIGS. Hereinafter, the configuration of FIG. 245 will be described.

  In FIG. 245, a characteristic point is that a base terminal (drain terminal) of a transistor 473b for supplying a reference current is connected to a terminal c. Therefore, the reference current can be interrupted by opening the terminal c or connecting it to the ground.

  Further, in order to prevent the reference current from the transistor 473a from flowing into the gate wiring 581 or the transistor 473b, a cut point 2451 is formed (configured). An example in which the cutting point 2451 is cut by irradiating a laser beam is illustrated.

  In FIG. 245, the base terminal (drain terminal) of the transistor 471b1 of the source driver IC 14a is connected to the terminal c1, and the base terminal (drain terminal) of the transistor 471b2 is connected to the terminal c2. Since the terminal c1 is open and the cut point 2451a is cut, the transistor 471b1 is configured so that no current flows. Therefore, the left end of the gate wiring 581a is in an open state, which matches the state of the source driver IC 14a in FIG.

  On the other hand, the base terminal (drain terminal) of the transistor 471b1 of the source driver IC 14b is connected to the terminal c1, and the base terminal (drain terminal) of the transistor 471b2 is connected to the terminal c2. Since the terminal c2 is open and the cut point 2451b is cut, no current flows through the transistor 471b2. Therefore, the right end of the gate wiring 581b is in an open state, which matches the state of the source driver IC 14b in FIG.

  As described above, the potential state of the terminal c can be changed according to the potential setting state of the IC chip. This change means that the terminal c is installed at a ground potential by soldering or is in an open state. Of course, the terminal c may be cut in the same manner as the cutting point 2451. Further, the cut point 2451 may form an analog switch or the like so that the analog switch can be electrically turned on / off.

  In FIG. 228, FIG. 211, and FIG. 213, the transistors 473b are formed or arranged at both ends of the gate wiring 581, and the reference currents of the transistors 473b arranged at both ends are matched to perform cascade connection.

  FIG. 250 is a modification of FIG. When a current flows through the gate wiring 581, the current flowing through the transistor 473 b changes from a normal value, and an error occurs in the gradation output current. The reason why the current flows through the gate wiring 581 is that a characteristic difference occurs between the left and right IC chips (particularly Vt), and the gate terminal voltages of the transistor 473b1 and the transistor 473b2 are different.

  In order to suppress the influence of different gate terminal voltages, in the present invention, as shown in FIG. 250, a state in which a reference current Ic1 is passed through a transistor 473b1 (see FIG. 250A). (The current is not supplied) and the state in which the reference current Ic2 is supplied to the transistor 473b2 (see FIG. 250B; no current is supplied to the transistor 473b1) is alternately performed.

  Note that as illustrated in FIGS. 245 and 249, in FIG. 250A, the drain terminal of the transistor 473b2 is preferably open. In FIG. 250B, the drain terminal of the transistor 473b1 is preferably open.

  In one horizontal scanning period, the state shown in FIG. 250A and the state shown in FIG. 250B are performed. The state in FIG. 250A and the state in FIG. 250B are set to have the same period.

  In FIG. 250A, the switches 1611a and 1611c are closed, and the reference current Ic1 is allowed to flow through the transistor 473b1. At this time, the switches 1611b and 1611d are opened. Therefore, no current flows through the transistor 473b2. With the above state, the transistor group 521c forms a current mirror circuit with the transistor 473b1 and is driven.

  In the next 1 / 2H (half of the horizontal scanning period) period (FIG. 250 (b)), the switches 1611b and 1611d are closed, and the reference current Ic2 is supplied to the transistor 473b2. At this time, the switches 1611a and 1611c are opened. Therefore, no current flows through the transistor 473b1. With the above state, the transistor group 521c forms a current mirror circuit with the transistor 473b2 and is driven.

  By repeating FIG. 250A and FIG. 250B alternately, the period for forming the transistor group 521c, the transistor 473b1, and the current mirror circuit and the period for forming the transistor group 521c, the transistor 473b2, and the current mirror circuit are alternated. Repeated. Therefore, even if characteristic unevenness occurs on the left and right sides of the IC chip 14, it can be suppressed.

  In the above embodiment, the states shown in FIGS. 250 (a) and 250 (b) are performed in one horizontal scanning period. However, the present invention is not limited to this. good.

  Consideration is also given to the arrangement of the unit transistors 484 in the transistor group 521c. Note that the following matters regarding the arrangement and configuration of the unit transistors 484 and the like also apply to the transistors 473a of the transistor group 521a and the transistors 473b of the transistor group 521b.

  The unit transistor group 521c needs to be regularly arranged or formed. Further, the unit transistors 484 in the unit transistor group 521c need to be regularly formed or arranged. For example, if the unit transistor 484 is missing, the characteristics of the surrounding unit transistors 484 are different from the characteristics of the other unit transistors 484. Further, it is necessary to regularly form or arrange the layout on the gate line of the transistor.

  FIG. 217 schematically shows the arrangement of the unit transistors 484 in the unit transistor group 521c in the output stage. 63 unit transistors 484 expressing 64 gradations are regularly arranged in a matrix. However, 64 unit transistors 484 can be arranged in 4 columns × 16 rows. However, since there are 63 unit transistors 484, one portion is not formed (shaded portion). Then, the characteristics of the unit transistors 484a, 484b, and 484c in the vicinity of the shaded area are manufactured differently from those of the other unit transistors 484.

  In order to solve this problem, in the present invention, a dummy transistor 1341 is formed or arranged in the shaded portion. Then, the characteristics of the unit transistor 484a, the unit transistor 484b, and the unit transistor 484c become the same as those of the other unit transistors 484. That is, according to the present invention, the unit transistors 484 are configured in a matrix by forming the dummy transistors 1341. Further, the unit transistors 484 are arranged so as not to be covered in a matrix. Alternatively, the unit transistors 484 are arranged so as to have line symmetry.

  In order to express 64 gradations, 63 unit transistors 484 are arranged in the transistor group 521c, but the present invention is not limited to this. The unit transistor 484 may be composed of a plurality of sub-transistors.

  FIG. 135A shows a unit transistor 484. In FIG. 135B, four sub-transistors 12181 constitute a unit transistor 484. The output current obtained by adding the plurality of sub-transistors 2181 is set to be the same as that of the unit transistor 484. That is, the unit transistor 484 includes four sub-transistors 2181.

  Note that the present invention is not limited to the unit transistor 484 configured by the four sub-transistors 2181, and any configuration may be employed as long as the unit transistor 484 is configured by the plurality of sub-transistors 2181. However, the sub-transistors 2181 are configured to output the same size or the same output current.

  In FIG. 135, S represents a source terminal of the transistor, G represents a gate terminal of the transistor, and D represents a drain terminal of the transistor. In FIG. 135 (b), the sub-transistors 2181 are arranged in the same direction. In FIG. 135 (c), the sub-transistors 2181 are arranged in different directions in the row direction. In FIG. 135 (d), the sub-transistors 2181 are arranged in different directions in the column direction and arranged so as to be point-symmetric. 135 (b), 135 (c), and 135 (d) are all regular.

  135 (a), (b), (c), and (d) are layouts, the sub-transistor 2181 may be connected in series as shown in FIG. 135 (e) to form a unit transistor 484. Further, as shown in FIG. 135 (f), the unit transistors 484 may be connected in parallel.

  When the formation direction of the unit transistor 484 or the sub-transistor 2181 is changed, the characteristics are often different. For example, in FIG. 135 (c), the unit transistor 484a and the sub-transistor 2181b have different output currents even when the voltages applied to the gate terminals are the same. However, in FIG. 135C, the same number of sub-transistors 2181 having different characteristics are formed. Therefore, variations in the transistor (unit) are reduced. Further, by changing the direction of the unit transistor 484 or the sub-transistor 2181 in which the formation direction is different, the characteristic difference is interpolated and the variation of the transistor (one unit) is reduced. Needless to say, the above matters also apply to the arrangement shown in FIG.

  Therefore, as shown in FIG. 136 and the like, the direction of the unit transistor 484 is changed, and the characteristics of the unit transistor 484 formed in the vertical direction and the characteristics of the unit transistor 484 formed in the horizontal direction are interpolated as the transistor group 521c. Thus, variations in the transistor group 521c can be reduced.

  FIG. 136 shows an embodiment in which the formation direction of the unit transistors 484 is changed for each column in the transistor group 521c. FIG. 137 shows an example in which the formation direction of the unit transistors 484 is changed for each row in the transistor group 521c. FIG. 138 shows an example in which the formation direction of the unit transistors 484 is changed for each row and column in the transistor group 521c. Note that the dummy transistor 1341 is also formed or arranged in accordance with this configuration requirement.

  In the above embodiment, unit transistors having the same size or the same current output are configured or formed in the transistor group 521c (see FIG. 139 (b)). However, the present invention is not limited to this. As shown in FIG. 139 (a), the 0th bit (switch 641a) connects (forms) one unit transistor 484a. The first bit (switch 641b) connects (forms) two units of unit transistors 484b. The second bit (switch 641c) connects (forms) four unit transistors 484c. The third bit (switch 641d) connects (forms) 8 unit transistors 484d. The fourth bit (not shown) connects (forms) 16 unit transistors 484a. The fifth bit (not shown) may connect (form) 32 unit transistors 484a. For example, a unit transistor of 16 units is a transistor that outputs a current corresponding to 16 units of the unit transistor 484.

  The unit transistor (* is an integer) can be easily formed by changing the channel width W proportionally (the channel length L is constant). However, in reality, even if the channel width W is doubled, the output current often does not double. In this case, the channel width W is determined by experiment by actually manufacturing a transistor. However, in the present invention, even if the channel width W deviates from the proportional condition, it is expressed as proportional.

  In FIGS. 167, 168, and 169, the current of the transistor 472b is defined by the resistor R1, but the current is not limited to this, and may be electronic volumes 451a and 451b as shown in FIG. 170, the electronic volume 451a and the electronic volume 451b can be operated independently. Therefore, the value of the current flowing through the transistor 472a1 and the transistor 472a2 can be changed. Therefore, it is possible to adjust the output current slope of the left and right output stages 521c of the chip. Note that one electronic volume 451 may be provided as shown in FIG. 171, and the two operational amplifiers 722 may be controlled. Further, the sleep switch 631 has been described with reference to FIG. Similarly, it goes without saying that a sleep switch may be arranged or formed as shown in FIG.

  Since the number of unit transistors 484 is very large in the one-stage configuration of the current mirror of FIGS. 166 to 172, the driver circuit output stage of the source driver IC (circuit) 14 will be described. For ease of explanation, FIGS. 168 and 169 will be described as an example. However, since the description relates to the number and total area of the transistors 473b and the number and total area of the unit transistors 484, it is needless to say that the description can be applied to other embodiments.

  In FIGS. 168 and 169, the total area of the transistors 473b in the transistor group 521b (WL size of the transistors 473b in the transistor group 521b × number of transistors 473b) is Sb. Note that in the case where the transistor group 521b is provided on the left and right of the gate wiring 581 as in FIGS. 168 and 169, the area is doubled. As shown in FIG. 167, the two cases are the area of the transistor 473b × 2. Needless to say, when the transistor group 521b includes one transistor 473b, the transistor group 521b has the size of one transistor 473b.

  The total area of the unit transistors 484 in the transistor group 521c (WL size of the transistors 484 in the transistor group 521c × number of transistors 484) is Sc. Let n be the number of transistor groups 521c. n is 176 in the case of the QCIF + panel (when a reference current circuit is formed for each RGB).

  The horizontal axis of FIG. 165 is Sc × n / Sb. The vertical axis is the fluctuation ratio, and the fluctuation ratio is 1 in the worst situation. As shown in FIG. 165, as Sc × n / Sb increases, the fluctuation ratio becomes worse. An increase in Sc × n / Sb indicates that the total area of the unit transistors 484 in the transistor group 521c is larger than the total area of the transistors 473b in the transistor group 521b when the number of output terminals n is constant. In this case, the fluctuation ratio becomes worse.

  The smaller Sc × n / Sb indicates that the total area of the unit transistors 484 in the transistor group 521c is smaller than the total area of the transistors 473b in the transistor group 521b when the number of output terminals n is constant. In this case, the fluctuation ratio becomes small.

  As for the variation allowable range, Sc × n / Sb is 50 or less. If Sc × n / Sb is 50 or less, the variation ratio is within an allowable range, and the potential variation of the gate wiring 581 becomes extremely small. Therefore, there is no occurrence of lateral crosstalk, and output variation is within an allowable range, so that a good image display can be realized. If Sc × n / Sb is 50 or less, it is an acceptable range, but if Sc × n / Sb is 5 or less, there is almost no effect. Conversely, Sb increases and the chip area of the IC 14 increases. Accordingly, Sc × n / Sb is preferably 5 or more and 50 or less.

  FIG. 185 illustrates the relationship between the IC breakdown voltage and the output variation of the unit transistors. With respect to the variation ratio of the vertical axis, the variation of the unit transistor 484 is set to 1 by the 1.8 (V) breakdown voltage process. Note that FIG. 185 shows the output variation of the unit transistor 484 manufactured by each withstand voltage process when the shape L / W of the unit transistor 484 is 12 (μm) / 6 (μm). In addition, a plurality of unit transistors are formed in each IC withstand voltage process, and output current variation is obtained. However, the breakdown voltage process is 1.8 (V) breakdown voltage, 2.5 (V) breakdown voltage, 3.3 (V) breakdown voltage, 5 (V) breakdown voltage, 8 (V) breakdown voltage, 10 (V) breakdown voltage, 15 ( V) Breakdown such as withstand voltage. However, for ease of explanation, the variation of the transistors formed at each breakdown voltage is entered in a graph and connected by a straight line.

  The reason why there is a correlation between the breakdown voltage and the output variation is presumed to be related to the gate insulating film of the transistor. When the breakdown voltage is high, the gate insulating film is thick. If the gate insulating film is thick, the mobility is lowered and the variation with respect to the film thickness is also increased.

  From FIG. 185, until the IC withstand voltage is about 13 (V), the increase rate of the variation ratio (output current variation of the unit transistor 484) with respect to the IC process is small. However, when the IC breakdown voltage is 15 (V) or more, the slope of the variation ratio with respect to the IC breakdown voltage increases.

  In FIG. 185, the variation ratio within 3 is the variation allowable range in the 64 gradation to 256 gradation display. However, this variation ratio varies depending on the area of the unit transistor 484 and L / W. However, even if the shape of the unit transistor 484 is changed, there is almost no difference in the variation tendency of the variation ratio with respect to the IC breakdown voltage. When the IC withstand voltage is 13 to 15 (V) or more, the variation ratio tends to increase.

  On the other hand, the potential of the output terminal 681 of the source driver IC (circuit) 14 changes depending on the program current of the driving transistor 11 a of the pixel 16. The gate terminal potential Vw when the driving transistor 11a of the pixel 16 passes white raster (maximum white display) current is used. A gate terminal potential Vb when the driving transistor 11a of the pixel 16 passes a black raster (full black display) current is used. The absolute value of Vw−Vb needs to be 2 (V) or more. Further, when the Vw voltage is applied to the output terminal 681, the channel-to-channel voltage of the unit transistor 484 needs to be 0.5 (V).

  Therefore, the output terminal 681 (the terminal 681 is connected to the source signal line 18 and the gate terminal voltage of the driving transistor 11a of the pixel 16 is applied during current programming) from 0.5 (V) to ((Vw A voltage of −Vb) +0.5) (V) is applied. Since Vw−Vb is 2 (V), a maximum of 2 (V) +0.5 (V) = 2.5 (V) is applied to the terminal 681. Therefore, even if the output voltage (current) of the source driver IC 14 is a rail-to-rail output, the IC withstand voltage needs to be 2.5 (V). The required amplitude range of the output terminal 681 is 2.5 (V) or more.

  From the above, it is preferable to use a process with a breakdown voltage of the source driver IC 14 of 2.5 (V) to 15 (V). More preferably, the source driver IC 14 has a withstand voltage of 3 (V) or more and 12 (V) or less. More preferably, the minimum breakdown voltage is 4.5 (V) or more from the viewpoint of relatively increasing the amplitude value of the driving transistor 11a, increasing the gate terminal voltage change of the transistor 11a with respect to the program current, and improving the program accuracy. It is preferable to make it. The IC withstand voltage is equivalent to the maximum power supply voltage that can be used. The power supply voltage that can be used is a voltage that can be used at all times and is not an instantaneous withstand voltage.

  In the above explanation, the withstand voltage process of the source driver IC 12 is assumed to be a process of 2.5 (V) or more and 13 (V) or less. However, this withstand voltage is also applied to an embodiment (such as a low-temperature polysilicon process) in which the source driver circuit 14 is formed directly on the array substrate 71. The use withstand voltage of the source driver circuit 14 formed on the array substrate 71 may be as high as 15 (V) or more. In this case, the power supply voltage used for the source driver circuit 14 may be replaced with the IC withstand voltage shown in FIG. Even in the source driver IC 14, the IC withstand voltage may be replaced with the power supply voltage to be used.

  The reason why the unit transistor 484 requires a certain transistor size is that the wafer 3441 has a mobility characteristic distribution. FIG. 344 conceptually illustrates the state of the characteristic distribution of the wafer 3441. In general, the wafer characteristic distribution 3442 has a strip shape. The characteristics of the band-shaped part are approximate.

  Therefore, the source driver IC chip 14 is laid out in the direction of the characteristic distribution 3442 in FIG. 345 (b) rather than laying out the source driver IC chip 14 as shown in FIG. 345 (a). That is, the reticle is laid out so that the longitudinal direction of the IC chip coincides with the direction of the characteristic distribution 3442 of the wafer 3441.

  When the characteristic distribution 3442 as shown in FIG. 344 is generated (it is estimated that it is generally generated), as shown in FIG. 350A, unit transistors 484 of the transistor group 521c are arranged in an orderly manner. Rather, the dispersion of the characteristics of the terminals 681 is smaller when the unit transistors 484 constituting the transistor group are distributed as shown in FIG. 350B. In FIG. 350, unit transistors 484 having the same hatching constitute a transistor group 521c.

  The characteristic variation of the unit transistor 484 varies depending on the output current of the transistor group 521c. The output current is determined by the efficiency of the EL element 15. For example, if the luminous efficiency of the G EL element is high, the program current output from the G output terminal 681 is small. Conversely, if the luminous efficiency of the B-color EL element is low, the program current output from the B-color output terminal 681 increases.

  A smaller program current means a smaller current output from the unit transistor 484. As the current decreases, the variation of the unit transistors 484 also increases. In order to reduce the variation of the unit transistors 484, the transistor size may be increased.

  FIG. 351 shows an example. In FIG. 351, since the output current of the R pixel is the smallest, the unit transistor 484R corresponding to the R pixel is made the largest. Further, since the output current of the G pixel is the largest, the size of the unit transistor 484 is the smallest. The middle is a B pixel, which is an intermediate size between the unit transistors 484 corresponding to the R pixel and the G pixel. From the above, it is very effective to determine and configure the size of the unit transistor 484 in accordance with the efficiency of the RGB EL elements (corresponding to the magnitude of the program current).

  The area of the unit transistor 484 is correlated with variations in output current. FIG. 186 is a graph when the area of the unit transistor 484 is constant and the transistor width W of the unit transistor 484 is changed. In FIG. 186, the variation of the channel width W = 2 (μm) of the unit transistor 484 is 1.

  As shown in FIG. 186, the variation ratio of the unit transistor gradually increases from 2 (μm) to 9 to 10 (μm), and the variation ratio tends to increase when the unit transistor is 10 (μm) or more. Also, the variation ratio tends to increase when the channel width W = 2 (μm) or less.

  In FIG. 186, the variation ratio within 3 is the variation allowable range in the 64 gradation to 256 gradation display. However, this variation ratio varies depending on the area of the unit transistor 484. However, even if the area of the unit transistor 484 is changed, there is almost no difference in the variation tendency of the variation ratio with respect to the IC breakdown voltage.

  From the above, the channel width W of the unit transistor 484 is preferably 2 (μm) or more and 10 (μm) or less. More preferably, the channel width W of the unit transistor 484 is preferably 2 (μm) or more and 9 (μm) or less. In addition, the channel width W of the unit transistor 484 is preferably formed in the above range in order to prevent linking of the gate wiring 581 in FIG.

  FIG. 187 is a graph of L / W of the unit transistor 484 and a deviation (variation) from the target value. When the L / W ratio of the unit transistor 484 is 2 or less, the deviation from the target value is large (the slope of the straight line is large). However, as L / W increases, the deviation of the target value tends to decrease. When the L / W of the unit transistor 484 is 2 or more, the change in deviation from the target value is small. The deviation (variation) from the target value is L / W = 2 or more and 0.5% or less. Therefore, it can be adopted in the source driver circuit 14 as transistor accuracy.

  From the above, the L / W of the unit transistor 484 is preferably 2 or more. However, large L / W means that L becomes long, so that the transistor size becomes large. Therefore, L / W is preferably 40 or less. More preferably, L / W is preferably 3 or more and 12 or less.

  The reason why the output variation becomes small when L / W is a relatively large value seems to be that the gate voltage of the corresponding unit transistor 484 becomes high, and the change in the output current with respect to the change in the gate voltage becomes small.

  The magnitude of L / W also depends on the number of gradations. When the number of gradations is small, there is no problem even if the output current of the unit transistor 484 varies due to the kink because the difference between the gradations is large. However, in a display panel with a large number of gradations, the difference between the gradations is small, so that the number of gradations is reduced if the output current of the unit transistor 484 varies even slightly due to the influence of kink.

In consideration of the above, the driver circuit 14 according to the present invention has the number of gradations as K and L / W of the unit transistor 484 (L is the channel length of the unit transistor 484 and W is the channel width of the unit transistor). ,
(√ (K / 16)) ≦ L / W ≦ and (√ (K / 16)) × 20
It is configured (formed) to satisfy this relationship.

  In FIG. 169 and the like, when the total area Sa of the transistors 473a of the transistor group 521a is set to be the total area Sb of the transistors 473b of the transistor group 521b, the relationship between the total area Sa and the total area Sb has a correlation with the output variation. This relationship is illustrated in FIG. Refer to FIG. 185 for the variation ratio and the like.

  The variation ratio is set to 1 when the total area Sb: total area Sa = 2: 1 (Sa / Sb = 1/2). As can be seen from FIG. 188, when Sa / Sb is small, the variation ratio suddenly deteriorates. In particular, when Sa / Sb = 1/2 or less, it tends to be worse. When Sa / Sb is 1/2 or more, output variation is reduced. The reduction effect is moderate. Further, the output variation is within an allowable range at about Sa / Sb = 1/2. In view of the above, it is preferable to form such that 1/2 <= Sa / Sb. However, as Sa increases, the IC chip size also increases. Therefore, the upper limit is preferably Sa / Sb = 4. That is, the relationship of 1/2 <= Sa / Sb <= 4 is satisfied.

  A> = B means that A is B or more. A> B means that A is larger than B. A <= B means A is B or less. A <B means that A is smaller than B.

  Furthermore, it is preferable that the total area Sb and the total area Sa are substantially equal. Further, it is preferable that the number of unit transistors 484 with one output and the number of transistors 633b in the transistor group 521c be the same. That is, in the case of 64 gradation display, 63 unit transistors 484 of 1 output are formed. Therefore, 63 transistors 633b constituting the transistor group 521c are formed.

  As described above, in the case of 64 gradations (6 bits for each of RGB), 63 unit transistors 484 are formed. Therefore, in the case of 256 gradations (8 bits for each of RGB), 255 unit transistors 484 are required.

  However, the current driving method has a characteristic effect that current can be added. Further, in the unit transistor 484, if the channel length L is made constant and the channel width W is halved, there is a characteristic effect that the current flowing through the transistor 484 becomes about ½ (there is a characteristic configuration). . Similarly, if the channel length L is made constant and the channel width W is made 1/4, there is a characteristic effect that the current flowing through the transistor 484 becomes about 1/4.

  FIG. 274 (b) shows a configuration of a transistor group 521c in which unit transistors 484 having the same size are arranged for each bit. For ease of explanation, it is assumed in FIG. 274 (a) that 63 unit transistors 484 are configured and a 6-bit transistor group 521c is configured (formed). Further, FIG. 274 (b) is assumed to be 8 bits.

  In FIG. 274 (b), the lower 2 bits (indicated by A) are constituted by transistors having a size smaller than that of the unit transistor 484. The 0th bit of the minimum bit is formed by 1/4 of the channel width W of the unit transistor 484 (indicated by the unit transistor 484b). The first bit is formed with a half of the channel width W of the unit transistor 484 (indicated by the unit transistor 484a).

  Needless to say, the configuration or arrangement of FIG. 274 can also be applied to the configurations of FIGS. 54, 217, 257 to 260, and the like.

  As described above, the lower 2 bits are formed by unit transistors having a size smaller than that of the upper unit transistor 484. Further, the number of regular unit transistors 484 is 63, which is not changed. Therefore, even if the bit number is changed from 6 bits to 8 bits, the transistor group 521c is not greatly different between FIG. 274 (a) and FIG. 274 (b).

  As shown in FIG. 274 (b), the size of the transistor group 521c in the output stage does not increase even when the 6-bit specification is changed to the 8-bit specification because the current can be added. This is because if the length L is kept constant and the channel width W is 1 / n, the current flowing through the transistor 484 is approximately 1 / n.

  As shown in FIG. 274 (b), when the transistor size is reduced as in the unit transistors 484a and 484b, the output current variation also increases. However, no matter how large the variation is, the output currents of the unit transistors 484a or 484b are added. Therefore, the 8-bit specification of FIG. 274 (b) can realize higher gradation output than the 6-bit specification of FIG. 274 (a). Of course, since the output variations of the unit transistors 484a and 484b are large, there is a possibility that accurate 8-bit display cannot be realized. However, a higher definition display can be realized than in FIG. 274 (a).

  Actually, even if the channel width W is halved, the output current is not exactly halved. Some correction is required. In the correction, a correction coefficient can be easily grasped by forming a test transistor and measuring it.

  In the present invention, a small unit transistor smaller than the unit transistor 484 of the upper bit is formed or arranged in order to produce (configure) the lower bit. This concept of small means that it is smaller than the output current of the unit transistor 484 constituting the upper bit. Therefore, not only the channel width W is smaller than that of the unit transistor 484, but also the case where the channel length L is also small is included. Other shapes are also included.

  In FIG. 274, the unit transistor 484 constituting the transistor group 521c has a plurality of sizes. In FIG. 274, there are two types. The reason for the two types is that if the size of the unit transistor 484 is different, the magnitude of the output current is not proportional to the shape, which makes design difficult. Therefore, the size of the unit transistor 484 included in the transistor 521c is preferably two types for low gradation and high gradation. However, the present invention is not limited to this. Needless to say, there may be three or more types.

  As shown in FIG. 166, the gate terminals of the unit transistors 484 constituting the transistor group 521c are connected by one gate wiring 581. The same applies to FIGS. 208, 214, 213, 215, 216, 211. The output current of the unit transistor 484 is determined by the voltage applied to the gate wiring 581. Therefore, if the unit transistors 484 in the transistor group 521c have the same shape, each unit transistor 484 outputs the same unit current.

  The present invention is not limited to the common gate wiring 581 of the unit transistors 484 constituting the transistor group 521c. For example, you may comprise as FIG. 352 (a). In FIG. 352 (a), a unit transistor 484 forming a current mirror with the transistor 473b1 and a unit transistor 484 forming a current mirror with the transistor 473b2 are arranged.

  The transistor 473b1 is connected to the gate wiring 581a. The transistor 473b2 is connected to the gate wiring 581b. In FIG. 352 (a), the top one unit transistor 484 is LSB (0th bit), and the second stage two unit transistors 484 are the first bit and the third stage four unit transistors. 484 is the second bit. The eight unit transistors 484 in the fourth set are the third bit.

  In FIG. 352 (a), by changing the voltage applied to the gate wiring 581a and the gate wiring 581b, the output current of each unit transistor 484 is supplied to the gate wiring 581 even if the size and shape of each unit transistor 484 are the same. It can be changed (changed) by the applied voltage.

  In FIG. 352 (a), the unit transistors 484 have the same size and the like, and the voltages of the gate wirings 581a and 581b are different. However, the present invention is not limited to this. The unit transistors 484 may have the same output current by changing the sizes of the unit transistors 484 and adjusting the voltages of the gate wirings 581a and 581b to be applied. In 274, the size of the unit transistor 484 constituting the low gradation bit is made smaller than that of the unit transistor 484 constituting the high gradation. When the size of the unit transistor 484 is reduced, the output variation is increased. In order to solve this problem, the low-gradation unit transistor 484 actually has a channel length L larger than that of the high gradation so that the area of the transistor 484 is not reduced, thereby suppressing variations.

  As shown in FIG. 354, when the size of the unit transistor 484 in the range of the low gradation region A is different from the size of the unit transistor 484 in the range of the high gradation region B, the output variation is a combination of two curves. . However, there is no problem in practical use. On the contrary, it is preferable that the size of the unit transistor 484 in the low gradation portion is larger than the size of the unit transistor 484 in the high gradation portion, so that the output variation per unit transistor 484 can be reduced.

  With the configuration as shown in FIG. 352, the output current of the unit transistor 484 can be made the same by adjusting the voltage applied to the gate wiring 581 regardless of the size of the unit transistor 484 of low gradation and high gradation.

  In the present invention, the gate wiring 581 is described as two types of 581a and 581b, but is not limited thereto. There may be three or more types. Also, the unit transistor 484 may have three or more shapes.

  FIG. 352 (b) shows an embodiment in which the unit transistors 484 have the same size and are constituted by two gate wirings 581. FIG. In FIG. 352 (b), the top two unit transistors 484 are LSB (0th bit), and the four unit transistors 484 in the second stage are the eight unit transistors in the first and third stages. The set of 484 is the second bit. The fourth unit of eight unit transistors 484 connected to the gate wiring 581b is the third bit.

  Also in FIG. 352 (b), by changing the voltage applied to the gate wiring 581a and the gate wiring 581b, the output current of each unit transistor 484 is supplied to the gate wiring 581 even if the size and shape of each unit transistor 484 are the same. It can be changed (changed) by the applied voltage.

  In FIG. 352 (b), one output current of the unit transistor 484a connected to the gate wiring 581a corresponding to the low gradation part is equal to the output current of the unit transistor 484 connected to the gate wiring 581b corresponding to the high gradation part. It is configured to be 1/2. The unit transistor 484a and the unit transistor 484 have the same shape.

  In order to make the output current of the unit transistor 484a ½ that of the unit transistor 484, the voltage applied to the gate wiring 581a is set lower than that of the gate wiring 581b. By adjusting the voltage applied to the gate wiring 581, the output current can be changed or adjusted even when the unit transistor 484 a and the unit transistor 484 have substantially the same shape.

  In the embodiment of FIG. 352, the voltage applied to the gate wiring 581 is changed. It goes without saying that the voltage applied to the gate wiring 581 can be applied from outside the source driver IC (circuit) 14. However, generally, the voltage of the gate wiring 581 can be adjusted or changed by changing or designing or configuring the configuration or size of the transistor 473b (transistor group 521b) forming a current mirror pair with the unit transistor 484. It goes without saying that the current Ic flowing through the transistor 473b (transistor group 521b) forming a current mirror pair with the unit transistor 484 can be changed or adjusted.

  More specifically, the configuration of FIGS. 274 and 352 to 354 is configured as shown in FIGS. 399 and 400.

  In FIG. 399, unit transistors 484a (D2, D3, D4,...) On the high gradation side are arranged with a multiplier of 2. On the other hand, unit transistors 484b (D1, D2) on the low gradation side are also arranged with a multiplier of 2. The unit transistor 484a and the unit transistor 484b have different unit output currents (the unit current of 484b is smaller than that of 484a. For example, the unit transistor W is narrower on the low gradation side). The low gradation side and high gradation side unit transistors 484 are connected by a common gate wiring 483, and are controlled by a reference current Ic flowing in the transistor 473b constituting the current mirror circuit.

  In FIG. 400, the unit transistors 484a (D2, D3, D4,...) On the high gradation side are arranged with a multiplier of 2. On the other hand, unit transistors 484b (D1, D2) on the low gradation side are also arranged with a multiplier of 2. The unit transistor 484a on the high gradation side forms a current mirror circuit with the transistor 473bh. The reference current flowing through the transistor 473bh is Ich. On the other hand, the unit transistor 484b on the low gradation side forms a current mirror circuit with the transistor 473bl. The reference current flowing through the transistor 473bl is Icl.

  With the above configuration, the unit output currents of the unit transistor 484a and the unit transistor 484b are different (the unit current of 484b is smaller than that of 484a). The unit transistors 484 on the low gradation side and the high gradation side are connected by different gate wirings 483.

  As described above, there are many modified embodiments in the present invention. For example, the combination of FIG. 399 and FIG. 400 is also illustrated. It goes without saying that the above matters can be applied to other embodiments of the present invention.

  The above embodiment has described the shape of the unit transistor 484 of the transistor group 521c. Similarly, the present invention can be applied to the transistor 473b and the like included in the transistor group 521b and the like. FIG. 353 shows an example. The transistor 521b includes two types of transistors 473b and 473bn. The transistor 473bn is larger than the transistor 473b.

  Preferably, the transistor group 521a, the transistor group 521b, the unit transistor group 521c, and the unit transistor 484 are preferably formed using transistors having a WL area within four times. More preferably, the transistor is configured with a transistor having a WL area within twice. Furthermore, it is preferable that all the transistors be the same size. That is, it is preferable that the current mirror circuit and the output current circuit 704 are configured by transistors having substantially the same shape.

  The total area Sa is set to be larger than the total area Sb. Preferably, it is configured to satisfy the relationship of 200Sb> = Sa> = 4Sb. Further, the total area of the transistors 633a constituting all the transistor groups 521b is set to be substantially equal to Sa.

  With the circuit configuration shown in FIG. 190, white balance adjustment is also easy. First, the white balance is adjusted by adjusting the external resistors R1r, R1g, and R1b with the RGB electronic volume 451 having the same set value. The current driver IC (circuit) 14 is characterized in that if white balance is achieved with a set value of some electronic volume, the brightness of the screen 50 can be adjusted while maintaining the white balance if the value of the electronic volume 451 is made the same. is there.

  FIG. 190 shows a structure in which power is supplied from both sides of the transistor group 521c, but the above items are not limited to this. As shown in FIG. 337, the same applies to the one-side power feeding configuration. First, RGB electronic volume 451 is set to the same setting value, and external resistors R1r, R1g, and R1b are adjusted to achieve white balance. Generally, white balance is achieved by setting Icr of the R circuit, Icg of the G circuit, and Icb of the B circuit to a predetermined ratio in consideration of the light emission efficiency of each RGB EL element. The current driver IC (circuit) 14 is characterized in that if white balance is achieved with a set value of some electronic volume, the brightness of the screen 50 can be adjusted while maintaining the white balance if the value of the electronic volume 451 is made the same. is there. In addition, although it is preferable to form or arrange | position RGB electronic volume independently of RGB, it is not limited to this. For example, it is possible to adjust the screen brightness while maintaining white balance even with one electronic volume 451 in RGB.

  In the present invention, by forming or arranging an electronic volume inside the source driver IC (circuit) 14, the reference current can be varied or changed by digital data control from the outside of the source driver IC (circuit) 14. .

  By changing or changing the reference current, the output current of the unit transistor 484 can be changed. For example, if the output current when one unit transistor 484 is on is 1 μA when the reference current Ic is 100 μA, if the reference current Ic is 50 μA, the output current of one unit transistor 484 is 0.5 μA. Become. If the reference current Ic is 200 μA, the output current of one unit transistor 484 is 2.0 μA. That is, it is preferable that the reference current Ic and the output current Id of the unit transistor 484 satisfy the proportional relationship (see the solid line in FIG. 392).

  Further, it is preferable that the setting data for setting the reference current Ic and the reference current Ic are configured to have a proportional relationship. For example, when the setting data is 1, the reference current Ic is 100 μA, and if this is the base, the reference current Ic is 200 μA when the setting data is 100. That is, it is preferable that the reference current Ic increase by 1 μA when the setting data increases by one.

  With the configuration described above, the RGB reference currents (Icr, Icg, Icb) can be changed while maintaining a linear relationship according to the setting data of the electronic volume 451. Accordingly, since the linear relationship is maintained, if the white balance is adjusted at any setting data, the white balance is maintained at any setting data. In this configuration, it is important to configure the white balance by adjusting the external resistors R1r, R1g, and R1b described above (this is a characteristic configuration).

  In the above embodiment, the white balance is adjusted by an external resistor, but it goes without saying that the resistor R1 may be built in the IC chip.

  Further, as shown in FIG. 391, a switch S for adjusting or controlling the resistance value may be added. For example, in FIG. 391 (a), the external resistor R1 is selected by selecting the switch S1. Further, the external resistor becomes R2 depending on the selection of the switch S2. Further, by selecting both the switches S1 and S2, the external resistance becomes a resistance value in which R1 and R2 are connected in parallel.

  FIG. 391 (b) shows a configuration in which resistors R1 and R2 are connected in series, and an external resistor can be set to R1 + R2 or R1 by the control of the switch S.

  With the configuration as shown in FIG. 391, the change range of the reference current Ic can be expanded. That is, the reference current can be adjusted not only by setting data of the electronic volume 451 but also by control of the switch S. Therefore, the luminance adjustment range (dynamic range) of the EL display panel of the present invention can be expanded.

  It goes without saying that the above configuration or method can be applied to the configurations of FIGS. 170, 171, 190, 327, and 328.

  In the present invention, the change of the reference current due to the one-step change of the electronic volume 451 is set to about 3%. For example, if the reference current changes from 1 to 3 times and the number of steps of the electronic volume is 64 steps of 6 bits, (3-1) /64=0.03, which is about 3%.

  If the change in the reference current per step is large, the change in the brightness of the screen 50 when the electronic volume is changed is large, and it is recognized as flicker when the change is made. Conversely, if the change in the reference current per step is small, the change in luminance of the screen 50 is small and the dynamic change in luminance adjustment is poor. In addition, increasing the number of steps is directly linked to increasing the size of the electronic volume 451, increasing the size of the source driver IC 14 and increasing the cost.

  From the above, it is preferable that the change in the reference current per step is in increments of 1% or more and 8% or less (although it is based on the base). Furthermore, it is preferable to make a unit of 1% or more and 5% or less. For example, if the electronic volume 451 is 8 bits (256 steps) and the change in the reference current is from 1 to 10 times, (10-1) /256=3.5% increments, and the condition is 1% or more and 5% or less. Is satisfied.

  In the above embodiment, the change in the reference current per step has been described. However, since the change in the reference current is a change in the screen luminance, the change in the screen 50 luminance per step of the electronic volume 451 or the anode (or Cathode) Needless to say, it can be rephrased as a change in current.

  In the above embodiment, as shown by the solid line a in FIG. 392, the reference current Ic and the output current Id of the unit transistor 484 preferably satisfy the proportional relationship. However, the present invention is not limited to this. For example, as indicated by a dotted line b in FIG. 392, non-linearity (preferably in the range of 1.8 to 2.8) may be used. By making it non-linear (preferably in the range of 1.8 to 2.8), the change in the reference current with respect to the design data of the electronic volume 451 approaches the square curve of human visual characteristics, so the gradation characteristics are good It becomes.

  In the above embodiment, the reference current is changed by the setting data of the electronic volume 451. However, the present invention is not limited to this. It goes without saying that the reference current may be changed, adjusted, or controlled by the voltage input / output terminal 3893 as shown in FIGS. 389 and 390.

  It goes without saying that the above operation, configuration or control method is applied to other embodiments.

  The electronic volume 451 shown in FIGS. 170, 171, 190, and 337 may be configured as shown in FIG. 389. In FIG. 389, a ladder resistor 3891 (resistance array or transistor array) and a switch 3892 correspond to the electronic volume 451. The ladder resistor 3891 may be any means as long as it generates a voltage at a constant interval or a predetermined interval. For example, it goes without saying that the transistor may be diode-connected, or may be configured or formed by the on-resistance of the transistor.

  Needless to say, the configuration and system including the ladder resistor 3891 and the switch circuit 3892 as described above or the configuration and system of the voltage input / output terminal 3893 can be applied to the precharge configuration shown in FIG. Further, the present invention can be applied to the color management processing configuration shown in FIGS. 328 and 329. Needless to say, the present invention can also be applied to voltage program configurations such as FIGS. 364, 367, 371, and 373.

  Also, the configurations of FIGS. 389 and 390 can be applied to the configurations of FIGS. 56 and 57. Further, the present invention can also be applied to a configuration in which a reference current is applied from both sides of a source driver IC (circuit) 14 as shown in FIG. Needless to say, the present invention can also be applied to FIGS. 208, 328, and 337. Further, it goes without saying that the present invention can be applied or implemented not only to the reference current but also to control, adjustment or variable of the current Ib in the upper stage (however, Ib should also be referred to as the reference current) as shown in FIGS.

  In FIG. 389, the transistor 473ar generates the reference current Icr of the R circuit, and the transistor 473ag generates the reference current Icg of the G circuit. The transistor 473ab generates a reference current Icb for the B circuit.

  In FIG. 389, the ladder resistor 3891 is shared by three RGB switch circuits (3892r, 3892g, and 3892b). Therefore, the formation area of the ladder resistor 3891 in the source driver IC (circuit) 14 can be reduced.

  Also in FIGS. 389 and 390, the RGB reference currents (Icr, Icg, Icb) can be changed while maintaining the linear relationship according to the setting data of the switch circuit 3892. Accordingly, since the linear relationship is maintained, if the white balance is adjusted at any setting data, the white balance is maintained at any setting data. In this configuration, white balance can be achieved by adjusting the external resistors R1r, R1g, and R1b described above.

  In FIG. 389, a voltage input / output terminal 3893 is a terminal for inputting an analog voltage from the outside of the driver IC (circuit) 14. The reference current Ic can be changed or adjusted by the analog voltage. Therefore, white balance adjustment and screen 50 brightness adjustment can be performed without using the switch circuit 3892.

  Note that the switch circuit 3892 is configured such that when the setting data is 0, all the switches are open. Accordingly, the setting data of the switch circuit 3892 is controlled to be 0 and the input voltage of the voltage input / output terminal 3892 is made valid. On the other hand, when the setting data of the switch circuit 3892 is other than 0, the voltage from the ladder resistor 3891 is input to the positive terminal of the operational amplifier 722.

  The voltage input / output terminal 3893 also functions as a monitor terminal for the output voltage from the switch circuit 3892. In other words, the selection voltage of the ladder resistor 3891 is selected by the switch circuit 3892, and which of the selected voltages is input to the operational amplifier 722 can be monitored.

  In FIG. 389, since there are many wirings between the ladder resistor 3891 (step voltage output unit) and the RGB switch circuit 3892, a chip area is required. FIG. 390 shows an embodiment in which one switch circuit 3892 is used for RGB. Even with the above configuration, white balance adjustment and the like can be realized without any problem in practice.

  In the above embodiment, the electronic volume 451 and the switch circuit 3892 are changed by digital setting data. However, the present invention is not limited to this. For example, as shown in FIG. 401, even if the input voltage (indicated by point c) of the operational amplifier 722 is changed (changed) by the digital-analog conversion circuit (D / A circuit) 551, the reference current Ic is controlled. Needless to say, it is good.

  In the one-stage source driver circuit as shown in FIG. 191, particularly when an image is displayed on the display panel, the source signal line potential varies depending on the current applied to the source signal line 18. There is a problem that the gate wiring 581 of the source driver IC 14 which is good against this potential fluctuation is fluctuated (see FIG. 184). As shown in FIG. 184, linking occurs in the gate wiring 581 at the point where the video signal applied to the source signal line 18 changes. Since the potential of the gate wiring 581 changes due to linking, the gate potential of the unit transistor 484 changes and the output current fluctuates. In particular, the potential fluctuation of the gate wiring 581 becomes crosstalk (lateral crosstalk) along the gate signal line 14.

  This fluctuation (linking of the gate wiring 581 (see FIG. 184)) is influenced by the power supply voltage of the source driver IC. This is because the peak value of linking increases as the power supply voltage increases. Worst, it swings to the supply voltage. The voltage of the gate wiring 581 has a steady value of 0.55 to 0.65 (V). Therefore, even if slight linking occurs, the fluctuation value of the magnitude of the output current is large.

  FIG. 163 shows the potential variation ratio of the gate wiring with reference to the time when the power supply voltage of the source driver IC 14 is 1.8 (V). The variation ratio increases as the power supply voltage of the source driver IC 14 increases. The allowable range of the fluctuation ratio is about 3. If the fluctuation ratio is larger than this, lateral crosstalk occurs. The variation ratio tends to increase with respect to the power supply voltage when the IC power supply voltage is 13 to 15 (V) or higher. Therefore, the power supply voltage of the source driver IC 14 needs to be 13 (V) or less.

  On the other hand, in order for the driving transistor 11a to pass a current from white display to black display, the potential of the source signal line 18 needs to be changed by a constant amplitude. This required amplitude range is 2.5 (V) or more. The required amplitude range is below the power supply voltage. This is because the output voltage of the source signal line 18 cannot exceed the power supply voltage of the IC.

  From the above, the power supply voltage of the source driver IC 14 needs to be 2.5 (V) or more and 13 (V) or less. By setting it within this range, fluctuations in the gate wiring 581 are suppressed to the specified range, and horizontal crosstalk does not occur, and a good image display can be realized.

  The wiring resistance of the gate wiring 581 is also a problem. In FIG. 167, the wiring resistance R (Ω) of the gate wiring 581 is a resistance of the entire wiring length from the transistor 473b1 to the transistor 473b2. Alternatively, the resistance is the total length of the gate wiring. The magnitude of the transient phenomenon of the gate wiring 581 also depends on one horizontal scanning period (1H). This is because if the 1H period is short, the influence of the transient phenomenon is large. The higher the wiring resistance R (Ω), the more likely the transient phenomenon occurs. This phenomenon becomes a problem particularly in the configuration of the one-stage current mirror connection shown in FIGS. 166 to 172. This is because the gate wiring 581 is long and the number of unit transistors 484 connected to one gate wiring 581 is large. Of course, it goes without saying that the multistage connection of FIG. 162 is also a problem.

  FIG. 164 is a graph in which the wiring resistance R (Ω) of the gate wiring 581, the 1H period T (sec), and the multiplication (R · T) are plotted on the horizontal axis and the variation ratio is plotted on the vertical axis. The fluctuation ratio of 1 is based on R · T = 100. As can be seen from FIG. 164, when R · T is 5 or less, the variation ratio tends to increase. Further, when R · T is 1000 or more, the variation ratio tends to increase. Therefore, R · T is preferably 5 or more and 1000 or less.

  Duty ratio is also an issue. This is because the variation of the source signal line 18 also increases due to the duty ratio. Here, the total area of the unit transistors 484 in the transistor group 521c (WL size of the transistors 484 in the transistor group 521c × number of transistors 484) is Sc.

  In FIG. 189, the horizontal axis represents the Sc × Duty ratio, and the vertical axis represents the fluctuation ratio. As can be seen from FIG. 189, the fluctuation ratio tends to increase when the Sc × Duty ratio is 50 or more. Further, the fluctuation allowable range is when the fluctuation ratio is 3 or less. Therefore, it is preferable to control so that the Sc × Duty ratio can be driven at 50 or less.

  The variation allowable range is that the Sc × Duty ratio b is 50 or less. If the Sc × Duty ratio is 50 or less, the fluctuation ratio is within an allowable range, and the potential fluctuation of the gate wiring 581 becomes extremely small. Accordingly, there is no occurrence of lateral crosstalk, and output variation is within an allowable range, so that a good image display can be realized. If the Sc × Duty ratio is 50 or less, it is acceptable, but if the Sc × Duty ratio is 5 or less, there is almost no effect. Conversely, the chip area of the source driver IC 14 increases. Therefore, the Sc × Duty ratio is preferably 5 or more and 50 or less.

  In the source driver IC (circuit) 14 of the present invention, the transistor 473b that forms a current mirror circuit with the unit transistor group 521c or the transistor group that constitutes the transistor 473b (see FIGS. 215 and 216) has the relationship of FIG. It is preferable to satisfy.

  A current supplied to the transistor 473b or a transistor group constituting the transistor 473b (see FIGS. 215 and 216) is Ic, and a current output from one unit transistor group 521 is Id. Id is a program current (suction or discharge current) output to the source signal line 18, and is a current when all of the unit transistors 484 constituting the transistor group 521c are in a selected state. Therefore, Id is the current at the maximum gradation applied to the pixel 16. Note that when there is one 473b as shown in FIG. 208, it may be used as Ic as it is, but when there are a plurality of transistors 473 (a plurality of groups) as shown in FIG. 211, the sum is used as Ic. That is, in FIG. 211, Ic = Ic1 + Ic2. As described above, the current Ic is the sum of the currents Ic flowing through the transistor group 521c and the transistor group constituting the current mirror circuit.

  The ratio (Ic / Id) of the currents Id and Ic needs to be 5 or more. In FIG. 386, the vertical axis represents the crosstalk ratio. Crosstalk is a phenomenon in which a potential change of the source signal line 18 due to image display propagates through the gate wiring 581 of the source driver IC (circuit) 14 and horizontal pulling occurs on the screen 50. Crosstalk is likely to occur at points where an image changes from white display to black display and from black display to white display (for example, white window display). When Ic / Id is 5 or less, the occurrence of crosstalk suddenly increases (crosstalk ratio increases), but when it is 5 or more, the slope of the curve decreases.

  As can be understood from FIG. 386, Ic / Id needs to be 5 or more. However, when the number is 100 or more, the size of the transistor group 521b constituting the transistor 473b is large and not practical. Therefore, Ic / Id needs to be 5 or more and 100 or less. More preferably, it is preferably 10 or more and 80 or less.

  For Ic / Id, it is necessary to consider the horizontal scanning time. This is because the time constant of the gate wiring 581 needs to be reduced as the horizontal scanning period H is shorter. When the horizontal scanning period H is H (milliseconds) (time for selecting one pixel row), it is preferable to satisfy the following relationship. The unit of Ic and Id is μA.

0.3 <= (Ic.H) / Id <= 6.0
More preferably, it is preferable to satisfy the following relationship.

0.5 <= (Ic · H) / Id <= 5.0
More preferably, the following relationship is satisfied.

0.6 <= (Ic.H) / Id <= 3.0
By setting the Ic and Id currents so as to satisfy the above relationship and designing the transistor group 521 or the transistors 484 and 473, the occurrence of crosstalk is extremely reduced.

  For example, in the case of a QVGA panel, approximately H = 1000 (milliseconds) / (60 (Hz) · 240 pixel rows) = 0.07 (milliseconds). If Ic = 18 (μA) and the maximum program current Id = 1 (μA), then (Ic · H) / Id = (18 · 0.07) /1=1.3, which satisfies the above equation.

  In the case of the XGA panel, H = 0.025 (milliseconds). If Ic = 18 (μA) and the maximum program current Id = 1 (μA), then (Ic · H) / Id = (60 · 0.025) /1=1.5, which satisfies the above equation.

  H is a fixed value in terms of the number of pixel rows in the panel, and Id is the maximum value of the program current. Therefore, it is a fixed value if the efficiency and display luminance of the EL element of the display panel are determined. Therefore, Ic may be determined so as to satisfy the above equation. For example, if H = 0.07 (milliseconds) and Id = 1 (μA), Ic satisfying 0.3 <= (Ic · H) / Id <= 6.0 is 4 (μA) or more. 86 (μA) or less. If H = 0.025 (milliseconds) and Id = 1 (μA), Ic satisfying 0.3 <= (Ic · H) / Id <= 8.0 is 12 (μA) or more. 240 (μA) or less.

  It goes without saying that the above relationship can also be applied to the source driver IC (circuit) 14 corresponding to the N-fold pulse driving according to the present invention and the configuration in which the pixel 16 in FIG. 323, FIG. 367, FIG.

  In FIG. 211, the reference current Ic1 flowing through the transistor 473b1 and the reference current Ic2 flowing through the transistor 473b2 are adjusted so that the cascade connection between the source driver ICs 14a and 14b can be satisfactorily performed as illustrated in FIG. did.

  In FIG. 211, the reference currents Ic1 and Ic2 are adjusted. However, if the gate wiring 581 has a resistance value greater than or equal to a predetermined value, even if the reference current Ic1 flowing through the transistor 473b1 and the reference current Ic2 flowing through the transistor 473b2 are the same, the output current of FIG. The tilt is corrected. This is because the correction current Id for correcting the inclination flows through the gate wiring 581 as shown in FIG.

  In order to facilitate understanding, specific numerical values will be described. Ic1 = Ic2 = 10 (μA). At this time, the gate terminal voltage V1 of the transistor 473b1 = 0.60 (V) and the gate terminal voltage V2 of the transistor 473b2 = 0.61 (V). Since the difference between the reference current flowing through the transistor 473b2 and the reference current flowing through the transistor 473b1 needs to be within 1%, 1% of the reference current = 10 (μA) is 0.1 (μA). Therefore, (V2−V1) /0.1 (μA) = (0.61−0.60) (V) /0.1 (μA) = 100 (KΩ). Therefore, by setting the resistance value of the gate wiring 581 to 100 (KΩ), the slope of the output current is adjusted, and the difference between the output currents of the ICs 14 arranged adjacent to each other is kept within 1%.

  The higher the resistance of the gate wiring 581, the smaller the magnitude of the correction current Id. However, if the resistance value of the gate wiring 581 is too high, the peak value of linking in FIG. 184 also increases and the occurrence of lateral crosstalk becomes significant. Therefore, an appropriate range exists for the resistance value of the gate wiring 581.

  The present invention is characterized in that all of the gate wiring 581 or at least a part of the gate wiring 581 is formed of a wiring made of polysilicon. Preferably, polysilicon other than the contact portion with the gate terminal of unit transistor 484 or the vicinity thereof is formed. The gate wiring 581 is formed or configured to have a target resistance value by adjusting the wiring width or by meandering.

  Suppression of the linking of the gate wiring can be achieved by setting the gate wiring 581 to a resistance value equal to or lower than a predetermined value. Further, this can be achieved by increasing the total area Sb of the transistor 473b (total area Sb of the transistor group 521b). Further, this can be achieved by increasing the reference current Ic.

  When the area of one output unit transistor 484 (total area of unit transistors 484 in one transistor group 521c) is S0, the total area Sb of transistors 473b of the transistor group 521b (when there are a plurality of transistor groups 521b as shown in FIG. 213) Is the total area of the transistors 473b of the plurality of transistor groups 521b). FIG. 192 shows the relationship when Sb / S0 is on the horizontal axis and allowable gate wiring resistance (KΩ) is on the vertical axis. The range below the solid line in FIG. 192 is an allowable range (a range that is not affected by the occurrence of linking). In other words, lateral crosstalk is practically acceptable.

  The horizontal axis in FIG. 192 is the size S0 of the unit transistor 484 per output with respect to the size Sb of the total transistor group 521b (in the case of 64 gradations, 63 unit transistors 484). Assuming that S0 is a fixed value, the resistance value that the gate wiring 581 can tolerate increases as Sb increases. This is because as Sb increases, the impedance with respect to the gate wiring 581 decreases and the stability increases.

  Since S0 generates an output current (program current), and the output variation needs to be a certain value or less, the size of S0 has a narrow design change range. On the other hand, there are design restrictions in order to set the resistance value of the gate wiring 581 to a predetermined value. In order to increase the resistance of the gate wiring 581, there are a problem that the wiring becomes thin and disconnection occurs, and a problem of stability. Further, increasing Sb increases the chip area and the cost. Therefore, it is preferable to set Sb / S0 to 50 or less from the problem of the chip size of the IC 14, and Sb / S0 should be set to 5 or more because of restrictions such as stable design of the gate wiring 581 and linking problems. preferable. Therefore, it is necessary to satisfy the condition of 5 <= Sb / S0 <= 50.

  From the graph (solid line) in FIG. 192, the slope of the solid line curve becomes gentler as Sb / S0 becomes smaller. Further, when Sb / S0 is 15 or more, the inclination tends to be constant. Therefore, when Sb / S0 is 5 or more and 15 or less, the resistance value of the gate wiring 581 needs to be 400 (KΩ) or less. Further, when Sb / S0 is 15 or more and 50 or less, it is necessary to set Sb / S0 × 24 (KΩ) or less. For example, when Sb / S0 = 50, it is necessary to set it to 50 × 24 = 1200 (KΩ) or less.

  There is a correlation between the reference current Ic flowing through the transistor 473b and the allowable gate wiring resistance. This is because the larger the reference current Ic, the lower the impedance when the gate wiring 581 is viewed from the transistor 473b. FIG. 193 shows the relationship. In FIG. 193, the horizontal axis represents the reference current Ic (μA) flowing through the transistor 473b (or the transistor group 521b). The vertical axis represents allowable gate wiring resistance (KΩ). The range below the solid line in FIG. 193 is an allowable range (a range that is not affected by the occurrence of linking). In other words, lateral crosstalk is practically acceptable.

  When the reference current Ic is increased, the stability of the gate wiring 581 is improved. However, the reactive current consumed by the source driver IC 14 increases, and the potential of the gate wiring 581 also increases. For this reason, the reference current Ic needs to be 50 (μA) or less.

  If the reference current Ic is reduced, the stability of the gate wiring 581 decreases, so that the resistance value of the gate wiring 581 needs to be decreased. However, when the reference current is lowered below a certain value, the variation in the output current from the unit transistor 521c increases. That is, the stability of the output current is lost. Therefore, the reference current Ic needs to be 2 (μA) or more. From the above, the reference current Ic flowing through the transistor 473b needs to be 2 (μA) or more and 50 (μA) or less.

  The graph (solid line) in FIG. 193 can be approximated by two straight lines. When Ic is 2 (μA) or more and 15 (μA) or less, the resistance value (MΩ) of the gate wiring 581 needs to be 0.04 × Ic (MΩ) or less. For example, if Ic = 15 (μA), the resistance value of the gate wiring 581 needs to satisfy the condition of 0.04 × 15 = 0.6 (MΩ) or less.

  When Ic is 15 (μA) or more and 50 (μA) or less, the resistance value (MΩ) of the gate wiring 581 needs to be 0.025 × Ic (MΩ) or less. For example, if Ic = 50 (μA), the resistance value of the gate wiring 581 needs to satisfy the condition of 0.025 × 50 = 1.25 (MΩ) or less.

  There is also a correlation between a period in which one pixel row is selected (one horizontal scanning period (1H)) and the resistance R (KΩ) of the gate wiring 581 × the length D (m) of the gate wiring 581. This is because the shorter the period of 1H, the shorter the period required for the potential of the gate wiring 581 to return to the normal value. Further, as shown in FIG. 211, when the gate wiring 581 length D (= chip length of the driver IC) becomes longer, the potential fluctuation of the unit transistor group 521c farthest from the transistor 473b exceeds the allowable range. This phenomenon is presumed to be caused by the parasitic capacitance between the unit transistor 484 and the source signal line 18. That is, when the chip length D of the driver IC 14 is increased, it is necessary to consider not only the resistance value of the simple gate wiring 581 but also the potential fluctuation of the gate wiring 581 due to parasitic capacitance.

  In FIG. 195, the horizontal axis represents one horizontal scanning period (μ seconds). The vertical axis represents the product of gate wiring resistance (KΩ) and chip length D (m). The range below the solid line in FIG. 195 is the allowable range. As for R · D, 9 (KΩ · m) is the production limit of the source driver IC. Above this, the cost increases and is not practical. On the other hand, when R · D is 0.05 or less, the current Id in FIG. 191 becomes too large, and the deviation of the adjacent output current becomes too large. Therefore, R · D (KΩ · m) needs to be 0.05 or more and 9 or less.

  When the transistor 11 constituting the pixel 16 is configured by a P channel, the program current flows in the direction from the pixel 16 to the source signal line 18. Therefore, the unit transistor 484 (see FIGS. 48 and 57) of the source driver circuit needs to be formed of an N-channel transistor. In other words, the source driver circuit 14 needs to be configured to draw the program current Iw.

  Therefore, when the driving transistor 11a of the pixel 16 (in the case of FIG. 1) is a P-channel transistor, the unit transistor 484 is configured with an N-channel transistor so that the source driver circuit 14 always draws the program current Iw. In order to form the source driver circuit 14 on the array substrate 71, it is necessary to use both an N channel mask (process) and a P channel mask (process). Describing conceptually, the display panel (display device) of the present invention comprises the pixel 16 and the gate driver 12 as P-channel transistors, and the source driver's pull-in current source transistor as an N-channel.

  Therefore, the transistor 11 of the pixel 16 is formed by a P-channel transistor, and the gate driver circuit 12 is formed by a P-channel transistor. Thus, by forming both the transistor 11 and the gate driver circuit 12 of the pixel 16 with P-channel transistors, the cost of the substrate 71 can be reduced. However, the source driver 14 needs to form the unit transistor 484 as an N-channel transistor. Therefore, the source driver circuit 14 cannot be formed directly on the substrate 71. Therefore, the source driver circuit 14 is manufactured separately using a silicon chip or the like and mounted on the substrate 71. That is, the present invention has a configuration in which a source driver IC 14 (means for outputting a program current as a video signal) is externally attached.

  Further, when the area of the unit transistor 484 is the same, the variation of the unit transistor 484 formed by the N channel is 70% compared to the variation of the unit transistor formed by the P channel. That is, when the unit transistor 484 is formed with the N channel, the variation can be reduced with the same transistor formation area. According to the result of the examination, in order to make the variation of the P-channel unit transistor the same as that of the N-channel unit transistor, a double formation area is required.

  Although the source driver circuit 14 is formed of a silicon chip, the present invention is not limited to this. For example, a large number of glass substrates may be simultaneously formed by low-temperature polysilicon technology, cut into chips, and loaded on the substrate 71. Although the description has been made assuming that the source driver circuit is loaded on the substrate 71, the present invention is not limited to loading. Any form may be used as long as the output terminal 521 of the source driver circuit 14 is connected to the source signal line 18 of the substrate 71. For example, a method of connecting the source driver circuit 14 to the source signal line 18 by TAB technology is exemplified. By separately forming the source driver circuit 14 on a silicon chip or the like, variation in output current can be reduced and a good image display can be realized. Moreover, cost reduction is possible.

  Further, the configuration in which the selection transistor of the pixel 16 is configured by a P channel and the gate driver circuit is configured by a P channel transistor is not limited to a self-luminous device (display panel or display device) such as an organic EL. For example, the present invention can be applied to a liquid crystal display device and FED (field emission display).

  When the switching transistors 11b and 11c of the pixel 16 are formed of P-channel transistors, the pixel 16 is selected by Vgh. The pixel 16 is in a non-selected state by Vgl. As described before, the voltage penetrates when the gate signal line 17a changes from on (Vgl) to off (Vgh) (penetration voltage). When the driving transistor 11a of the pixel 16 is formed of a P-channel transistor, the current does not flow through the transistor 11a due to the punch-through voltage in the black display state. Therefore, good black display can be realized. It is difficult to realize black display, which is a problem of the current driving method.

  In the present invention, the on-voltage is Vgh by configuring the gate driver circuit 12 with a P-channel transistor. Therefore, matching with the pixel 16 formed by the P channel transistor is good. Further, in order to exert the effect of improving the black display, the driving transistor 11a and the source signal are generated from the anode voltage Vdd as in the configuration of the pixel 16 in FIGS. 1, 2, 32, 113, and 116. It is important to configure the program current Iw to flow into the unit transistor 484 of the source driver circuit 14 via the line 18. Therefore, it is excellent synergistic effect that the gate driver circuit 12 and the pixel 16 are composed of P channel transistors, the source driver circuit 14 is mounted on the substrate, and the unit transistors 484 of the source driver circuit 14 are composed of N channel transistors. To demonstrate. Further, the unit transistor 484 formed by the N channel has a smaller variation in output current than the unit transistor 484 formed by the P channel. When compared with the transistor 484 having the same area (W · L), the variation in output current of the N-channel unit transistor 484 is 1 / 1.5 to 1/2 compared to the P-channel unit transistor 484. . For this reason, the unit transistor 484 of the source driver IC 14 is preferably formed of an N channel.

  The same applies to FIG. 42B. In FIG. 42B, current does not flow into the unit transistor 484 of the source driver circuit 14 via the driving transistor 11b. However, the configuration is such that the program current Iw flows from the anode voltage Vdd into the unit transistor 484 of the source driver circuit 14 via the programming transistor 11 a and the source signal line 18. Therefore, as in FIG. 1, the gate driver circuit 12 and the pixel 16 are configured by P-channel transistors, the source driver circuit 14 is mounted on the substrate, and the unit transistors 484 of the source driver circuit 14 are configured by N-channel transistors. Exerts an excellent synergistic effect.

  In the present invention, the driving transistor 11a of the pixel 16 is configured by the P channel, and the switching transistors 11b and 11c are configured by the P channel. Further, the unit transistor 484 in the output stage of the source driver IC 14 is configured with N channels. Preferably, the gate driver circuit 12 is composed of a P-channel transistor.

  Needless to say, the above-described reverse configuration is effective. The driving transistor 11a of the pixel 16 is configured with an N channel, and the switching transistors 11b and 11c are configured with an N channel. Further, the unit transistor 484 in the output stage of the source driver IC 14 is configured as a P channel. Preferably, the gate driver circuit 12 is composed of an N channel transistor. This configuration is also a configuration of the present invention.

  Hereinafter, the reference current circuit will be described. As shown in FIG. 68, the reference current circuit 691 is formed (arranged) for each of R, G, and B. Further, the reference current circuits 691R, 691G, and 691B are arranged close to each other.

  The R reference current circuit 654R is provided with a volume (electronic volume) 491R for adjusting the reference current, and the G reference current circuit 654G is provided with a volume (electronic volume) 491G for adjusting the reference current. The circuit 654B is provided with a volume (electronic volume) 491B for adjusting the reference current.

  Note that the volume 491 and the like are preferably configured to change with temperature so that the temperature characteristics of the EL element 15 can be compensated. 69, the reference current circuit 691 is controlled by a current control circuit 692. By controlling (adjusting) the reference current, the unit current output from the unit transistor 484 can be changed.

  An output pad 681 is formed or arranged at the output terminal of the IC chip. This output pad is connected to the source signal line 18 of the display panel. The output pad 681 has bumps (projections) formed by a plating technique or a nail head bonder technique. The height of the protrusion is set to be 10 μm or more and 40 μm or less.

  The bumps and the source signal lines 18 are electrically connected via a conductive bonding layer (not shown). Conductive bonding layer is mainly composed of epoxy, phenolic, etc. as adhesive and mixed with flakes such as silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO2) Or an ultraviolet curable resin. The conductive bonding layer is formed on the bump by a technique such as transfer. The connection between the bump or output pad 681 and the source signal line 18 is not limited to the above method. Alternatively, the film carrier technology may be used without mounting the IC 14 on the array substrate. Further, the source signal line 18 or the like may be connected using a polyimide film or the like.

  In the present invention, since the reference current circuit 691 is separated into three systems for R, G, and B, the light emission characteristics and temperature characteristics can be adjusted by R, G, and B, respectively. White balance can be obtained (see FIG. 70).

  Next, the precharge circuit will be described. As described above, in the current driving method, the current written to the pixel is small during black display. For this reason, if the source signal line 18 or the like has a parasitic capacitance, there is a problem that a sufficient current cannot be written to the pixel 16 in one horizontal scanning period (1H). In general, a current-driven light-emitting element has a weak black level current value of about several nA, and thus it is difficult to drive a parasitic capacitance (wiring load capacitance) that seems to be about several tens of pF in its signal value. . In order to solve this problem, before writing image data to the source signal line 18, a precharge voltage is applied, and the potential level of the source signal line 18 is set to the black display current (basically the transistor 11a of the pixel). It is effective to set 11a to an off state. For the formation (creation) of the precharge voltage, it is effective to output a constant voltage at the black level by decoding the upper bits of the image data.

  Note that the precharge is a method of forcibly applying a voltage to the source signal line 18 at the beginning of 1H or the like. The voltage is used to turn off the driving transistor 11a (illustrated in the case of FIG. 1, but is not limited thereto, and may be a voltage-driven pixel configuration). When the driving transistor 11a is a P channel, a voltage close to the anode voltage is applied. That is, a voltage for turning off is applied. In the case of the N channel, a voltage close to the cathode voltage is applied.

  Note that the precharge voltage generation circuit (precharge voltage source 3041) is preferably formed or arranged at both ends of the source driver circuit (IC) 14 as shown in FIG. This is to suppress a voltage drop when the precharge voltage is applied.

  The application of the precharge voltage as described above is a method of applying a voltage for forcibly turning off the driving transistor 11a. Further, it means that a voltage is applied to the source signal line 18 to forcibly charge and discharge.

  Although the precharge voltage is applied, in order to change the potential of the source signal line 18, the potential of the source signal line 18 is changed not only by applying a voltage but also by applying a current (charging or discharging). Can be made. Therefore, the technical idea of applying the precharge voltage includes applying a precharge current.

  The present invention is characterized in that the driving transistor is a P-channel and the precharge voltage is equal to or lower than the anode voltage Vdd (anode voltage Vdd-1.5 (V). In addition, at least one of RGB is other. It is characterized in that the precharge voltage can be made different.

  FIG. 65 shows an example of a current output type source driver IC (circuit) 14 having a precharge function of the present invention. FIG. 65 shows a case where a precharge function is mounted in the output stage of a 6-bit constant current output circuit. In FIG. 65, the precharge control signal is a dot clock signal CLK that is decoded by the NOR circuit 652 when the upper 3 bits D3, D4, and D5 of the image data D0 to D5 are all 0 and has a reset function by the horizontal synchronization signal HD. The AND circuit 653 is connected to the output of the counter circuit 651 and outputs the black level voltage Vp for a certain period. In other cases, the output current from the current output stage 654 (specifically, the configuration of FIGS. 48, 56, 57, etc.) is applied to the source signal line 18 (from the source signal line 18 to the program current Iw). Absorb). With this configuration, when the image data is in the 0th to 7th gradations close to the black level, a voltage corresponding to the black level is written only for a certain period at the beginning of one horizontal period, and the burden of current driving is reduced. It becomes possible to make up for insufficient writing. The complete black display is the 0th gradation, and the complete white display is the 63rd gradation (in the case of 64 gradation display).

  In FIG. 65, when the precharge voltage is applied, the precharge voltage is applied to the point B of the internal wiring 483. Therefore, the precharge voltage is also applied to the current output stage 654. However, since the current output stage 654 is a constant current circuit, it has a high impedance. Therefore, even if a precharge voltage is applied to the constant current circuit 654, no problem occurs in circuit operation. In order to prevent the precharge voltage from being applied to the current output stage 654, the switch 655 may be disposed by cutting at point A in FIG. 65 (see FIG. 66). The switch is interlocked with the precharge switch 481a and is controlled to be turned off when the precharge switch 481a is on.

  The precharge may be performed in the entire gradation range, but preferably, the gradation for precharging should be limited to the black display region. That is, the writing image data is determined, and the black region gradation (low luminance, that is, the writing current is small (small) in the current driving method) is selected and precharged (referred to as selective precharging). When pre-charging is performed on all gradation data, this time, a decrease in luminance (not reaching the target luminance) occurs in the white display area. Moreover, the subject that a vertical stripe is displayed on an image may generate | occur | produce.

  Preferably, selective precharge is performed in a gradation region from gradation 0 to 1/8 of all gradations of gradation data (for example, in the case of 64 gradations, the 0th to 7th gradations are performed). In the case of image data up to, after precharging, the image data is written). Further, it is preferable that selective precharge is performed with gradations in a region of gradations 0 to 1/16 of gradation data (for example, in the case of 64 gradations, images from the 0th gradation to the 3rd gradation are used. Data and time, precharge and then write image data).

  In particular, in order to increase the contrast in black display, it is also effective to detect only the gradation 0 and precharge. The black display is extremely good. The method of precharging only the gradation 0 has less adverse effects on image display. Therefore, it is preferable to adopt as the most precharge technology.

  It is also effective to vary the precharge voltage and gradation range for R, G, and B. This is because the EL display element 15 has different emission start voltages and emission luminances for R, G, and B. For example, R is a selective precharge with the gradation of the gradation data from 0 to 1/8 of the gradation data (for example, in the case of 64 gradations, the images from the 01st gradation to the 7th gradation are used. When data, pre-charge and then write image data). Other colors (G, B) are selectively precharged with gradations in the range of gradations 0 to 1/16 of gradation data (for example, in the case of 64 gradations, the 3rd floor from the 0th gradation) The image data up to the time of the adjustment and the control such as writing the image data after precharging are performed. As for the precharge voltage, if R is 7 (V), a voltage of 7.5 (V) is written to the source signal line 18 for the other colors (G, B). The optimum precharge voltage is often different depending on the production lot of the EL display panel. Therefore, it is preferable that the precharge voltage is configured to be adjustable with an external volume or the like. This adjustment circuit can also be easily realized by using an electronic volume circuit.

  Note that the precharge voltage is preferably set to be equal to or lower than the anode voltage Vdd-0.5 (V) in FIG. 1 and within the anode voltage Vdd-2.5 (V).

  Even in the method of precharging only gradation 0, a method of precharging by selecting one or two colors of R, G, B is also effective. Less harmful to image display. It is also effective to precharge when the screen brightness is less than or equal to a predetermined brightness. In particular, when the brightness of the screen 50 is low, black display is difficult. By performing precharge driving such as 0 gradation precharge when the luminance is low, the contrast of the image is improved.

  In addition, the 0th mode in which no precharge is performed, the first mode in which only the gradation 0 is precharged, the second mode in which the precharge is performed in the range from the gradation 0 to the gradation 3, and the precharging is performed in the range from the gradation 0 to the gradation 7. It is preferable that a third mode to be charged, a fourth mode to be precharged in a range of all gradations, and the like are set, and these are switched by a command. These can be easily realized by configuring (designing) a logic circuit in the source driver IC (circuit) 14.

  FIG. 66 is a specific configuration diagram of the selective precharge circuit section. PV is a precharge voltage input terminal. Individual precharge voltages are set for R, G, and B by an external input or an electronic volume circuit. Note that although individual precharge voltages are set for R, G, and B, the present invention is not limited to this. R, G, and B may be common. This is because the precharge voltage correlates with Vt of the driving transistor 11a of the pixel 16, and this pixel 16 is the same for the R, G, and B pixels. When the W / L ratio of the driving transistor 11a of the pixel 16 is different between R, G, and B (having different designs), the precharge voltage should be adjusted corresponding to the different designs. Is preferred. For example, if the channel length L of the driving transistor 11a is increased, the diode characteristics of the transistor 11a are deteriorated and the source-drain (SD) voltage is increased. Therefore, the precharge voltage needs to be set lower than the source potential (Vdd).

  The precharge voltage PV is input to the analog switch 561. The analog switch W (channel width) needs to be 10 μm or more in order to reduce the on-resistance. However, if W is too large, the parasitic capacitance increases, so the thickness is made 100 μm or less. More preferably, the channel width W is preferably 15 μm or more and 60 μm or less.

  Note that this selective precharge may be fixed by precharging only gradation 0 or precharging in the range of gradation 0 to gradation 7, but the low gradation basin (gradation 0 in FIG. 79). To gradation R1 or gradation (R1-1)) may be linked to the low gradation area. That is, the selective precharge is performed in this range when the low gradation region is from gradation 0 to gradation R1, and is performed in this range when the low gradation region is from gradation 0 to gradation R2. Implement in conjunction. Note that this control method has a smaller hardware scale than other methods.

  The switch 481a is controlled to be turned on / off by the application state of the above signal, and the precharge voltage PV is applied to the source signal line 18 when the switch 481a is turned on. The time for applying the precharge voltage PV is set by a separately formed counter (not shown). This counter is configured to be set by a command. The precharge voltage application time is preferably set to 1/100 or more and 1/5 or less of one horizontal scanning period (1H). For example, if 1H is 100 μsec, it is 1 μsec or more and 20 μsec (1/100 of 1H or more and 1/5 or less of 1H). More preferably, it is 2 μsec or more and 10 μsec (2/100 of 1H or more and 1/10 or less of 1H).

  FIG. 67 is a modification of FIG. 65 or FIG. FIG. 67 shows a precharge circuit that determines whether or not to precharge according to input image data and performs precharge control. For example, precharge is set when the image data is only gradation 0, setting is performed when the image data is only gradations 0 and 1, gradation 0 is always precharged, and gradation 1 is continuously greater than a predetermined value. In such a case, a precharge setting can be made.

  FIG. 67 shows an example of a current output type source driver IC (circuit) 14 having a precharge function of the present invention. FIG. 67 shows a case where a precharge function is mounted in the output stage of a 6-bit constant current output circuit. In FIG. 67, the coincidence circuit 671 decodes according to the image data D0 to D5, and determines whether or not to precharge by the REN terminal input having a reset function by the horizontal synchronization signal HD and the dot clock CLK terminal input. The coincidence circuit 671 has a memory, and holds a precharge output result based on image data of several H or several fields (frames). Based on the holding result, it has a function of determining whether or not to precharge and performing precharge control. For example, it is possible to perform setting so that the gradation 0 is always precharged and the gradation 1 is precharged when the gradation 1 is continuously generated for 6H (6 horizontal scanning periods) or more. In addition, it is possible to perform setting so that the gradations 0 and 1 are always precharged, and the gradation 2 is continuously precharged when the gradation 2 is continuously generated for 3F (three frame periods) or more.

  The output of the coincidence circuit 671 and the output of the counter circuit 651 are ANDed by an AND circuit 653, and the black level voltage Vp is output for a certain period. In other cases, the output current from the current output stage 654 described with reference to FIG. 52 and the like is applied to the source signal line 18 (the program current Iw is absorbed from the source signal line 18). Other configurations are the same as or similar to those shown in FIGS. In FIG. 67, the precharge voltage is applied to point A, but it goes without saying that it may be applied to point B (see also FIG. 66).

  FIG. 223 shows an embodiment in which the precharge voltage can be changed according to the gradation in addition to FIG. In FIG. 223, it is possible to easily change the precharge voltage in accordance with the applied image data. The precharge voltage can be changed by the electronic volume 451 according to the image data (D3 to D0). In FIG. 223, since the D3 to D0 bits are connected to the electronic volume, it can be seen that the low gradation precharge voltage can be changed. This is because the black display write current is very small and the white display write current is large. Therefore, the precharge voltage is increased as the low gradation region is reached. Since the driving transistor 11a of the pixel 16 is a P channel, the anode voltage (Vdd) is a black display voltage. As the high gradation region is reached, the precharge voltage is lowered (when the pixel transistor 11a is in the P channel). That is, the voltage programming method is implemented in the low gradation display, and the current programming method is implemented in the high gradation display (white display).

  In the precharge circuit in FIG. 223, it is possible to select whether to precharge only the gradation 0 or to precharge in the range from the gradation 0 to the gradation 7. In addition, the precharge voltage for each gradation can also be changed by the electronic volume 451. Other configurations are the same as those shown in FIGS. 65, 66, and 67, and thus description thereof is omitted.

  Good results can also be obtained by varying the precharge voltage PV application time according to the image data applied to the source signal line 18. For example, the application time is lengthened in gradation 0 for full black display, and shorter than that in gradation 4. It is also possible to obtain a good result by setting the application time in consideration of the difference between the image data before 1H and the image data to be applied next. For example, when writing a current to display a pixel in white on the source signal line 1H before and writing a current to display a black in the pixel to the next 1H, the precharge time is lengthened. This is because the black display current is very small. On the other hand, when writing the current to make the pixel display black on the source signal line 1H before, and writing the current to make the black display on white next 1H, shorten the precharge time or precharge the current. Stop (do not do). This is because the white display write current is large.

  It is also effective to change the precharge voltage according to the image data to be applied. This is because the writing current for black display is very small and the writing current for white display is large. Therefore, the precharge voltage is increased (with respect to Vdd when the pixel transistor 11a is in the P channel) as the low gradation region is reached, and the precharge voltage is decreased (pixel) as the high gradation region is obtained. A control method in which the transistor 11a is in the P channel) is also effective.

Hereinafter, for ease of understanding, description will be made with reference to FIG. Needless to say, the items described below can be applied to the precharge circuits shown in FIGS.
When the program current open terminal (PO terminal) is “0”, the switch 655 is turned off, and the IL terminal, the IH terminal, and the source signal line 18 are disconnected (the Iout terminal is connected to the source signal line 18). ) Therefore, the program current Iw does not flow through the source signal line 18. The PO terminal is set to “1” when the program current Iw is applied to the source signal line, turns on the switch 655, and flows the program current Iw to the source signal line 18.

  When “0” is applied to the PO terminal and the switch 655 is opened, no pixel row in the display area is selected. The unit transistor 484 does not keep current based on the input data (D0 to D5) and is drawn from the source signal line 18. This current is a current that flows from the Vdd terminal of the selected pixel 16 to the source signal line 18 via the transistor 11a. Therefore, when no pixel row is selected, there is no path for current to flow from the pixel 16 to the source signal line 18. The time when no pixel row is selected occurs between the time when an arbitrary pixel row is selected and the next pixel row is selected. Note that a state in which no pixel (pixel row) is selected and there is no path for flowing into (flowing out) the source signal line 18 is referred to as an all non-selection period.

  When the output terminal 681 is connected to the source signal line 18 in this state, the unit transistor 484 that is turned on (actually, the switch 481 that is controlled by the data of the D0 to D5 terminals is used. Current). For this reason, the charge charged in the parasitic capacitance of the source signal line 18 is discharged, and the potential of the source signal line 18 rapidly decreases. As described above, when the potential of the source signal line 18 is lowered, it takes time to restore the original potential due to the current originally written in the source signal line 18.

  In order to solve this problem, the present invention applies “0” to the PO terminal during all non-selection periods, turns off the switch 655 in FIG. 66, and disconnects the output terminal 681 and the source signal line 18. By disconnecting, no current flows from the source signal line 18 to the unit transistor 484, and therefore no potential change of the source signal line 18 occurs during the entire non-selection period. As described above, good current writing can be performed by controlling the PO terminal during the entire non-selection period and disconnecting the current source from the source signal line 18.

  In addition, the area of white display area (area with constant brightness) (white area) and the area of black display area (area with luminance below predetermined) (black area) are mixed on the screen. It is effective to add a function of stopping the precharge when the ratio is in a certain range (appropriate precharge). This is because vertical stripes occur in the image within this certain range. Of course, conversely, precharging may be performed within a certain range. Also, when the image moves, the image becomes noise-like. Appropriate precharging can be easily realized by counting (calculating) data of pixels corresponding to the white area and the black area with an arithmetic circuit.

  It is also effective to make the precharge control different for R, G, and B. This is because the EL display element 15 has different emission start voltages and emission luminances for R, G, and B. For example, R is the ratio of the white area of the predetermined luminance: the black area of the predetermined luminance is stopped or started when the ratio is 1:20 or more, and G and B are the ratio of the white area of the predetermined luminance: the black area of the predetermined luminance. Is a method of stopping or starting the precharge at 1:16 or more. According to the experiment and examination results, in the case of the organic EL panel, the precharge is performed when the ratio of the white area of the predetermined luminance to the black area of the predetermined luminance is 1: 100 or more (that is, the black area is 100 times or more of the white area). Is preferably stopped. Furthermore, it is preferable to stop the precharge when the ratio of the white area with the predetermined luminance to the black area with the predetermined luminance is 1: 200 or more (that is, the black area is 200 times or more of the white area).

  Further, precharge will be described. FIG. 232 shows another embodiment of the precharge circuit. The difference from the embodiment of FIG. 66 is that the precharge switch 481a is controlled by precharge enable (PEN), precharge select (PSL), and the like. The control switch is OPV. The switch 656 in the current output stage is controlled by the PO signal.

  As shown in FIG. 251, the precharge voltage may be divided by a constant voltage to generate a plurality of precharge voltages. In FIG. 251, the Vp voltage is divided by the resistor R, and the divided voltage reduces the impedance via the operational amplifier 722 to generate the precharge voltages Vp1 and Vp2. One of the precharge voltages (Vp1, Vp2) is selected according to the image data and is output from the terminal 681. The selection is performed by the switches 481a and 481b.

  In this embodiment of the present invention, whether or not to precharge is determined by the image data. As this control, the PSL signal and the PEN signal perform important functions.

  As described before, as shown in FIG. 235, RGB image data (RDATA, GDATA, BDATA) is 8 bits each. The RGB 8-bit image data is gamma-converted by the gamma circuit 834 to become a 10-bit signal. The signal subjected to gamma conversion is subjected to FRC processing by a frame rate control (FRC) circuit 835 and converted to 6-bit image data. A precharge control circuit (PC) 2351 generates a precharge control signal (set to H level when precharging and set to L level when not precharging) from the converted 6-bit image data. A method for generating this precharge will be described later.

  FIG. 236 is a block diagram centering on the precharge circuit 2363 of the source driver IC (circuit) 14. The precharge circuit 2363 corresponds to circuits such as FIGS. 66, 232, and 233. The precharge control circuit 2351 outputs a precharge control signal PC signal (red (RPC), green (GPC), blue (BPC)). The PC signal is generated by the precharge control circuit 2351 of the control IC 81 shown in FIG. 235, and the PC signal is input to the selector circuit 2362 of the source driver IC 14 shown in FIG.

  The selector circuit 2362 sequentially latches in the latch circuit 2361 corresponding to the output stage in synchronization with the main clock. The latch circuit 2361 has a two-stage structure of a latch circuit 2361a and a latch circuit 2361b. The latch circuit 2361b sends data to the precharge circuit 2363 in synchronization with the horizontal scanning clock (1H). That is, the selector sequentially latches the image data and PC data for one pixel row, and stores the data in the latch circuit 2361b in synchronization with the horizontal scanning clock (1H).

  In FIG. 236, R, G, and B of the latch circuit 2361 are RGB image data 6-bit latch circuits, and P is a latch circuit that latches 3 bits of the precharge signals (RPC, GPC, and BPC). .

  The precharge circuit 2363 turns on the switch 481a and outputs the precharge voltage to the source signal line 18 when the output of the latch circuit 2361b is at the H level. The current output circuit 654 outputs a program current to the source signal line 18 according to the image data.

  If the configurations of FIGS. 235 and 236 are schematically illustrated, the configuration of FIG. 237 is obtained. 237 and 238 show a configuration in which a plurality of source driver ICs (circuits) 14 are stacked on one display panel (cathode connection of source driver ICs) as shown in FIG. Also, CSEL1 and CSEL2 in FIGS. 237 and 238 are select signals for the IC chip. The IC chip is selected by the CSEL signal to determine which image data and PC signal are input.

  In the configurations of FIGS. 236 and 237, a PC signal is generated corresponding to each RGB image data. The precharge is preferably applied for each RGB as described above. However, in moving image display and natural image display, it is often unnecessary to determine whether or not to precharge for each RGB. That is, RGB may be converted (converted) into a luminance signal, and it may be determined whether or not to precharge based on the luminance. This is the configuration of FIG. 238. In the configuration of FIG. 237, the PC signal requires 3 bits (RPC, GPC, BPC), but in the configuration of FIG. 238, the PC signal may be 1 bit of RGBPC. Therefore, in the latch circuit 2361 in FIG. 236, P may be a 1-bit latch. In the following description, the description will be made without considering RGB from the viewpoint of facilitating the explanation and drawing.

  In the configuration of the present invention described above, the controller 81 generates a PC signal (precharge control signal) based on the image data, and the source driver IC 14 latches the PC signal and synchronizes with the 1H synchronization signal in the source signal line 18. It is characterized in that it is applied to. Further, as shown in FIG. 235, the controller 81 can easily change the generation of the precharge signal by a precharge mode (PMODE) signal. For example, PMODE is a mode in which only gradation 0 is precharged, a mode in which a certain gradation range such as gradation 0-7 is precharged, and precharge when image data changes from bright image data to dark image data. Examples include a mode for precharging when low gradation display is continuously performed in a certain frame.

  Note that the present invention is not limited to determining whether or not to precharge one pixel data. For example, the precharge determination may be performed based on the image data of a plurality of pixel rows. In addition, the precharge determination may be performed in consideration of the image data of the surrounding pixels to be precharged (for example, weighting processing). Further, a method of changing the precharge judgment between a moving image and a still image is also exemplified. The above matter is important in that good versatility is exhibited when the controller generates a precharge signal based on image data. Hereinafter, the precharge determination and the precharge mode will be mainly described.

  Note that whether or not to precharge may be determined based on the image data of the previous pixel row (or the image data applied to the source signal line immediately before). For example, if the image data applied to a certain source signal line 18 is white-> black-> black, a precharge voltage is applied when changing from white to black. This is because black gradation is difficult to write. In the case of black to black, no precharge voltage is applied. This is because the potential of the source signal line 18 in the black display first is the black display potential to be written next. The above operation can be realized more easily by forming (arranging) a line memory for one pixel row (requires two lines of memory for FIFO) in the controller 81.

  In the present invention, the precharge drive is described as outputting a precharge voltage, but the present invention is not limited to this. A method of writing a current shorter than one horizontal scanning period and larger than the program current to the source signal line 18 may be used. That is, a method of writing the precharge current to the source signal line 18 and then writing the program current to the source signal line 18 may be used. There is no difference in that the precharge current also physically causes a voltage change. A method of performing precharge with a precharge current is also within the category of precharge driving of the present invention. For example, in FIG. 223, the precharge voltage changes by switching the electronic volume 451. This electronic volume 451 may be changed to a current output electronic volume. The change can be easily realized by combining a plurality of current mirror circuits. In FIGS. 232 and 233, the precharge voltage Vp may be changed to a current output composed of a current mirror circuit. In the present invention, for ease of explanation, it is assumed that precharge driving is performed with a precharge voltage.

  The application of the precharge voltage (current) is not limited to the application of a constant precharge voltage (current). For example, a plurality of precharge voltages may be applied to the source signal line. For example, after applying the first precharge voltage 5 (V) for 5 (μsec), the second precharge voltage 4.5 (V) is applied for 5 (μsec). Thereafter, the program current Iw is applied to the source signal line 18. Alternatively, the precharge voltage may be changed in a sawtooth shape. A rectangular wave may be applied. Further, a precharge voltage (current) may be superimposed on a regular program current (voltage). Further, the magnitude of the precharge voltage (current) and the application period of the precharge voltage (current) may be changed according to the image data. Further, the type of applied waveform, the value of the precharge voltage, and the like may be changed according to the value of the image data.

  Although the present invention is described as applying a precharge voltage (current) in the current drive method, the precharge drive is also effective in the voltage drive method. In the voltage driving method, the size of the driving transistor for driving the EL element 15 is large, so that the gate capacitance is large. Therefore, there is a problem that it is difficult to write a regular program voltage. In response to this problem, by performing precharge before applying the program voltage, the driving transistor can be reset, and good writing can be realized. Therefore, the precharge driving method of the present invention is not limited to current program driving. In the embodiments of the present invention, for ease of explanation, the current program driving pixel configuration (see FIG. 1 and the like) will be described as an example.

  In the embodiment of the present invention, the precharge driving method does not affect only the driving transistor 11a. For example, in the pixel configuration of FIG. 38, the transistor 11a constituting the current mirror circuit is also acted to exert the effect. The precharge drive system of the present invention is intended to charge and discharge the parasitic capacitance of the source signal line 18 as viewed from the source driver IC (circuit) 14, but of course, in the source driver IC (circuit) 14. The purpose is to charge and discharge the parasitic capacitance.

  The precharge voltage (current) is intended to improve black display, but is not limited thereto. If a white write precharge voltage (current) that makes white display easy to write is applied, good white display can be realized. In other words, the precharge driving of the present invention applies pre-charging by applying a predetermined voltage (current) for facilitating writing of the program current (program voltage) before writing the program current (program voltage). It is.

  Although the present invention is described as precharging with black display, this is basically a case where the current is sucked from the driving transistor 11a into the source driver IC (circuit) 14 by a sink current. When the driving transistor 11a or the like is an N-channel transistor, the source driver IC (circuit) 14 is programmed with a discharge current. In this case, a pixel configuration that is white and difficult to write may occur. Therefore, the precharge driving method of the present invention changes the source signal line 18 and the like to a predetermined potential, and precharging with white display or precharging with black display is merely an embodiment. Therefore, it is not limited to these.

  The application timing of the precharge voltage (current) is preferably written while the pixel row to which the program voltage (current) is written is selected. However, the precharge voltage (current) is not limited to this. In a selected state, a precharge voltage (current) may be applied to the source signal line 18 to perform precharge, and then a pixel row in which a program current (voltage) is written may be selected.

  Further, although the precharge voltage is applied to the source signal line 18, other methods are also exemplified. For example, the applied voltage (Vdd) to the anode terminal or the applied voltage (Vss) to the cathode terminal may be changed (a precharge voltage is applied). By changing the anode voltage or the cathode voltage, the writing capability of the driving transistor 11a is expanded. Therefore, the precharge effect is exhibited. In particular, the effect of implementing a method of changing the anode voltage (Vdd) in a pulse manner is high.

  FIG. 239 (a) is an explanatory diagram when only gradation 0 is precharged. Precharge with only gradation 0 is a preferable method because there is no gradation skip and good black display can be realized. In FIG. 239, the row number indicates the pixel row number. In the pixel row, image data is sequentially rewritten from the first pixel row to the n pixel row, and when current programming is performed up to the final pixel row n, current programming is started from the first pixel row.

  The image data is 64-gradation image data. The image data takes a value from 0 to 63. Of course, when the gradation is 256, values from 0 to 255 are taken. PSL is a precharge select signal, which permits the output of the precharge voltage when it is at the H level (symbol H). At the L level, no precharge voltage is output. PEN is a precharge enable signal. This PEN is a signal output by the determination of the controller 81. That is, the controller sets the PEN signal to the H or L level based on the image data. When PEN is at the H level, it is a determination signal for precharging, and when it is at the L level, it is a determination signal for not precharging. In FIG. 239, the PEN signal is at the H level only at gradation 0. The P output is an on / off state of the switch 481a (see FIGS. 232 and 233). In the table, ◯ indicates that the switch 481a is in an on state (a state in which the precharge voltage Vp is applied to the source signal line 18). X indicates that the switch 481a is in an off state (a state in which a precharge voltage is not applied to the source signal line 18).

  In FIG. 239 (a), the PEN signal is H at locations corresponding to pixel row number 3 and pixel row number 8. At the same time, in pixel row number 3 and pixel row number 8, since the PSL signal is also at the H level, the P output is in a state where the precharge voltage Vp is output. In FIG. 239 (b), the PEN signal is The PSL signal is the L level, which is the same as that in Fig. 239 (a), so that the P output does not continue and the state is x (the precharge voltage Vp is not output). A signal is also output from the controller 81. However, the PEN signal is preferably adjustable by the user.

  Further, the period during which the precharge voltage Vp is output can be set by the counter 651 in FIG. This counter is a programmable counter and operates based on a set value from a controller or a set value of a user. The counter 651 is configured to operate in synchronization with the main clock (CLK).

  FIG. 240A is an explanatory diagram when only the gradations 0 to 7 are precharged. The method of precharging only in the low gradation region is effective as a measure for solving the problem that current driving is difficult to write in the black display region. Note that the controller 81 can set which range is precharged.

  In FIG. 240, the PEN signal is at the H level only at the gradation 0-7. The P output is an on / off state of the switch 481a (see FIGS. 232, 233, etc.). In FIG. 240 (a), since the image data is 7 or less at locations corresponding to pixel row numbers 3, 5, 6, 7, 11, 12, and 13, the PEN signal is H. At the same time, since the PSL signal is also at the H level, the P output is ◯ (a state where the precharge voltage Vp is output). In FIG. 240B, since the PSL signal is at the L level, all the P outputs are x (a state where no precharge voltage is applied).

  FIG. 241 is an explanatory diagram of a driving method for performing precharging when the luminance of the pixel 16 is lowered. In the current program method, the program current Iw when the luminance of the pixel 16 is increased (white display) is large. Therefore, even if the source signal line 18 has a parasitic capacitance, the parasitic capacitance can be charged and discharged sufficiently. However, when the pixel 16 is programmed to display black, the program current is small and the parasitic capacitance of the source signal line 18 cannot be sufficiently charged / discharged. Therefore, when the program current written to the pixel 16 becomes large, it is often unnecessary to precharge. Conversely, when the current written to the pixel 16 is small (when black display is performed), it is necessary to precharge.

  FIG. 241 is an explanatory diagram of a driving method for performing precharging when the luminance of the pixel 16 is lowered. The image data of the first pixel row is 39. Therefore, the source signal line 18 holds a potential for current-programming the pixel 16 to the image data 39. The image data of the second pixel row is 12. Therefore, the source signal line 18 needs to have a potential corresponding to the image data 12. However, the program current decreases from gradation 39 to gradation 12. Therefore, a state where the source signal line 18 cannot be sufficiently charged / discharged may occur. In order to cope with this problem, precharging is performed (PEN signal is at H level). Similar determination results are obtained for pixel rows 3, 5, 6, 8, 11, 12, 13, and 15.

  The image data in the third pixel row is zero. Therefore, the source signal line 18 holds a potential for current-programming the pixel 16 to the image data 0. The image data in the fourth pixel row is 21. Therefore, the source signal line 18 needs to have a potential corresponding to the image data 21. The program current increases from gradation 0 to gradation 21. Therefore, the source signal line 18 can be sufficiently charged / discharged. Therefore, it is not necessary to precharge the fourth pixel row.

  The above determination is performed by the controller 81. As a result of the implementation, the PEN signal becomes the H level in the pixel rows 2, 3, 5, 6, 8, 11, 12, 13, and 15 as illustrated in FIG. That is, the pixel row is precharged. In FIG. 241 (a), since the PSL signal is also at the H level, as can be seen from the P output column, the P output is indicated by ○ in the pixel rows 2, 3, 5, 6, 8, 11, 12, 13, and 15. (Precharge). Note that precharge is not performed in other pixel rows.

  In FIG. 241 (b), the PEN signal is the same as that in FIG. 241 (a), but the PSL signal is at the L level. Therefore, the P output is constantly maintained and the state is x (the precharge voltage Vp is not output). Basically, the PEN signal is also output from the controller 81. However, the PEN signal is preferably adjustable by the user.

  FIG. 242 shows a combination of the precharge methods of FIG. 240 and FIG. In this method, precharging is performed when the luminance of the pixel 16 is low, and precharging is performed when the program current of the pixel 16 has low luminance of 0-7 gradation. It can be changed by the set value of the controller IC 81 at which gradation or less the precharge is performed. Also, the user can change it. The change is made to the table inside the controller from the microcomputer via the serial interface.

  The image data is the same as in the embodiment of FIG. However, in FIG. 242, since the image data is 12 in the second pixel row and the image data is 12 in the 15th pixel row, the PEN signal is an L level determination result. As described above, the parasitic capacitance of the source signal line 18 can be charged / discharged if the program current Iw is larger than a certain level. Therefore, there is no need to precharge. Conversely, when precharged, the potential of the source signal line 18 changes to the black display potential, and it takes time to return to the halftone display potential.

  The above determination is performed by the controller 81. As a result of the implementation, the PEN signal becomes H level in the pixel rows 3, 5, 6, 8, 11, 12, and 13 as illustrated in FIG. That is, the pixel row is precharged. In FIG. 242 (a), since the PSL signal is also at the H level, as can be seen from the P output column, the P output is ◯ (precharged) in the pixel rows 3, 5, 6, 8, 11, 12, and 13. ) Note that precharge is not performed in other pixel rows. In FIG. 242 (b), the PEN signal is the same as that in FIG. 242 (a), but the PSL signal is at the L level. Therefore, the P output is constantly maintained and the state is x (the precharge voltage Vp is not output).

  The above embodiment does not describe the precharge of each RGB, but it goes without saying that it is preferable to perform the precharge determination for each RGB as shown in FIG. This is because image data is different for each RGB. In particular, as shown in FIGS. 41, 125, and 126, good results can be obtained when RGB pixels are arranged in the column direction. This is because pixel data of the same color is continuously applied to each source signal line.

  FIG. 243 shows a driving method in which precharging is performed in the range of gradations 0-7 as in FIG. The controller 81 determines the precharge for each RGB. As a result of the implementation, as illustrated in FIG. 243, in the R image data, the PEN signal becomes H level in the pixel rows 3, 5, 6, 7, 8, 11, 12, and 13. That is, the pixel row is precharged. In the G image data, the PEN signal becomes H level in the pixel rows 3, 7, 9, 11, 12, 13, and 14. That is, the pixel row is precharged. In the B image data, the PEN signal becomes H level in the pixel rows 1, 2, 3, 6, 7, 8, 9, and 15. That is, the pixel row is precharged.

  In the above embodiment, it is determined whether or not to precharge corresponding to the pixel row. However, the present invention is not limited to this. It goes without saying that the size or change of image data applied to each pixel in units of frames (fields) may be determined to determine whether or not to precharge. FIG. 244 shows an example thereof.

  FIG. 244 shows changes in image data focusing on a certain pixel 16. The first row of the table in FIG. 244 indicates the frame number. The second row of the table shows changes in image data programmed in a certain pixel 16. FIG. 244 shows a modified example of the driving method in which precharging is performed at gradation 0 as in FIG. In FIG. 239, the precharge is always performed at gradation 0. FIG. 244 shows a method of precharging when gradation 0 continues for a certain frame. Continuation is indicated by a counter.

  In FIG. 244 (a), tone is 0 in frames 3, 4, 5, 6, 11, and 12. Therefore, the count value is sequentially counted from the third frame to the sixth frame. In addition, it is counted in frames 11 and 12. In FIG. 244 (a), control is performed so that precharge is performed when gradation 0 continues for three frames. Accordingly, the P output becomes ◯ (a precharge voltage is output) in frames 5 and 6. In frames 11 and 12, gradation 0 is continuous for only two frames, so precharge is not performed.

  In FIG. 244 (b), the count control is performed by the PSL signal. When the PSL signal is at H level, the count value is increased. In FIG. 244 (b), since the PSL signal is at the L level in the frames 5 and 12, it is not counted up. Therefore, the precharge voltage is output only in the frame 6.

  In FIG. 244, precharge is performed when gradation 0 continues for a certain number of frames. However, the present invention is not limited to this, and as described with reference to FIG. 240, a certain gradation range (for example, gradation 0). It may be controlled to precharge when −7) continues. Moreover, it is not limited to continuous frames, and may be discrete. Further, it may be controlled to precharge when a certain gradation range (for example, only gradation 0, gradation 0-7, etc.) continues in a continuous pixel row.

  As described above, in the precharge driving method of the present invention, it is determined whether or not to precharge based on the value of the image data or the change state of the image data or the image data value near the pixel to be precharged and its change, Apply precharge voltage (current). Information on whether or not to apply precharge is held in a source driver IC (circuit). Therefore, since the source driver IC (circuit) 14 only includes a latch circuit 2361 (holding circuit or storage means (memory)) for latching the precharge signal, the configuration is easy. In addition, any precharge method can be dealt with only by changing the program of the controller IC.

  The above precharge is illustrated in FIGS. 288 to 291. The precharge voltage is preferably configured so as to be freely set with an electronic volume or the like.

  In FIGS. 288 to 292, the upper drawing shows the potential of the source signal line 18 in a state where no precharge is applied. The driving transistor of the pixel 16 is a P channel. The pixel data is displayed as 64 gradations for easy understanding. Therefore, a voltage close to the anode voltage (Vdd) is applied as the precharge voltage (PRV). By applying the precharge voltage (PRV), current is prevented from flowing through the driving transistor. Alternatively, it is difficult for current to flow. That is, the pixel 16 is displayed in black. When the driving transistor is N-channel, a voltage close to the ground (GND) potential or the cathode voltage (Vss) is applied as the precharge voltage so that no current flows through the driving transistor.

  The above is the case where the pixel is displayed in black or close to black by applying a precharge voltage. However, white display may be obtained by applying a precharge voltage. Therefore, the application of the precharge voltage is not limited to the black display voltage. In this method, a voltage is applied to the source signal line 18 so that the source signal line 18 has a constant potential.

  In addition, when the driving transistor 11a of the pixel 16 is a P channel as in FIG. 1, it is important that the switching transistor 11b is also formed of a P channel. This is because black display is facilitated by the punch-through voltage when the switching element 11b changes from the on state to the off state. Therefore, when the driving transistor 11a of the pixel 16 has an N channel, it is important to form the switching transistor 11b also with an N channel. This is because black display is facilitated by the punch-through voltage when the switching element 11b changes from the on state to the off state.

  The lower part illustrates the source signal line potential when a precharge voltage (PRV) is applied to the source signal line 18. The location of the arrow indicates the application position of the precharge voltage (PRV). The application position of the precharge voltage is not limited to the beginning of 1H. A precharge voltage may be applied during a period up to 1 / 2H. When a precharge voltage is applied to the source signal line 18, it is preferable to operate the OEV terminal of the gate driver 12a on the selection side so that none of the gate signal lines 17a is selected.

  FIG. 288 shows the All precharge mode. At the beginning of 1H, a precharge voltage (PRV) is applied to the source signal line. By applying a precharge voltage (PRV) to the source signal line 18, the black display voltage is applied to the source signal line 18 at one end.

  FIG. 289 shows the source signal line potential when the precharge voltage is applied only in the 0 gradation (complete black display) in the selective precharge mode.

  FIG. 290 shows a selective precharge mode. In the case of 8 gradations or less, the source signal line potential when a precharge voltage is applied is shown.

  FIG. 291 shows an adaptive precharge mode. When precharge is performed only for the 0th gradation and the 0th gradation is continuous, after the precharge is performed once, the continuous 0th gradation is not displayed. The precharge is not performed. In the adaptive precharge mode of FIG. 291, when performing selective precharge to 8 gradations or less, if 8 gradations or less continue, after performing the precharge once, to 8th gradation or less. Does not perform precharge.

  FIG. 342 explains the adaptive precharge method. There are many types of adaptive precharge. In the case of determination of 1st 32nd gradation (intermediate value), the most significant bit (MSB) bit of image data (image data is 6 bits in the figure) is used as a determination bit. In the case of determining the set value, the set value data and the image data are compared, and when the image data is larger than the set data, the determination bit is set to 1. In other cases, the determination bit is set to 0.

  Further, as shown in FIG. 2, the current image data (target image data to be precharged) is compared with the selected precharge range, and if within the selected precharge range, the precharge bit is set to 1. If it is out of range, the precharge bit is set to zero.

  Next, as indicated by 3, when both the precharge bit and the decision bit are 1, precharge is performed. In other cases, it is not precharged.

  In the case of the current driving method, the current flowing through the source signal line 18 is small. Therefore, the source signal line 18 may be in a floating state, and the potential may be uncertain. As a countermeasure, a method of applying a precharge voltage to the source signal line 18 and stabilizing the potential of the source signal line 18 is exemplified.

  FIG. 292 is an embodiment in which the precharge voltage is applied to the source signal line 18 and is stabilized. A precharge voltage is applied simultaneously to the source signal line 18 at the end or beginning of one field or one frame. FIG. 293 shows a modification thereof. A precharge voltage is applied to the odd-numbered source signal lines 18 in the first field, and a precharge voltage is applied to the even-numbered source signal lines 18 in the second field.

  As shown in FIG. 341, the precharge voltage is preferably applied 1H or more before the display period. In FIG. 341, precharge is performed before B = 2H (two horizontal scanning periods). This is because if the precharge is performed immediately before the display period, the potential of the source signal line 18 greatly fluctuates due to the precharge, and the luminance of the first pixel row in the image display may be lowered and adversely affected.

  It should be noted that the precharging method or configuration or apparatus of the present invention described with reference to FIGS. 292, 291 or the like is implemented, configured, or configured in FIGS. 67, 223, 232, 233 to 244, 305 to 311, or the like. It goes without saying that it can be applied.

  In FIG. 237 and the like, pixel data R, G, B data and precharge data (PRC, PGC, PBC) are applied in parallel to the source driver circuit 14, but the present invention is not limited to this. When configured to apply in parallel as described above, the number of wires connecting the controller 81 and the source driver IC 14 increases. Therefore, there is a problem that the number of pins of the controller 81 increases and the controller size increases.

As shown in FIG. 253, the present invention is configured by 6 bits of image data (DAT) and 4 bits of control data (DCTL), and the controller is configured to control image data and precharge data with 10 bits. The voltage is applied from 81 to the source driver 14.
Specifically, image transfer is performed serially using a four-times clock of one clock in the conventional case (when RGB data is transferred in parallel). That is, as shown in FIG. 253 (see DAT), R data 6 bits, G data 6 bits, B data 6 bits, and control data 6 bits are transferred in one conventional clock period. Image data and control data are handled as setting data.

  R, G, B, and data identification data (D) are identified by 4 bits of DCTL. As described above, the image data and the control data are serially transferred (four phases), whereby the number of wires connecting the controller 81 and the t source driver 14 is reduced, and the control IC 81 can be downsized.

  FIG. 252 is a table showing data identification (DCTL) and setting data (DAT). In FIG. 252, data identification (DCTL) indicates the type of setting data (DAT), and setting data (DAT) indicates the contents.

  When the upper 3 bits of DCTL are 0, this indicates that the setting data (DCTL) is red (R) image data (corresponding to R [5: 0] in FIG. 253). Six bits of the setting data (DCTL) indicate 64-gradation image data (0 for the 0th gradation and 63 for the 63rd gradation). The least significant bit of DCTL indicates the presence / absence of precharge (PRC terminal in FIG. 237). 1 indicates that precharging is performed, and 0 indicates that precharging is not performed.

  When the upper 3 bits of DCTL are 1, it indicates that the setting data (DCTL) is green (G) image data (G [5: 0] in FIG. 253 corresponds). Six bits of the setting data (DCTL) indicate 64-gradation image data (0 for the 0th gradation and 63 for the 63rd gradation). The least significant bit of DCTL indicates the presence or absence of precharge (PGC terminal in FIG. 237).

Similarly, when the upper 3 bits of DCTL are 2, it indicates that the setting data (DCTL) is blue (B) image data (corresponding to B [5: 0] in FIG. 253). Six bits of the setting data (DCTL) indicate 64-gradation image data (0 for the 0th gradation and 63 for the 63rd gradation). The least significant bit of DCTL indicates the presence or absence of precharge (PBC terminal in FIG. 237).
When DCTL [3: 0] is 8, it indicates that the setting data (DCTL) is red (R) reference current setting data. When DCTL [3: 0] is 9, it indicates that the setting data (DCTL) is green (G) reference current setting data. When DCTL [3: 0] is 10, it indicates that the setting data (DCTL) is blue (B) reference current setting data. The change of the reference current electronic volume has been described with reference to FIGS. 170, 171, 190, etc., and will not be described.

  Similarly, when DCTL [3: 0] is 12, it indicates that the setting data (DCTL) is red (R) precharge voltage setting data. When DCTL [3: 0] is 13, it indicates that the setting data (DCTL) is green (G) precharge voltage setting data. When DCTL [3: 0] is 14, it indicates that the setting data (DCTL) is blue (B) precharge voltage setting data. The change of the precharge voltage electronic volume has been described with reference to FIG.

  FIG. 253 is a system in which image data (DAT) is 6 bits and control data (DCTL) is 4 bits, and image data, precharge data, etc. are applied from 10 to the source driver 14 in 10 bits. Further, in this embodiment, image transfer is performed serially using a 4 × clock. However, the present invention is not limited to this. For example, as shown in FIG. 347, the RGB data as the image data and the control data D may be serially transmitted, and the image data and the control data may be identified by an ID signal. When the ID data is at the H level, it means image data, and when the ID data is at the L level, it means control data.

  Further, as shown in FIG. 348, image data may be transferred in RGB serial, and whether or not each image data is precharged may be determined by a precharge identification signal PRC. In FIG. 348, when the PRC signal is at the H level, the corresponding image data is controlled to be applied to the source signal line 18 after being precharged, and when the PRC signal is at the L level, it is controlled not to be precharged.

  Needless to say, the image data and the control data may be serially transmitted as shown in FIG. Of course, the image data may be serially transmitted and the control data may be transmitted in parallel.

  In FIG. 349 and the like, input data to the source driver IC (circuit) 14 is serially transmitted. The present invention is not limited to this. For example, as illustrated in FIG. 407, a differential signal may be transmitted. Examples of means for making a differential signal include LVDS and RSDS.

  In FIGS. 408 and 409, serial video data or the like is converted into a higher frequency differential signal and transmitted, and the differential signal is returned to the serial video data and input to the source driver circuit (IC) 14. Alternatively, the data is further converted into parallel data and input to the source driver circuit (IC) 14. That is, video data is converted into serial data and differential signals and transmitted. Needless to say, in transmission, some sections, all sections, or some data signals may be transmitted in parallel.

  As shown in FIG. 407, serial data from the video signal processing circuit of the main body circuit (for example, 1601 in FIG. 160) is converted into a differential signal by a transceiver (T) 4071a. By converting to a differential signal, the amplitude of the signal is reduced, it is less susceptible to noise, and unnecessary radiation is also reduced. Therefore, the distance between the transceiver (T) 4071a and the receiver (R) 4071b can be increased. In addition, the number of signal lines can be reduced.

  The differential signal is converted into serial data by the receiver (R) 4071b. Of course, it goes without saying that the function of the controller IC 4081 of FIG. 408 may be taken in and converted into parallel data. The receiver (R) 4071b restores the serial data before differential signal conversion by the transceiver 4071a.

  FIG. 408 shows a configuration example in which a serial-parallel conversion circuit 4081 is arranged or formed at the next stage of the receiver (R) 4071b. This corresponds to a serial-parallel conversion circuit 4081 (specifically, a controller IC (circuit) (control means) composed of an ASIC. Serial data is converted into parallel data by the serial-parallel conversion circuit 4081, and the converted parallel data is the source. It is input to a driver IC (circuit) 14.

  The control data includes, for example, precharge control data such as FIGS. 67 and 223, electronic volume data such as FIGS. 170, 171, 190, 389, and 390, control data of FIG. 252, and FIG. Various control data such as on / off data of the switch 481, on / off data and on / off timing data of the switch 1611 of FIG. 250, switching data of the switches 2561 and 655 of FIG. 251, and pixel thinning control data of FIG.

  FIG. 254 shows the connection increase between the control IC 81 and the source driver circuit 14 and the gate driver circuit 12. Connection wiring can be omitted by serially transferring image data, electronic volume data, and precharge data as DCTL and DAT. Note that by performing serial-parallel conversion at the input stage of the source driver circuit 14, the precharge data and image data latch or holding circuit becomes the same as that shown in FIG. The 4 bits of GCTL are clock, start pulse, up / down switching, and enable signal.

  In FIG. 232, the switch 481a is turned on / off to output the precharge voltage Vp from the terminal 681, and the switch 655 is turned on / off by the PO signal to apply the program current Iw from the terminal 681 to the source signal line 18. However, in the configuration of FIG. 232, when the switch 481a is closed and the precharge voltage Vp is applied to the terminal 681, the precharge voltage Vp is also applied to the current output circuit 654 (unit transistor group 521c). When a precharge voltage is applied to the current output circuit 654, an abnormal operation may occur in the current output circuit 654.

  As shown in FIG. 233, the switch 655 is disposed between the current output circuit 654 and the point A, and the switch 656 is controlled by inverting the logic of the OPV signal by the inverter 62. To do. That is, when the switch 481a is closed, the switch 656 is opened (open). With this configuration, when the precharge voltage Vp is applied to the terminal 681, the switch 655 is open, so that the precharge voltage is not applied to the current output circuit 654. This timing chart is shown in FIG. In FIG. 234 (a), the PO signal is L during the period t in which the OPV signal is H. More preferably, the switch 655 is turned off (open) before and after the period in which the switch 481a is closed. That is, as shown in FIG. 234 (b), the PO signal is set to the L level during the period t2 including before and after the period when the OPV signal is H. This is to prevent the adverse effect of the transient phenomenon due to the on / off of the switch 481a.

  As shown in FIG. 1, when the driving transistor 11a and the selection transistors (11b, 11c) of the pixel 16 are P-channel transistors, a punch-through voltage is generated. This is because the potential fluctuation of the gate signal line 17a penetrates to the terminal of the capacitor 19 through the GS capacitance (parasitic capacitance) of the selection transistors (11b, 11c). When the P-channel transistor 11b is turned off, the voltage becomes Vgh. Therefore, the terminal voltage of the capacitor 19 is slightly shifted to the Vdd side. For this reason, the gate (G) terminal voltage of the transistor 11a rises, resulting in a black display. Therefore, good black display can be realized.

  However, complete black display of the 0th gradation can be realized, but it is difficult to display the 1st gradation. Alternatively, a large gradation jump occurs from the 0th gradation to the first gradation, or blackout occurs in a specific gradation range.

  The configuration for solving this problem is the configuration of FIG. It has a function of raising the output current value. The main purpose of the raising circuit 541 is to compensate the punch-through voltage. Further, even when the image data has a black level of 0, a certain amount of current (several tens of nA) flows, and can be used for black level adjustment.

  Basically, FIG. 54 is obtained by adding a raising circuit (portion surrounded by a dotted line in FIG. 54) to the output stage of FIG. FIG. 54 assumes that the current value raising control signal is 3 bits (K0, K1, K2), and outputs a current value 0 to 7 times the current value of the grandchild current source by this 3-bit control signal. It is possible to add to the current.

  The above is the basic outline of the source driver IC (circuit) 14 of the present invention. Hereinafter, the source driver IC (circuit) 14 of the present invention will be described in more detail.

  There is a linear relationship between the current I (A) flowing through the EL element 15 and the light emission luminance B (nt). That is, the current I (A) flowing through the EL element 15 is proportional to the light emission luminance B (nt). In the current driving method, one step (gradation step) is a current (unit transistor 484 (one unit)).

  Human vision of brightness has a square characteristic. That is, when changing with a square curve, the brightness is recognized as changing linearly. However, in the relationship shown in FIG. 83, the current I (A) flowing through the EL element 15 and the light emission luminance B (nt) are proportional to each other in both the low luminance region and the high luminance region. Therefore, if the step is changed step by step (one gradation), the luminance change for one step is large (black skip occurs) in the low gradation portion (black region). Since the high gradation portion (white region) substantially coincides with the linear region of the square curve, the luminance change for one step is recognized as changing at equal intervals. From the above, in the current driving method (when one step is in increments of current) (in the current driving source driver IC (circuit) 14), the display of the black display region becomes a particular problem.

  To solve this problem, the slope of the current output in the low gradation region (gradation 0 (full black display) to gradation (R1)) is reduced, and the maximum gradation (R) from the high gradation region (gradation (R1)). )) Increase the current output slope. In other words, in the low gradation region, the current amount is increased with a small amount (one step) per gradation. In the high gradation region, the current amount increases with one gradation (one step). By making the amount of current changing per step different between the high gradation region and the low gradation region, the gradation characteristic becomes close to a square curve, and blackout does not occur in the low gradation region.

  In the above embodiment, the current gradient has two steps of the low gradation region and the high gradation region. However, the present invention is not limited to this. Needless to say, there may be three or more stages. However, it is needless to say that the case of two stages is preferable because the circuit configuration is simplified. Preferably, the gamma circuit is preferably configured so as to generate a gradient of five or more steps.

  The technical idea of the present invention is a circuit for performing gradation display by current output in a current-driven source driver IC (circuit), etc. Therefore, the display panel is limited to an active matrix type. (Instead, a simple matrix type is also included.) This means that a plurality of current increase amounts per gradation step exist.

  In a current-driven display panel such as an EL, display luminance changes in proportion to the amount of current applied. Therefore, in the source driver IC (circuit) 14 of the present invention, the luminance of the display panel can be easily adjusted by adjusting the reference current that causes the current to flow through one current source (one unit transistor) 484. .

  In the EL display panel, the luminous efficiency is different between R, G, and B, and the color purity with respect to the NTSC standard is shifted. Therefore, in order to optimize the white balance, it is necessary to appropriately adjust the RGB ratio. Adjustment is performed by adjusting the respective reference currents of RGB. For example, the R reference current is set to 2 μA, the G reference current is set to 1.5 μA, and the B reference current is set to 3.5 μA. As described above, it is preferable that at least one color reference current among at least a plurality of display color reference currents can be changed, adjusted, or controlled.

  In the current driving method, the relationship between the current I flowing through the EL and the luminance has a linear relationship. Therefore, the white balance adjustment by mixing RGB only needs to adjust the RGB reference current at one point of predetermined luminance. That is, if the RGB reference current is adjusted at one point with a predetermined luminance and the white balance is adjusted, the white balance is basically achieved over all gradations. Therefore, the present invention is characterized in that it includes an adjusting unit that can adjust the RGB reference currents, and includes a one-point bent or multi-point bent gamma curve generating circuit (generating unit). The above items are circuit systems peculiar to the current control EL display panel.

  In the gamma circuit of the present invention, as an example, the increase is 10 nA per gradation in the low gradation area (the slope of the gamma curve in the low gradation area). Further, it increases by 50 nA per gradation in the high gradation area (gamma curve inclination in the high gradation area).

  The increase in current per gradation in the high gradation area / the increase in current per gradation in the low gradation area is referred to as a gamma current ratio. In this embodiment, the gamma current ratio is 50 nA / 10 nA = 5. The RGB gamma current ratio is the same. That is, in RGB, the current (= program current) flowing in the EL element 15 is controlled with the gamma current ratio being the same.

  If the gamma current ratio is adjusted to be the same in RGB as described above, the circuit configuration is facilitated. For each color, a constant current circuit for generating a reference current to be applied to the low gradation part and a constant current circuit for generating a reference current to be applied to the high gradation part are manufactured, and a volume for adjusting the current flowing relatively to these is adjusted. This is because it is sufficient to produce (arrange).

  FIG. 56 is a configuration diagram of a constant current generating circuit unit in a low current region. FIG. 57 is a configuration diagram of the constant current circuit portion and the raised current circuit portion in the high current region. As shown in FIG. 56, a reference current INL is applied to the low current source circuit unit, which basically becomes a unit current, and the required number of unit transistors 484 are operated by the input data L0 to L4, and the sum thereof is obtained. The program current IwL of the low current part flows.

  Further, as shown in FIG. 57, the reference current INH is applied to the high current source circuit unit, which basically becomes a unit current, and the necessary number of unit transistors 484 are operated by the input data H0 to L5. As a sum, the program current IwH of the low current portion flows.

The raised current circuit section is the same, and a reference current INH is applied as shown in FIG. 57. This current basically becomes a unit current, and the necessary number of unit transistors 484 are operated by the input data AK0 to AK2. As a sum, the current IwK corresponding to the raised current flows. The program current Iw flowing in the source signal line 18 is Iw = IwH + IwL + IwK. The ratio of IwH and IwL, that is, the gamma current ratio satisfies the first relationship described above.

  As shown in FIGS. 56 and 57, the on / off switch 481 includes an inverter 562, and an analog switch 561 composed of a P-channel transistor and an N-channel transistor. As described above, the switch 481 includes the inverter 562 and the analog switch 561 including the P-channel transistor and the N-channel transistor, so that the on-resistance can be reduced, and the voltage drop between the unit transistor 484 and the source signal line 18 is reduced. It can be made extremely small. Needless to say, this also applies to other embodiments of the present invention.

  The operation of the low current circuit unit in FIG. 56 and the high current circuit unit in FIG. 57 will be described. The source driver IC (circuit) 14 of the present invention is composed of 5 bits of low current circuit portions L0 to L4 and 6 bits of high current circuit portions H0 to H5. Note that data input from the outside of the circuit is 6 bits of D0 to D5 (64 gradations for each color). The 6-bit data is converted into 5 bits L0 to L4 and 6 bits of the high current circuit portions H0 to H5, and a program current Iw corresponding to the image data is applied to the source signal line. That is, the input 6-bit data is converted into 5 + 6 = 11-bit data. Therefore, a highly accurate gamma curve can be formed.

  As described above, the input 6-bit data is converted into 5 + 6 = 11-bit data. In the present invention, the number of bits (H) of the circuit in the high current region is the same as the number of bits of the input data (D), and the number of bits (L) of the circuit in the low current region is the number of bits of the input data (D). -1. Note that the bit number (L) of the circuit in the low current region may be the bit number −2 of the input data (D). With this configuration, the gamma curve in the low current region and the gamma curve in the high current region are optimal for image display on the EL display panel.

  The gate driver circuit 12 is normally composed of an N channel transistor and a P channel transistor. However, it is preferable to form the P channel transistor alone. This is because the number of masks required for manufacturing the array is reduced, and the manufacturing yield and throughput can be improved. Therefore, as illustrated in FIGS. 1 and 2 and the like, the transistor constituting the pixel 16 is a P-channel transistor, and the gate driver circuit 12 is also formed or constituted by a P-channel transistor. If the gate driver circuit is composed of an N-channel transistor and a P-channel transistor, the required number of masks is 10. However, if only a P-channel transistor is formed, the required number of masks is 5.

  However, if the gate driver circuit 12 or the like is composed of only P-channel transistors, a level shifter circuit cannot be formed on the array substrate 71. This is because the level shifter circuit is composed of an N channel transistor and a P channel transistor.

  Hereinafter, the gate driver 12 of the present invention in which the gate driver circuit 12 built in the substrate 71 is composed of only P-channel transistors will be described. As described above, the pixel 16 and the gate driver circuit 12 are formed by only P-channel transistors (that is, all transistors formed on the substrate 71 are P-channel transistors. Conversely, N-channel transistors are formed. This is because the number of masks required for manufacturing the array is reduced, and the manufacturing yield and throughput are expected to be improved. Moreover, since it is possible to work on improving only the performance of the P-channel transistor, it is easy to improve characteristics as a result. For example, the Vt voltage can be reduced (for example, closer to 0 (V)) and the Vt variation can be reduced more easily than the CMOS structure (configuration using P-channel and N-channel transistors).

  In the embodiment of the present invention, the pixel configuration in FIG. 1 will be mainly illustrated and described, but the present invention is not limited to this, and it goes without saying that other pixel configurations may be used. Further, the configuration or arrangement of the gate driver 12 described below is not limited to a self-luminous device such as an organic EL display panel. The present invention can also be used for a liquid crystal display panel, an electromagnetic floating display panel, an FED (field emission display), or the like. For example, in the liquid crystal display panel, the configuration or system of the gate driver circuit 12 of the present invention may be adopted as control of the pixel selection switching element. Further, when the gate driver circuit 12 is used in two phases, one phase may be used for selecting a switching element of the pixel, and the other may be connected to one terminal of the storage capacitor in the pixel. This method is called independent CC drive. Needless to say, the configuration described with reference to FIGS. 71 and 73 can be applied not only to the gate driver circuit 12 but also to the shift register circuit of the source driver circuit 14.

  FIG. 71 is a block diagram of the gate driver circuit 12 of the present invention. For ease of explanation, only four stages are shown, but basically, unit gate output circuits 711 corresponding to the number of gate signal lines 17 are formed or arranged.

  As shown in FIG. 71, in the gate driver circuit 12 (12a, 12b) of the present invention, four clock terminals (SCK0, SCK1, SCK2, SCK3), one start terminal (data signal (SSTA)), shift It is composed of signal terminals of two inverting terminals (DIRA and DIRB, which apply signals of opposite phases) that control the direction upside down. In addition, the power supply terminal includes an L power supply terminal (VBB) and an H power supply terminal (Vd).

  By configuring the pixel 16 with a P-channel transistor, matching with the gate driver circuit 12 formed with the P-channel transistor is improved. P-channel transistors (transistors 11b, 11c, and transistor 11d in the pixel configuration of FIG. 1) are turned on with an L voltage. On the other hand, the L voltage is also the selection voltage in the gate driver circuit 12. As can be seen from the configuration of FIG. 73, the P-channel gate driver has good matching when the L level is selected. This is because the L level cannot be maintained for a long time. On the other hand, the H voltage can be held for a long time.

  By configuring the driving transistor (transistor 11a in FIG. 1) for supplying current to the EL element 15 with a P channel, the cathode of the EL element 15 can be configured as a solid electrode of a metal thin film. In addition, a current can flow through the EL element 15 in the forward direction from the anode potential Vdd. From the above, it is preferable that the transistor of the pixel 16 be a P channel and the transistor of the gate driver 12 be a P channel. From the above, the matter that the transistor (driving transistor, switching transistor) constituting the pixel 16 of the present invention is formed by the P channel and the transistor of the gate driver circuit 12 is constituted by the P channel is not a mere design matter. .

  A level shifter (LS) circuit may be formed directly on the substrate 71. That is, a level shifter (LS) circuit is formed by N-channel and P-channel transistors. A logic signal from a controller (not shown) is boosted by a level shifter circuit formed directly on the substrate 71 so as to conform to the logic level of the gate driver circuit 12 formed of a P-channel transistor. The boosted logic voltage is applied to the gate driver circuit 12.

  Note that the level shifter circuit may be formed of a semiconductor chip and mounted on the substrate 71 by COG. The source driver circuit 14 is formed of a semiconductor chip and is mounted on the substrate 71 by COG. However, the source driver circuit 14 is not limited to being formed of a semiconductor chip, and may be formed directly on the substrate 71 using polysilicon technology.

  When the transistor 11 constituting the pixel 16 is configured by a P channel, the program current flows in the direction from the pixel 16 to the source signal line 18. Therefore, the unit current circuit 484 (see FIGS. 56, 57, etc.) of the source driver circuit needs to be composed of N-channel transistors. In other words, the source driver circuit 14 needs to be configured to draw the program current Iw.

  Therefore, when the driving transistor 11a of the pixel 16 (in the case of FIG. 1) is a P-channel transistor, the unit transistor 484 is configured with an N-channel transistor so that the source driver circuit 14 always draws the program current Iw. In order to form the source driver circuit 14 on the array substrate 71, it is necessary to use both an N channel mask (process) and a P channel mask (process). Describing conceptually, the display panel (display device) of the present invention comprises the pixel 16 and the gate driver 12 as P-channel transistors, and the source driver's pull-in current source transistor as an N-channel.

  Therefore, the transistor 11 of the pixel 16 is formed by a P-channel transistor, and the gate driver circuit 12 is formed by a P-channel transistor. Thus, by forming both the transistor 11 and the gate driver circuit 12 of the pixel 16 with P-channel transistors, the cost of the substrate 71 can be reduced. However, the source driver 14 needs to form the unit transistor 484 as an N-channel transistor. Therefore, the source driver circuit 14 cannot be formed directly on the substrate 71. Therefore, the source driver circuit 14 is manufactured separately using a silicon chip or the like and mounted on the substrate 71. Although the source driver circuit 14 is formed of a silicon chip, the present invention is not limited to this. For example, a large number of glass substrates may be simultaneously formed by low-temperature polysilicon technology, cut into chips, and loaded on the substrate 71. Although the description has been made assuming that the source driver circuit is loaded on the substrate 71, the present invention is not limited to loading. Any form may be used as long as the output terminal 681 of the source driver circuit 14 is connected to the source signal line 18 of the substrate 71. For example, a method of connecting the source driver circuit 14 to the source signal line 18 by TAB technology is exemplified. By separately forming the source driver circuit 14 on a silicon chip or the like, variation in output current can be reduced and a good image display can be realized. Moreover, cost reduction is possible.

  Further, the configuration in which the selection transistor of the pixel 16 is configured by a P channel and the gate driver circuit is configured by a P channel transistor is not limited to a self-luminous device (display panel or display device) such as an organic EL. For example, the present invention can be applied to a liquid crystal display device and FED (field emission display).

  A common signal is applied to each unit gate output circuit 711 at the inverting terminals (DIRA, DIRB). Incidentally, as can be understood from the equivalent circuit diagram of FIG. 73, voltage values having opposite polarities are input to the inverting terminals (DIRA and DIRB). When the scanning direction of the shift register is reversed, the polarity of the voltage applied to the inverting terminals (DIRA, DIRB) is reversed.

  In the circuit configuration of FIG. 71, the number of clock signal lines is four. Four is the optimum number in the present invention, but the present invention is not limited to this. Four or less may be sufficient.

  Inputs of clock signals (SCK 0, SCK 1, SCK 2, SCK 3) are different in adjacent unit gate output circuits 711. For example, in the unit gate output circuit 711a, the clock terminal SCK0 is input to OC and SCK2 is input to RST. The same applies to the unit gate output circuit 711c. In a unit gate output circuit 711b (next unit gate output circuit) adjacent to the unit gate output circuit 711a, the clock terminal SCK1 is input to OC and SCK3 is input to RST. Therefore, as for the clock terminal input to the unit gate output circuit 711, SCK0 is input to OC, SCK2 is input to RST, the next stage is SCK1 of the clock terminal is input to OC, SCK3 is input to RST, and further to the next stage. The clock terminals input to the unit gate output circuit 711 are alternately changed such that SCK0 is input to OC and SCK2 is input to RST.

  FIG. 73 shows a circuit configuration of the unit gate output circuit 711. The transistors to be configured are composed of only the P channel. FIG. 74 is a timing chart for explaining the circuit configuration of FIG. 72 shows a timing chart for a plurality of stages in FIG. Therefore, the overall operation can be understood by understanding FIG. The understanding of the operation is achieved by understanding the timing chart of FIG. 74 with reference to the equivalent circuit diagram of FIG. 73 rather than the description of the text. Therefore, detailed description of the operation of each transistor is omitted.

  If a driver circuit configuration is created using only the P channel, it is basically possible to maintain the gate signal line 17 at the H level (Vd voltage in FIG. 73). However, it is difficult to maintain the L level (VBB voltage in FIG. 73) for a long time. However, it can be sufficiently maintained for a short period of time, such as when a pixel row is selected.

  When the switching transistors 11b and 11c of the pixel 16 are formed of P-channel transistors, the pixel 16 is selected by Vgh. The pixel 16 is in a non-selected state by Vgl. As described before, the voltage penetrates when the gate signal line 17a changes from on (Vgl) to off (Vgh) (penetration voltage). When the driving transistor 11a of the pixel 16 is formed of a P-channel transistor, the current does not flow through the transistor 11a due to the punch-through voltage in the black display state. Therefore, good black display can be realized. It is difficult to realize black display, which is a problem of the current driving method. However, by configuring the gate driver circuit 12 with a P-channel transistor, the ON voltage becomes Vgh. Therefore, matching with the pixel 16 formed by the P channel transistor is good. Further, as in the pixel 16 configuration of FIGS. 1, 2, 32, 113, and 116, the unit transistor 484 of the source driver circuit 14 is programmed from the anode voltage Vdd through the driving transistor 11a and the source signal line 18. It is important to configure the current Iw to flow. Therefore, it is excellent synergistic effect that the gate driver circuit 12 and the pixel 16 are composed of P channel transistors, the source driver circuit 14 is mounted on the substrate, and the unit transistors 484 of the source driver circuit 14 are composed of N channel transistors. To demonstrate.

  The same applies to FIG. 42B. In FIG. 42B, current does not flow into the unit transistor 484 of the source driver circuit 14 via the driving transistor 11b. However, the configuration is such that the program current Iw flows from the anode voltage Vdd into the unit transistor 484 of the source driver circuit 14 via the programming transistor 11 a and the source signal line 18. Therefore, as in FIG. 1, the gate driver circuit 12 and the pixel 16 are configured by P-channel transistors, the source driver circuit 14 is mounted on the substrate, and the unit transistors 484 of the source driver circuit 14 are configured by N-channel transistors. Exerts an excellent synergistic effect.

  N1 changes depending on the signal input to the IN terminal and the SCK clock input to the RST terminal, and n2 becomes an inverted signal state of n1. Although the potential of n2 and the potential of n4 have the same polarity, the potential level of n4 is further lowered by the SCK clock input to the OC terminal. Corresponding to this lowering level, the Q terminal is maintained at the L level during that period (ON voltage is output from the gate signal line 17). The signal output to the SQ or Q terminal is transferred to the unit gate output circuit 711 in the next stage.

  In the circuit configurations of FIGS. 71 and 73, the gate signal line 17 is selected as shown in FIG. 75A by controlling the timing of the applied signals at the IN (INA, INB) terminal and the clock terminal. The state and the state of selecting the two-gate signal line 17 as shown in FIG. 75B can be realized using the same circuit configuration.

  In the selection-side gate driver circuit 12a, the state shown in FIG. 75A is a driving method in which one pixel row (51a) is simultaneously selected (normal driving). The selected pixel row is shifted one row at a time. FIG. 75B shows a configuration for selecting two pixel rows. This driving method is the simultaneous selection driving (a method of forming a dummy pixel row) of a plurality of pixel rows (51a, 51b) described with reference to FIGS. The selected pixel row is shifted by one pixel row, and two adjacent pixel rows are selected simultaneously. In particular, in the driving method of FIG. 75B, the pixel row 51b is precharged with respect to the pixel row (51a) holding the final video. Therefore, the pixel 16 can be easily written. In other words, the present invention can be realized by switching between the two driving methods by a signal applied to the terminal.

  75 (b) shows a method of selecting 16 adjacent pixel rows, but as shown in FIG. 76, 16 adjacent pixel rows may be selected (FIG. 76 shows 3 pixel rows). This is an embodiment in which pixel rows at distant positions are selected). Further, in the configuration of FIG. 73, control is performed with a set of four pixel rows. Of the four pixel rows, it is possible to control whether one pixel row is selected or two consecutive pixel rows are selected. This is a restriction that four clocks (SCK) are used. If eight clocks (SCK) are used, control can be performed with a set of eight pixel rows.

  The operation of the gate driver 12a on the selection side is the operation of FIG. As shown in FIG. 75A, one pixel row is selected, and the selected position is shifted one pixel row at a time in synchronization with one horizontal synchronization signal. Further, as shown in FIG. 75B, two pixel rows are selected, and the selected position is shifted by one pixel row in synchronization with one horizontal synchronization signal.

  The screen may be divided. The two divisions include a configuration in which the screen is vertically divided at the center of the screen and a configuration in which the pixel rows are divided for each pixel as illustrated in FIG. In FIG. 255, the source signal line 18a is connected to the source driver IC 14a. The source signal line 18a is connected to pixels in even pixel rows. A source signal line 18b is connected to the source driver IC 14b. The source signal line 18b is connected to pixels in odd pixel rows. In the above embodiment, the source driver IC 14 driven for each pixel row is made different. However, the present invention is not limited to this, and the source driver IC 14 driven for every two pixel rows or more may be made different. good. Needless to say, the source driver IC (circuit) 14 and the pixel 16 may be connected in a staggered manner.

  In the embodiment of FIG. 255, the method uses two source driver ICs 14. FIG. 272 shows a configuration using one source driver IC (circuit) 14. The pixels in the pixel column of the display panel are alternately connected to different source signal lines 18 (18a, 18b). For ease of explanation, it is assumed that the pixels in the pixel column are alternately connected to different source signal lines 18, but the present invention is not limited to this, and is arranged in a staggered arrangement as in FIG. Needless to say, they may be connected or alternately connected every two pixels.

  In FIG. 272, the odd-numbered output terminals of the source driver IC 14 may be programmed currents in the even-numbered pixel rows (of course, as a technical category, the program voltage may be used. The above matters are shown in FIG. 255). The even-numbered output terminal outputs a program current (or a program voltage) to an odd-numbered pixel row. Therefore, the adjacent output terminals of the source driver IC 14 perform current programming (or voltage programming, of course) on the pixels in one pixel column, and the adjacent source signal lines 18 have alternately different pixels (odd number and even number). ) Pixels are driven.

  In the source driver IC (circuit) 14 of the present invention, the program current is generated by the unit transistors 484 of the unit transistor group 521c. The variation in output current between adjacent unit transistor groups 521c is small. Therefore, as shown in FIG. 272, uniform image display can be realized by driving one pixel column using adjacent output terminals. Also, since two pixel rows can be selected simultaneously, the program current application period applied to one pixel can be doubled compared to the conventional configuration. Therefore, it is possible to sufficiently write the program current even in the low gradation display with a minute current output. The above effects are the same in the embodiment of FIG.

  In the embodiment of FIG. 272, one pixel column is driven using two adjacent output terminals, but the present invention is not limited to this. For example, one pixel column may be driven using four adjacent output terminals. In this case, the first terminal drives the 4nth pixel (n is an integer of 1 or more). The second terminal drives the 4n + 1 (n is an integer equal to or greater than 1) pixel, and the third terminal drives the 4n + 2 (n is an integer equal to or greater than 1) pixel. The fourth terminal drives the 4n + 3 (n is an integer of 1 or more) pixel. In the embodiment of FIG. 272, it is needless to say that the source driver circuit (IC) 14 is not limited to one source driver circuit (IC) 14, and a plurality of source driver circuits (IC) 14 may be used.

  In the embodiment of FIG. 255, the pixel to be selected is divided into left and right. However, the present invention is not limited to this. As shown in FIG. 270, two source signal lines 18 (18a, 18b) are arranged between the pixel columns, and a program current (voltage) is applied to each pixel 16. May be supplied. The source signal line 18a is connected to a source driver circuit (IC) 14a disposed on the upper side of the panel, and the source signal line 18b is connected to a source driver circuit (IC) 14b disposed on the lower side of the panel.

  In the configuration of FIG. 270, when two pixel rows are simultaneously selected (see FIG. 24), the source driver circuit (IC) 14 may be one. That is, one of the source driver circuits 14a or 14b may be used. This embodiment is illustrated in FIG. In FIG. 271, only the source driver circuit (IC) 14a is formed, stacked, mounted, or connected.

  In FIG. 271, source signal lines 18 a and 18 b are connected by a short wiring 2711. Alternatively, the short wiring 2711 is formed simultaneously with the formation of the array. When the short wiring 2711 is formed simultaneously with the formation of the array, the short wiring 2711 needs to be cut using a laser or the like when a plurality of source driver circuits (IC) 14 are used as shown in FIG.

  There is a problem with the gate driver formed of the P-channel TFT shown in FIGS. That is, the potential output to the gate signal line 17 cannot be maintained at the L level. Another problem is that the potentials of adjacent gate signal lines cannot be continuously maintained at the L level (accurately, but can be maintained continuously, but since a through current flows, power consumption is large and impractical). That is, in FIG. 71, the gate signal lines 17b1 and 17b3 can be simultaneously set to the L level, but the gate signal lines 17b1 and 17b2 cannot be maintained (turned on) at the same time. This operation is not a problem when used as the gate driver 12a (pixel selection side). However, when it is used as the gate driver 12b (EL selection side), it becomes a problem. This is because a duty ratio of ½ (see FIG. 93 or the like) or higher cannot be realized.

  This problem can be solved by configuring as shown in FIG. In FIG. 267, two EL selection side gate drivers 12b are formed (arranged or configured). The gate driver 12b1 controls on / off of the odd-numbered gate signal line 17b. The gate driver 12b2 controls on / off of the even-numbered gate signal line 17b. If the start pulses (ST) of the gate drivers 12b1 and 12b2 are applied simultaneously, the ON voltage (L level) can be applied simultaneously to the odd-numbered gate signal lines 17b and the even-numbered gate signal lines 17b. Therefore, it is possible to simultaneously select the continuous gate signal lines 17b and apply the ON voltage.

  In FIG. 267, a plurality of gate driver circuits 12b on the EL side selection side are configured. However, the present invention is not limited to this. A plurality of gate driver circuits 12a on the pixel selection side may be configured. The two-pixel row simultaneous selection drive of FIG. 75 (b) can be realized. This configuration is illustrated in FIG. The gate driver circuit on the pixel selection side includes 12a and 12b.

  As a feature of current drive, a program current can be added only by short-circuiting a plurality of output terminals. For example, when the first terminal outputs 10 μA and the second terminal outputs 20 μA, the output obtained by short-circuiting the first terminal and the second terminal is 10 + 20 = 30 μA. In voltage driving, a plurality of output terminals cannot be short-circuited. For example, when the first terminal outputs 1V and the second terminal outputs 2V, the output in which the first terminal and the second terminal are short-circuited is short-circuited and destroyed. It is.

  As described above, in the case of current driving (current control method), no problem occurs even if the output terminal is short-circuited. By applying this characteristic effect, the number of gradations can be easily increased. FIG. 256 shows an example. Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 256 is a block diagram of the source driver IC of the present invention. In FIG. 256, reference numeral 521c denotes a transistor group. 1 in the transistor group 521c indicates that one unit transistor 484 is formed. Further, 1 outputs a program current for one gradation, and the least significant bit corresponds. 2 shown in the transistor group 521c indicates that two unit transistors 484 are formed. Also, a program current for two gradations is output, and the second bit corresponds. Similarly, 4 indicates that four unit transistors 484 are formed. Also, a program current for 4 gradations is output, and the third bit corresponds. Similarly, 8 indicates that eight unit transistors 484 are formed. A program current for 8 gradations is output, and the fifth bit corresponds. 16 indicates that 16 unit transistors 484 are formed. Reference numeral 16 outputs a program current corresponding to the gradation, and the fifth bit corresponds. Similarly, 32 indicates that 32 unit transistors 484 are formed. In addition, 32 outputs a program current corresponding to the gradation, and the sixth bit corresponds. Therefore, the transistor group 521c can output 64 levels of program current.

  In the current driver IC of the present invention, one transistor group 521c is formed (configured) for each output terminal 681. As a feature of current drive, a program current can be added only by short-circuiting a plurality of output terminals. Therefore, it is easy to increase the number of gradations by combining outputs from a plurality of output terminals. For example, if one output has 64 gradations, 64 + 64-1 = 127 gradations can be realized by combining the two outputs. Note that −1 is because there is a 0th gradation. For ease of explanation, it is assumed that the source driver IC of the present invention basically has 128 outputs with 64 gradations.

  Therefore, the 128-output 64-gradation driver IC 14 can be used as a 64-output 127-gradation driver IC. FIG. 256 shows an example. A switch (SW) 2561 is arranged between the two outputs. When the driver IC 14 is used for 64 gradations, the switch 2561 is used in an open state. When used for 127 gradations, the switch 2561 is used in a closed state. The switch is an analog switch. Further, the switch 2561 is configured to be controlled to open and close by a logic signal at the control terminal of the IC 14.

In FIG. 256, if the switches 655a and 655b are used in the closed state, it can be used as a 64-gradation driver with 128 outputs. Switch 2561 is closed. If the switch 655a is closed and the switch 655b is opened, a program current of 127 gradations can be output from the terminal 681a. Therefore, a program current can be applied to the pixel 16 (not shown) connected to the source signal line 18a. At this time, a program current cannot be applied to the source signal line 18b. However, if the switch 655a and the switch 655b are alternately controlled to be closed and opened, the program current can be alternately output to the adjacent output terminals 681a and 681b. While switching alternately, the scanning of the gate signal line 17 is synchronized. Therefore, a program current can be applied to the source signal lines 18a and 18b. Bit input. Therefore,
When it is not necessary to switch the source signal lines 18a and 18b (when used as a 127-level source driver IC from the beginning), it is used as shown in FIG. At this time, the switch 655 is unnecessary.

  Each transistor group 521c has a 6-bit input. Therefore, 6 bits are input to the transistor group 521c1 according to the number of gradations until the 64th or 63rd gradation, and all 6 bits input to the transistor 521c2 are set to 0. From the 64th gradation or the 65th gradation, 6 bits are input to the transistor group 521c1 in accordance with the number of gradations, and all 6 bits input to the transistor 521c2 are set to 1 (add program current for 63 gradations). ). The transistor group 521c2 operates 63 unit transistors 484 at once.

  In FIG. 256, current output of 127 gradations is performed by combining two current output stages (521c, etc.). However, 128 gradations are insufficient for one gradation. This is because there are only 63 unit transistors 484 constituting the transistor group 521c. Therefore, even if the two transistor groups 521c are combined, the number of unit transistors 484 is 126. Therefore, at gradation 0, even if the number of operations of the unit transistor 484 is 0, only 127 gradations can be expressed.

  FIG. 257 shows a configuration for solving this problem. One unit of selection unit transistor 2571 is added (formed or arranged) to the transistor group 521c2. In the case of using 128 gradations (when using 64 gradations or more), the selection unit transistor 2571 is operated. The transistor group 521c2 is composed of 64 unit transistors 484. The transistor group 521c2 operates 64 unit transistors 484 at once. In the case of 128 gradations or less (less than), all the unit transistors 484 of the transistor group 521c2 are inactive, and in the case of 128 gradations or more, the unit transistors 484 of the transistor group 521c2 are operated. Therefore, the transistor group 521c2 may be one having 64 unit transistors 484 from the beginning. The unit transistor 484 of the transistor group 521c1 is changed corresponding to the bit according to the number of gradations.

  The source driver circuit (IC) 14 configures a standard transistor group 521 including 63 unit transistors 484 expressing 64 gradations or 63 unit transistors 484 and one selection unit transistor 2571 as a standard cell. deep. By laying out a plurality of standard cells, a source driver circuit (IC) having an arbitrary gradation can be easily formed (configured). Needless to say, the standard cell is not limited to 63 unit transistors 484 but may be composed of 127 and 255 unit transistors 484.

  The above embodiment is a case of 64 gradations and 128 gradations. The present invention is not limited to this. For example, in the case of 256 gradations, it may be configured as shown in FIG. A switch (SW) 2561 is arranged between the two outputs. When the driver IC 14 is used for 64 gradations, the switch 2561 is used in an open state. When 256 gradations are used, the switch 2561 is used in a closed state. The switch 2561 is configured to be controlled to open and close by a logic signal at the control terminal of the IC 14.

  In the above embodiments, 14 is a source driver IC. However, the present invention is not limited to this. For example, 14 may be a source driver circuit formed by low-temperature polysilicon technology, CGS technology, or the like. That is, the source driver circuit 14 formed directly on the substrate 71 may be used. The above matters are the same for the following embodiments.

  256 to 259 are configurations in which one source driver IC (circuit) 14 is connected to each source signal line 18. However, the present invention is not limited to this. For example, as shown in FIG. 260, the source driver IC (circuit) 14 of the present invention may be connected to both ends of one source signal line.

  Each source signal line 18 is connected to a source driver IC 14a at one end and connected to the source driver IC 14b at the other end. The transistor group 521c1 of the source driver IC 14a includes 63 unit transistors 484. The transistor group 521c2 of the source driver IC 14b includes 63 unit transistors 484 and one selection unit transistor 2571.

  The transistor group 521c2 may be composed of 64 unit transistors 484. The transistor group 521c2 has only two modes in which all 64 unit transistors 484 operate or are not operated. Therefore, the transistor may be 64 times as large as the unit transistor 484.

  With the above configuration, in the transistor group 521c1, the corresponding unit transistors 484 operate according to input data up to 64 gradations, and the transistors 521c2 operate collectively at 64 gradations or more.

  That is, in the configuration of FIG. 260, the source driver IC 14a capable of expressing 64 gradations is connected to one end of the source signal line 18, and the other number of unit transistors 484 constituting the transistor group 521c1 of the source driver IC 14a is connected to the other end of the source signal line. A transistor group 521c2 composed of +1 unit transistors 484 is connected. The source driver IC 14b may be composed of 64 times as many transistors as the unit transistor 484.

  That is, 128 gradations can be easily realized by using the source driver IC 14a having 63 unit transistors 484 and the source driver IC 14b having 64 unit transistors 484. When two source driver ICs 14a each including 63 unit transistors 484 are used, 127 gradations can be expressed. For image display, there is no practical difference between 127 gradations and 128 gradations. Therefore, two source driver ICs 14a each including 63 unit transistors 484 may be used.

  In the case of 64 gradations or less (less than), all the unit transistors 484 of the transistor group 521c2 are inactive, and in the case of 64 gradations or more, the unit transistors 484 of the transistor group 521c2 are operated. Therefore, the transistor group 521c2 may be one having 64 unit transistors 484 from the beginning. The unit transistor 484 of the transistor group 521c1 is changed corresponding to the bit according to the number of gradations. Therefore, multi-gradation display can be realized by using a plurality of 64-gradation source driver ICs 14.

  In the case of 128 gradations or more, 64 unit transistors 484 of the transistor group 521c of the source driver IC 14 may be configured. With the configuration in FIG. 260, multi-gradation display can be easily realized using the source driver IC (circuit) 14 having a small number of gradations. This is an application of the characteristic effect of the current drive system that the output current can be added by simply short-circuiting a plurality of output terminals.

  The embodiment of FIG. 260 is an embodiment in which the output terminals of two source driver circuits (IC) 14 are connected to one source signal line 18. However, the present invention is not limited to this. It goes without saying that the output terminals of three or more source driver circuits (IC) 14 may be connected to one source signal line 18. It goes without saying that the technical idea of the switch 2561 in FIG. 256 may be introduced into the configuration in FIG. 260.

  FIG. 268 is a configuration diagram of an EL display panel. Built-in gate driver circuits 12 a and 12 b are formed (arranged) on the left and right of the display screen 50. Source driver circuits 14a and 14b are stacked. The source driver circuit 14 is a driver IC made of a silicon chip, and is COG mounted on the array substrate 71. Further, the source driver circuit 14 is illustrated by a dotted line.

  The cathode wiring 2682 is disposed (formed) at a position located on the back surface of the source driver IC 14 and on the surface of the array. The source driver circuit (IC) 14 is formed (manufactured) by a semiconductor chip and mounted on the array substrate 71 by COG (chip on glass) technology. The reason why the cathode wiring 2682 can be disposed (formed) under the source driver IC 14 is that there is a space of 10 μm to 30 μm in the substrate on the back surface of the source driver circuit (IC) 14. This space is generated by the thickness of the COG terminal.

  In FIG. 268, the cathode wiring 2682 is described as being formed (configured or arranged) under the source driver IC 14, but the present invention is not limited to this. For example, the anode wiring 2681 may be replaced.

  As shown in FIG. 268, cathode wirings 2682a and 2682b are formed at both ends of the panel. Further, the cathode wirings 2682a and 2682b are short-circuited by the cathode wiring 2682d. A cathode wiring 2682 c is branched from the cathode wiring 2682 d and connected to the cathode electrode 106. Therefore, the cathode electrode 106 is electrically connected by the cathode wirings 2682a, 2682b, and 2682c. As described above, by using the space under the IC 14 and disposing the cathode wiring 2682 and the like, it can be connected to the cathode electrode 106 and the like at many places, the potential gradient of the cathode electrode 106 does not occur, and the image display is uniform. Can be realized.

  In FIGS. 268 and 269, reference numeral 2684 denotes a cascade wiring. The cascade wiring 2684 connects the terminal 2683a of the source driver IC 14a and the terminal 2683b of the source driver IC 14b. The cascade wiring 2684 has a function of passing a reference current or a similar current in order to cascade-connect two ICs. That is, the reference current inside the source driver IC 14a is transferred to the source driver IC 14b through the cascade wiring 2683, and the source driver IC 14b uses the reference current as its own reference current, so that the output current difference between the two ICs 14a and 14b is Disappear.

  In FIG. 268, if the cascade wiring 2683 is not provided, the cathode wiring 2682 can be disposed between the two source driver ICs 14a and 14b. However, in reality, the cascade wiring 2683 is necessary. In the present invention, the cathode wiring 2682 is formed under the IC 14 so that it can be connected to the central portion of the cathode electrode 106.

  In FIG. 268, the anode wiring 2681 is arranged outside the cathode wiring 2682. The anode wirings 2681a and 2681b are short-circuited by the anode wiring 2681c. An anode voltage Vdd (see FIG. 1 and the like) is supplied from the anode wiring 2681c to each pixel.

  The configuration of FIG. 268 is a configuration in which the cathode wiring 2682 is formed under the source driver IC 14. The present invention is not limited to this. For example, you may comprise as FIG.

  In FIG. 269, a cathode wiring 2682d is arranged under the source driver IC 14a. In addition, the anode wiring 2681d is arranged in the source driver IC 14b, and the anode wiring 2681d and the anode wiring 2681c are connected by the anode wiring 2681e.

  As described above, by forming the wiring under the source driver IC 14, the cathode potential and the anode potential can be stabilized.

  In FIG. 268 and FIG. 269, the anode or cathode wiring is formed or arranged under the IC 14. The present invention is not limited to this. For example, the configuration of FIG. 380 is illustrated. FIG. 380 shows a configuration in which a cathode wiring 2682 and an anode wiring 2681 are formed or arranged under the IC 14. A plurality of anode wirings 2681 and cathode wirings 2682 (two in FIG. 380) are arranged between the ICs 14a and 14b. At least one cathode wiring 2682 is connected to the central and end cathode films of the screen 50. Among them, one cathode wiring 2682 is arranged under the IC 14a. At least one anode wiring 2681 among the plurality of anode wirings 2681 is connected to the center portion and the end portion of the screen 50. Among them, one anode wiring 2681 is disposed under the IC 14b. Further, the plurality of anode wirings 2681 are short-circuited in the vicinity of the screen 50.

  In particular, FIG. 380 is characterized in that a plurality of power supply wirings (anode wiring, cathode wiring, etc.) are arranged or formed on the array substrate 71 located under the IC chip 14. Also, the wiring disposed below the IC chip 1 is used, and the cathode electrode (see 106 in FIGS. 10 and 11) and the cathode wiring 2682 are contacted (connected) at a plurality of locations. In addition, a feeding point is provided at both ends of an anode wiring 2681 (arranged or formed on the upper side of the screen 50) that branches the anode wiring (see Vdd in FIG. 1 and the like) of the pixel 16. By having the feeding point on both sides, even if the current flowing into Vdd of the pixel 16 increases, the occurrence of a voltage drop is small.

  If the wiring resistance of the anode wiring 2681 and the cathode wiring 2682 is high, a voltage drop occurs, and a sufficient voltage is not applied to the EL element 15 and the driving transistor 11a. A method for solving this problem is the embodiment of FIG. In FIG. 385, a metal thin film 3851 made of a metal material of the kassort electrode 106 is laminated on the thin film wirings of the cathode wiring 2682 and the anode wiring 2681. Low wiring resistance can be realized by laminating metal materials. The metal thin film 3851 of the cathode electrode 106 is manufactured in a process of laminating the cathode electrode 106 on the EL element 15. This can be easily realized by processing a mask at the time of mask vapor deposition, which is a process of patterning the EL element 15. In the processing, the metal thin film 3851 is formed through the holes by drilling a mask at a location where the metal thin film 3851 is to be formed.

  In FIG. 385, the metal material of the kassort electrode 106 is laminated on the thin film wirings of the cathode wiring 2682 and the anode wiring 2681. However, the present invention is not limited to this, and the anode electrode material may be laminated. Needless to say. Further, the metal material is laminated on the thin film wirings of both the cathode wiring 2682 and the anode wiring 2681. However, the present invention is not limited to this, and it may be laminated on one wiring. In particular, since the anode wiring 2681 is greatly affected by a voltage drop, it is preferable to realize a low resistance value by stacking.

  Note that the material to be laminated is not limited to a metal material, and any material can be used as long as a low resistance value can be realized. For example, ITO, carbon, etc. are illustrated. Further, the lamination is not limited to a single layer, and may be a laminated structure of a plurality of films. Moreover, an alloy etc. may be sufficient. For example, ITO, which is a pixel electrode, and Li, Al, or the like may be stacked.

  In order to arrange the cascade wiring 2683 well, a source driver IC may be configured as shown in FIG. In FIG. 338, a reference current source is disposed or formed at one end of the source driver IC, and a cascade current source is disposed at the other end.

  Note that the cascade wiring 2684 is not limited to being formed on the array substrate 71. For example, as shown in FIG. 339, a cascade wiring pattern 2684 may be formed using a flexible substrate 84 or a printed substrate, and cascade connection may be performed via the flexible substrate 84 or the like. Further, when the source driver IC 14 is COF-mounted, as shown in FIG. 340, a cascade wiring 2684 may be formed on the film for COF, and the source driver ICs 14 may be cascade-connected.

  Hereinafter, a high-quality display method using a current driving method (current programming method) will be described with reference to the drawings. In the current programming method, a current signal is applied to the pixel 16 to cause the pixel 16 to hold the current signal. Then, a current held in the EL element 15 is applied.

  The EL element 15 emits light in proportion to the magnitude of the applied current. That is, the light emission luminance of the EL element 15 has a linear relationship with the value of the current to be programmed. On the other hand, in the voltage programming method, the applied voltage is converted into current by the pixel 16. This voltage-current conversion is non-linear. Non-linear conversion complicates the control method.

  In the current driving method, the value of video data is linearly converted into a program current as it is. As a simple example, in the case of 64 gradation display, 0 of the video data is set to the program current Iw = 0 μA, and the video data 63 is set to the program current Iw = 6.3 μA (having a proportional relationship). Similarly, the video data 32 has a program current Iw = 3.2 μA, and the video data 10 has a program current Iw = 1.0 μA. That is, the video data is directly converted into the program current Iw in a proportional relationship.

  In order to facilitate understanding, description will be made assuming that the video data and the program current are converted in a proportional relationship. Actually, video data and program current can be converted more easily. This is because the unit current of the unit transistor 484 corresponds to 1 of video data as shown in FIG. Furthermore, the unit current can be easily adjusted to an arbitrary value by adjusting the reference current circuit. This is because the reference current is provided for each of the R, G, and B circuits, and white balance can be achieved over the entire gradation range by adjusting the reference current circuit to the RGB circuit. This is a synergistic effect of the current program method and the configuration of the source driver circuit 14 and the display panel of the present invention.

  The EL display panel is characterized in that the program current and the light emission luminance of the EL element 15 have a linear relationship. This is a major feature of the current programming method. That is, the emission luminance of the EL element 15 can be adjusted linearly by controlling the magnitude of the program current.

  In the driving transistor 11a, the voltage applied to the gate terminal and the current flowing through the driving transistor 11a are nonlinear (often a square curve). Therefore, in the voltage program method, the program voltage and the light emission luminance are in a non-linear relationship, and the light emission control is extremely difficult. Compared with the voltage program, the light emission control is extremely easy in the current program method. In particular, in the pixel configuration of FIG. 1, the program current and the current flowing through the EL element 15 are theoretically equal. Accordingly, the light emission control is very easy to understand and control. The N-fold pulse driving according to the present invention is also excellent in that it is easy to control light emission since the light emission luminance can be grasped by calculating with the program current set to 1 / N. When the pixel configuration in FIG. 38 or the like is a current mirror configuration, the driving transistor 11b and the programming transistor 11a are different from each other, causing a deviation in current mirror magnification, which causes an error factor in light emission luminance. However, the pixel configuration in FIG. 1 does not have this problem because the driving transistor and the programming transistor are the same.

  In the EL element 15, the light emission luminance changes in proportion to the input current amount. The voltage (anode voltage) applied to the EL element 15 is a fixed value. Therefore, the light emission luminance of the EL display panel is proportional to the power consumption.

  From the above, the video data and the program current are proportional, the program current and the light emission luminance of the EL element 15 are proportional, and the light emission luminance and the power consumption of the EL element 15 are proportional. Therefore, if the video data is subjected to logic processing, the current consumption (power) of the EL display panel, the light emission luminance of the EL display panel, and the power consumption of the EL display panel can be controlled. That is, the luminance and power consumption of the EL display panel can be grasped by performing logic processing (addition or the like) on the video data. Therefore, processing such as preventing the peak current from exceeding the set value is extremely easy.

  In particular, the EL display panel of the present invention is a current drive system. In addition, image display control with a characteristic configuration is easier. There are two distinct image display control methods. One is control of the reference current. The other is duty ratio control. By combining the reference current control and the ratio control singly or in combination, a wide dynamic range, high image quality display, and high contrast can be realized.

  First, in the reference current control, as shown in FIG. 77, the source driver IC (circuit) 14 includes a circuit for adjusting the reference current of each RGB. Further, the program current Iw from the source driver circuit 14 is determined by how many unit transistors 484 are being output. The current output from one unit transistor 484 is proportional to the magnitude of the reference current. Therefore, by adjusting the reference current, the current output by one unit transistor 484 is determined, and the magnitude of the program current is determined. Since the reference current and the output current of the unit transistor 484 are in a linear relationship, and the program current and the luminance are in a linear relationship, if the white balance is adjusted by adjusting the reference current of each RGB in white raster display , White balance is maintained in all gradations.

  FIG. 77 shows a configuration in which current mirrors are connected in multiple stages, but the present invention is not limited to this. It goes without saying that even the single-stage source driver IC (circuit) 14 shown in FIGS. 166 to 170 can easily adjust the reference current and maintain the white balance in all gradations. Needless to say, the luminance of the EL display panel can be controlled by adjusting the reference current.

  FIG. 78 shows a duty ratio control method. FIG. 78A shows a method of continuously inserting the non-display area 52. Suitable for video display. Also, FIG. 78 (a1) is the darkest image, and FIG. 78 (a4) is the brightest. The duty ratio can be freely changed by controlling the gate signal line 17b. FIG. 78C shows a method of inserting the non-display area 52 by dividing it into a large number. Particularly suitable for still image display. Also, FIG. 78 (c1) is the darkest image, and FIG. 78 (c4) is the brightest. The duty ratio can be freely changed by controlling the gate signal line 17b. FIG. 78 (b) is an intermediate state between FIG. 78 (a) and FIG. 78 (c). Similarly in FIG. 78B, the duty ratio can be freely changed by controlling the gate signal line 17b.

  The dispersion of the display area 53 is 220/4 = 55 when the number of pixel rows of the display panel is 220 and 1/4 duty, and is adjusted from 1 to 55 (brightness from 1 to 55 times the brightness). it can). Further, if the number of pixel rows of the display panel is 220 and 1/2 Duty, 220/2 = 110, so 1 to 110 (adjustable from 1 brightness to 110 times the brightness). Therefore, the adjustment range of the brightness of the screen brightness 50 is very wide (the dynamic range of image display is wide). Further, there is a feature that the number of gradations that can be expressed can be maintained regardless of the brightness. For example, in the case of 64-gradation display, 64-gradation display can be realized regardless of whether the screen 50 brightness in white raster is 300 nt or 3 nt.

  As described above, the duty can be easily changed by controlling the start pulse to the gate driver 12b. Accordingly, it is possible to easily change various duties such as 1/2 Duty, 1/4 Duty, 3/4 Duty, and 3/8 Duty.

  In the duty ratio driving in units of one horizontal scanning period (1H), an on / off signal of the gate signal line 17b may be applied in synchronization with the horizontal synchronizing signal. Furthermore, the duty ratio can be controlled even in units of 1H or less. This is the driving method of FIGS. 145 and 146. By performing OEV2 control within the 1H period, it is possible to perform brightness control (duty ratio control) in a minute step (see also FIG. 109 and its description, and also refer to FIG. 175 and its description). .

  The duty ratio control within 1H is performed when the duty ratio is ¼ duty or less. If the number of pixel rows is 220 pixel rows, it is 55/220 Duty or less. That is, it is performed in the range of 1/220 to 55/220 Duty. This is performed when a change in one step changes from 1/20 (5%) or more after change to after change. More preferably, it is desirable to perform minute duty ratio drive control by performing OEV2 control even with a change of 1/50 (2%) or less. That is, in the duty ratio control by the gate signal line 17b, when the brightness change after the change from before the change becomes 5% or more, the change amount is gradually changed by the control by the OEV2 so that the change amount becomes 5% or less. Let For this change, it is preferable to introduce the Wait function described in FIG.

  The duty ratio control within 1H when the duty ratio is ¼ duty or less is due to the large amount of change per step, but since the image is halftone, even minute changes are visually recognized. It is also because it is easy. Human vision has a low ability to detect changes in brightness on dark screens above a certain level. In addition, even on a bright screen above a certain level, the detection capability for brightness change is low. This seems to be because human vision depends on the square characteristic.

  FIG. 174 is a graph showing the detection function for a screen change. The horizontal axis represents screen brightness (nt). The vertical axis represents the allowable change (%). The permissible change (%) describes the limit point whether the change rate (%) of the brightness changed from the arbitrary duty to the next duty is permissible. However, the allowable change (%) has a large change rate depending on the content of the image (change rate, scene, etc.). Also, it tends to depend on personal video detection capabilities.

  As can be seen from FIG. 174, when the luminance of the screen 50 is high, the allowable change with respect to the duty change is large. Further, even when the brightness of the screen 50 is dark, the allowable change with respect to the duty change tends to be large. However, in the case of halftone display, the limit value (%) of the allowable change is small. This is because the image is halftone, and even a minute change is easily recognized visually.

  As an example, if there are 200 pixel rows on the panel, OEV2 control is performed at 50/200 duty or less (1/200 or more and 50/200 or less), and duty ratio control is performed for a period of 1H or less. When changing from 1/200 Duty to 2/200 Duty, the difference between 1/200 Duty and 2/200 Duty is 1/200, which is a change of 100%. This change is completely visually recognized as flicker. Therefore, OEV2 control (see FIG. 175 and the like) is performed, and current supply to the EL element 15 is controlled in a period of 1H (one horizontal scanning period) or less. Although the duty ratio control is performed in the 1H period or less (within 1H period), the present invention is not limited to this. As can be seen in FIG. 19, the non-display area 52 is continuous. That is, control such as the 10.5H period is also within the scope of the present invention. In other words, the present invention is not limited to the 1H period (a fractional part is generated) and performs duty ratio driving.

  When changing from 40/200 Duty to 41/200 Duty, the difference between 40/200 Duty and 41/200 Duty is 1/200, and the change is 2.5% at (1/200) / (40/200). Whether or not this change is visually recognized as flicker is likely to depend on the screen brightness 50. However, since 40/200 Duty is a halftone display, it is visually sensitive. Therefore, it is desirable to perform OEV2 control (see FIG. 175 etc.) and control the current supply to the EL element 15 in a period of 1H (one horizontal scanning period) or less.

  As described above, the driving method and the display device according to the present invention can store the current value flowing through the EL element 15 in the pixel 16 (corresponding to the capacitor 19 in FIG. 1), the driving transistor 11a, and the light emitting element (EL A display panel having a configuration capable of turning on and off a current path with respect to the element 15 (a pixel configuration shown in FIGS. 1, 43, 113, 114, 117, and the like corresponds), and at least displaying a display image 19 is generated in the state (depending on the brightness of the image, the screen 50 is a display region 53 (may be a duty 1/1) driving method, and duty ratio driving (at least a part of the screen 50). If the driving method or driving state in which the non-display area 53 becomes a non-display area 53) is equal to or less than a predetermined duty ratio, it is limited within one horizontal scanning period (1H period) or in units of 1H period By controlling the current applied to the element 15, and performs brightness control of the display screen 50. The control is carried out by OEV2 control (see Figure 175 and the description thereof with regard OEV2).

  The predetermined duty ratio for performing duty ratio control other than 1H unit is performed when the duty ratio is equal to or less than ¼ duty. Conversely, when the duty ratio is equal to or higher than the predetermined duty ratio, duty ratio control is performed in units of 1H. Or, OEV2 control is not performed. Further, duty ratio control other than the 1H period is performed when a change in one step changes from 1/20 (5%) or more after change to after change. More preferably, it is desirable to perform minute duty ratio drive control by performing OEV2 control even with a change of 1/50 (2%) or less. Alternatively, it is carried out with a luminance of 1/4 or less of the maximum luminance of the white raster.

  According to the duty ratio control drive of the present invention, as shown in FIG. 79, if the number of gradation representations of the EL display panel is 64 gradations, the display brightness (nt) of the display screen 50 is any brightness. Even so, the 64 gradation display is maintained. For example, even when the number of pixel rows is 220 and only one pixel row is in the display area 53 (display state) (Duty ratio 1/220), 64-gradation display can be realized. This is because an image is sequentially written in each pixel row by the program current Iw of the source driver circuit 14, and this one pixel row is sequentially displayed by the gate signal line 17b.

  Of course, even when all of the 220 pixel rows are in the display area 53 (display state) (Duty ratio 220/220 = Duty ratio 1/1), 64-gradation display can be realized. This is because images are sequentially written to the pixel rows by the program current Iw of the source driver circuit 14, and all the pixel rows are simultaneously displayed by the gate signal lines 17b. Further, even when only 20 pixel rows are in the display region 53 (display state) (Duty 20/220 = Duty 1/11), 64-gradation display can be realized. This is because an image is sequentially written in each pixel row by the program current Iw of the source driver circuit 14, and the 20 pixel rows are sequentially scanned and displayed by the gate signal line 17b.

  Since the duty ratio control drive of the present invention is the control of the lighting time of the EL element 15, the brightness of the screen 50 with respect to the duty ratio has a linear relationship. Therefore, it is very easy to control the brightness of the image, the signal processing circuit is simple, and the cost can be reduced. As shown in FIG. 77, the RGB reference current is adjusted to achieve white balance. In the duty ratio control, white balance is maintained at any gradation and brightness of the screen 50 in order to simultaneously control the brightness of R, G, and B.

  In the duty ratio control, the luminance of the screen 50 is changed by changing the area of the display region 53 with respect to the display screen 50. Naturally, the current flowing through the EL display panel changes in proportion to the display area 53. Therefore, by calculating the sum total of the video data, the total current consumption flowing through the EL element 15 of the display screen 50 can be calculated. Since the anode voltage Vdd of the EL element 15 is a DC voltage and is a fixed value, if the total current consumption can be calculated, the total power consumption can be calculated in real time according to the image data. If the calculated total power consumption is predicted to exceed the prescribed maximum power, the reference current in FIG. 77 may be adjusted by an adjustment circuit such as an electronic volume, and the RGB reference current may be controlled to be suppressed.

  In addition, a predetermined luminance in white raster display is set, and this time is set so as to minimize the duty ratio. For example, the duty ratio is set to 1/8. For natural images, the duty ratio is increased. The maximum duty is 1/1. For example, a natural image in which an image is displayed only 1/100 of the screen 50 is set to Duty 1/1. The duty ratio 1/1 to the duty ratio 1/8 is smoothly changed depending on the display state of the natural image on the screen 50.

  As described above, as an example, in white raster display (all pixels are lit 100% in a natural image), the duty ratio is 1/8, and 1/100 pixels of the screen 50 are lit. The state is a duty ratio of 1/1. The approximate power consumption can be calculated by the number of pixels × the ratio of the number of lit pixels × Duty ratio.

  For ease of explanation, assuming that the number of pixels is 100, the power consumption in white raster display is 100 × 1 (100%) × Duty ratio 1/8 = 80. On the other hand, the power consumption of a natural image in which 1/100 is lit is 100 × (1/100) (1%) × Duty ratio 1/1 = 1. Duty 1/1 to Duty ratio 1/8 is a smooth duty ratio control so that flicker does not occur according to the number of lighting pixels of the image (actually, the total current of the lighting pixels = the sum of the program currents of one frame). Is done.

  As described above, the power consumption ratio of white raster is 80, and the power consumption ratio of a natural image in which 1/100 is lit is 1. Therefore, the maximum current can be suppressed by setting a predetermined luminance in white raster display and setting this time so as to minimize the duty ratio.

  In the present invention, the sum of the program currents for one screen is S, the duty ratio is D, and drive control is performed with S × D. Also, the total program current in the white raster display is Sw, the maximum duty ratio is Dmax (usually, the duty ratio 1/1 is the maximum), the minimum duty ratio is Dmin, and any natural This is a drive method and a display device that realizes the drive method in which the relationship of Sw × Dmin> = Ss × Dmax is maintained when the total program current in the image is Ss.

  The maximum duty ratio is 1/1. The minimum is preferably a duty ratio of 1/16 or more. That is, the duty ratio is set to 1/8 or more and 1/1 or less. Needless to say, the use of 1/1 is not restricted. Preferably, the minimum duty ratio is 1/10 or more. This is because if the duty ratio is too small, the occurrence of flicker is conspicuous, and the luminance change of the screen due to the image content becomes too large, making it difficult to see the image.

  As described above, the program current is proportional to the video data. Therefore, the sum of program currents is synonymous with the sum of program currents. Although the sum of program currents for one frame (one field) period is obtained, the present invention is not limited to this. Pixels to which program current is added at a predetermined interval or a predetermined period in one frame (one field) May be sampled to obtain the sum of program currents (video data). Further, sum data before and after a frame (field) to be controlled may be used, or duty ratio control may be performed using sum data obtained by estimation or prediction.

  In the above description, the control is performed with the duty ratio D. However, the duty ratio is a predetermined period (usually one field or one frame. In other words, in general, a cycle in which image data of an arbitrary pixel is rewritten. Or the time during which the EL element 15 is turned on. That is, a duty ratio of 1/8 means that the EL element 15 is lit during a 1/8 period (1F / 8) of one frame. Therefore, the duty ratio can be read as Duty ratio = Ta / Tf, where Tf is the period when the pixel 16 is rewritten and the lighting period Ta of the pixel.

  In addition, although the period time in which the pixel 16 is rewritten is Tf and is based on Tf, the present invention is not limited to this. The duty ratio control drive of the present invention does not need to be completed in one frame or one field. That is, the duty ratio control may be performed with several fields or several frame periods as one cycle (see FIG. 104 and the like). Therefore, Tf is not limited to the cycle of rewriting pixels, and may be one frame or one field or more. For example, if the lighting period Ta is different for each field or frame, the repetition period (period) may be Tf and the total lighting period Ta of this period may be employed. That is, Ta may be the average lighting time of several fields or several frame periods. The same applies to the duty ratio. When the duty differs for each frame (field), an average duty ratio of a plurality of frames (fields) may be calculated and used.

  Therefore, the sum of program currents in white raster display is Sw, the sum of program currents in an arbitrary natural image is Ss, the minimum lighting period is Tas, and the maximum lighting period is Tam (usually Tam = Tf). To Tam / Tf = 1), a driving method for maintaining the relationship of Sw × (Tas / Tf)> = Ss × (Tam / Tf) and a display device that realizes the driving method.

  As a method for controlling the brightness of the screen 50, there is the configuration described in FIG. That is, by adjusting the reference current, the screen current 50 is changed by changing the current flowing through the unit transistor 484 and adjusting the magnitude of the program current. The reference current adjustment method is described with reference to FIG.

  491R in FIG. 77 is a volume for adjusting the reference current of red (R). However, the expression “volume” is for ease of explanation, and it is actually an electronic volume. The reference current IaR of the R circuit can be linearly adjusted in 64 steps by a 6-bit digital signal from the outside. It is configured as follows. By adjusting the reference current IaR, the current flowing through the transistor 471R and the transistor 472a forming the current mirror circuit can be linearly changed. Therefore, the current flowing through the transistor 472b in the transistor group 521a and the transistor 472b that has passed the current changes, the transistor 473a in the transistor group 521b that forms the current mirror circuit with the transistor 472b changes, and the transistor 473b that has passed the current through the transistor 473a. Changes. Accordingly, since the drive current (unit current) of the unit transistor 484 changes, the program current can be changed. The same applies to the G reference current IaG and the B reference current IaB.

  FIG. 77 shows a three-stage transistor connection of a parent and a descendant, but the present invention is not limited to this. For example, as shown in FIGS. 166 to 170, it goes without saying that the present invention can be applied to a single-stage configuration in which a circuit for generating a reference current and a unit transistor 484 are directly connected. That is, the present invention is a circuit configuration in which the program current or the program voltage can be changed by one reference current or reference voltage, and the brightness of the screen 50 is changed by the reference current or reference voltage.

  Note that the transistor 521b does not need to be formed or configured in both of the source driver circuits (IC) 14, and may be only one as shown in FIG.

  As shown in FIG. 77, the (electronic) volume 491 is formed in red (R), green (G), and B (blue) circuits, respectively. Therefore, by adjusting the volumes 491R, 491G, and 491B, the currents of the unit transistors 484 connected thereto can be changed (controlled or adjusted). Therefore, white (W) adjustment can be easily performed by adjusting the RGB ratio. Of course, if the RGB reference currents (currents flowing through the transistors 472R, 472G, and 472B) are adjusted in advance at the time of shipment, RGB electronic volumes (491R, 491G, and 491B) can be separately changed. Thus, white (W) balance adjustment can also be performed. For example, in FIGS. 169 and 170, the value of the resistor R1 is adjusted so that white balance is obtained in each RGB circuit. In this state, if the switches S of the electronic volume 451 in FIGS. 169 and 170 are switched to the same RGB, the screen brightness can be adjusted while maintaining the white balance.

As described above, the reference current driving method of the present invention adjusts the RGB reference current values so that white balance is achieved. With this state as the center, the RGB reference current is adjusted at the same ratio. White balance is maintained because adjustment is performed at the same ratio.
As described above, the program current can be changed linearly by adjusting the electronic volume 491. For ease of explanation, the pixel configuration shown in FIG. 1 will be described as an example. However, the present invention is not limited to this, and it is needless to say that other pixel configurations may be used.

  As shown or described in FIG. 77, the program current can be linearly adjusted by controlling the reference current. This is because the output current of one unit transistor 484 changes. When the output current of the unit transistor 484 is changed, the program current Iw is also changed. The larger the current programmed in the pixel capacitor 19 (actually, the voltage corresponding to the program current) is, the larger the current flowing through the EL element 15 is. The current flowing through the EL element 15 and the light emission luminance are linearly proportional. Therefore, the light emission luminance of the EL element 15 can be linearly changed by changing the reference current.

  The source driver circuit (IC) 14 of the present invention changes the program current Iw by controlling the number of unit transistors 484 connected to the terminal 681. The program current Iw was realized by changing the reference current Ic as described with reference to FIGS. 389 and 392.

  However, the present invention is not limited to this, as long as a constant reference (voltage, current, setting data, etc.) can be changed and the current Iw output from the terminal 681 can be changed by this change. Either is acceptable. However, it is important to change the program current Iw of each output terminal 681 at the same rate due to a change in the reference. Note that the present invention is not limited to changes in the program current Iw. It may be a program voltage. This is because the luminance of the screen 50 can be adjusted by changing the program voltage of each terminal 681 at the same rate. Further, the white balance can be adjusted by changing the RGB terminal.

  FIG. 402 shows an embodiment of the present invention that does not include a reference current Ic adjustment circuit. The terminal 681 is supplied with the program current Iw from the operational amplifier 722 by the transistor 471. The program current Iw is determined by the voltage applied to the operational amplifier 522 by the sampling circuit 4022.

  The 8-bit video data is converted into analog data by the D / A circuit 551, and the analog data is gain-adjusted by the variable amplifier circuit 4021. The gain-adjusted analog data is sampled by the horizontal scanning clock in the sampling circuit 4022 and held in each capacitor C. Note that the gain of the variable amplifier circuit 4021 is set by 8-bit data.

  As an example of the variable amplifier circuit 4021, the configuration of FIG. 403 is illustrated. In FIG. 403, analog data of the DA circuit 551 is applied to the Vin terminal. The gain is set by a switch Sx connected in series with the resistor Rx. The switch Sx is controlled by gain setting data at 8 bits. The gain setting data can be changed in units of one frame or one field.

  That is, the gain is set by closing one of the switches Sx. The control of the switch Sx corresponds to the switch circuit 3892 in FIG. 389 and the electronic volume 451 in FIG. That is, the program current Iw can be changed or adjusted by controlling the switch Sx.

Therefore, in FIG. 402, analog data is sampled and held at C, and the program current Iw is applied to the source signal line 18 by the sampled and held voltage. The program current Iw is changed (controlled) by the gain data of the variable amplifier 4021.
Also in the configuration of FIG. 402, the brightness of the screen 50 can be adjusted (variable) all at once by the gain setting data. Therefore, the n-fold pulse driving, the duty driving, etc. of the present invention can be realized. Also, by providing the variable amplifier 4021 for each RGB, white balance adjustment and color management control can be realized (see FIGS. 327 to 337). That is, in the display panel or device of the present invention, the driving method and configuration of the present invention can be realized even if the source driver circuit (IC) 14 having the configuration of FIG. 402 is used.
In the present invention, screen brightness and the like are controlled using at least one of the reference current control method described in FIG. 77 and the duty ratio control method described in FIG. Preferably, it is preferable to implement a combination of the methods shown in FIGS. 77 and 78.

  Hereinafter, the driving method using the method described in FIGS. 77 and 78 will be described in more detail. One object of the driving method of the present invention is to limit the upper limit of current consumption consumed by the EL display panel. In the EL display panel, the luminance is proportional to the current flowing through the EL element 15. Therefore, if the current flowing through the EL element 15 is increased, the luminance of the EL display panel can be increased. The current consumed (= power consumption) increases in proportion to the luminance.

  When used for a portable device, the capacity of a battery or the like is limited. Further, the scale of the power supply circuit increases as the current consumed increases. Therefore, it is necessary to provide a limit for the consumed current. Providing this limit (peak current suppression) is one object of the present invention.

  Further, the display is improved by increasing the contrast of the image. Display is improved by converting the image so that there is an edge and displaying the image. The second object of the present invention is to improve the image display as described above. The present invention that realizes the above two purposes (or one) will be referred to as AI driving.

  First, for ease of explanation, it is assumed that the IC chip 14 of the present invention has a 64-gradation display. In order to realize AI driving, it is desirable to expand the gradation expression range. For ease of explanation, the source driver IC (circuit) 14 according to the present invention has 64 gradation display and the image data has 256 gradation. This image data is subjected to gamma conversion so as to match the gamma characteristic of the EL display device. The gamma conversion is performed by expanding the input 256 gradations to 1024 gradations. The gamma-converted image data is subjected to error diffusion processing or frame rate control (FRC) processing so as to conform to the 64 gradations of the source driver IC 14 and is applied to the source driver IC 14.

  FRC realizes high gradation display by superimposing image display for each field. In the error diffusion processing, as shown in FIG. 99 as an example, the image data of the pixel A is distributed to 7/16 on the right, 3/16 on the lower left, 5/16 on the lower, and 1/16 on the lower right. Is the method. High gradation display can be realized by distributed processing. It is a kind of area gradation.

  For ease of illustration, FIGS. 80 and 81 will be described assuming that 64 gradation display is converted to 512 gradation. The conversion is performed by an error diffusion processing method or frame rate control (FRC). However, in FIG. 80, it may be interpreted that the brightness of the image is converted rather than performing the gradation conversion.

  FIG. 80 explains the image conversion processing by the driving method of the present invention. In FIG. 80, the horizontal axis represents gradation (number). The larger the gradation (number) is, the brighter the screen 50 is. Conversely, the smaller the gradation (number), the darker the image. The vertical axis is frequency. The frequency indicates a histogram of the brightness of the pixels constituting the image. For example, A1 in FIG. 80 (a) indicates that the image has the largest number of pixels having a luminance of 24 gradation levels.

  FIG. 80A shows an example in which the display brightness is changed while maintaining the number of gradation representations of the image. When A1 is an original image, the original image has an expression range of approximately 64 gradations. A2 is an example in which the center of brightness is converted to 256 gradations while maintaining the number of gradation representations. Similarly, A3 is an example in which the center of brightness is converted to 448 gradations while maintaining the number of gradation representations. Such conversion can be achieved by converting the image data by adding data of a predetermined size.

  However, the gradation conversion in FIG. 80A is difficult to realize with the driving method of the present invention. In the driving method of the present invention, the gradation conversion shown in FIG.

  FIG. 80B is an example in which the frequency distribution of the original image is enlarged. When B1 is an original image, the original image has an expression range of approximately 64 gradations. B2 is an example in which the gradation expression range is expanded to 256 gradations. The brightness of the screen becomes brighter and the gradation expression range is expanded. B3 is an example in which the gradation expression range is further expanded to 512 gradations. The screen display brightness is further increased and the gradation expression range is expanded.

  The realization of FIG. 80B can be easily realized by the driving method of the present invention. This can be realized by changing the reference current described in FIG. Further, this can be realized by changing (controlling) the duty ratio of FIG. Alternatively, it can be realized by combining the methods of FIG. 77 and FIG. The brightness control of the image is easy by the reference current control or the duty ratio control. For example, if the duty ratio is 1/4 and the display state is B2 in FIG. 80B, if the duty ratio is 1/16, the display state is B1 in FIG. 80B. Further, if the duty ratio is halved, the display state of B3 in FIG. The same applies to the reference current control. The image display of FIG. 80 (b) can be achieved by setting the magnitude of the reference current to double or 1/4.

  The horizontal axis in FIG. 80 (b) represents the number of gradations. The driving method of the present invention does not increase the number of gradations. The driving method of the present invention is characterized in that the number of gradations is maintained even when the display luminance changes as described in FIG. That is, in FIG. 80B, it is assumed that the number of 64 gradations of B1 is converted to 256 gradations in B2. However, the gradation number of B2 is 64 gradations. One gradation range is expanded four times compared to B1. The conversion from B1 to B2 is nothing but the dynamic conversion of the image display. Therefore, it is equivalent to realizing high gradation display. Therefore, high quality display can be realized.

Similarly, in FIG. 80B, it is assumed that the number of 64 gradations of B1 is converted to 512 gradations in B3. However, the number of gradations of B3 is 64 gradations. One gradation range is expanded eight times compared to B1. The conversion from B1 to B3 is nothing but the dynamic conversion of the image display. In FIG. 80A, the brightness of the screen 50 can be improved. However, the entire screen 50 becomes whitish (white floating). However, the increase in current consumption is relatively small (although the current consumption increases in proportion to the screen brightness). In FIG. 80B, the luminance of the screen 50 can be improved and the gradation display range is expanded, so there is no deterioration in image quality. However, the increase in current consumption is large.

  If the number of gradations is proportional to the screen luminance, and the original image has 64 gradations, the increase in the number of gradations (expansion of dynamic range) = the increase in luminance. Therefore, power consumption (current consumption) increases. In order to solve this problem, the present invention combines either the reference current of FIG. 77 and the method of adjusting (controlling), the method of controlling the duty ratio of FIG. 78, or a combination of both.

  When the image data of one screen is large as a whole, the total sum of the image data becomes large. For example, since the white raster has 63 gradations as image data in the case of 64-gradation display, the number of pixels of the screen 50 × 63 is the total sum of the image data. In the white window display of 1/100 and the white display portion displaying white with the maximum luminance, the number of pixels of the screen 50 × (1/100) × 63 is the total sum of the image data.

  In the present invention, a value capable of predicting the total sum of image data or the amount of current consumption of the screen is obtained, and duty ratio control or reference current control is performed based on this sum or value.

  Although the sum of the image data is obtained, the present invention is not limited to this. For example, an average level of one frame of image data may be obtained and used. In the case of an analog signal, the average level can be obtained by filtering the analog image signal with a capacitor. A direct current level may be extracted from an analog video signal through a filter, and the direct current level may be AD converted to be a sum of image data. In this case, the image data can also be referred to as an APL level.

  It is also preferable to obtain data that can estimate the sum of image data or the sum of image data from 30 frames to 300 frames, and perform duty ratio control based on the size of this data. The total data changes slowly according to image changes. The longer the frame period for obtaining the total data, the slower the brightness change of the image.

  Further, it is not necessary to add all the data of the image constituting the screen 50, and 1 / W (W is a value greater than 1) of the screen 50 may be picked up and extracted, and the sum of the picked up data may be obtained. .

  In order to facilitate the description, the description will be made assuming that the sum of the image data is also obtained in the above case. In many cases, the sum of the image data coincides with the determination of the APL level of the image. The sum total of image data includes means for digital addition, but the method for obtaining the sum total of digital and analog image data is hereinafter referred to as an APL level for ease of explanation.

  Since the APL level is 6 bits for each of RGB in the white raster, 63 (indicated by 63 as data representation because it is the 63rd gradation) × number of pixels (176 × RGB × for the QCIF panel) 220). Therefore, the APL level is maximized. However, since the current consumed by the RGB EL elements 15 is different, it is preferable to calculate the image data separately for RGB.

For this problem, the arithmetic circuit shown in FIG. 84 is used. In FIG. 84, reference numerals 841 and 842 are multipliers. Reference numeral 841 denotes a multiplier for weighting the emission luminance. R, G, and B have different visibility. The visibility in NTSC is R: G: B = 3: 6: 1. Accordingly, the R multiplier 841R performs a multiplication of 3 times on the R image data (Rdata). The G multiplier 841G multiplies G image data (Gdata) by 6 times. Further, the B multiplier 841B performs multiplication of 1 time on the B image data (Bdata).
The EL element 15 has different luminous efficiencies for RGB. Usually, the luminous efficiency of B is the worst. Next, G is bad. R has the best luminous efficiency. Therefore, the multiplier 842 weights the light emission efficiency. The R multiplier 842R multiplies the R image data (Rdata) by the R luminous efficiency. The G multiplier 842G multiplies the G image data (Gdata) by the G light emission efficiency. The B multiplier 842B multiplies the B image data (Bdata) by the B light emission efficiency.

  The results of multipliers 841 and 842 are added by adder 843 and accumulated in summation circuit 844. Based on the result of the summation circuit 87, the duty ratio control in FIG. 77 and the reference current control in FIG. 78 are performed.

  When the control is performed as shown in FIG. 84, the duty ratio control and the reference current control for the luminance signal (Y signal) can be performed. However, when a luminance signal (Y signal) is obtained and duty control or the like is performed, a problem may occur. For example, a blue back display. In the blue back display, the current consumed by the EL panel is relatively large. However, the display brightness is low. This is because the visibility of blue (B) is low. Therefore, the sum (APL level) of the luminance signal (Y signal) is calculated to be small, so that the duty control becomes high. Accordingly, flicker occurs.

  For this problem, the multiplier 841 may be used as through. This is because the sum (APL level) with respect to the current consumption is obtained. It is desirable to obtain the total APL level by taking both the sum (APL level) based on the luminance signal (Y signal) and the sum (APL level) based on the current consumption into consideration. Duty ratio control and reference current control are performed according to the total APL level.

  Since the black raster is the 0th gradation in the case of the 64 gradation display, the APL level is 0 and becomes the minimum value. In the driving method of FIG. 80, power consumption (current consumption) is proportional to image data. The image data does not need to count all the bits of the data constituting the screen 50. For example, when the image is expressed by 6 bits, only the upper bits (MSB) may be counted. In this case, the number of gradations is 32 or more and one count is made. Accordingly, the APL level changes depending on the image data constituting the screen 50.

  In the present invention, the reference current control of FIG. 78 or the duty ratio control of FIG. 77 is performed according to the magnitude of the obtained APL level.

  In order to facilitate understanding, specific numerical values will be exemplified. However, this is virtual, and it is actually necessary to determine control data and a control method by experiment and image evaluation.

  The current that can flow maximum in the EL panel is 100 (mA). In the case of white raster display, the total (APL level) is assumed to be 200 (no unit). When the APL level is 200, it is assumed that 200 (mA) flows through the EL panel when applied to the panel as it is. When the APL level is 0, the current flowing through the EL panel is 0 (mA). When the APL level is 100, the duty ratio is ½.

  Therefore, when the APL is 100 or more, it is necessary to make the limit 100 (mA) or less. Most simply, when the APL level is 200, the duty is (1/2) × (1/2) = 1/4, and when the APL level is 100, the duty is 1/2. When the APL level is 100 or more and 200 or less, the duty is controlled to be between 1/4 and 1/2. The duty ratio of 1/4 to 1/2 can be realized by controlling the number of gate signal lines 17b to be simultaneously selected by the gate driver 12b on the EL selection side.

  However, if the duty ratio control is performed considering only the APL level, the luminance of the screen 50 changes according to the average luminance (APL) of the screen 50 according to the image, and flicker occurs. In response to this problem, the APL level to be calculated is held for a period of at least 2 frames, preferably 10 frames, more preferably 60 frames or more, and calculation is performed during this period, and the duty ratio by duty ratio control is calculated by this APL level. calculate. In addition, it is preferable to perform duty ratio control by extracting image features such as the maximum luminance (MAX), minimum luminance (MIN), and luminance distribution state (SGM) of the screen 50. Needless to say, the above items also apply to the reference current control.

  It is also important to perform black stretching and white stretching by extracting image features. This may be performed in consideration of the maximum luminance (MAX), the minimum luminance (MIN), and the luminance distribution state (SGM). For example, in FIG. 81A, the center data Kb of the image is distributed in the vicinity of 256 gradations, and the high brightness portion Kc is distributed in the vicinity of 320 gradations. Further, the low luminance portion Ka is distributed in the vicinity of 128 gradations.

  FIG. 81B shows an example in which black extension and white extension are performed on the image shown in FIG. However, it is not necessary to perform black stretching and white stretching simultaneously, and only one of them may be performed. Further, the central portion of the image (Kb in FIG. 81 (a) may also be moved to the low gradation portion or the high gradation portion. The appropriate movement information includes APL level, maximum luminance (MAX), minimum luminance ( MIN), luminance distribution state (SGM), but it may be an empirical matter, because it affects human visual sensitivity, so image evaluation and experiment are repeated. However, image processing such as black stretching or white stretching can be easily realized because the gamma curve can be obtained by calculation or from a lookup table.By performing processing as shown in FIG. , The image has a stickiness, and a good image display can be realized.

Note that the brightness of the screen 50 is changed by duty ratio control as shown in FIG. FIG. 82A shows a driving method in which the display area 53 is continuously changed. The screen 50 brightness in FIG. 82 (a2) is brighter than the screen 50 brightness in FIG. 82 (a1). The brightest is the state shown in FIG. The drive by duty ratio control in FIG. 82 (a) is suitable for moving image display.
FIG. 82B shows a driving method in which the display area 53 is divided and changed. In FIG. 82 (b1), display areas 53 are generated at two places on the screen 50 as an example. In FIG. 82 (b2), the display area 53 is generated at two places on the screen 50 as in FIG. 82 (b1), but the number of pixel rows in the display area 53 is increased at one of the two places (one side). 1 pixel row is the display area 53, and the other pixel line is the display area 53). In FIG. 82 (b3), the display area 53 is generated at two places on the screen 50 as in FIG. 82 (b2), but the pixel row of the display area 53 is increased at one place out of the two places (both). 2 pixel rows are the display area 53). As described above, the duty ratio control may be performed by dispersing the display area 53. In general, FIG. 82B is suitable for still image display.

  In FIG. 82 (b), the dispersion of the display area 53 is 2 dispersion. However, this is to facilitate drawing. Actually, the dispersion of the display area 53 is 3 dispersions or more.

  FIG. 83 is a block diagram of the drive circuit of the present invention. Hereinafter, the drive circuit of the present invention will be described. In FIG. 83, a Y / UV video signal and a composite (COMP) video signal can be input from the outside. The switch circuit 831 selects which video signal is input to.

  The video signal selected by the switch circuit 831 is decoded and AD converted by a decoder and an A / D circuit, and converted into digital RGB image data. RGB image data is 8 bits each. The RGB image data is subjected to gamma processing by a gamma circuit 834. At the same time, a luminance (Y) signal is obtained. The RGB image data is converted into 10-bit image data by gamma processing.

  After the gamma processing, the image data is subjected to FRC processing or error diffusion processing in the processing circuit 835. RGB image data is converted into 6 bits by FRC processing or error diffusion processing. This image data is subjected to AI processing or peak current processing in an AI processing circuit 836. In addition, the moving image detection circuit 837 performs moving image detection. At the same time, color management processing is performed by the color management circuit 838.

  The processing results of the AI processing circuit 836, the moving image detection circuit 837, and the color management circuit 838 are sent to the arithmetic circuit 839, where the arithmetic processing circuit 839 converts the result into control arithmetic, duty ratio control, and reference current control data. The data is sent to the source driver circuit 14 and the gate driver circuit 12 as control data.

  The duty ratio control data is sent to the gate driver circuit 12b, and duty ratio control is performed. On the other hand, the reference current control data is sent to the source driver circuit 14 and the reference current control is performed. Image data that has been subjected to gamma correction and subjected to FRC or error diffusion processing is also sent to the source driver circuit 14.

  The image data conversion in FIG. 81B needs to be performed by gamma processing of the gamma circuit 834. The gamma circuit 834 performs gradation conversion using a multipoint broken gamma curve. The 256-gradation image data is converted to 1024 gradations by a multipoint broken gamma curve.

  The gamma circuit 834 performs gamma conversion with a multipoint broken gamma curve, but the present invention is not limited to this. As shown in FIG. 85, gamma conversion may be performed using a one-point broken gamma curve. Since the hardware scale constituting the one-point broken gamma curve is small, the cost of the control IC can be reduced.

  In FIG. 85, a is a polygonal line gamma conversion at the 32nd gradation. b is a polygonal line gamma conversion at the 64th gradation. c is a polygonal line gamma conversion at the 96th gradation. d is a polygonal line gamma conversion at the 128th gradation. If the image data is concentrated in high gradations, the gamma curve d in FIG. 85 is selected to increase the number of gradations in the high gradations. When the image data is concentrated in the low gradation, the gamma curve a in FIG. 85 is selected in order to increase the number of gradations in the low gradation. If the distribution of image data is dispersed, gamma curves such as b and c in FIG. 85 are selected. In the above embodiment, the gamma curve is selected. However, actually, the gamma curve is not selected because it is generated by calculation.

  The gamma curve is selected in consideration of the APL level, maximum luminance (MAX), minimum luminance (MIN), and luminance distribution state (SGM). Further, the duty ratio control and the reference current control are taken into consideration.

  FIG. 86 shows an example of a multipoint broken gamma curve. When the image data is concentrated at high gradations, the n gamma curve in FIG. 85 is selected to increase the number of gradations at high gradations. When the image data is concentrated in the low gradation, the gamma curve a in FIG. 85 is selected in order to increase the number of gradations in the low gradation. If the distribution of the image data is dispersed, an n-1 gamma curve is selected from b in FIG. The gamma curve is selected in consideration of the APL level, maximum luminance (MAX), minimum luminance (MIN), and luminance distribution state (SGM). Further, the duty ratio control and the reference current control are taken into consideration.

  It is also effective to change the gamma curve selected in accordance with the environment used by the display panel (display device). In particular, in an EL display panel, a good image display can be realized indoors, but a low gradation portion cannot be seen outdoors. The EL display panel is for self light emission. Therefore, as shown in FIG. 87, the gamma curve may be changed. The gamma curve a is an indoor gamma curve. The gamma curve b is an outdoor gamma curve. The gamma curves a and b are switched by the user operating the switch. Alternatively, the brightness of outside light may be detected by a photo sensor and automatically switched. Although the gamma curve is switched, the present invention is not limited to this. It goes without saying that a gamma curve may be generated by calculation. In the case of the outdoors, the low gradation display portion cannot be seen due to the strong external light. Therefore, it is effective to select the gamma curve b that crushes the low gradation part.

  In the outdoors, it is also effective to generate a gamma curve as shown in FIG. In the gamma curve a, the output gradation is set to 0 until the 128th gradation. Gamma conversion is performed from 128 gradations. As described above, power consumption can be reduced by performing gamma conversion so that the low gradation portion is not displayed at all. Also, gamma conversion may be performed as in the gamma curve b in FIG. The gamma curve in FIG. 88 sets the output gradation to 0 up to the 128th gradation. For 128 or more, the output gradation is 512 or more. The gamma curve b in FIG. 88 has the effect of making the image display easier to see even outdoors by displaying a high gradation part and reducing the number of output gradations.

  In the drive system of the present invention, image brightness is controlled by duty ratio control and reference current control, and the dynamic range is expanded. In addition, high contrast display is realized.

  In the liquid crystal display panel, white display and black display are determined by the transmittance from the backlight. Even when the non-display area 52 is generated on the screen 50 as in the duty ratio drive of the present invention, the transmittance in black display is constant. On the contrary, when the non-display area 52 is generated, the white display luminance in one frame period is lowered, so that the display contrast is lowered.

  In the EL display panel, black display is a state in which the current flowing through the EL element 15 is zero. Therefore, even when the non-display area 52 is generated on the screen 50 as in the duty ratio driving of the present invention, the luminance of black display is zero. When the area of the non-display area 52 is increased, the white display luminance is lowered. However, since the luminance of black display is 0, the contrast is infinite. Therefore, the duty ratio driving is an optimal driving method for the EL display panel. The same applies to the reference current control. Even if the magnitude of the reference current is changed, the luminance of black display is zero. Increasing the reference current increases the white display luminance. Therefore, a good image display can be realized even in the reference current control.

  In the duty ratio control, the number of gradations is maintained in the entire gradation range, and the white balance is maintained in the entire gradation range. Further, the luminance change of the screen 50 can be changed by nearly 10 times by the duty ratio control. Further, since the change has a linear relationship with the duty ratio, it is easy to control. However, since the duty ratio control is N-fold pulse driving, the magnitude of the current flowing through the EL element 15 is large, and the magnitude of the current flowing through the EL element is always large regardless of the brightness of the screen 50. There is a problem that the EL element 15 is easily deteriorated.

  In the reference current control, when the screen brightness 50 is increased, the reference current amount is increased. Therefore, the current flowing through the EL element 15 is increased only when the screen 50 is high. Therefore, the EL element 15 is not easily deteriorated. The problem tends to be that it is difficult to maintain white balance when the reference current is changed.

  In the present invention, both reference current control and duty ratio control are used. When the screen 50 is close to white raster display, the reference current is fixed to a constant value, and only the duty ratio is controlled to change the display luminance or the like. When the screen 50 is close to black raster display, the duty ratio is fixed to a constant value, and only the reference current is controlled to change the display brightness.

  The duty ratio control is performed in a range where the data sum / maximum value is 1/10 or more and 1/1. The data sum / maximum value is synonymous with the lighting rate. If the data sum / maximum value is 1, the lighting rate is 100% (basically the maximum white raster display). If the data sum / maximum value is 0, the lighting rate is 0% (basically a complete black raster display).

  The lighting rate is a ratio with respect to the maximum current flowing in the anode or cathode of the panel (where duty is 1/1). For example, if the maximum current flowing through the cathode is 100 mA, the lighting rate is 30/100 = 30% (0.3) when a current of 30 mA flows at a duty ratio of 1/1. In the case of the pixel configuration shown in FIG. 1 and the like, since a program current is added to the anode, it is necessary to consider the calculation of the lighting rate. The cathode is only the current consumed by the EL element.

  Although the lighting rate is a ratio with respect to the maximum current flowing through the anode or cathode of the panel, it is needless to say that it can be rephrased as a ratio of the maximum current flowing through all the EL elements of the panel.

  In this specification, when the lighting rate is described without any notice, the duty ratio is 1/1. If a current of 20 mA flows at a duty ratio of 1/3, the lighting rate is (20 mA × 3) / 100 mA = 60% (0.6).

  The above items apply not only to the EL panel or EL display device having the pixel configuration shown in FIG. 1, but also to the EL panel or EL display device having another pixel configuration such as those shown in FIGS. 2, 38, 43, and 46. Needless to say, you can.

  The data sum / maximum value (lighting rate) is obtained from the sum of the video data. When the input video signal is Y, U, or V, it may be obtained from a Y (luminance) signal. However, in the case of an EL panel, since the light emission efficiency differs between R, G, and B, the value obtained from the Y signal does not become the power consumption. Therefore, in the case of Y, U, and V signals, the current consumption (power consumption) can be obtained by converting the signals into R, G, and B signals and multiplying them by a coefficient that converts the current into R, G, and B. preferable. However, simply obtaining the current consumption from the Y signal may be considered to facilitate circuit processing.

  It is assumed that the lighting rate is converted by the current flowing through the panel. This is because, in the EL display panel, the light emission efficiency of B is poor, and thus when the display of the sea is displayed, the power consumption increases at a stretch. Therefore, the maximum value is the maximum value of the power supply capacity. The data sum is not a simple addition value of video data, but video data converted into current consumption. Therefore, the lighting rate is also obtained from the current used for each image with respect to the maximum current.

  The data sum / maximum value is in the range of 1/100 to 1/1. In addition, the change in the reference current magnification (change in the output current of the unit transistor 484) is performed in a range where the data sum / maximum value is 1/10 to 1/1000. More preferably, the data sum / maximum value is in the range of 1/100 to 1/2000. It is preferable that the reference current control and the duty ratio control do not overlap. In FIG. 89, when the data sum / maximum value is 1/100 or less, the reference current magnification is changed, and when the data sum / maximum value is 1/100 or more, the duty ratio is changed. Therefore, there is no overlap.

  Here, for ease of explanation, the maximum duty ratio is assumed to be a duty ratio 1/1 and the minimum is assumed to be a duty ratio 1/8. The reference current is changed from 1 to 3 times. Further, the data sum means the sum of the data on the screen 50, and the maximum value (of the data sum) is assumed to be the sum of the image data in the white raster display at the maximum luminance. Needless to say, it is not necessary to use a duty ratio of 1/1. The duty ratio 1/1 is described as the maximum value. Needless to say, in the driving method of the present invention, the maximum duty ratio may be set to 210/220 or the like. 220 represents the number of pixel rows of the QCIF + display panel.

  When the duty ratio = 1/1, the meaning of setting the lighting rate to 0% means that N-times pulse driving is not performed. This is because 1/1 is the maximum luminance display, and the program current writing is not improved by N-fold pulse driving. As the lighting rate becomes 100%, setting the duty ratio to 1 / n and increasing n does not contribute to the improvement of programming current writing. However, it is only implemented to reduce the power consumption of the panel. This can be easily understood since N-fold pulse driving does not include performing duty 1/1. According to the present invention, when the lighting rate is low (duty ratio approaches 1/1), the reference current is set to 1 or more, and the screen is brightened. This operation does not correspond to the implementation of N-fold pulse driving.

  The maximum duty ratio is preferably set to 1/1 and the minimum is preferably within 1/16. More preferably, the duty ratio is within 1/10. This is because the occurrence of flicker can be suppressed. The change range of the reference current is preferably within 4 times. More preferably, it is within 2.5 times. This is because if the multiple of the reference current is too large, the linearity of the reference current generating circuit is lost and white balance deviation occurs.

  Data sum / (maximum value of data sum) = 1/100 is, for example, 1/100 white window display. In a natural image, it means a state in which the data sum of pixels for image display can be converted to 1/100 of white raster display. Therefore, the display of one bright spot per 100 pixels also has a data sum / maximum value of 1/100.

  The above items apply not only to the EL panel or EL display device having the pixel configuration shown in FIG. 1, but also to the EL panel or EL display device having another pixel configuration such as those shown in FIGS. 2, 38, 43, and 46. Needless to say, you can.

  In the following description, the maximum value is an added value of white raster image data, but this is for ease of description. The maximum value is the maximum value generated in the image data addition processing or APL processing. Therefore, the data sum / maximum value is a ratio to the maximum value of the image data of the screen to be processed.

  Note that the data sum may be calculated based on current consumption or luminance. Here, for ease of explanation, it is assumed that luminance (image data) is added. In general, the method of adding luminance (image data) is easy to process, and the hardware scale of the controller IC can be reduced. Further, it is preferable because a flicker is not generated by duty ratio control and a wide dynamic range can be obtained.

  FIG. 89 shows an example in which the reference current control and the duty ratio control of the present invention are implemented. In FIG. 89, when the data sum / maximum value is 1/100 or less, the magnification of the reference current is changed to 3 times. The duty ratio is changed from 1/1 to 1/8 at 1/100 or more. Therefore, since the data sum / maximum value is 1/1 to 1/10000, the duty ratio control is 8 times, and the reference current control is 3 times, a change of 8 × 3 = 24 times is performed. Since both the reference current control and the duty ratio control change the screen brightness, a 24 times dynamic range is realized.

  When the data sum / maximum value is 1/1, the duty ratio is 1/8. Therefore, the display brightness is 1/8 of the maximum value. Since the data sum / maximum value is 1, it is a white raster display. That is, in white raster display, the display brightness is reduced to 1/8, the maximum. 1/8 of the screen 50 is the image display area 53, and the non-display area 52 occupies 7/8. In an image having a data sum / maximum value close to 1/1, most of the pixels 16 are in high gradation display. In terms of a histogram, the majority of data is distributed in the high gradation area of the histogram. In this image display, the image is crushed white and there is no sharpness. Therefore, a gamma curve n or a value close to n in FIG. 86 or the like is selected.

  When the data sum / maximum value is 1/100, the duty ratio is 1/1. The entire screen 50 is a display area 53. Therefore, N-fold pulse driving is not performed. The light emission luminance of the EL element 15 becomes the display luminance of the screen 50 as it is. Most of the image display is black display, and an image is partially displayed. In terms of an image, an image display with a data sum / maximum value of 1/100 is an image in which the moon appears in a dark night sky. Setting the duty ratio to 1/1 in this image means that the moon portion is displayed with a brightness 8 times the brightness of the white raster. Therefore, an image display with a wide dynamic range can be realized. Since the image is displayed in the 1/100 area, even if the luminance of the 1/100 area is increased by 8 times, the increase in power consumption is slight.

  In an image whose data sum / maximum value is close to 1/100, most of the pixels 16 are in low gradation display. In terms of a histogram, the majority of data is distributed in the low gradation area of the histogram. In this image display, the image is blacked out and there is no sharpness. For this reason, a gamma curve similar to b or b in FIG. 86 or the like is selected.

  As described above, the driving method of the present invention is a driving method that increases the x multiplier of gamma as the duty ratio increases. In this driving method, the x multiplier of gamma is reduced as the duty ratio is reduced.

  In FIG. 89, when the data sum / maximum value is 1/100 or less, the magnification of the reference current is changed to 3 times. When the data sum / maximum value is 1/100, the duty ratio is 1/1, and the screen brightness is increased by the duty ratio. As the data sum / maximum value becomes smaller than 1/100, the magnification of the reference current is increased. Therefore, the light emitting pixel 16 emits light with higher luminance. For example, a data sum / maximum value of 1/1000 is an image in which a star appears in a dark night sky when expressed as an image. Setting the duty ratio to 1/1 in this image means that the star portion is displayed with a brightness 8 × 2 = 16 times the brightness of the white raster. Therefore, an image display with a wide dynamic range can be realized. Since the image is displayed in the 1/1000 area, even if the luminance of the 1/1000 area is increased 16 times, the increase in power consumption is slight.

  The control of the reference current is that it is difficult to maintain white balance. However, in the image in which stars appear in the dark night sky, even if the white balance is shifted, the white balance shift is not visually recognized. From the above, the present invention in which the reference current control is performed in a range where the data sum / maximum value is very small is an appropriate driving method.

  When the data sum / maximum value is 1/1000, the duty ratio is 1/1. The entire screen 50 is a display area 53. Therefore, N-fold pulse driving is not performed. The light emission luminance of the EL element 15 becomes the display luminance of the screen 50 as it is. Most of the image display is black display, and an image is partially displayed.

  In an image having a data sum / maximum value close to 1/1000, most of the pixels 16 are in low gradation display. In terms of a histogram, the majority of data is distributed in the low gradation area of the histogram. In this image display, the image is blacked out and there is no sharpness. For this reason, a gamma curve similar to b or b in FIG. 86 or the like is selected.

  As described above, the driving method of the present invention is a driving method that increases the x multiplier of gamma as the reference current decreases. Further, this is a driving method in which the x multiplier of gamma is decreased as the reference current increases.

In FIG. 89, the change in the reference current and the change in the duty ratio control are illustrated linearly. However, the present invention is not limited to this. As shown in FIG. 90, the reference current magnification control and duty ratio control may be curved. In FIGS. 89 and 90, since the data sum / maximum value on the horizontal axis is a logarithm, it is natural that the lines of the reference current control and the duty ratio control become curves. The relationship between the data sum / maximum value and the reference current magnification and the relationship between the data sum / maximum value and the duty ratio control are preferably set in accordance with the contents of the image data, the image display state, and the external environment.
89 and 90 show an embodiment in which the RGB duty ratio control and the reference current control are made the same. The present invention is not limited to this. As shown in FIG. 91, the slope of the reference current magnification may be changed in RGB. In FIG. 91, the slope of the change in the reference current magnification for blue (B) is the largest, the slope of the change in the reference current magnification for green (G) is the next largest, and the change in the reference current magnification for red (R) is increased. The inclination is minimized. When the reference current is increased, the current flowing through the EL element 15 is also increased. The EL elements have different luminous efficiencies for RGB. Further, when the current flowing through the EL element 15 is increased, the light emission efficiency with respect to the applied current is deteriorated. In particular, the tendency is remarkable in B. Therefore, white balance cannot be achieved unless the reference current amount is adjusted in RGB. Therefore, as shown in FIG. 91, when the reference current magnification is increased (region where the current flowing through each RGB EL element 15 is large), it is effective to make the RGB reference current magnification different so that white balance can be maintained. is there. The relationship between the data sum / maximum value and the reference current magnification and the relationship between the data sum / maximum value and the duty ratio control are preferably set in accordance with the contents of the image data, the image display state, and the external environment.

  FIG. 91 shows an example in which the reference current magnification is varied between RGB. In FIG. 92, the duty ratio control is also different. The sum of data / maximum value is 1/100 or more, B and G are the same, and the slope of R is reduced. G and R are 1/100 or less and the duty ratio is 1/1, while B is 1/100 or less and the duty ratio is 1/2. The above driving method can be implemented by the driving method described with reference to FIGS. If driven as described above, RGB white balance adjustment can be optimized. The relationship between the data sum / maximum value and the reference current magnification and the relationship between the data sum / maximum value and the duty ratio control are preferably set in accordance with the contents of the image data, the image display state, and the external environment. Further, it is preferable that the user can set or adjust freely.

  FIGS. 89 to 91 show a method of changing the reference current magnification and the duty ratio with the sum of data / maximum value being 1/100 as an example. The reference current magnification and the duty ratio are changed with the data sum / maximum value as a boundary, so that the region where the reference current magnification changes and the region where the duty ratio changes do not overlap. With this configuration, it is easy to maintain white balance. That is, the duty ratio is changed when the data sum / maximum value is 1/100 or more, and the reference current is changed when the data sum / maximum value is 1/100 or less. The region where the reference current magnification is changed is not overlapped with the region where the duty ratio is changed. This method is a characteristic method of the present invention.

  Although the duty ratio is changed when the data sum / maximum value is 1/100 or more and the reference current is changed when the data sum / maximum value is 1/100 or less, the reverse relationship may be used. That is, the duty ratio may be changed when the data sum / maximum value is 1/100 or less, and the reference current may be changed when the data sum / maximum value is 1/100 or more. Also, the duty ratio is changed when the data sum / maximum value is 1/10 or more, the reference current is changed when the data sum / maximum value is 1/100 or less, and the data sum / maximum value is 1/100 or more and 1/10 or less. Then, the reference current magnification and the duty ratio may be set to constant values.

  In some cases, the present invention is not limited to the above method. As shown in FIG. 93, the duty ratio may be changed when the data sum / maximum value is 1/100 or more, and the B reference current may be changed when the data sum / maximum value is 1/10 or less. The reference current change of B and the duty ratio of RGB are overlapped with each other.

  When a bright screen and a dark screen are alternately repeated at a high speed, flicker occurs when the duty ratio is changed according to the change. Therefore, when changing from a certain duty ratio to another duty ratio, it is preferable to provide a hysteresis (time delay). For example, assuming that the hysteresis period is 1 sec, the previous duty ratio is maintained even if the screen brightness is bright and dark but is repeated a plurality of times within the 1 sec period. That is, the duty ratio does not change.

  This hysteresis (time delay) time is called Wait time. Also, the duty ratio before the change is called the pre-change duty ratio, and the duty ratio after the change is called the post-change duty ratio.

  When the duty ratio before change is small and changes to another duty ratio, flicker is likely to occur due to the change. The state where the duty ratio before change is small is a state where the data sum of the screen 50 is small or a state where there are many black display portions on the screen 50. Therefore, it is considered that the screen 50 has a halftone display and high visibility. In addition, in a region where the duty ratio is small, the difference from the change duty tends to increase. Of course, when the duty ratio difference increases, control is performed using the OEV2 terminal. However, OEV2 control also has a limit. From the above, when the duty ratio before change is small, it is necessary to lengthen the wait time.

  When the pre-change duty ratio is changed to another duty ratio, flicker due to the change is less likely to occur. The state where the duty ratio before change is large is a state where the data sum of the screen 50 is large or a state where there are many white display portions on the screen 50. Therefore, it seems that the entire screen 50 is white and the visibility is low. From the above, when the duty ratio before change is large, the wait time may be short.

  The above relationship is illustrated in FIG. The horizontal axis is the duty ratio before change. The vertical axis represents the wait time (seconds). When the duty ratio is 1/16 or less, the wait time is increased to 3 seconds (sec). When the duty ratio is 1/16 or more and the duty ratio is 8/16 (= 1/2), the wait time is changed from 3 seconds to 2 seconds in accordance with the duty ratio. When the duty ratio is 8/16 or more and the duty ratio is 16/16 = 1/1, the duty ratio is changed from 2 seconds to 0 seconds according to the duty ratio.

  As described above, the duty ratio control of the present invention changes the wait time according to the duty ratio. When the duty ratio is small, the wait time is lengthened, and when the duty ratio is large, the wait time is shortened. That is, in the driving method in which at least the duty ratio is variable, the duty ratio before the first change is smaller than the duty ratio before the second change, and the wait time of the first before-change duty ratio is the second It is characterized in that it is set longer than the wait time of the duty ratio before change.

  In the above embodiment, the wait time is controlled or specified based on the duty ratio before change. However, the difference between the pre-change duty ratio and the post-change duty ratio is slight. Therefore, in the above-described embodiment, the pre-change duty ratio may be read as the post-change duty ratio.

  In the above embodiment, the pre-change duty ratio and the post-change duty ratio have been described. Needless to say, when the difference between the pre-change duty ratio and the post-change duty ratio is large, it is necessary to increase the wait time. Needless to say, when the difference in duty ratio is large, it is preferable to change to the duty ratio after change via the duty ratio in the intermediate state.

  The duty ratio control method of the present invention is a driving method that takes a longer wait time when the difference between the pre-change duty ratio and the post-change duty ratio is large. That is, this is a driving method in which the wait time is changed in accordance with the difference in duty ratio. Further, this is a driving method in which the wait time is increased when the difference in duty ratio is large.

  The duty ratio method of the present invention is a driving method characterized in that when the duty ratio difference is large, the duty ratio is changed to the changed duty ratio via the duty ratio in the intermediate state.

  In the example of FIG. 94, the wait time with respect to the duty ratio is assumed to be the same for R (red), G (green), and B (blue). However, it goes without saying that the present invention may change the wait time in RGB as shown in FIG. This is because the visibility is different between RGB. By setting the wait time according to the visibility, a better image display can be realized.

  Data sum / (maximum value of data sum) = 1/100 is, for example, 1/100 white window display. In a natural image, it means a state in which the data sum of pixels for image display can be converted to 1/100 of white raster display. Therefore, the display of one bright spot per 100 pixels also has a data sum / maximum value of 1/100.

  In the following description, the maximum value is an added value of white raster image data, but this is for ease of description. The maximum value is the maximum value generated in the image data addition processing or APL processing. Therefore, the data sum / maximum value is a ratio to the maximum value of the image data of the screen to be processed.

  However, the sum of data does not require accurate addition of data for one screen. An addition value of one screen may be estimated (predicted) from an addition value of pixel data obtained by sampling one screen. The same applies to the maximum value. Also, predicted values or estimated values from a plurality of fields or a plurality of frames may be used. In addition to the addition of image data, the APL level of video data may be obtained by a low-pass filter circuit, and this APL level may be used as the data sum. The maximum value at this time is the maximum value of the APL level when video data having the maximum amplitude is input.

  Note that the data sum may be calculated based on the current consumption of the display panel or the luminance. Here, for ease of explanation, it is assumed that luminance (image data) is added. In general, the process of adding luminance (image data) is easy.

  In FIG. 197, the horizontal axis represents the data sum / maximum value. The maximum value is 1. The vertical axis represents the DUTY ratio. Data sum = maximum value (data sum / maximum value = 1) is the maximum white display state in all pixel rows. When the data sum / maximum value is small, the screen is dark or has a small image display area. At this time, the DUTY ratio is increased. Therefore, the luminance of the pixel displaying the image is high. For this reason, the dynamic range of the image is expanded and high-quality display is performed. When the data sum / maximum value is large (the maximum value is 1), the screen is a bright screen or a wide image display area. At this time, the DUTY ratio is reduced. Therefore, the luminance of the pixel displaying the image is low. Therefore, power consumption can be reduced. Since the amount of light emitted from the screen is large, the image does not feel dark.

  In FIG. 197, the DUTY ratio value reached when the data sum / maximum value is 1.0 is changed. For example, when the duty ratio is 1/2, 1/2 of the screen is in the image display state. Therefore, the image is bright. When DUTY ratio = 1/8, 1/8 of the screen is in the image display state. Therefore, the brightness is 1/4 compared with DUTY ratio = 1/2.

  In the driving method of the present invention, the image luminance is controlled by the data sum or the like, and the dynamic range is expanded. In addition, high contrast display is realized.

  In the liquid crystal display panel, white display and black display are determined by the transmittance from the backlight. Even when a non-display area is generated on the screen as in the driving method of the present invention, the transmittance in black display is constant. On the contrary, when the non-display area is generated, the white display luminance in one frame period is lowered, so that the display contrast is lowered.

  In the EL display panel, black display is a state in which the current flowing through the EL element is zero. Therefore, even when a non-display area is generated on the screen as in the driving method of the present invention, the luminance of black display is zero. When the area of the non-display area is increased, the white display luminance is lowered. However, since the luminance of black display is 0, the contrast is infinite. Therefore, a good image display can be realized.

  In the driving method of the present invention, the number of gradations is maintained over the entire gradation range, and white balance is maintained over the entire gradation range. Further, the luminance change of the screen can be changed nearly 10 times by the DUTY ratio control. Further, since the change has a linear relationship with the DUTY ratio, the control is easy. Further, R, G, and B can be changed at the same ratio. Therefore, the white balance is maintained at any duty ratio.

  The relationship between the data sum / maximum value and the DUTY ratio is preferably set according to the content of the image data, the image display state, and the external environment. Further, it is preferable that the user can set or adjust freely.

  The above switching operation displays the display screen very brightly when the power of a mobile phone, a monitor, etc. is turned on. After a certain period of time, the display brightness is reduced to save power. Use. It can also be used as a function for setting the brightness desired by the user. For example, when outdoors, the screen is very bright. This is because the surroundings are bright outdoors and the screen cannot be seen at all. In other words, the curve a in FIG. 197 is selected outdoors. However, if display is continued with high luminance, the EL element deteriorates rapidly. For this reason, when it is very bright, it is configured to return to normal luminance in a short time. For example, normally, the curve of c is selected. Furthermore, when displaying with high brightness, the display brightness can be increased by the user pressing the button.

  Therefore, it is preferable that the user can be switched with a button, can be automatically changed in a setting mode, or can be switched automatically by detecting the brightness of external light. Further, it is preferable that the display brightness is set to 50%, 60%, and 80% and can be set by the user. Further, it is preferable that the duty ratio curve, inclination, etc. are rewritten by an external microcomputer or the like. Further, it is preferable that one can be selected from a plurality of stored duty curves.

  Needless to say, it is preferable to select the DUTY ratio curve in consideration of the APL level, maximum luminance (MAX), minimum luminance (MIN), and luminance distribution state (SGM).

  As described above, for example, a is an outdoor curve. c is an indoor curve. b is a curve for an intermediate state between indoor and outdoor. Switching between the curves a, b, and c is performed by the user operating the switch. Alternatively, the brightness of outside light may be detected by a photo sensor and automatically switched. Although the gamma curve is switched, the present invention is not limited to this. It goes without saying that a gamma curve may be generated by calculation.

  The DUTY ratio in FIG. 197 is a straight line, but is not limited to this. As shown in FIG. 198, it may be a one-point folding curve.

  When the image data sum is small, the c curve in FIG. 198 is selected. The effect of reducing power consumption is exhibited. There is no degradation of image display. When the image data sum is large, the a curve is selected. The image display is not bright and the occurrence of flicker is reduced.

  In another embodiment of the present invention, the DUTY ratio is changed in a range where the data sum / maximum value is 1/10 or more (see FIG. 199). This is because an image whose data sum / maximum value is close to 1 is rarely generated, and when the data sum / maximum value is up to 1 and the DUTY ratio is changed as shown in FIG. More preferably, the change of the DUTY ratio is performed in a range where the data sum / maximum value is 8/10 or more.

  In FIG. 199, when the data sum / maximum value is 0.9 or less, the DUTY ratio is changed from 1 to 1/5. Therefore, a dynamic range of 5 times is realized.

  When the data sum / maximum value is 0.9 or more, it is 1/5. Therefore, the display brightness is 1/5 of the maximum value. Data sum / maximum value = 1 is white raster display. That is, in white raster display, the display brightness is reduced to 1/5, which is the maximum.

  When the data sum / maximum value is 0.1 or less, the DUTY ratio is 1/1. 1/10 of the screen is a display area. The light emission luminance of the EL element becomes the display luminance of the pixel as it is. Most of the image display is black display, and an image is partially displayed. In terms of an image, an image display with a data sum / maximum value of 0.1 or less is an image in which the moon appears in a dark night sky. Setting the DUTY ratio to 1/1 in this image means that the moon portion is displayed with a luminance five times that of the white raster. Therefore, an image display with a wide dynamic range can be realized. Since the image is displayed in the 1/10 area, even if the brightness of the 1/10 area is increased 5 times, the increase in power consumption is slight.

  In an image having a data sum / maximum value close to 0, most of the pixels are in low gradation display. In terms of a histogram, the majority of data is distributed in the low gradation area of the histogram. In this image display, the image is blacked out and there is no sharpness. Therefore, the dynamic range of the black display part is widened by controlling the gamma curve.

  In the above embodiment, when the data sum / maximum value is 0, the DUTY ratio is set to 1. However, the present invention is not limited to this. Needless to say, the DUTY ratio may be smaller than 1 as shown in FIG. Further, the curve of the DUTY ratio may be a curve as shown in FIG.

  As shown in FIG. 202, the DUTY ratio curve may be changed for red (R), green (G), and blue (B) pixels. In FIG. 202, the slope of the blue (B) DUTY ratio change is the largest, the slope of the green (G) DUTY ratio change is the next largest, and the slope of the red (R) DUTY ratio change is the largest. It is small. If driven as described above, RGB white balance adjustment can be optimized. The relationship between the data sum / maximum value and the DUTY ratio is preferably set according to the content of the image data, the image display state, and the external environment. Further, it is preferable that the user can set or adjust freely.

  When a bright screen and a dark screen are alternately repeated at a high speed, flicker occurs when the DUTY ratio is changed according to the change. Therefore, when changing from one DUTY ratio to another DUTY ratio, it is preferable to change by providing hysteresis (time delay) as shown in FIG. For example, assuming that the hysteresis period is 1 sec, the previous DUTY ratio is maintained even if the screen brightness is bright and dark but is repeated a plurality of times within the 1 sec period. That is, the DUTY ratio does not change.

  This hysteresis (time delay) time is called Wait time. Further, the DUTY ratio before the change is called a pre-change DUTY ratio, and the DUTY ratio after the change is called a post-change DUTY ratio.

  When the pre-change DUTY ratio is changed to another DUTY ratio, flicker is likely to occur due to the change. The state where the DUTY ratio before change is small is a state where the data sum of the screen is small or a state where there are many black display portions on the screen.

  Therefore, it seems that the screen is halftone and the visibility is high. In addition, in a region where the DUTY ratio is small, the difference from the change DUTY ratio tends to increase. Of course, when the difference in DUTY ratio becomes large, control is performed using OEV. However, OEV control also has a limit. From the above, when the DUTY ratio before change is small, it is necessary to lengthen the wait time.

  When the pre-change DUTY ratio is changed to another DUTY ratio, flicker due to the change is less likely to occur. The state where the DUTY ratio before change is large is a state where the data sum of the screen is large or a state where there are many white display portions on the screen. Therefore, it seems that the entire screen is white and the visibility is low. From the above, when the DUTY ratio before change is large, the wait time may be short.

  The above relationship is illustrated in FIG. The horizontal axis is the pre-change DUTY ratio. The vertical axis represents the wait time (seconds). When the DUTY ratio is 1/16 or less, the wait time is increased to 3 seconds (sec). When the DUTY ratio is 1/16 or more and the DUTY ratio is 8/16 (= 1/2), the wait time is changed from 3 seconds to 2 seconds in accordance with the DUTY ratio. When the DUTY ratio is 8/16 or more and the DUTY ratio is 16/16 = 1/1, the DUTY ratio is changed from 2 seconds to 0 seconds in accordance with the DUTY ratio.

  As described above, the DUTY ratio control of the present invention changes the wait time according to the DUTY ratio. When the DUTY ratio is small, the wait time is lengthened, and when the DUTY ratio is large, the wait time is shortened. That is, in the driving method in which at least the DUTY ratio is variable, the DUTY ratio before the first change is smaller than the DUTY ratio before the second change, and the wait time of the first DUTY ratio before the second change is The DUTY ratio before change is set longer than the wait time.

  In the above embodiment, the wait time is controlled or specified based on the pre-change DUTY ratio. However, the difference between the pre-change DUTY ratio and the post-change DUTY ratio is slight. Therefore, the before-change DUTY ratio may be read as the after-change DUTY ratio in the above-described embodiment.

  Further, in the above embodiment, the description has been made based on the pre-change DUTY ratio and the post-change DUTY ratio. Needless to say, when the difference between the pre-change DUTY ratio and the post-change DUTY ratio is large, it is necessary to increase the wait time. Needless to say, when the difference in the DUTY ratio is large, it is preferable to change to the post-change DUTY ratio via the intermediate DUTY ratio.

  The DUTY ratio control method of the present invention is a driving method that takes a longer wait time when the difference between the pre-change DUTY ratio and the post-change DUTY ratio is large. That is, this is a driving method in which the wait time is changed in accordance with the difference in the DUTY ratio. Further, this is a driving method in which the wait time is lengthened when the difference in the DUTY ratio is large.

  The DUTY ratio method of the present invention is a driving method characterized in that when the difference in DUTY ratio is large, the DUTY ratio is changed to the post-change DUTY ratio via the intermediate DUTY ratio.

  In the above embodiments, the wait time for the DUTY ratio is described as being the same for R (red), G (green), and B (blue). However, needless to say, the present invention may change the wait time by R, G, and B. This is because the visibility is different between RGB. By setting the wait time according to the visibility, a better image display can be realized.

  The above embodiment is an embodiment related to duty ratio control. It is preferable to set the wait time for the reference current control. FIG. 96 shows an example.

  When the reference current is small, the screen 50 is dark, and when the reference current is large, the screen 50 is bright. That is, when the reference current magnification is small, it can be rephrased as a halftone display state. When the reference current magnification is high, the image display state is high brightness. Therefore, when the reference current magnification is low, the wait time needs to be increased because the visibility to changes is high. On the other hand, when the reference current magnification is high, the wait time may be short because the visibility to the change is low. Therefore, as shown in FIG. 96, the Wait time with respect to the reference current magnification may be set.

  It is desirable that the reference current magnification with respect to the data sum can be changed from the outside of the panel module. Changes from the outside may be written into the memory of the panel module control circuit 839 (see FIGS. 83 and 205 and the description thereof) using a microcomputer or the like.

  FIG. 224 is an explanatory diagram of a method of changing the reference current magnification. The horizontal axis of FIG. 224 is an address number. Address numbers are from 0 to 511, and are 9 bits. Further, although the horizontal axis is an address, it may be considered that it corresponds to the data sum / maximum value described with reference to FIGS. That is, when data sum = maximum value, data sum / maximum value = 1. It may be considered that this state corresponds to address 511. When data sum × 2 = maximum value, data sum / maximum value = ½. It may be considered that this state corresponds to address 255.

  Data (reference current magnification) for each address is sequentially rewritten by data values applied to the address bus and the data bus as shown in FIG.

  The reference current on the vertical axis varies depending on the memory state. A solid line a shows a case where the reference current magnification is not changed to 1 regardless of the address value. In the dotted line b, when the data sum is large (the entire screen 50 is close to white display), the reference current is not changed from 1, and when the data sum is small (whether the screen 50 is close to black display or display In a state where there are few pixels), the change in the reference current is increased. Therefore, the dynamic range of image display is expanded. In the d-dot chain line c-line, the change is made constant when the data sum is large to small.

  As described above, the applicability of the driving method of the present invention is expanded by rewriting the reference current magnification. In FIG. 224, the data for each address is rewritten so that the lines become a, b, and c. However, the present invention is not limited to this. ) May be stored and controlled to be selected and switched.

  FIG. 226 is an explanatory diagram of a method for changing the duty ratio. The horizontal axis in FIG. 226 is an address number. Address numbers range from 0 to 255, and are 8 bits. Further, although the horizontal axis is an address, it may be considered that it corresponds to the data sum / maximum value described with reference to FIGS. That is, when data sum = maximum value, data sum / maximum value = 1. It may be considered that this state corresponds to address 255. When data sum × 2 = maximum value, data sum / maximum value = ½. It may be considered that this state corresponds to address 127. The data (duty ratio) for each address is sequentially rewritten by data values applied to the address bus and the data bus as shown in FIG.

  The reference current on the vertical axis varies depending on the memory state. A solid line a shows a case where the duty ratio is not changed to 1 regardless of the address value. In the dotted line b, when the data sum is large (when the entire screen 50 is close to white display), the duty ratio is not changed from 0.2, and when the data sum is small (whether the screen 50 is close to black display) In the state where the number of displayed pixels is small), the change in the duty ratio is increased. Therefore, the dynamic range of image display is expanded. In the d-dot chain line c-line, the change is made constant when the data sum is large to small.

  As described above, the applicability of the driving method of the present invention is expanded by rewriting the duty ratio. In FIG. 226, the data for each address is rewritten so as to be the a, b, and c lines. However, the present invention is not limited to this. ) May be stored and controlled to be selected and switched. Needless to say, FIG. 224 and FIG. 226 may be implemented in combination with each other.

  In the present invention, data sum or APL is calculated (detected), and duty ratio control and reference current control are performed based on these values. FIG. 98 is a flowchart for obtaining the duty ratio and the reference current magnification.

  As shown in FIG. 98, a rough APL is calculated for the input image data (a temporary APL is calculated). The value of the reference current and the reference current magnification are determined from this APL. The determined reference current and reference current magnification are converted into electronic volume data and applied to the source driver circuit 14.

  On the other hand, image data is input to a gamma processing circuit, and gamma characteristics are determined. APL is calculated from the image data processed with the gamma characteristic. The duty ratio is determined from the calculated APL. Next, the duty pattern is determined based on whether the image is a moving image or a still image. The duty pattern is a distribution state of the non-display area 52 and the display area 53. In the case of a moving image, the non-display area 52 is inserted at a time. In the case of a still image, the non-display area 52 is dispersed and inserted. Therefore, in the case of a still image, the non-display area 52 and the display area non-display area 52 are converted into a duty pattern to be inserted in a distributed manner. In the case of a moving image, the non-display area 52 is converted into a duty pattern to be inserted at once. The converted pattern is applied as a start pulse ST (see FIG. 6) of the gate driver circuit 12b.

  94 and FIG. 95 explain that the wait time is controlled according to the duty ratio, and FIGS. 89 to 93 explain that the duty ratio control is performed according to the data sum. FIG. 103 is a detailed explanatory diagram for further performing duty ratio control and wait time. However, for ease of explanation, the time factor and the like are reduced and expressed.

  In FIG. 103, the top row shows frame (field) numbers. The second row shows the APL level (data sum corresponds). The third row shows the corresponding duty ratio calculated from the APL level. The bottom row shows a duty ratio (processing duty ratio) obtained by correcting the wait time. That is, according to the APL level of each frame, the corresponding duty ratio (third stage) is 8/64 → 9/64 → 9/64 → 10/64 → 9/64 → 10/64 → 11/64 → 11/64 → 12 / 64 → 14/64 →...

  For the corresponding duty ratio, the processing duty ratio is 8/64 → 8/64 → 9/64 → 9/64 → 9/64 → 10/64 → 10/64 → 11/64 → considering the wait time. 12/64 → 12/64 →...

  In FIG. 103, the corresponding duty ratio is corrected based on the wait time. In addition, the processing duty ratio is an integer for the numerator (FIG. 107 compares the numerator with a decimal point). In FIG. 103, the driving is performed so that the change of the duty ratio is smooth and the flicker is hardly generated. In FIG. 103, the corresponding duty ratios are changed to 9/64, 10/64, and 9/64 in frames 3, 4, and 5, but the wait time control is performed, and the processing duty ratio is 9/64, 9 / 64 and 9/64 (corrected portions are indicated by dotted lines in frame 4). In FIG. 103, the corresponding duty ratios are changed to 12/64, 14/64, and 11/64 in frames 9, 10, and 11, but the wait time control is performed, and the processing duty ratio is 12/64. , 12/64, and 11/64 (corrected portions are indicated by dotted lines in the frame 10). By performing the wait time control as described above, the duty ratio control is provided with hysteresis (time delay or low-pass filter) so that the duty ratio does not change even if the APL level changes rapidly.

  The duty ratio control as described above need not be completed in one frame or one field. Duty ratio control may be performed in a period of several fields (several frames). In this case, the duty ratio is an average value of several fields (several frames) as the duty ratio. Even when the duty ratio control is performed in several fields (several frames), the period of several fields (several frames) is preferably 6 fields (six frames) or less. This is because flicker may occur when the value exceeds this value. Also, the number field (several frames) is not an integer, and may be 2.5 frames (2.5 fields). That is, it is not limited to a field (frame) unit.

  FIG. 104 shows an example in which the duty ratio control is performed in several fields (several frames). FIG. 104 illustrates the concept when several fields (several frames) are performed. M is a length for performing duty ratio control. If one field (one frame) has 256 pixel rows, M = 1024 corresponds to four fields (4 frames). That is, FIG. 104 shows an embodiment in which the duty ratio control is performed with 4 fields (4 frames).

  M indicates a data string held in the shift register 61b of the virtual gate driver 12b (see FIG. 6). The retained data string retains data (on / off voltage) indicating whether the voltage applied to the gate signal line 17b is an off voltage or an on voltage. The average value of the retained data string indicates the duty ratio. In FIG. 104, it is needless to say that M = N. In addition, it goes without saying that the duty ratio control may be performed in a relationship of M <N in some cases.

  For example, in the retained data string of M = 1024, if the on-voltage data is 256 and the off-voltage is 768, the duty ratio is 256/1024 = 1/4. Note that the distribution state of the on-voltage data is held together when the display image is a moving image, and the distribution state of the on-voltage data is held dispersedly when the display image is a still image.

  That is, the on / off voltage data string is virtually applied sequentially to the gate signal line 17b of the EL display panel. By sequentially applying the on / off voltage, the EL display panel is subjected to duty ratio control and is reported with a predetermined brightness.

  FIG. 105 is a block diagram of a circuit configuration for realizing the duty ratio control of FIG. First, the video signal (image data) is converted into a luminance signal by the Y conversion circuit 1051. Next, the APL operation circuit 1052 determines the APL level (data sum or data sum / maximum value). Based on this APL level, the duty ratio is calculated in units of fields (frames), and the result is stored in the stack 1053. The stack circuit 1053 has a first in first out configuration. Note that the duty ratio is corrected by the wait time control and stored in the stack circuit 1053. The duty ratio data stored in the stack 1053 is applied as an ST pulse (see FIG. 6) of the shift register 61b by the parallel / serial conversion (P / S) circuit 1054, and depends on the order of the applied data. The gate driver circuit 12b outputs the on / off voltage of the gate signal line 17b.

  In the above embodiment, the duty ratio control is performed in the field or frame. However, the present invention is not limited to this. For example, one frame = 4 fields, and duty ratio control may be performed in units of a plurality of fields. By performing duty ratio control using a plurality of fields, it is possible to realize a smooth image display in which no flicker occurs.

  In FIG. 106, 1-1 indicates the first field of one frame, 1-2 indicates the second field of one frame, 1-3 indicates the third field of one frame, and 1-4 indicates This means the fourth field of one frame. 2-1 means the first field of two frames.

  When the duty ratio is changed from 128/1024 to 132/1024, it is 128/1024 for 1-1, 129/1024 for 1-2, 130/1024 for 1-3, 131/1024 for 1-4, 2- 1 is changed to 132/1024. Due to the above change, it gradually changes from 128/1024 to 132/1024.

  When the duty ratio is changed from 128/1024 to 130/1024, 128/1024 for 1-1, 128/1024 for 1-2, 129/1024 for 1-3, 129/1024 for 1-4, 2- 1 is changed to 130/1024. Due to the above changes, the speed gradually changes from 128/1024 to 130/1024.

  When the duty ratio is changed from 128/1024 to 136/1024, 128/1024 for 1-1, 130/1024 for 1-2, 132/1024 for 1-3, 134/1024 for 1-4, 2- 1 is changed to 136/1024. Due to the above changes, the speed gradually changes from 128/1024 to 136/1024.

  The numerator of the duty ratio in the field (frame) duty ratio control need not be an integer. For example, as shown in FIG. 107, control may be performed so that the number is after the decimal point. The numerator can be easily achieved by controlling the OEV2 terminal. In addition, by using the average duty ratio in a plurality of frames (fields), it is possible to generate a fractional fraction in the denominator of the duty ratio. Conversely, a fractional part may be generated in the denominator of the duty ratio. In FIG. 107, the numerator is set to a decimal point such as 30.8 or 31.2. It should be noted that the decimal point can be eliminated by setting the denominator and numerator to a large integer greater than a certain value.

  The above items apply not only to the EL panel or EL display device having the pixel configuration shown in FIG. 1, but also to the EL panel or EL display device having another pixel configuration such as those shown in FIGS. 2, 38, 43, and 46. Needless to say, you can.

  The duty ratio pattern is changed between the moving image and the still image. If the duty ratio pattern is suddenly changed, an image change may be recognized. Also, flicker may occur. This problem occurs due to the difference between the duty ratio of the moving image and the duty ratio of the still image. In the moving image, a duty pattern for inserting the non-display area 52 at once is used. For a still image, a duty pattern in which the non-display area 52 is inserted in a distributed manner is used. The ratio of the area of the non-display area 52 / the screen area 50 is the duty ratio. However, even if the duty ratio is the same, human visibility varies depending on the dispersion state of the non-display area 52. This is thought to be due to the dependence on human video response.

  In the intermediate moving image, the non-display area 52 has a distribution state that is intermediate between the distribution state of the moving image and the distribution state of the still image. Note that a plurality of intermediate moving images may be prepared, and selected from a plurality of intermediate moving images corresponding to the moving image state or the still image state before the change. Examples of the plurality of intermediate moving image states include a configuration in which the non-display area is distributed in a manner close to that of the moving image display, and the non-display area 52 is divided into three. On the contrary, a state in which the non-display area is dispersed in a large number like a still image is illustrated.

  Some still images are bright and some are dark. The same applies to videos. Therefore, it is only necessary to determine which intermediate moving image state is to be changed according to the state before the change. In some cases, a moving image may be transferred to a still image without going through an intermediate moving image. You may transfer from a still image to a moving image without going through an intermediate moving image. For example, an image with low brightness on the screen 50 does not feel strange even if the moving image display and the still image display move directly. Further, the display state may be shifted via a plurality of intermediate moving image displays. For example, the state may be changed from the duty state of the moving image display to the duty ratio state of the intermediate moving image display 1 and further to the duty state of the intermediate moving image display 2 and then to the duty state of the still image display.

  As shown in FIG. 108, when moving from the moving image display to the still image display, the intermediate moving image state is passed. Also, the display is shifted from the still image display to the moving image display via the intermediate moving image display. It is preferable to set a wait time for the transition time of each state.

  FIG. 110 shows the duty ratio and the number of non-display area dispersions when moving a moving image, a still image, and an intermediate moving image. In FIG. 110, when the moving image still image level is 0, the image display is the moving image level, and when it is 1, the image display is in the quasi-moving image (intermediate moving image) state. In the case of 2, it indicates that the image display is in a still image state.

  The division number is the division number of the non-display area 52. 1 indicates that the non-display area 52 is collectively inserted into the screen. 30 indicates that the non-display area 52 is divided into 30 and inserted. Similarly, 50 indicates that the non-display area 52 is divided into 50 and inserted. As described before, the duty ratio shows the luminance reduction rate of white display. That is, a duty ratio of 1/2 indicates that the display state is 1/2 of the maximum white luminance.

  As illustrated in FIG. 110, the moving image still image level is changed through an intermediate moving image (quasi moving image) state when moving from a moving image to a still image and when moving from a still image to a moving image.

  As shown in FIG. 111, it is preferable to provide a wait time for the time from the moving image to the still image. The wait time may be determined according to the moving image ratio. The number of different data on the horizontal axis in FIG. 110 indicates the ratio of moving images detected by moving image detection between a certain frame and the next frame. That is, the horizontal axis represents the ratio of pixels that are calculated between frames and that have different image data. Therefore, the larger the numerical value, the closer to the moving image display. In FIG. 110, the closer to the moving image display, the longer the wait time is secured.

  The above items apply not only to the EL panel or EL display device having the pixel configuration shown in FIG. 1, but also to the EL panel or EL display device having another pixel configuration such as those shown in FIGS. 2, 38, 43, and 46. Needless to say, you can.

The precharge drive has been described with reference to FIGS. 288 to 291 and the like. The application of the precharge voltage is preferably linked to the lighting rate or the duty ratio. It is preferable not to apply the precharge voltage to a place where it is not necessary. This is because a decrease in brightness of white display may occur. Therefore, it is preferable that application of the precharge voltage is limited.
The precharge driving is performed in order to eliminate the phenomenon that the white display portion crosstalks downward, particularly in the current driving method. Therefore, this crosstalk is conspicuous in an image having a lot of black display portions on the screen and partly displaying white. This is because if the entire screen 50 is displayed in white, it is not visually recognized even if crosstalk occurs. Therefore, it is not necessary to perform precharge driving.

  The present invention reduces the duty ratio when the lighting rate is high (the screen 50 has a large amount of white display as a whole). That is, n of duty1 / n is increased. When the lighting rate is low (the screen 50 has a large number of black display portions as a whole), the duty is increased. That is, it approaches to duty 1/1. Therefore, there is a correlation between the duty ratio and the lighting rate. Of course, the lighting rate (data sum / maximum value) is obtained from the video data, and the duty ratio control is performed from the lighting rate.

  As shown in FIG. 294 (a), there is a relationship between the duty ratio and the lighting rate (%). FIG. 294 (b) shows a precharge on / off state. In FIG. 294 (b), precharge driving is set at a duty ratio of 80% or more. However, even if the precharge drive is used, the precharge drive of the present invention includes an all precharge mode, an adaptive precharge mode, a 0 grayscale precharge mode, and a selective grayscale precharge mode. Therefore, in FIG. 294 (b), the point is that the precharge drive is set to be performed, and the drive state differs depending on which precharge is performed. What is important is to change whether or not to perform precharge driving depending on the duty ratio or the lighting rate.

  There is also a correlation between the duty ratio or lighting rate (%) and gamma control. 301 and 302 are explanatory diagrams thereof. FIG. 301 (a1) is an explanatory diagram in the case of an image with many gradation displays. That is, the image has a low lighting rate. In FIG. 301 (a1), the horizontal axis represents the gradation number, and the vertical axis represents the frequency generated at each gradation. For example, FIG. 301 (a1) shows that a certain display image has 250 display pixels for the 10th gradation, and 400 display pixels for the 7th gradation. The number of display pixels beyond the 15th gradation is very small.

  FIG. 295 shows the duty ratio with respect to the lighting rate. In the image display of FIG. 301 (a1), since the lighting rate of the display image is close to 0%, the duty ratio is approximately 1/1. The gradation is proportional to the luminance. Therefore, as shown in FIG. 301 (a2), the frequency corresponding to the gradation number (= luminance) is displayed on the vertical axis in each gradation. Then, as shown in FIG. 301 (a2), it can be seen that the display can be performed from the lower gradation to the higher gradation.

  FIG. 301 (b1) is an explanatory diagram in the case of an image with many high gradation displays. That is, the image has a high lighting rate. Similar to FIG. 301 (a1) in FIG. 301 (b1), the horizontal axis represents the gradation number, and the vertical axis represents the frequency generated at each gradation. For example, FIG. 301 (b1) shows that a certain display image has 100 display pixels in the 50th gradation, and 400 display pixels in the 56th gradation. The number of display pixels smaller than the 45th gradation is very small.

  FIG. 295 shows the duty ratio with respect to the lighting rate. In the image display of FIG. 301 (b1), if the lighting rate of the display image is close to 100%, the duty ratio is approximately 1/4. The gradation is proportional to the luminance. Therefore, as shown in FIG. 301 (b2), the frequency with respect to the gradation number (= luminance) is displayed on the vertical axis in each gradation. Then, as shown in FIG. 301 (b2), the image is completely crushed in the low gradation region.

  In FIG. 301 (b), since the gradation display of the image is crushed and the image has no resolution, it is necessary to change the gamma curve. That is, it is necessary to increase the coefficient, which is a multiplier of the gamma curve, to make the gamma curve steep.

  From the above, in the present invention, the coefficient of the gamma curve is changed according to the lighting rate or the duty ratio. FIG. 302 is an explanatory diagram thereof.

  The present invention reduces the duty ratio when the lighting rate is high (the screen 50 has a large white display portion as a whole). That is, n of duty1 / n is increased. When the lighting rate is low (the screen 50 has a large number of black display portions as a whole), the duty is increased. That is, it approaches to duty 1/1. Therefore, there is a correlation between the duty ratio and the lighting rate. Of course, the lighting rate (data sum / maximum value) is obtained from the video data, and the duty ratio control is performed from the lighting rate.

  As shown in FIG. 302A, it is assumed that there is a relationship between the duty ratio and the lighting rate (%). In the graph of FIG. 302 (b), the vertical axis indicates the coefficient of the gamma curve. In FIG. 302 (b), the gamma curve coefficient is set to be large when the duty ratio is 70% or more. That is, the gradation expression is increased in the high gradation region so that the gamma curve becomes steep. Therefore, the whiteout image is improved.

  Note that as shown in FIG. 343, increasing the gamma coefficient in a small region where the duty ratio is smaller than a certain value may improve the image display.

  Further, in order to describe the duty ratio control, the power supply circuit of the organic EL display device of the present invention will be described. FIG. 112 is a block diagram of the power supply circuit of the present invention. Reference numeral 1122 denotes a control circuit. The midpoint potential of the resistors 1125a and 1125b is controlled, and the gate signal of the transistor 1126 is output. The power source Vpc is applied to the primary side of the transformer 1121, and the primary side current is transmitted to the secondary side by the on / off control of the transistor 1126. 1123 is a rectifier diode, and 1124 is a smoothing capacitor.

  FIG. 201 is a block diagram of the power supply circuit of the present invention. Reference numeral 1122 denotes a control circuit. By applying on / off control to the transistor 1775, the current flowing through the coil 1771 and the drive waveform are changed, and the charge charged in the capacitor 1774 is controlled. The midpoint potential of the resistors 1125a and 1125b is controlled, and the gate signal of the transistor 1126 is output. The Vdd voltage (anode voltage) can be changed by changing the resistance value of the resistor. Since the voltage is generated by the coil (transformer) 1771, the cathode voltage (Vss) also changes due to the change in the anode voltage. That is, as the anode voltage (Vdd) increases, the cathode voltage (Vss) also shifts.

  For example, consider a case where the anode voltage (Vdd) is 6 (V) and the cathode voltage (Vss) is −6 (V). When the anode voltage (Vdd) is changed to 9 (V) by 3 (V), the cathode voltage (Vss) is shifted from −6 (V) to −3 (V). This is an effect that the input side and the output side of the transformer 1121 are insulated.

  The current-driven organic EL display panel has the following characteristics from the viewpoint of potential. In the pixel configuration of the present invention, as described in FIG. 1 and the like, the driving transistor 11a is a P-channel transistor. The unit transistor 484 of the source driver 14 that generates the program current is an N-channel transistor. With this configuration, the program current is a sink current (sink current) that flows from the pixel 16 toward the source driver IC (circuit) 14. Therefore, the potential operation is performed with the anode (Vdd) as the origin. That is, since the program to the pixel 16 is a current, the potential of the source driver IC (circuit) 14 may be any as long as a driving voltage margin is secured.

  The control circuit 1122 is controlled by a logic circuit such as a controller. Therefore, it is necessary to match the grounds of the control circuit 1122 and the logic circuit. However, the transformer 1121 is separated from the input side and the output side. The current program type source driver IC (circuit) 14 acts on the output side and operates based on the anode potential (Vdd). Therefore, the ground of the source driver IC (circuit) 14 does not need to match the ground of the control circuit 1122 and the logic circuit. At this point, the source driver IC 14 is of a current programming system, and generates an anode voltage (Vss) using the transformer 1122 (if further applied, generates a cathode voltage (Vss) based on the anode voltage (Vdd)). The combination that the driving transistor 11a of the pixel 16 is a P channel exhibits a synergistic effect.

  The organic EL display panel operates with absolute values of the anode (Vdd) and the cathode (Vss). For example, when Vdd = 6 (V) and Vss = −6 (V), the operation is performed at 6 − (− 6) = 12 (V). In the power supply circuit using the transformer 1121 of the present invention in FIG. 112, the cathode voltage (Vss) changes with the anode (Vdd) as a reference. The anode voltage (Vdd) is the reference position of the program current of the current-driven source driver IC (circuit) 14 of the present invention. That is, it operates with the anode voltage (Vdd) as the origin. Conversely, the potential or control of the cathode voltage (Vss) may be rough. Also for this reason, the power supply circuit of the present invention using the transformer of FIG. 112, the organic EL panel having the current-driven pixel 16 configuration, and the current-programmed source driver IC (circuit) 14 exhibit a synergistic effect. I understand that. It is also important that the cathode voltage shifts due to changes in the anode voltage.

  In the organic EL panel, the current Idd that flows from the anode Vdd into the driving transistor 11a and the current Iss that flows from the EL element 15 to the cathode Vss substantially match. That is, there is a relationship of Idd = Iss. Actually, Idd> Iss, but since this difference is the program current of the source driver IC (circuit) 14, it is negligible and can be ignored. 112 and 177, the current output from the anode Vdd and the current drawn from the cathode Vss are identical in configuration. Also in this respect, the synergistic effect of the combination of the organic EL panel and the power supply circuit using the transformer 1121 of the present invention is great.

  Needless to say, when the driving transistor 11a of the pixel 16 is an N-channel transistor, the same effect can be obtained if the unit transistor 484 of the source driver IC (circuit) 14 is a P-channel transistor.

  It is efficient to generate the Vgh voltage, Vgl voltage of the gate driver circuit 12, the power supply voltage of the source driver circuit, etc. from the cathode voltage (Vss) or (and) the anode voltage (Vdd). Further, the transformer 1121 may have a four-terminal configuration of two input terminals and two output terminals, or as shown in FIG. 112, it is desirable that the input two terminals and the output be a middle point and have three terminals. The transformer 1121 includes a single-winding transformer (coil).

  The power source Vpc is applied to the primary side of the transformer 1121, and the primary side current is transmitted to the secondary side by the on / off control of the transistor 1126. 1123 is a rectifier diode, and 1124 is a smoothing capacitor.

  The output voltage of the anode voltage Vdd is adjusted by the resistor 1125b. Vss is a cathode voltage. As shown in FIG. 178, the cathode voltage Vss is configured to select and output two voltages. Selection is performed with the switch 1781. The generation of two voltages (−9 (V) and −6 (V) in FIG. 178) as the cathode voltage can be easily generated by providing an intermediate tap on the output side of the transformer 1121. Further, two windings for −9 (V) and −6 (V) are formed on the output side of the transformer 1121, and it can be generated more easily by selecting one of these windings. This is also an excellent point of the present invention. In addition, FIG. 178 is characterized in that the cathode voltage (Vss) is switched. If the anode is changed as the potential origin, the circuit configuration becomes complicated and the cost increases. On the other hand, the cathode voltage (Vss) does not affect the image display even if a potential error of about 10% occurs (insensitive). Therefore, it is an excellent feature of the present invention that the cathode voltage is set based on the anode voltage and the cathode voltage (Vss) is changed in accordance with the temperature characteristics of the panel. In addition, the transformer 1121 has many advantages in that the cathode voltage and the anode voltage can be easily changed by changing the ratio between the number of input windings and the number of output windings. It is also advantageous to change the anode voltage (Vdd) by changing the switching state of the transistor 1776. In FIG. 178, −9 (V) is selected by the switch 1781.

  In FIG. 178, the cathode voltage Vss is selected from two voltages, but is not limited to this and may be two or more. The cathode voltage may be continuously changed using a variable regulator circuit.

  The selection of the switch 2021 is based on the output result from the temperature sensor 701. When the panel temperature is low, -9 (V) is selected as the Vss voltage. When the panel temperature is above a certain level, -6 (V) is selected. This is because the EL element 15 has a temperature characteristic, and the terminal voltage of the EL element 15 increases on the low temperature side. In FIG. 178, one voltage is selected from two voltages to be Vss (cathode voltage). However, the present invention is not limited to this, and the Vss voltage can be selected from three or more voltages. May be. The above matters are similarly applied to Vdd. The present invention is also characterized in that the cathode voltage (Vss) is lowered at low temperatures below a certain level.

  In FIG. 178, the cathode voltage is switched (changed) by the temperature sensor 701. However, the present invention is not limited to this. For example, as shown in FIG. 177, a variable resistor (posistor, thermistor, etc.) is formed or arranged in parallel or in series with a resistor 1775 that determines the output voltage, and the resistance value can be changed depending on the temperature as a whole. May be.

  As shown in FIG. 178, the power consumption of the panel can be reduced by configuring so that a plurality of voltages can be selected depending on the panel temperature. This is because the Vss voltage may be lowered when the temperature is below a certain temperature. Usually, Vss = −6 (V) having a low voltage can be used. Note that the switch 2021 may be configured as illustrated in FIG. The generation of a plurality of cathode voltages Vss can be easily realized by taking out an intermediate tap from the transformer 1121 in FIG. The same applies to the anode voltage Vdd. As an example, the configuration of FIG. 179 is illustrated. In FIG. 179, a plurality of cathode voltages are generated using an intermediate tap of a transformer 1771.

  FIG. 180 is an explanatory diagram of potential setting. In this example, for ease of explanation, the source driver IC 14 will be described on the basis of GND. The power source of the source driver IC 14 is Vcc. Vcc may match the anode voltage (Vdd). In the present invention, Vcc <Vdd is set from the viewpoint of power consumption. Preferably, the Vcc voltage of the source driver IC (circuit) preferably satisfies the relationship of Vdd−1.5 (V) <= Vcc <= Vdd. For example, if Vdd = 7 (V), Vcc preferably satisfies the condition of Vdd−1.5 = 5.5 (V) to 7 (V). The Vcc voltage is the maximum voltage for operating the switch 481 in FIGS. 48 and 166.

  The off voltage Vgh of the gate driver circuit 12 is set to be equal to or higher than the Vdd voltage. Preferably, the relationship of Vdd + 0.2 (V) <= Vgh <= Vdd + 2.5 (V) is satisfied. For example, if Vdd = 7 (V), Vgh satisfies the condition of 7 + 0.2 = 7.2 (V) or more and 7 + 2.5 = 9.5 (V) or less. The above conditions apply to both the pixel selection side (transistors 11b and 11c in the pixel configuration of FIG. 1) and the EL selection side (transistor 11d in the pixel configuration of FIG. 1).

  The on-voltage Vgl of the switching transistor that generates a program current path with the driving transistor 11a (corresponding to the transistors 11b and 11c in the pixel configuration of FIG. 1) is Vdd-Vdd or lower and Vdd-Vdd-4. It is preferable to satisfy the condition of (V) or substantially coincide with the cathode voltage Vss. Similarly, the ON voltage on the EL selection side (which corresponds to the transistor 11d in the pixel configuration of FIG. 1) is the same. That is, if the anode voltage is 7 (V) and the cathode voltage is -6 (V), the on-voltage Vgl is 7-7 (V) = 0 (V) or less. 7-7-4 = -4 (V) It is preferable to be in the range. Alternatively, the on voltage Vgl is preferably substantially equal to the cathode voltage and is set to −6 (V) or the vicinity thereof.

  Note that when the driving transistor 11a of the pixel 16 is an N-channel transistor, Vgh is an on-voltage. In this case, it goes without saying that the off voltage may be replaced with the on voltage.

  A problem of the power supply circuit of the present invention is that Vgh, Vgl voltage, etc. are generated from the anode voltage Vdd and / or the cathode voltage Vss. An anode voltage or the like is generated by the transformer 1121, and DCDC converter Vgh and Vgl voltages are applied from this voltage.

  However, Vgh and Vgl are control voltages for the gate driver circuit 12, and if these voltages are not applied, the transistor 11 of the pixel will be in a floating state. Further, if there is no Vcc voltage, the source driver IC (circuit) 14 is also in a floating state, causing malfunction. Therefore, as shown in FIG. 181, it is necessary to apply the Vdd and Vss voltages after applying the Vgh, Vgl, and Vcc voltages to the panel, after the lapse of T1 time, or simultaneously.

  The present invention solves this problem with the configuration shown in FIG. In FIG. 182, reference numeral 1783a denotes a power supply circuit including a transformer 1121 and the like. Reference numeral 1783b denotes a power supply circuit that receives the voltage from the power supply circuit 1783a and generates Vgh, Vgl, Vcc voltage, and the like, and includes a DCDC converter circuit, a regulator circuit, and the like. Reference numeral 1821 denotes a switch. This applies to thyristors, mechanical relays, electronic relays, transistors, analog switches, and the like.

  In FIG. 182 (a), the power supply circuit 1783a first generates an anode voltage (Vdd) and a cathode voltage (Vss). When this occurs, the switch 1821a is open. Therefore, the anode voltage (Vdd) is not applied to the display panel. The anode voltage (Vdd) and the cathode voltage (Vss) generated in the power supply circuit 1783a are applied to the power supply circuit 1783b, and Vgh, Vgl, and Vcc voltages are generated in the power supply circuit 1783b and applied to the display panel. After applying the Vgh, Vgl, and Vcc voltages to the display panel, the switch 1821a is turned on (closed), and the anode voltage (Vdd) is applied to the display panel.

  In FIG. 182 (a), only the anode voltage (Vdd) is blocked by the switch 1821a. This is because if the anode voltage (Vdd) is not applied, a path for applying a current to the EL element 15 is not generated, and a path for flowing to the source driver IC (circuit) 14 is not generated. Therefore, the display panel does not malfunction or float.

  Of course, as shown in FIG. 182 (b), the voltage applied to the display panel may be controlled by on / off controlling both of the switches 1821a and 1821b. However, the switches 1821a and 1821b must be closed at the same time, or control must be performed so that the switch 1821b is closed after the switch 1821a is closed.

  The above is the configuration in which the switch 1821 is formed or arranged at the Vdd terminal of the power supply circuit 1783a. FIG. 183 shows a configuration in which the switch 1821 is not formed or arranged. The anode voltage (Vdd) and the Vgh voltage are approximated, and the anode voltage (Vdd) and the Vcc voltage are approximated. If the Vgh voltage is applied, the gate driver 12 turns off the gate signal lines 17a and 17b. It is utilized that Vgh is applied and the transistor 11 (transistor 11b, transistor 11c, and transistor 11d in the configuration of FIG. 1) is turned off. If the transistor 11 is in the OFF state, no current path flows from the driving transistor 11a to the EL element 15, and no program current path flows from the driving transistor 11a to the source driver IC (circuit) 14. The display panel does not malfunction or malfunction.

  When the anode voltage (Vdd) and the Vgh voltage are approximate, even if the resistor 1831a is short-circuited, almost no current flows through the resistor. Therefore, almost no power loss occurs. For example, if the anode voltage (Vdd) = 7 (V), Vgh = 8 (V), and the resistance 1831a is 10 (KΩ), then (8−7) /10=0.1, so that the resistance 1831a Is 0.1 (mA). Vgh is an off voltage. Further, since the voltage is output from the gate driver circuit 12, the current used is small. The present invention takes advantage of this property. That is, the gate signal line 17 can be held at the off voltage (Vgh) or a potential in the vicinity thereof by the resistor 1831a in which the anode voltage (Vdd) terminal and the Vgh terminal are short-circuited. Therefore, a current path flowing from the anode voltage (Vdd) to the EL element 15 does not occur, and an abnormal operation does not occur in the display panel. Needless to say, the shift register 61 (see FIG. 6) of the gate driver circuit 12 is operated to control the off voltage (Vgh) to be output from all the gate signal lines 17.

  Thereafter, the power supply circuit 1783b is fully operated, and the prescribed Vgh voltage, Vgl voltage, and Vcc voltage are output from the power supply circuit 1783b.

  Similarly, when the anode voltage (Vdd) and the Vcc voltage are approximate, even if the resistor 1831b is short-circuited, almost no current flows through the resistor. Therefore, almost no power loss occurs. For example, if the anode voltage (Vdd) = 7 (V), Vcc = 6 (V), and the resistance 1831a is 10 (KΩ), then (7−6) /10=0.1, so that the resistance 1831b Is 0.1 (mA). Vcc is a voltage used in the source driver IC (circuit) 14, but the current consumed by Vcc is on / off of the shift register circuit of the source driver circuit 14 and the switch 481 (see FIGS. 48 and 166). It is a grade used for control, and is slight.

  The present invention takes advantage of this property. That is, current can be prevented from flowing into the unit transistor 484 by turning off the switch 481 of the source driver circuit 14 by the resistor 1831b in which the anode voltage (Vdd) terminal and the Vcc terminal are short-circuited. . Therefore, since a current path from the anode voltage (Vdd) to the source signal line 18 does not occur, no abnormal operation occurs in the display panel. Needless to say, the shift register of the source driver circuit 14 is operated so that the current paths of the unit transistors 484 are disconnected from all the source signal lines 17.

  In FIG. 183, the cathode voltage (Vss) terminal and the Vgl terminal may be short-circuited with a resistor (not shown). Due to the short circuit of the resistor, the cathode voltage (Vss) is applied to the Vgl terminal when the cathode voltage (Vss) is generated. Therefore, the gate driver circuit 12 operates normally.

  In FIG. 183, the Vgh terminal is short-circuited by the resistor 1831 at the anode voltage (Vdd). However, when the driving transistor 11a is an N-channel transistor, the anode voltage (Vdd) and the Vgl terminal or the cathode voltage (Vss) are used. Needless to say, the Vgl terminal and the Vgl terminal are short-circuited.

  Although the anode voltage (Vdd) and the Vgh voltage, and the anode voltage (Vdd) and the Vcc voltage are short-circuited (connected) with a relatively high resistance, the present invention is not limited to this. The resistor 1831 may be replaced with a switch such as a relay or an analog switch. That is, the relay is closed when the anode voltage (Vdd) is generated. Therefore, an anode voltage (Vdd) is applied to the Vgh terminal and the Vcc terminal. Next, when a Vgh voltage, a Vhl voltage, a Vcc voltage, or the like is generated in the power supply circuit 1783b, the relay is opened, and the anode voltage (Vdd) and the Vgh terminal, and the anode voltage (Vdd) and the Vcc terminal are disconnected.

  The transformer 1121 is relatively high. Therefore, as shown in FIG. 206, it is mounted on a substrate 83 disposed at a position facing the source driver IC 14. The board 83 is attached to the chassis 2061 to improve heat dissipation from the transformer 1121 and the like. Chip components 2063 such as chip capacitors and chip resistors are mounted on the substrate 83. A panel module operation button 2062 is arranged on the front surface of the transformer 1121.

  Countermeasures for heat generation from the EL display panel are important. As a countermeasure against heat generation, a chassis 2061 made of a metal material is attached to the back surface of the panel (the surface from which light from the display screen 50 does not appear) (see FIG. 206). In order to improve heat dissipation, the chassis 2061 is formed with irregularities (not shown). In addition, an adhesive layer is disposed between the chassis 2061 and the sealing lid 85 in the panel. A material having good thermal conductivity is used for the adhesive layer. For example, a paste made of silicon resin or silicon material is exemplified. These are often used as an adhesive (adhesive) between the regulator IC and the heat sink. Note that the adhesive layer is not limited to the function of adhering, and may be only the function of closely attaching the chassis and the panel.

  In the organic EL display panel, an EL element 15 is formed (arranged) between the anode Vdd and the cathode Vss. An anode Vdd voltage and a cathode Vss voltage are supplied from the power supply circuit of FIG. When the EL element 15 does not emit light, the current flowing between the anode and the cathode is zero. In the duty ratio control of the present invention, the on / off voltage of the gate signal line 17b is applied for each pixel row, and the current control of the EL element 15 is performed. Further, the position of the gate signal line 17b to which the ON voltage is applied is scanned. For example, FIG. 97 shows an embodiment in which the non-display area 52 is divided into four. 97 (a), (b), (c), and (d), the size of the non-display area 52 is different. However, the non-display area 52 is scanned (moved) from the upper part to the lower part of the screen 50. Similarly, the display area 53 is scanned downward from the top of the screen 50. No current flows through the EL element 15 of the pixel 16 corresponding to the non-display area 52. On the other hand, a current flows through the EL element 15 of the pixel 16 corresponding to the display region 53.

  Here, in order to explain the problem, a display pattern in which the non-display area 52 and the display area 53 are repeated for each pixel row is illustrated. This display state is a black and white horizontal stripe display. That is, the odd pixel rows are displayed in white and the even pixel rows are displayed in black. This display pattern is called one horizontal stripe.

  A state in which the number of pixel rows is 220 pixel rows and the duty ratio is 110/220 is illustrated. The duty ratio 110/220 is a state in which an on voltage and an off voltage are applied to the gate signal line 17b for each pixel row. Further, the position of the gate signal line 17b to which the on voltage or the off voltage is applied is scanned in synchronization with the horizontal synchronizing signal. Therefore, if attention is paid to the gate signal line 17b of a certain pixel row, the on-voltage application state and the off-voltage application state are alternately repeated on the gate signal line 17b in synchronization with the horizontal synchronization signal. Considering the entire screen 50, an on-voltage is applied to even-numbered pixel rows. During this period, an off voltage is applied to the odd-numbered pixel rows. A turn-on voltage is applied to the odd-numbered pixel rows after one horizontal scanning period. During this period, an off-voltage is applied to the even pixel rows.

  In one horizontal stripe display in which the odd pixel rows are displayed in white and the even pixel rows are displayed in black, a current flows from the power supply circuit to the display region when an ON voltage is applied to the odd pixel rows. However, when the on-voltage is applied to the even-numbered pixel row, the even-numbered pixel row displays black, so that no current flows from the power supply circuit to the display area. Therefore, the power supply circuit repeats the operation of supplying current and the operation of not supplying current at every horizontal scanning period. This operation is not preferable for the power supply circuit. This is because a transient phenomenon occurs in the power supply circuit and the power supply efficiency deteriorates.

  A driving method for solving this problem is shown in FIG. In FIG. 100, the duty ratio is not halved, a plurality of duty ratio states are generated in the screen 50, and control is performed so that a current always flows even in one horizontal stripe display.

  100 (a) and 100 (b) generate a duty ratio 1/2, a duty ratio 1/1, and a duty ratio 1/3, and realize the duty ratio 1/2 as a whole (average of one frame period). Yes. As described above, by combining a plurality of duty ratios in one frame period, the output current from the power supply circuit is not turned on / off even in the case of one horizontal stripe display. That is, many regular display patterns such as one horizontal stripe are often displayed. In contrast, when duty ratio control is performed using a duty ratio pattern in which the widths of the non-display areas 52 are equally spaced, a load is likely to occur on the power supply circuit. Therefore, it is preferable to drive so that a plurality of duty ratio patterns are generated on the screen 50 simultaneously. Moreover, it is preferable that the duty ratio pattern is not a single duty ratio pattern but a predetermined duty ratio as an average of one frame or a full number frame (field).

  In FIG. 100, needless to say, the duty ratio pattern is scanned from the top to the bottom of the screen 50 as shown in FIG. In the duty ratio control method of the present invention, the scanning position is moved for each pixel row in synchronization with the horizontal synchronization signal. However, the present invention is not limited to this. For example, the scanning position may be moved by a plurality of pixel rows in synchronization with the horizontal synchronization signal. Further, the scanning direction is not limited from the top to the bottom of the screen 50. For example, the first field may be scanned from the top of the screen 50 downward, and the second field may be scanned from the bottom of the screen 50 upward.

  FIG. 100 shows a driving method in which an ON voltage is applied and an OFF voltage is applied to each gate signal line 17b in one discrete pixel row. However, the present invention is not limited to this. FIG. 101a) shows the driving state of FIG. Driving that achieves the same screen 50 brightness can be realized with the duty ratio pattern of FIG. In FIG. 101B, pixel rows to which an on voltage or an off voltage are applied are continuous.

  There are a variety of duty ratio patterns for realizing the same screen 50 luminance. As shown in FIG. 102 (a), there is a pattern in which the non-display area 52 is dispersed very much, and there is a pattern in which the dispersion state of the non-display area 52 is relatively reduced as shown in FIG. The pattern in FIG. 102 (a) is the same if the duty ratio of the pattern in FIG. 102 (b) is reduced. Therefore, the brightness of the screen 50 can be made the same.

  There is a close relationship between duty ratio control and power supply capacity. The power supply size increases as the maximum power supply capacity increases. In particular, when the display device is mobile, a large power source becomes a serious problem. EL has a proportional relationship between current and luminance. In black display, no current flows. The maximum current flows in the white raster display. Therefore, the change in current due to the image is large. When the change in current is large, the power supply size increases and the power consumption increases.

  In the present invention, when the lighting rate is high, 1 / n of duty control is increased to reduce current consumption (power consumption). Conversely, when the lighting rate is low, the duty ratio is set to 1 or close to 1 so that the maximum luminance is displayed. This control method will be described below.

  First, the relationship between the lighting rate (data sum / maximum value) and the duty ratio is shown in FIG. It is assumed that the lighting rate is converted by the current flowing through the panel as described above. This is because, in the EL display panel, the light emission efficiency of B is poor, and thus when the display of the sea is displayed, the power consumption increases at a stretch. Therefore, the maximum value is the maximum value of the power supply capacity. The data sum is not a simple addition value of video data, but video data converted into current consumption. Therefore, the lighting rate is also obtained from the current used for each image with respect to the maximum current.

  FIG. 295 shows an example in which the duty ratio is 1/1 when the lighting rate is 0%, and the minimum duty ratio is 1/4 when the lighting rate is 100%. FIG. 296 shows the result of multiplication of power and lighting rate. If the lighting rate is 0 to 100% in FIG. 295 and the duty ratio is constantly 1/1, the curve indicated by a in FIG. 296 is obtained. The vertical axis in FIG. 296 is the ratio of power used to the power supply capacity (power ratio). That is, in the curve a, the lighting rate and the power consumption are in a proportional relationship. Therefore, when the lighting rate is 0%, the power consumption is 0 (power ratio 0), and when the lighting rate is 100%, the power consumption is 100 (power ratio 100%).

  A curve b in FIG. 296 is an example in which power limitation is performed with the duty ratio curve in FIG. 295. Since the duty ratio is 1/4 when the lighting rate is 100%, the power ratio is 25% of 1/4 compared to the curve a. The curve b is operating in a range smaller than the electric power 1/3. Therefore, when duty ratio control is performed as shown in FIG. 295, 1/3 of the power supply capacity is sufficient as compared with the conventional case (curve a). That is, in the present invention, the power supply size can be reduced as compared with the conventional one. Further, if the lighting rate continues to be high in the prior art (curve a), the current flowing through the panel is large, and the panel is deteriorated due to heat generation. However, in the present invention in which the duty ratio control is performed, an average current flows through the panel regardless of the lighting rate, as can be seen from the curve b. Therefore, there is little heat generation and the panel does not deteriorate.

  In the duty ratio curve of FIG. 295, an example in which the minimum duty ratio is halved is a curve c. Further, the curve d is an example in which the minimum duty ratio is 1/3. Similarly, the example is curve e with a minimum duty ratio of 1/8.

  In FIG. 295, the duty ratio curve is a straight line. However, the duty ratio curve can be generated by a wide variety of straight lines or curves. For example, FIG. 297 (a1) is a duty ratio control curve such that the power ratio is 30% or less (see FIG. 297 (a2)). FIG. 297 (b1) is a duty ratio control curve so that the power ratio is 20% or less (see FIG. 297 (b2)).

  The duty ratio control curve allows the user to freely switch between FIGS. 297 (a) and (b) with a button according to the external environment. When the external environment is bright, the duty ratio curve shown in FIG. 297 (a1) is selected. When the external environment is dark, the duty ratio curve shown in FIG. 297 (b1) is selected. Further, it is preferable that the duty ratio control curve is configured to be freely changed.

When changing the power consumption of EL, the method of FIG. 298 (b) is also effective. FIG. 298 (a) shows an example of a duty ratio control curve with a duty ratio of 1/1 and 300 (nt) at this time. This method has relatively high power. FIG. 298 (b) is an improvement method of FIG. 298 (a). The duty ratio is 1/1 (150 (nt) in the example) and the screen current is improved by increasing the reference current in the region where the lighting rate is low (300 (nt) in the example). As described above, in the present invention, it is effective to use the duty ratio control and the reference current control in combination.
As described with reference to FIG. 296, the power source capacity can be reduced as compared with the conventional case by the duty ratio control of the present invention. However, the power supply capacity may be exceeded when the display state of the screen changes suddenly. For example, as shown in FIG. 299, from a dark night view (assuming that it is operating in FIG. 299 (a), duty 1/1) to a bright beach (assuming that it is operating in FIG. 299 (b), duty 1/4). It is a change.

  As described above, the duty change is slowly changed to prevent the occurrence of flicker. Basically, the current consumed by each image data is sequentially added, and the duty ratio is changed by the average value of the addition (referred to as average control). Therefore, even if the night view of FIG. 299 (a) changes to the beach screen of FIG. 299 (b), the duty ratio is maintained for a certain period. For this reason, when a beach image is displayed in a state where the duty ratio 1/1 in FIG. 299 (a) is maintained, the current used changes suddenly and exceeds the power supply capacity.

  In response to this problem, the present invention monitors the current used for the display image in real time. When the monitored current exceeds the power capacity, emergency processing is performed so that the power capacity is not exceeded. It is easy to obtain the current used (power used) in real time. All the image data is simply converted into current and the sum is obtained. FIG. 300 shows this control method.

  In FIG. 300 (a), when it is determined that the current used on the duty 1/1 screen exceeds the power supply capacity by real-time control, black insertion is performed as shown in FIG. 300 (b). Therefore, it is maintained without exceeding the power source capacity. For example, if the power ratio is allowed up to 50% and the duty ratio of the power ratio 50% is ½, when the power ratio becomes 50%, the control shifts to the control in FIG. In this case, the black insertion screen is a ½ area, and the area having a duty ratio of 1/1 (maximum white raster) is a ½ area.

  In the above state, as shown in FIG. 300C, when the beach image is displayed on the entire screen, it is displayed with the maximum duty ratio 1/2. This is the real control (emergency processing). Thereafter, the process shifts to the averaging process, where the duty ratio is gradually lowered and settles at a duty ratio of 1/4 as shown in FIG. 300 (d).

  The EL display panel has a problem that an image is burned due to deterioration of the EL element 15. In particular, images are easy to burn in with a fixed pattern. In order to cope with this problem, the present invention includes a sub-image display area 50b (sub-screen) for displaying a fixed pattern. The display area 50a (main screen) is a moving image display area such as a television image.

  In the EL display panel of the present invention shown in FIG. 147, the gate driver circuit 12 is common to the sub screen 50b and the main screen 50a. The sub screen 50a has 20 pixel rows or more. Therefore, as an example, the screen 50 includes 220 pixel rows of the main screen 50a and 24 pixel rows of the sub screen 50b. The number of pixel columns is 176 × RGB (see FIG. 148).

  The main screen 50a and the sub screen 50b may be clearly separated as shown in FIG. In FIG. 149, a space BL is provided between the main screen 50a and the sub screen 50b. The space BL is an area where the pixels 16 are not formed.

  Note that W / L (W is the channel width of the driving transistor and L is the channel length of the driving transistor) of the driving transistor 17a of the pixels on the main screen (main panel) and the sub screen (subpanel) may be changed. . Basically, the W / L of the sub screen (sub panel) is increased. Further, the size of the pixel 16a of the main screen (main panel) 50a and the size of the pixel 16b of the sub screen (sub panel) 50b may be changed. Alternatively, the anode power or cathode power of the main screen (main panel) 50a and the anode voltage Vdd or the cathode voltage Vss of the sub screen (sub panel) 50b may be different voltages, and the applied voltage may be changed.

  Further, when the sub panel 71a and the main panel 71a are used as shown in FIG. 150B, the buffer is provided between the sealing substrate (sealing thin film layer) 85a and the sealing substrate (sealing thin film layer) 85b. A sheet 1504 is disposed or formed. Examples of the buffer sheet 1504 include a plate or sheet made of metal such as magnesium alloy, and a plate or sheet made of resin such as polyester.

  As shown in FIG. 147, FIG. 148, FIG. 149, FIG. 150, etc., in an EL display device composed of a plurality of screens, the N-fold pulse drive (duty ratio control drive) described in FIG. 14, FIG. Thus, the brightness of the plurality of screens 50 can be easily changed.

  In order to change the luminance of the plurality of screens 50, the gate driver 12b for selecting the EL side is separated for each screen 50 as shown in FIG. The gate drivers 12b1 and 12b2 share the CLK signal line (see CLK in FIG. 6). Therefore, the time for the gate driver 12b of the screen 50a and the screen 50b to select one pixel row is the same (the shift time of the gate driver 12b is the same (one horizontal scanning period is the same)).

  On the other hand, in the start signal line (ST), the gate driver 12b1 and the gate driver 12b2 are separate (see ST in FIG. 6). That is, the start signal line ST1 is input to the gate driver 12b1, and the start signal line ST2 is input to the gate driver 12b2. As the number of start pulses applied to the start signal line ST increases, the duty ratio increases (closes to 1), and thus the brightness of the screen 50 increases. On the contrary, since the duty ratio with a small number of start pulses applied to the start signal line ST becomes small (approaching 0), the brightness of the screen 50 becomes low.

  From the above, the number of signal lines can be reduced by sharing the clock (CLK) signal lines of the gate drivers 12b1 and 12b2. By separating the start signal lines of the gate driver 12b1 and the gate driver 12b2, the luminance control of the screen 50 is facilitated. Therefore, it is easy to adjust the brightness of the screen 50a and the screen 50b.

  As shown in FIG. 150, a sub panel 71b for displaying the sub screen 50b may be provided separately. The main panel 71a and the sub panel 71b are connected to the source signal lines 18a and 18b by a flexible substrate 84. A connection wiring 1503 is formed on the flexible substrate 84. An analog switch group including analog switches 1501 is disposed at the end of the source signal line 18a. The analog switch 1501 controls whether or not the current signal from the source driver circuit 14 is supplied to the sub panel 71b.

  In order to perform on / off control of the analog switch 1501, a switch control line 1502 is formed. The signal supply to the sub-panel is controlled by a logic signal to the switch control line 1502, and an image is displayed.

  Note that the gate signal line 17 is formed on the WR side as described with reference to FIG. 9 without forming the gate driver circuit or the gate driver IC chip on the sub-panel 71b, and the lighting control line 401 described with reference to FIG. May be formed or arranged (see FIG. 151).

  The analog switch 1501 is preferably a CMOS type in which a P channel and an N channel are combined as shown in FIG. An inverter 1521 is arranged in the middle of the switch control line 1502 to control the switch 1501 on and off. Further, as shown in FIG. 153, the analog switch 1501b may be formed of only the P channel.

  When the number of source signal lines 18 is different between the sub panel 71b and the main panel 71a, the configuration may be as shown in FIG. The outputs of the analog switches 1501a and 1501b are shorted and connected to the same terminal 1322a. Further, as shown in FIG. 155, the output of the analog switch 1501b may be connected to the Vdd voltage so as not to be turned on. Further, as illustrated in FIG. 156, analog switches 1501a (1501a1 and 1501a2) may be disposed or formed at the end of the source signal line 18 that is not required to be connected to the sub-panel 71b. The analog switch 1501a is configured to apply an off voltage and not turn on.

  Burn-in occurs when an image does not change for a certain period or longer. In the present invention, when the data sum is small, the DUTY ratio is increased to expand the dynamic range. However, if the data sum is small, image sticking occurs if the still image is displayed continuously. In order to solve this problem, it is only necessary to detect that a still image is displayed for a certain period of time and reduce the DUTY ratio or reduce the reference current. The present invention is a driving method for changing (decreasing) a duty ratio or (and) a reference current when a still image state continues for a certain period.

  The problem is how to detect how still images are continuous. Still detection can be realized by taking a difference in image data between frames or fields. However, in order to obtain a difference between frames, a frame memory is required. In the present invention, this problem is solved by performing a difference operation on image data of only sample points of image data. 204 and 205 are explanatory diagrams thereof.

  In FIG. 204, the image data constituting the screen 50 is sampled at regular intervals, the sum of the sampled image data (the sum is executed by the SUM circuit 2051) is obtained, and then compared with the sum of the image data of the frames. If the sums match or are similar in size, it is a still image. The determination is made in units of several seconds or tens of seconds. That is, the comparison of the sum (performed by the comparison circuit 2052) is performed for each frame (field) (of course, it may be performed at a plurality of frames or field intervals). In some cases, the comparison result may be determined as a still image, but if the DUTY ratio or the reference current is not changed immediately and continues for a certain period or longer, the fixed pattern is displayed and the DUTY ratio or the reference current is displayed. To change.

  In the embodiment, the sum of the sampled image data is taken and compared. However, the present invention is not limited to this, and it goes without saying that a difference may be taken for each pixel data to detect whether it is a still image. . The difference is preferably calculated between adjacent pixels. Of course, it goes without saying that still image detection may be performed by accumulating an image for each frame in the frame memory and performing an inter-frame calculation.

  In FIGS. 89, 90, 224, and 295, the case where the reference current is 1 is described as a reference, and the maximum duty ratio is 1/1. However, the present invention is not limited to this. For example, as shown in FIG. 383, the reference current may be changed to 1 or 1/3 with 1/2 as the center. The maximum may be set to 0.5. The duty ratio may also be changed to 0.5 or less around 0.25. Moreover, 0.5 may be set as the maximum.

  Further, as illustrated in FIG. 355, the minimum value of the reference current may be set to 1, and the maximum value may be set to 3, so that the reference current may be changed into a plurality of values. Further, as shown in FIG. 357, it is needless to say that the duty ratio may be controlled to be the lowest at 80% of the lighting rate and to be increased at 100% or 60%.

  As shown in FIG. 356, the reference current may be changed to 3 or 1 with 2 at the center. The maximum may be 3. Needless to say, the duty ratio may be changed to 0.25 or the like with 0.5 being the maximum. The same applies to FIG. 336.

  Also, as shown in FIG. 404, the duty is reduced in the low lighting rate region (lighting rate of 20% or less in FIG. 404) (FIG. 404 (a)), and the reference current ratio is increased as the duty decreases. (FIG. 404 (b)) may be used. By performing the duty ratio control and the reference current ratio control at the same time as described above, there is no change in brightness as shown in FIG. 404 (c).

  In FIG. 404, in the region where the lighting rate is high (40% or more in FIG. 404), the duty ratio is decreased, but the reference current ratio is kept constant at 1. Therefore, since the luminance decreases as the duty ratio decreases, the power consumption of the panel can be controlled (basically reduced).

  In the driving method in which the maximum duty ratio is 1/1, it is preferable to insert the non-display area 52 in a lump as shown in FIG. 358 (a) shows a state with a duty ratio of 1/1, FIG. 358 (b) shows a state with a duty ratio of 0.7, FIG. 358 (c) shows a state with a duty ratio of 0.6, and FIG. (D) is a state with a duty ratio of 0.5.

  In the present invention, the precharge driving method has been described. The concept of lighting rate was also explained. It is also effective to change the precharge voltage depending on the lighting rate. Note that the lighting rate is synonymous with current consumption when duty control is not performed. That is, the lighting rate is derived by adding image data. This is because in the case of current driving, image data and power consumption are proportional, and the lighting rate is derived from the image data.

  Precharge drive is similar to voltage drive. This is because a voltage is applied to the source signal line 18 and a precharge voltage is applied to the gate voltage of the driving transistor 11a to prevent the driving transistor 11a from flowing a current to the EL element 15. Therefore, the reference for the precharge voltage is the anode potential (Vdd).

  When the anode potential changes, it is necessary to change the precharge voltage. As shown in FIG. 385, the anode wiring 2681 is lowered in resistance so that the anode potential (Vdd) does not change. However, when the lighting rate is high, the amount of current flowing through the anode wiring 2681 is large, and thus a voltage drop occurs. The voltage drop is proportional to the current consumption. Therefore, the voltage drop of the anode voltage is proportional to the lighting rate.

  From the above, it is preferable to change the precharge voltage in correlation with the lighting rate. The source driver circuit of the present invention includes an electronic volume 451 as shown in FIG. Therefore, the precharge voltage can be easily changed by controlling the electronic volume 451. Needless to say, the precharge voltage may be generated and applied not only by the electronic volume control 451 but also by a DA circuit outside the source driver IC (circuit) 14.

  The voltage drop generated at the anode terminal can be grasped by the following processing. First, the resistance value from the anode voltage source to each pixel is known at the stage of design. This is because the resistance value is determined from the sheet resistance value of the metal thin film of the anode wiring 2681. The current consumption flowing through the anode terminal 2681 can be determined by processing the video data. 83, 84, 98, 201, 205, 295, 296, 298, etc., as described above, as derivation of duty ratio, data sum, lighting rate (= data sum / maximum value), etc. explained. The ability to easily derive the current flowing through the anode is a major feature of the current programming method.

  Therefore, if the resistance value of the anode wiring 2681 and the current flowing through the anode wiring 2681 (panel consumption current) are known, the voltage drop generated at the anode terminal can be known. The current consumption is derived in real time by processing one frame of image data. Therefore, the voltage drop of the anode terminal in the pixel 16 is also determined in real time.

  From the above, the anode voltage at the pixel 16 (in consideration of the voltage drop) is derived in real time, and the precharge voltage is determined in consideration of this voltage drop. Note that the determination of the precharge voltage is not limited to being performed in real time. It goes without saying that it may be performed intermittently. In addition, when performing duty ratio control, the electric current which flows into an anode changes with duty ratio. Therefore, it is necessary to consider current consumption by duty ratio control. When the duty ratio is 1/1, the lighting rate is the same as the current consumption (power). In this specification, for ease of explanation, in FIG. 384 and the like, the duty ratio is assumed to be 1/1. That is, it is assumed that the lighting rate is proportional to the current flowing through the anode.

  In the description, anode current = lighting rate is described. However, in the pixel configuration of FIG. 1 and the like, a program current flowing into the source driver IC is also added to the anode terminal (the source terminal of the driving transistor 11a). Therefore, the reality is somewhat different. Further, the current flowing through the anode wiring is mainly described, but it goes without saying that the current flowing through the cathode wiring 2682 may be replaced.

  FIG. 384 (a) illustrates that the voltage drop of the anode voltage of the pixel 16 from Vdd (lighting rate 0%) to Vr (lighting rate 100%) occurs according to the lighting rate.

  FIG. 384 (b) shows the precharge voltage output to the terminal 681 with respect to the lighting rate. The rising position of the driving transistor 11a is at a position that is lowered by D (V) from Vdd. Therefore, a voltage that is lowered by D (V) from Vd becomes a precharge voltage at a lighting rate of 0%. The solid line in FIG. 384 (b) uses the voltage drop Vr (V) of the anode terminal in FIG. 384 (a) as it is. Therefore, the precharge voltage with a lighting rate of 100% is Vdd-D-Vr.

  The dotted line in FIG. 384 (b) is obtained by changing the precharge voltage at a lighting rate of 40% or more and below. The precharge voltage is Vdd-D (V) up to a lighting rate of 40%, and the precharge voltage is Vdd-D-Vr (V) above 40%. By controlling as indicated by the dotted line, the circuit for deriving the precharge voltage is simplified.

  The anode voltage Vdd depends on the magnitude of the program current Iw. The pixel configuration in FIG. 1 will be described as an example. As shown in FIG. 393 (a), during current programming, the programming current Iw flows from the driving transistor 11a into the source signal line 18. When the program current Iw is large, the channel-to-channel voltage of the driving transistor 11a increases. FIG. 393 (b) is a graph of FIG. 393 (a). When the channel voltage is V1 (actually 0 on the horizontal axis is the Vdd voltage), the program current I1 flows. When the channel voltage is V2 (actually 0 on the horizontal axis is the Vdd voltage), the program current I2 flows. In order to pass a large program current Iw, it is necessary to increase the anode voltage Vdd.

  In the above embodiment, it is necessary to increase the anode voltage Vdd when the program current Iw is large. Conversely, when the program current Iw is small, it means that the anode voltage Vdd may be low. If the anode voltage Vdd is lowered, the power consumption of the panel can be reduced, and the power consumed by the driving transistor 11a can also be reduced, so that heat generation can be reduced and the life of the EL element 15 can be extended. .

  The program current Iw also changes with a change in the reference current. If the reference current Ic is increased, the program current Iw is also relatively increased (discussed on the raster screen when the gradation data of the screen is constant). If the reference current Ic decreases, the program current Iw also becomes relatively small. Here, for ease of explanation, an increase or decrease in the program current Iw is described as being synonymous with an increase or decrease in the reference current Ic.

  FIG. 394 is a block diagram of the power supply circuit of the present invention. Vin is an unregulator voltage from a battery (not shown) of the main body. The DCDC converter 3941a generates an anode voltage Vdd by boosting from the Vin voltage with reference to the GND voltage. For ease of explanation, it is assumed that the power supply voltage Vcc and the anode voltage Vdd of the source driver IC are the same. By setting Vdd = Vcc, the number of power supplies is reduced and the circuit configuration is facilitated. Further, as described with reference to FIG. 45, an overvoltage is not applied to the source driver IC. On the other hand, the DCDC converter 3941b generates a base voltage Vdw by boosting from the Vin voltage with reference to the GND voltage.

  The regulator 3944 generates the cathode voltage Vss from the Vdw voltage and the Vdd voltage with the Vdd voltage as the ground voltage. With the above configuration, if the Vdd voltage increases, the Vss voltage also increases in proportion.

  As can be understood from FIG. 1, a constant current Iw is generated by the driving transistor 11 a, and a program current Iw flows through the EL element 15. Therefore, power consumption is a potential difference between Vdd and Vss. In the configuration of FIG. 394, the Vss voltage is also shifted in the same direction due to the shift of the Vdd voltage. Therefore, even if the anode voltage changes, the voltage applied between the EL element 15 and the driving transistor 11a is constant.

  As described with reference to FIG. 393, the anode voltage needs to be increased as the program current Iw (reference current Ic) increases. This is because the GND potential is fixed. Note that the Vcc of the IC voltage is also changed simultaneously with the change of the anode voltage (Vdd = Vcc). When Vdd−Vss is a constant voltage and Vdd increases, the voltage applied to the EL element 15 decreases. Therefore, the EL element 15 does not operate in the saturation region. However, the region where Iw (Ic) must be increased is a region with a low lighting rate, and the pixel is subjected to high luminance control (see FIGS. 295 to 298, 197 to 202, and the description thereof). ) Therefore, even if the luminance of the pixel 16 with a low lighting rate and high luminance display is lowered, the image display is hardly affected. The power consumption, which is an advantage, is greater.

  If Vdd = Vcc, as shown in FIG. 395, it may be generated by dividing resistance (R1, R2) between the anode voltage vdd and GND. This is because the Vcc voltage is used for generating a precharge voltage inside the IC. Since the precharge voltage is based on Vdd, Vcc and Vdd need to be linked. As shown in FIG. 395, an electrolytic capacitor C is inserted.

FIG. 396 illustrates the relationship between the gate-off voltage (Vgh) and the gate-on voltage (Vgl) (see also FIG. 180 and its description). In FIG. 396 (a), the Vgh voltage is made larger than the anode voltage Vdd. The Vgl voltage is higher than the Vss voltage.
FIG. 396 (b) shows a state where the anode voltage Vdd is shifted to be higher than the reference voltage Vdd (indicated by voltage Vdd1). In FIG. 396 (b), the Vgh voltage is increased in conjunction with the change in Vdd. The Vgl voltage is not changed from FIG. 396 (a).

  FIG. 396 (b) shows a state where the anode voltage Vdd is shifted to be higher than the reference voltage Vdd (indicated by voltage Vdd1). In FIG. 396 (b), the Vgh voltage is not interlocked with the change in Vdd. The Vgl voltage is not changed from FIG. 396 (a). As described above, the gate signal line voltages Vgh and Vgl may be either.

  FIG. 397 shows a relationship between the lighting rate and the anode voltage as an example. Vdd + 2 and Vdd + 4 do not indicate absolute voltages, but are relatively illustrated for ease of explanation. Note that the high luminance control is performed on the pixels in the low lighting rate region, see FIGS. 295 to 298, FIGS. 197 to 202, FIGS. 383, 384, and the like and the description thereof.

  In FIG. 397, the reference current (program current) is increased when the lighting rate is 25% or less. In this state, since the anode voltage needs to be increased, the anode voltage is increased as the reference current increases. The reference current is increased when the lighting rate is 75% or more. As the reference current increases, the anode voltage increases.

  In FIG. 398, the reference current (program current) is changed stepwise according to the lighting rate. As the reference current changes, the anode voltage also changes.

  In FIGS. 394 to 398, the anode voltage is changed by changing the reference current (program current). However, this is a case where the driving transistor 11a is the P channel, and it goes without saying that the cathode voltage is changed when the driving transistor 11a is the N channel.

Note that the anode voltage with respect to the magnitude of the program current (the magnitude of the reference current) may be changed as shown in FIG. A solid line a in FIG. 405 is an example in which the anode voltage is changed in proportion to the program current (reference current). A dotted line b in FIG. 405 shows an embodiment in which the anode voltage is changed when the current is equal to or higher than a predetermined program current (reference current). In the dotted line b, since the change point of the anode voltage with respect to the reference current is one point, the circuit configuration is easy.
In FIGS. 394 and 395, instead of the DCDC converter or regulator, a booster circuit or the like may be formed or configured using the transformer (single-winding transformer, multiple-winding transformer) described in FIGS. 177 and 179, or a coil. Needless to say.

  In the above embodiment, the anode voltage is changed according to the magnitude of the reference current or the program current. However, a change in the magnitude of the reference current or the program current is synonymous with changing the potential of the source signal line 18. In the case where the driving transistor 11a shown in FIG. 1 is a P channel, increasing the program current Iw or the reference current is to lower the potential of the source signal line 18 (close to the GND potential). Conversely, to reduce the program current Iw or the reference current is to increase the potential of the source signal line 18 (closer to the anode Vdd).

  From the above, control may be performed as shown in FIG. That is, when the potential of the source signal line 18 is 0 (GND), the anode voltage is set highest (the reference current and the program current are the maximum values). When the potential of the source signal line 18 is the Vdd potential, the anode voltage is made the lowest (the reference current and the program current are the minimum values). By configuring or controlling as described above, the period during which a high voltage is applied to the EL element 15 can be shortened, and the life of the EL element 15 can be extended.

  Next, examples of the display device of the present invention that implements the driving system of the present invention will be described. FIG. 157 is a plan view of a mobile phone as an example of an information terminal device. An antenna 1571, a numeric keypad 1572, and the like are attached to the housing 1573. 1572 and the like are display color switching keys, power on / off, and frame rate switching keys.

  When the key 1572 is pressed once, the display color is set to the 8-color mode, then when the same key 1572 is pressed, the display color is set to the 4096 color mode, and when the key 1572 is pressed further, the display color is set to the 260,000 color mode. But you can. The key is a toggle switch that changes the display color mode each time it is pressed. In addition, you may provide the change key with respect to a display color separately. In this case, there are three (or more) keys 1572.

  The key 1572 may be a push switch, a mechanical switch such as a slide switch, or may be switched by voice recognition or the like. For example, voice input of 4096 colors to the receiver, for example, “high quality display”, “4096 color mode” or “low display color mode” is input to the receiver and displayed on the display screen 50 of the display panel. The display color is changed. This can be easily realized by adopting the current speech recognition technology.

  Further, the display color may be switched electrically, or may be a touch panel that is selected by touching a menu displayed on the display unit 50 of the display panel. Further, it may be configured to be switched by the number of times the switch is pressed, or to be switched by rotation or direction like a click ball.

  Although 1572 is a display color switching key, it may be a key for switching the frame rate. Moreover, it is good also as a key etc. which switch a moving image and a still image. A plurality of requirements such as a moving image, a still image, and a frame rate may be switched at the same time. Alternatively, the frame rate may be changed gradually (continuously) as long as the pressure is kept pressed. This case can be realized by making the resistor R of the capacitor C and the resistor R constituting the oscillator a variable resistor or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Alternatively, a plurality of capacitors may be formed on the semiconductor chip, one or more capacitors may be selected, and these may be connected in parallel in a circuit.

  An important function of the display panel is that images of a plurality of formats can be displayed. For example, a digital video camera (DVC) needs to be able to display NTSC and PAL images. Hereinafter, a method for displaying images of a plurality of formats on one panel will be described. For ease of explanation, it is assumed that the display panel is a QVGA panel of horizontal 320 RGB × vertical 240 dots, and an NTSC image and a PAL image are displayed on the panel having the number of pixels of QVGA.

  FIG. 275 is an explanatory diagram for displaying NTSC and PAL images. The NTSC image is 720 RGB horizontal by 480 dots vertical. Further, it is assumed that the PAL image is 720 RGB × 576 dots in the horizontal direction.

  First, a case where an NTSC screen is displayed as shown in FIG. 275 (a) will be described. The horizontal video signal of the NTSC image is 720 dots. Since the QVGA panel has 320 horizontal dots, it is necessary to thin out 720 dots to 320 dots. Therefore, it is necessary to perform a pixel thinning process in which 9 pixels are changed to 8 pixels. This processing method will be described later. In the vertical direction, the number of effective pixels of the video signal of the NTSC image is 480 dots. Since the QVGA panel has 240 dots, the processing is easy because only two pixel rows are thinned out into one pixel row. That is, in the interlaced image, the 240 pixel rows of the first field are displayed as they are in the first field. In the second field, the 240 pixel rows in the second field are displayed as they are.

  FIG. 275 (b) is an explanatory diagram for displaying a PAL screen. The video signal of the PAL image is 720 dots. On the other hand, in the vertical direction, the number of effective scanning lines is 576. Therefore, in the case of an interlace signal, there are 576/2 = 288 pixel rows in each field. When the NTSC screen and the PAL screen are displayed on the QVGA panel, the number of pixel rows in each field is too different between the NTSC and the PAL. In other words, NTSC has 240 pixel rows, while PAL has 288 pixel rows. Therefore, a part of the screen is displayed in the PAL for sharing. That is, 640 dots out of 720 horizontal dots are displayed (in 1/2, 320 dots out of 720/2 dots (QVGA horizontal pixel number) are displayed. The vertical direction is also deleted at the rate of horizontal dot deletion 288. × (640/720) = 256 dots Furthermore, in order to keep the number of vertical dots of QVGA to 240, 256 dots are thinned out to 240 dots. In order to change 256 dots to 240 dots, it is necessary to change 16 dots to 15 dots.

  Therefore, in NTSC, it is important to thin out 9 dots to 8 dots in horizontal pixels, and in PAL, it is important to establish a method to thin out 16 dots in 15 pixels to 15 dots. is there.

  The present invention is characterized in that image data is created by adding adjacent pixel data at a certain ratio. The addition is performed so that at least the denominator is a multiple of 2 such as 1/2, 1/4, 1/8, 1/16 (however, accuracy is not reduced). Also, the sum of the coefficients to be multiplied is set to 1. For example, if the coefficients for the first pixel are 1/2, 1/4, and 1/8 and the coefficient for the second pixel is 1/8, 1/2 + 1/4 + 1/8 + 1/8 = 1. It becomes. The calculation is preferably performed so as to maintain the luminance position of each pixel, and it is preferable that the both ends or one end of the screen perform different calculations from the other pixels.

  First, the NTSC horizontal pixel thinning method will be described with reference to FIG. For ease of explanation, a method of thinning out 360 dots of NTSC video signals every 2 dots in advance to 360 dots, and thinning out the pixels to 320 dots will be described. Therefore, 9 pixels are thinned out to 8 pixels. Needless to say, the pixels may be directly thinned from 720 dots to 320 dots. In this case, pixel thinning is performed from 18 dots to 16 dots. Further, the pixel thinning calculation may be changed in the field.

  FIG. 276 shows the calculation with a set of RGB pixels as one pixel. In FIG. 276, 9 pixels are obtained by dividing 360 dots by 9 pixels and performing calculations. Note that before conversion, the first pixel, the second pixel, the third pixel,... Further, the converted pixel is called a first pixel, a second pixel, a third pixel,.

  The first pixel of the 8 pixel set adds 1/2 times + 1/4 times + 1/8 times the data of the first pixel of the 9 pixel set and 1/8 times of the second pixel data of the 9 pixel set. The calculation is performed, and the calculation result is the first pixel of the 8-pixel set. It should be noted that there is no bit drop in the operation. That is, 1/8 times does not shift the data by 3 bits, but adds the data by a fixed multiple and bit shifts the added data to obtain a result.

  For example, the fifth pixel of the 8-pixel set adds 1/4 times + 1/8 times the data of the fifth pixel of the 9-pixel set and 1/2 + 1/8 times of the sixth pixel data of the 9-pixel set. The calculation is performed, and the calculation result is the fifth pixel of the 8-pixel set. At this time, if the fifth pixel data of the 9-pixel set is 250 = B′11111010 ′, 117 = B′01110101 ′, 250 × 2 + 250 + 117 × 4 + 117 = 1335 is obtained. When this result 1335 is multiplied by 1/8, 1335/8 = 166 (the result is rounded down). If the calculation is performed as described above, there is no bit loss, and 1/4 times + 1/8 times the data of the fifth pixel of the 9-pixel set and 1/2 + 1/8 times of the sixth pixel data of the 9-pixel set. Addition operations can be performed. As described above, the present invention is expressed as 1/4 times + 1/8 times or the like, which means that the data is equivalently 1/4 times + 1/8 times. Therefore, any calculation method may be used.

  That is 1/4 times + 1/8 times the data of the fifth pixel in the 9-pixel set and 1/2 + 1/8 times the data of the sixth pixel in the 9-pixel set. Accordingly, the coefficients used are 1/4, 1/8, 1/2, and 1/8. The coefficient is 1/4 + 1/8 + 1/2 + 1/8 = 1/1. The present invention is also characterized in that the addition value of the coefficient of calculation is 1/1. By making it 1/1, the calculation becomes easy.

  When the calculation is performed according to the present invention, a multiple of the calculation coefficient is changed. When performing an operation of adding 1/4 times + 1/8 times the data of the fifth pixel in the 9-pixel set and 1/2 + 1/8 times the data of the sixth pixel in the 9-pixel set, the maximum coefficient is 8 It is. In this case, the image data is doubled when it is 1/4, the image data is 4 times when it is 1/2, and the image data is multiplied when it is 1/8. That is, the case of the maximum coefficient (8 in this embodiment) is replaced with 1 time, and when it is half (4), it is doubled, and when it is half (2), it is 4 times. Then, the added data is divided by the maximum coefficient (which is 8) (specifically, the data is shifted right by 3 bits).

  When the maximum coefficient is 16, 1/16 is replaced with 1 time, and when it is half (8), it is doubled, and when it is half (4), it is quadrupled. Furthermore, in the case of half (2), it is increased to 8 times. Then, the added data is divided by the maximum coefficient (16) (specifically, the data is shifted to the right by 4 bits).

  As described above, according to the calculation method of the present invention, the 1 / m coefficient m is a multiple of 2, and the added value of the coefficient to be calculated is 1, so that the calculation can be performed with a smaller number of bits and the calculation speed can be reduced. Can also be faster.

  Although derailment has occurred, the description will be further made with reference to FIG. The second pixel of the 8-pixel set performs an operation of adding 1/2 times + 1/4 times the data of the second pixel of the 9-pixel set and 1/4 times of the third pixel data of the 9-pixel set, The calculation result is the second pixel of the 8-pixel set.

  Similarly, the third pixel of the 8-pixel set is 1/2 times + 1/8 times the data of the third pixel of the 9-pixel set, and 1/4 times + 1/8 times of the third pixel data of the 9-pixel set. Is calculated, and the calculation result is the third pixel of the 8-pixel set.

  Similarly, the third pixel of the 8-pixel set is 1/2 times + 1/8 times the data of the third pixel of the 9-pixel set, and 1/4 times + 1/8 times of the third pixel data of the 9-pixel set. Is calculated, and the calculation result is the third pixel of the 8-pixel set.

  The fourth pixel of the 8-pixel set performs an operation of adding 1/2 times the data of the fourth pixel of the 9-pixel set and 1/2 times the fifth pixel data of the 9-pixel set, and the calculation result is 8 The fourth pixel in the pixel set is assumed.

  The fifth pixel of the 8-pixel set adds 1/4 times + 1/8 times the data of the fifth pixel of the 9-pixel set and 1/2 times + 1/8 times of the sixth pixel data of the 9-pixel set. The calculation is performed, and the calculation result is the fifth pixel of the 8-pixel set.

  The sixth pixel of the 8-pixel set performs an operation of adding 1/4 times the data of the sixth pixel of the 9-pixel set and 1/2 times + 1/4 times of the seventh pixel data of the 9-pixel set, The calculation result is the sixth pixel in the 8-pixel set.

  The seventh pixel of the 8-pixel set adds 1/8 times the data of the seventh pixel of the 9-pixel set and 1/2 times + 1/4 times + 1/8 times the eighth pixel data of the 9-pixel set. The calculation is performed, and the calculation result is the seventh pixel in the 8-pixel set.

  The 8th pixel of the 8 pixel set performs an operation of adding 0/1 times the data of the 8th pixel of the 9 pixel set and 1/1 times the 9th pixel data of the 9 pixel set, and the operation result is 8 The eighth pixel of the pixel set is assumed.

  Note that the calculation may be performed by shifting the table of FIG. 276 by one frame in the first field and the second field. The border of pixel field is not noticeable.

  The above is a method of thinning out 9 pixels to 8 pixels. The method of FIG. 276 is not limited to this, and can be applied to other pixel thinning. FIG. 277 shows an example of a method of thinning out pixels from 5 pixel rows to 4 pixel rows. In this case, it is the same as the method of thinning out 9 pixels to 8 pixels.

  The first pixel of the 5-pixel set performs an operation of adding 1/2 times + 1/4 times the data of the first pixel of the 5-pixel set and 1/4 times of the second pixel data of the 5-pixel set, The calculation result is a first pixel in a 4-pixel set.

  Similarly, the second pixel of the 4-pixel set performs an operation of adding ½ times the data of the second pixel of the 5-pixel set and ½ times of the third pixel data of the 5-pixel set. The result is the second pixel in the 4-pixel set.

  Similarly, the third pixel of the 4-pixel set adds ¼ times the data of the third pixel of the 5-pixel set and ½ times + 1/4 times of the fourth pixel data of the 5-pixel set. And the calculation result is set as the third pixel of the four-pixel set.

  The fourth pixel of the four-pixel set performs an operation of adding 0/1 times the data of the fourth pixel of the five-pixel set and 1/1 times the fifth pixel data of the five-pixel set. The fourth pixel in the pixel set is assumed.

  As described above, according to the calculation method of the present invention, the 1 / m coefficient m is a multiple of 2, and the added value of the coefficient to be calculated is 1, so that the calculation can be performed with a smaller number of bits and the calculation speed can be reduced. Can also be faster.

  In the examples of FIGS. 276 and 277 described above, the calculation is performed with a set of RGB pixels as one dot. However, when the RGB pixel group is implemented in units of one dot, the resolution is reduced. In the following embodiments, in order to solve this problem, R, G, and B are individually performed in consideration of the pixel position of the panel to be converted. By implementing the following embodiments, a good resolution can be realized with a QVGA panel.

  In FIG. 278, Rx, Gx, and Bx (x indicates a dot number) are original video signals before conversion. The original video signal is sent for 720 dots with R, G, and B as one set (the luminance signal is for 720 dots). Xx, Yx, Zx (x indicates a pixel number) indicates a pixel of the panel. Originally, it is easier to understand the expression Rx, Gx, and Bx, but it cannot be distinguished from the original video signal (video signal before pixel thinning), so X, Y, and Z are used. To facilitate understanding, it may be considered that X = R, Y = G, and Z = B.

  In FIG. 278, the upper row is an original video signal (video signal before pixel thinning). Therefore, since the number of dots is 720 dots, the pixel number is changed from 1 to 720. The display method (calculation direction) is from left to right. The lower row shows the pixel position of the panel. Since the number of dots on the panel is 320 dots, the pixel number is 1 to 320. FIG. 278 shows an example in which 720 dots are thinned out to 320 dots.

  As can be understood from FIG. 278, the original video signal and the pixel position of the panel coincide with each other periodically. The dots R1, G1, B1 to R3, G3, B3 coincide with the set of X1, Y1, Z1, and X2 pixels. Similarly, R4, G4, and B4 to R6, G6, and B6 dots match the set of Y2, Z2, X3, and Y3 pixels. The same applies hereinafter.

  As described above, the set of 3 dots in the original video signal (3 dots considering RGB as 1 dot) and the 4 pixels of the panel match. Therefore, the pixel thinning calculation is preferably performed as shown in FIG. As shown in FIG. 279, the first pixel X1 and the last pixel Z320 of the panel are subjected to irregular processing (see FIGS. 279 (a) and (d)). This is because there is no pixel to be calculated. Other than that, it is calculated regularly.

  In the following embodiments, it is described that the image data is multiplied by 1/8 as in FIG. The processing method for calculating 1/8 times has been described with reference to FIG.

In FIG. 279 (a),
X1 = R1 × 8/8
Y1 = G1 × 3/8 + G2 × 5/8
Z1 = B2 × 5/8 + B3 × 3/8
X2 = R3 × 7/8 + R4 × 1/8
And calculate. X1 is originally intended to be calculated as R0 × 1/8 + R1 × 7/8, or R1 × 8/8 because there is no R0 data.

  Needless to say, the calculation may be performed by generating a nonexistent R0 for convenience of calculation. In this case, the calculation can be performed as X1 = R0 × 1/8 + R1 × 7/8.

The next block is as shown in FIG. 279 (b),
Y2 = G3 × 1/8 + G4 × 7/8
Z2 = B4 × 3/8 + B5 × 5/8
X3 = R5 × 5/8 + R6 × 3/8
Y3 = G6 × 7/8 + G7 × 1/8
And calculate. That is, the first coefficient in the calculation of the first equation is 1/8, and the second coefficient is 7/8. When these two coefficients are added, it becomes 1. Similarly, the first coefficient in the calculation of the second equation is 3/8, and the second coefficient is 5/8. When these two coefficients are added, it becomes 1. In addition, the first coefficient in the calculation of the third equation is 5/8, and the second coefficient is 3/8. When these two coefficients are added, it becomes 1. In addition, the first coefficient in the calculation of the fourth equation is 7/8, and the second coefficient is 1/8. When these two coefficients are added, it is set to 1.

  Furthermore, when the first coefficients 1/8, 3/8, 5/8, and 1/8 of the four equations are added, the result is 2. In other words, it becomes 1 when the coefficients of the two equations are added. Since there are four equations, the added value is set to 2. Similarly, when the second coefficients 7/8, 5/8, 3/8, and 1/8 of the four equations are added, the result is 2. That is, when the coefficients of the two expressions are added, the result is 1, and the expression is 4, so the added value is 2.

  Further, at least two coefficients in the equation are exchanged in one glock. For example, in FIG. 279 (b), the first coefficient of the second equation is 3/8 and the second coefficient is 5/8. The first coefficient in the third equation is 5/8, and the second coefficient is 3/8. The first coefficient of the first equation is 1/8 and the second coefficient is 7/8. In contrast, the first coefficient of the third equation is 7/8, and the second coefficient is 1/8.

  In addition, when the first coefficients of the pair formula are added, the result is set to 1. For example, in FIG. 279 (b), the first coefficient of the second expression is 3/8, and the first coefficient of the third expression is 5/8. Therefore, 3/8 + 5/8 = 1/1. Similarly, the second coefficient of the second equation is 5/8 and the third second coefficient is 3/8. Therefore, 5/8 + 3/5 = 8/8 = 1/1 = 1.

  In addition, the denominator of the coefficient of each equation is set to a multiplier of 2 as a result, such as 1, 2, 4, 8, 16, and so on. Note that the fact that the denominator is a multiplier of 2 does not mean that a multiplier of 2 is used when performing an addition operation. As described above, it goes without saying that the numerical value when adding may be changed or changed to another numerical value. When expressed as in FIG. 279, it is simply expressed as a multiplier of 2. Further, although the calculation is described as being performed by addition, the present invention is not limited to this. Addition can be performed by bit shift, or by combining multiplication or subtraction. Therefore, the addition is a means for facilitating explanation or understanding, and is not limited. In other words, obtaining an addition or sum is a technical idea or concept that includes other methods such as bit shift.

  By implementing the method or method of the present invention as described above, pixel thinning with high resolution can be realized.

Similarly, the next block is as shown in FIG. 279 (c),
Z2 = B6 × 1/8 + B7 × 7/8
X2 = R7 × 3/8 + R8 × 5/8
Y3 = G8 × 5/8 + G9 × 3/8
Z3 = B9 × 7/8 + B10 × 1/8
And calculate. Naturally, the first coefficient in the calculation of the first equation is 1/8 and the second coefficient is 7/8, as in the previous block calculation. When these two coefficients are added, it becomes 1. Similarly, the first coefficient in the calculation of the second equation is 3/8, and the second coefficient is 5/8. When these two coefficients are added, it becomes 1. In addition, the first coefficient in the calculation of the third equation is 5/8, and the second coefficient is 3/8. When these two coefficients are added, it becomes 1. In addition, the first coefficient in the calculation of the fourth equation is 7/8, and the second coefficient is 1/8. When these two coefficients are added, it is set to 1.

  Furthermore, when the first coefficients 1/8, 3/8, 5/8, and 1/8 of the four equations are added, the result is 2. That is, when the coefficients of the two expressions are added, the result is 1, and the number of expressions is 4. Therefore, the added value is set to 2. Similarly, when the second coefficients 7/8, 5/8, 3/8, and 1/8 of the four equations are added, the result is 2. That is, when the coefficients of the two expressions are added, the result is 1, and the expression is 4, so the added value is 2.

The last next block is as shown in FIG.
...
...
Y320 = G719 × 5/8 + G720 × 3/8
Z320 = B720 × 8/8
And calculate.

  Z320 is originally intended to be calculated as B720 × 7/8 + B721 × 1/8, or B720 × 8/8 because there is no B721 data.

  Needless to say, for the sake of calculation, B721 that does not exist may be generated to perform the calculation. In this case, the calculation can be performed as X360 = B720 × 7/8 + B721 × 1/8.

  The above embodiment is a pixel thinning method for displaying an image of a 720-dot video signal on a QVGA panel having 320 horizontal dots. The present invention is not limited to this, and can be used for conversion to other numbers of dots. FIG. 280 shows a pixel thinning method for converting a 720-dot video signal to 360 dots.

  In FIG. 280, similarly to FIG. 278, Rx, Gx, and Bx (x indicates a dot number) are original video signals before conversion. The original video signal is sent for 720 dots with R, G, and B as one set (the luminance signal is for 720 dots). Xx, Yx, Zx (x indicates a pixel number) indicates a pixel of the panel.

  In FIG. 280, the upper row is an original video signal (video signal before pixel thinning). Therefore, since the number of dots is 720 dots, the pixel number is changed from 1 to 720. The display method (calculation direction) is from left to right. The lower row shows the pixel position of the panel. Since the number of dots of the panel is 360 dots, the pixel number is 1 to 360.

  As can be understood from FIG. 280, the original video signal and the pixel position of the panel periodically coincide. R1, G1, B1 to R2, G2, B2 dots coincide with the set of X1, Y1, Z1 pixels. Similarly, R3, G3, and B3 to R4, G4, and B4 dots match the set of X2, Y2, and Z3 pixels. The same applies hereinafter.

  FIG. 281 displays the calculation formula. As described above, the number of equations for each block is determined in a block in which a set of pixels matches. In FIG. 279, the equation block is composed of four equations, and in FIG. 281 the equation block is composed of three equations.

  As described above, the set of 2 dots of the original video signal (considering RGB as 1 dot, 2 dots) matches the 3 pixels of the panel. Therefore, the pixel thinning calculation is preferably performed as shown in FIG. As shown in FIG. 281, the first pixel X1 and the last pixel Z360 of the panel undergo irregular processing (see FIGS. 281 (a) and (f)). This is because there is no pixel to be calculated. Other than that, it is calculated regularly.

In the following embodiments, it is described that the image data is multiplied by 1/8 as in FIG. In FIG. 279 (a),
X1 = R1 × 8/8
Y1 = G1 × 1/2 + G2 × 1/2
Z1 = B2 × 7/8 + B3 × 1/8
(Calculate or process). X1 is originally intended to be calculated as R0 × 1/8 + R1 × 7/8, or since R0 data does not exist, X1 = R1 × 8/8.

  Needless to say, the calculation may be performed by generating a nonexistent R0 for convenience of calculation. In this case, the calculation can be performed as X1 = R0 × 1/8 + R1 × 7/8.

The next block is as shown in FIG.
X2 = R2 × 1/8 + R3 × 7/8
Y2 = G3 × 1/2 + G4 × 1/2
Z2 = B4 × 7/8 + B5 × 1/8
And calculate. That is, the first coefficient in the calculation of the first equation is 1/8, and the second coefficient is 7/8. When these two coefficients are added, it becomes 1. Similarly, the first coefficient in the calculation of the second equation is ½, and the second coefficient is ½. When these two coefficients are added, it becomes 1. In addition, the first coefficient in the calculation of the third formula is 7/8, and the second coefficient is 1/8. When these two coefficients are added, it becomes 1.

  Further, when the coefficients 1/8, 7/8, 1/2, 1/2, 7/8, and 1/8 of the three expressions are added, the result is 3. That is, 3 is obtained by adding the coefficients of the three equations. The added value of the coefficients per expression is set to 1.

  Further, at least two coefficients in the equation are exchanged in one glock. For example, in FIG. 281 (b), the first coefficient of the first equation is 1/8 and the second coefficient is 7/8. In contrast, the first coefficient of the third equation is 7/8, and the second coefficient is 1/8.

  In the second expression that is not related to the previous replacement, the first coefficient of the first expression is ½, and the second coefficient is also ½. The coefficient of the equation is the same as 1/2. Therefore, the corresponding expression is configured not to be necessary.

  In addition, when the first coefficients of the pair formula are added, the result is set to 1. For example, in FIG. 281 (b), the first coefficient of the first expression is 1/8, and the first coefficient of the third expression is 7/8. Therefore, 1/8 + 7/8 = 8/8 = 1/1.

  In addition, the denominator of the coefficient of each equation is set to a multiplier of 2 as a result, such as 1, 2, 4, 8, 16, and so on. Note that the fact that the denominator is a multiplier of 2 does not mean that a multiplier of 2 is used when performing an addition operation. As described above, it goes without saying that the numerical value when adding may be changed or changed to another numerical value. When expressed as shown in FIG. 281, it is simply expressed as a multiplier of 2. Further, although the calculation is described as being performed by addition, the present invention is not limited to this. Addition can be performed by bit shift, or by combining multiplication or subtraction. Therefore, the addition is a means for facilitating explanation or understanding, and is not limited. In other words, obtaining an addition or sum is a technical idea or concept that includes other methods such as bit shift.

Similarly, the next block is as shown in FIG.
X3 = R4 × 1/8 + R5 × 7/8
Y3 = G5 × 1/2 + G6 × 1/2
Z3 = B6 × 7/8 + B7 × 1/8
And
Similarly, the next block is as shown in FIG.
X4 = R6 × 1/8 + R7 × 7/8
Y4 = G7 × 1/2 + G8 × 1/2
Z4 = B8 × 7/8 + B9 × 1/8
And

As shown in FIG. 281 (d), the last next block is
X360 = R718 × 1/8 + R719 × 7/8
Y360 = G719 × 1/2 + G720 × 1/2
Z360 = B720 × 8/8
And calculate.

  Z360 is originally intended to perform an operation as B720 × 7/8 + B721 × 1/8, or B720 × 8/8 because there is no B721 data.

  Needless to say, for the sake of calculation, B721 that does not exist may be generated to perform the calculation. In this case, the calculation can be performed as X360 = B720 × 7/8 + B721 × 1/8.

  The above embodiment is a method for displaying an image of a display panel having a square lattice pixel configuration. The pixel thinning method of the present invention can also be applied to a delta arrangement pixel structure.

  FIG. 282 shows a pixel thinning method for converting a 720-dot video signal into a 160-dot delta arrangement. In FIG. 282, as in FIG. 278, Rx, Gx, and Bx (x indicates a dot number) are original video signals before conversion. The original video signal is sent for 720 dots with R, G, and B as one set (the luminance signal is for 720 dots). Xx, Yx, Zx (x indicates a pixel number) indicates a pixel of the panel. In the delta arrangement, the pixel position is shifted by 1/2 pixel for each pixel row. Therefore, the odd pixel row is given a coefficient a, which is indicated as Xax, Yax, Zax (x indicates a pixel number), and the even pixel row is given a coefficient b, Xbx, Ybx, Zbx (x is the pixel number) ).

  In FIG. 282, the upper row is an original video signal (video signal before pixel thinning). Therefore, since the number of dots is 720 dots, the pixel number is changed from 1 to 720. The display method (calculation direction) is from left to right. However, this matter is similar to the previous embodiment, but is not limited. Further, the positional relationship of the delta arrangement is not limited. This is because the delta arrangement varies depending on the type of panel. However, the delta arrangement is the same in any panel that RGB is formed or configured as a set of delta arrangements. The second row shows the pixel positions of the odd pixel rows of the panel. Since the number of dots on the panel is 160 dots, the pixel number is from 1 to 160. The third row shows the pixel positions of the even pixel rows of the panel. The number of dots on the panel is 160 dots, and the pixel number is changed from 1 to 161 because of the delta arrangement.

  As can be understood from FIG. 282, the original video signal and the pixel position of the panel periodically coincide with each other. The dots R1, G1, B1 to R3, G3, B3 coincide with the set of Xa1, Ya1 pixels. Similarly, the dots R4, G4, and B4 to R6, G6, and B6 match the set of Za1 and Xa2 pixels. The same applies hereinafter. Further, the even pixel rows are arranged with a shift of 1/2 pixel with respect to the odd pixel rows.

  FIG. 283 (1) displays the calculation formula. As described above, the number of equations for each block is determined in a block in which a set of pixels matches. In FIG. 282, the expression block is composed of two expressions. First, for ease of explanation, an odd pixel row processing method will be described first with reference to FIG. 283 (1).

  As described above, the set of 3 dots of the original video signal (3 dots considering RGB as 1 dot) and the 2 pixels of the panel match. In the following embodiments, the image data is described as being 3/4 times the image data, as in FIG.

In FIG. 283 (1) (a),
Xa1 = R1 × 3/4 + R2 × 1/4
Ya1 = G2 × 1/4 + G3 × 3/4
(Calculate or process).

  That is, the first coefficient in the calculation of the first equation is 3/4, and the second coefficient is 1/4. When these two coefficients are added, it becomes 1. Similarly, the first coefficient in the calculation of the second equation is 1/4, and the second coefficient is 3/4. When these two coefficients are added, it becomes 1.

  Furthermore, when the coefficients 3/4, 1/4, 1/4, and 3/4 of the three expressions are added, the result is 2. In other words, it becomes 2 when the coefficients of the two equations are added. The added value of the coefficients per expression is set to 1.

  Furthermore, the coefficients of the formulas are changed into two in one glock. For example, in FIG. 283 (1), the first coefficient of the first equation is 3/4 and the second coefficient is 1/4. In contrast, the first coefficient of the second equation is 1/4, and the second coefficient is 3/4.

  In addition, when the first coefficients of the pair formula are added, the result is set to 1. For example, in FIG. 283 (1), the first coefficient of the first expression is 3/4, and the first coefficient of the second expression is 1/4. Therefore, 3/4 + 1/4 = 4/4 = 1/1.

  In addition, the denominator of the coefficient of each equation is set to a multiplier of 2 as a result, such as 1, 2, 4, and the like. Note that the fact that the denominator is a multiplier of 2 does not mean that a multiplier of 2 is used when performing an addition operation. As described above, it goes without saying that the numerical value when adding may be changed or changed to another numerical value. When expressed as in FIG. 283, it is simply expressed as a multiplier of 2. Further, although the calculation is described as being performed by addition, the present invention is not limited to this. Addition can be performed by bit shift, or by combining multiplication or subtraction. Therefore, the addition is a means for facilitating explanation or understanding, and is not limited. In other words, obtaining an addition or sum is a technical idea or concept that includes other methods such as bit shift.

The next block is as shown in FIGS. 283 (1) and (b),
Za1 = B4 × 3/4 + B5 × 1/4
Xa2 = R5 × 1/4 + R6 × 3/4
And calculate.

Similarly, as shown in FIGS. 283 (1) and (c), the next block is
Ya2 = G7 × 3/4 + G8 × 1/4
Za2 = B8 × 1/4 + B9 × 3/4
And The same applies hereinafter.

  Next, a processing method for even-numbered pixel rows will be described with reference to FIG. For ease of explanation, it is assumed that the odd-numbered pixel rows are arranged with pixels from the left position, and the even-numbered pixel rows are arranged shifted to the right by 0.5-pixel odd-numbered pixel rows. is not. Accordingly, FIG. 283 (1) and FIG. 283 (2) are interchanged depending on the pixel arrangement of the panel, and the calculation may be started by shifting by one or two or more expressions.

In FIG. 283 (2) (a),
Zb1 = B2 × 1/1
Xb2 = R3 × 1/2 + R4 × 1/2
(Calculate or process).

  There is only one coefficient in the first equation. However, the coefficient is 1/1. Since the addition value of the coefficient per one expression is 1 for one coefficient, the processing method of the present invention is satisfied. Therefore, the second coefficient is not necessary.

  The first coefficient in the calculation of the second equation is ½, and the second coefficient is ½. When these two coefficients are added, it becomes 1.

  Further, when the coefficients 1/1, 1/2, and 1/2 of the two expressions are added, the result is 2. In other words, it becomes 2 when the coefficients of the two equations are added. The added value of the coefficients per expression is set to 1.

The next block is as shown in FIGS. 283 (2) (b),
Yb2 = G5 × 1/1
Zb2 = B6 × 1/2 + B7 × 1/2
And calculate.

Similarly, the next block is as shown in FIGS. 283 (2) (c),
Xb3 = G8 × 1/1
Yb3 = G8 × 1/2 + G9 × 1/2
And The same applies hereinafter.

The last block needs to be irregularly processed as shown in FIGS. 283 (2) (h). This is because the start position of the pixel starts from Z as shown in FIGS. 283 (2) (a). So the last block is
Xb161 = R719 × 1/1
It is necessary to.

  The above embodiment is a method of thinning out pixels in a 160-dot delta arrangement. The present invention can also be applied to delta arrangement pixel structures of other pixel configurations.

  FIG. 284 shows a pixel thinning method for converting a 720-dot video signal into a 180-dot delta arrangement. In FIG. 284, as in FIG. 278, Rx, Gx, and Bx (x indicates a dot number) are original video signals before conversion. The original video signal is sent for 720 dots with R, G, and B as one set (the luminance signal is for 720 dots). Xx, Yx, Zx (x indicates a pixel number) indicates a pixel of the panel. In the delta arrangement, the pixel position is shifted by 1/2 pixel for each pixel row. Therefore, an odd pixel row is given a coefficient a, which is indicated as Xax, Yax, Zax (x is a pixel number), and an even pixel row is given a coefficient b, Xbx, Ybx, Zbx (x is a pixel number) ).

  In FIG. 284, the upper row is an original video signal (video signal before pixel thinning). Therefore, since the number of dots is 720 dots, the pixel number is changed from 1 to 720. The display method (calculation direction) is from left to right. However, this matter is similar to the previous embodiment, but is not limited. Further, the positional relationship of the delta arrangement is not limited. This is because the delta arrangement varies depending on the type of panel. However, the delta arrangement is the same in any panel that RGB is formed or configured as a set of delta arrangements. The second row shows the pixel positions of the odd pixel rows of the panel. Since the number of dots on the panel is 180 dots, the pixel number is changed from 1 to 180. The third row shows the pixel positions of the even pixel rows of the panel. The number of dots on the panel is 180 dots, and the pixel numbers are changed from 1 to 181 because of the delta arrangement.

  As can be understood from FIG. 284, the original video signal and the pixel position of the panel periodically coincide with each other. The dots R1, G1, B1 to R4, G4, B4 coincide with the set of Xa1, Ya1, Za1 pixels. Similarly, R5, G5, and B5 to R8, G8, and B8 dots match the set of Xa2, Ya2, and Za2 pixels. The same applies hereinafter. Further, the even pixel rows are arranged with a shift of 1/2 pixel with respect to the odd pixel rows.

  FIG. 285 (1) displays the calculation formula. As described above, the number of equations for each block is determined in a block in which a set of pixels matches. In FIG. 285, the equation block is composed of three equations. First, for ease of explanation, an odd pixel row processing method will be described first with reference to FIG. 285 (1).

  As described above, a set of 4 dots of the original video signal (4 dots considering RGB as 1 dot) and the 3 pixels of the panel match. In the following embodiments, it is described that the image data is multiplied by 7/8 as in FIG.

In FIGS. 285 (1) (a),
Xa1 = R1 × 7/8 + R2 × 1/8
Ya1 = G2 × 1/2 + G3 × 1/2
Za1 = R3 × 1/8 + R4 × 7/8
(Calculate or process).

  That is, the first coefficient in the calculation of the first equation is 7/8, and the second coefficient is 1/8. When these two coefficients are added, it becomes 1. Similarly, the first coefficient in the calculation of the second equation is ½, and the second coefficient is ½. When these two coefficients are added, it becomes 1. Similarly, the first coefficient in the calculation of the third equation is 1/8, and the second coefficient is 7/8. When these two coefficients are added, it becomes 1.

  Further, when the coefficients 7/8, 1/8, 1/2, 1/2, 1/8, and 7/8 of the three expressions are added, the result is 3. That is, 3 is obtained by adding the coefficients of the three equations. The added value of the coefficients per expression is set to 1.

  Furthermore, the coefficients of the formulas are changed into two in one glock. For example, in FIG. 285 (1), the first coefficient of the first equation is 7/8 and the second coefficient is 1/8. The first coefficient of the third equation is 1/8, and the second coefficient is 7/8.

  In addition, the denominator of the coefficient of each equation is set to a multiplier of 2 as a result, such as 1, 2, 4, and the like. Note that the fact that the denominator is a multiplier of 2 does not mean that a multiplier of 2 is used when performing an addition operation. As described above, it goes without saying that the numerical value when adding may be changed or changed to another numerical value. When expressed as in FIG. 285, it is simply expressed as a multiplier of 2. Further, although the calculation is described as being performed by addition, the present invention is not limited to this. Addition can be performed by bit shift, or by combining multiplication or subtraction. Therefore, the addition is a means for facilitating explanation or understanding, and is not limited. In other words, obtaining an addition or sum is a technical idea or concept that includes other methods such as bit shift. That is, the present invention may be any method or method as long as the process of FIG. 285 can be performed using some means.

The next block is shown in FIGS. 285 (1) (b),
Xa2 = R5 × 7/8 + R6 × 1/8
Ya2 = G6 × 1/2 + G7 × 1/2
Za2 = B7 × 1/8 + B8 × 7/8
And calculate.

Similarly, the next block is as shown in FIGS. 285 (1) (c),
Xa3 = R9 × 7/8 + R10 × 1/8
Ya3 = G10 × 1/2 + G11 × 1/2
Za3 = B11 × 1/8 + B12 × 7/8
And The same applies hereinafter.

  Next, an even pixel row processing method will be described with reference to FIG. For ease of explanation, it is assumed that the odd-numbered pixel rows are arranged with pixels from the left position, and the even-numbered pixel rows are arranged shifted to the right by 0.5-pixel odd-numbered pixel rows. is not. Therefore, depending on the pixel arrangement of the panel, FIG. 285 (1) and FIG. 285 (2) may be interchanged, and the calculation may be started with one or two or more shifts.

In FIG. 285 (2) (a),
Zb1 = B1 × 1/8 + B2 × 7/8
(Calculate or process).

In FIGS. 285 (2) and (b),
Xb181 = B719 × 7/8 + B720 × 7/8
(Calculate or process).

  Above (a) and (h) are irregular blocks. This comes from the pixel arrangement of the delta arrangement, and there is no difference in calculation processing.

  That is, the first coefficient is 1/8 or 7/8, and the second coefficient is 7/8 or 1/8. When these two coefficients are added, it becomes 1.

In FIGS. 285 (1) and (b),
Xb2 = R3 × 7/8 + R4 × 1/8
Yb2 = G4 × 1/2 + G5 × 1/2
Zb2 = R5 × 1/8 + R6 × 7/8
(Calculate or process).

  That is, the first coefficient in the calculation of the first equation is 7/8, and the second coefficient is 1/8. When these two coefficients are added, it becomes 1. Similarly, the first coefficient in the calculation of the second equation is ½, and the second coefficient is ½. When these two coefficients are added, it becomes 1. Similarly, the first coefficient in the calculation of the third equation is 1/8, and the second coefficient is 7/8. When these two coefficients are added, it becomes 1.

  Further, when the coefficients 7/8, 1/8, 1/2, 1/2, 1/8, and 7/8 of the three expressions are added, the result is 3. That is, 3 is obtained by adding the coefficients of the three equations. The added value of the coefficients per expression is set to 1.

  Furthermore, the coefficients of the formulas are changed into two in one glock. For example, in FIGS. 285 (2) and (b), the first coefficient of the first equation is 7/8, and the second coefficient is 1/8. The first coefficient of the third equation is 1/8, and the second coefficient is 7/8.

The next block is as shown in FIGS. 285 (2) (c),
Xb3 = R7 × 7/8 + R8 × 1/8
Yb3 = G8 × 1/2 + G9 × 1/2
Zb3 = B9 × 1/8 + B10 × 7/8
And calculate.

Similarly, the next block is as shown in FIGS. 285 (2) (d),
Xb4 = R11 × 7/8 + R12 × 1/8
Yb4 = G12 × 1/2 + G13 × 1/2
Zb4 = B13 × 1/8 + B14 × 7/8
And The same applies hereinafter.

  The above embodiment has been a pixel thinning process in the horizontal direction. Hereinafter, a vertical pixel thinning method will be described. As described above, the video signal of the PAL image is 720 dots. On the other hand, in the vertical direction, the number of effective scanning lines is 576. Therefore, in the case of an interlace signal, there are 576/2 = 288 pixel rows in each field. When displaying an NTSC screen and a PAL screen on a QVGA panel, the number of pixel rows in each field is too different between NTSC and PAL. In other words, NTSC has 240 pixel rows, while PAL has 288 pixel rows. Therefore, a part of the screen is displayed in the PAL for sharing. That is, 640 dots out of 720 horizontal dots are displayed (in 1/2, 320 dots out of 720/2 dots (QVGA horizontal pixel number) are displayed. The vertical direction is also deleted at the rate of horizontal dot deletion 288. × (640/720) = 256 dots Furthermore, in order to keep the number of vertical dots of QVGA to 240, 256 dots are thinned out to 240 dots. In order to change 256 dots to 240 dots, it is necessary to change 16 dots to 15 dots From the above, it is important to establish a method for thinning out 16 dots to 15 dots in vertical pixels in PAL. is there.

  In the PAL image, it is necessary to realize a method of thinning out pixels from 16 pixel rows to 15 pixel rows. FIG. 286 is an explanatory diagram of a method of thinning out pixels from 16 pixel rows to 15 pixel rows. In FIG. 286, (1) is the first field processing method, and (2) is the second field processing method. Therefore, the processing (1) and (2) may be reversed.

  FIG. 286 shows a pixel thinning method for converting a video signal of 256 pixel rows into 240 pixel rows. In FIG. 286, Rx, Gx, and Bx (x indicates a pixel row number) are original video signals before conversion. X in Xx, Yx, and Zx indicates a pixel row number.

The processing is changed by 1/16 in the upper and lower pixels. In FIG. 286 (1) (a),
X1 = R1 × 15/16 + R2 × 1/16
Y1 = G1 × 15/16 + G2 × 1/16
Z1 = R1 × 15/16 + R2 × 1/16
(Calculate or process).

  The first coefficient in the calculation of the first to third expressions is 15/16, and the second coefficient is 1/16. When these two coefficients are added, it becomes 1.

  In addition, the denominator of the coefficient of each equation is set to a multiplier of 2 as a result, such as 1, 2, 4, 8, 16, and so on. Note that the fact that the denominator is a multiplier of 2 does not mean that a multiplier of 2 is used when performing an addition operation. As described above, it goes without saying that the numerical value when adding may be changed or changed to another numerical value. When expressed as in FIG. 285, it is simply expressed as a multiplier of 2. Further, although the calculation is described as being performed by addition, the present invention is not limited to this. Addition can be performed by bit shift, or by combining multiplication or subtraction. Therefore, the addition is a means for facilitating explanation or understanding, and is not limited. In other words, obtaining an addition or sum is a technical idea or concept that includes other methods such as bit shift. That is, the present invention may be any method or method as long as the process of FIG. 285 can be performed using some means.

The next block is as shown in FIGS. 286 (1) and (b),
X2 = R2 × 14/16 + R3 × 2/16
Y2 = G2 × 14/16 + G3 × 2/16
Z2 = R2 × 14/16 + R3 × 2/16
(Calculate or process).

  The first coefficient in the calculation of the first to third expressions is 14/16, and the second coefficient is 2/16. When these two coefficients are added, it becomes 1.

Similarly, as shown in FIGS. 286 (1) and (c), the next block is
X3 = R3 × 13/16 + R4 × 3/16
Y3 = G3 × 13/16 + G4 × 3/16
Z3 = R3 × 13/16 + R4 × 3/16
(Calculate or process).

  The first coefficient in the calculation of the first to third expressions is 13/16, and the second coefficient is 3/16. When these two coefficients are added, it becomes 1.

Hereinafter, similarly, the numerator of the first coefficient is decreased by one and the second coefficient is increased by one. As shown in FIGS. 286 (1) and (e), the fifteenth block after performing the above processing is as follows.
X15 = R15 × 1/16 + R16 × 15/16
Y15 = G15 × 1/16 + G16 × 15/16
Z15 = R15 × 1/16 + R16 × 15/16
(Calculate or process).

The 15 blocks are repeated, and as shown in FIGS. 286 (1) and (f), as in FIGS. 286 (1) and (a),
X16 = R16 × 15/16 + R17 × 1/16
Y16 = G16 × 15/16 + G17 × 1/16
Z16 = R16 × 15/16 + R17 × 1/16
(Calculate or process).

  The block repetition is illustrated in FIG. FIG. 287 is a conceptual diagram in which 256 pixel rows are thinned out to 240 pixel rows. The 256 pixel row is divided into blocks each having 16 pixel rows. That is, 1 to 16 pixel rows, 17 to 32 pixel rows, 33 to 48 pixel rows,... 251 to 256 pixel rows. Sixteen pixel rows of each block are thinned out into 15 pixel rows.

  If the processing of FIG. 286 (1) is performed in the same manner in the first field and the second field, a block line is generated every 15 pixel rows. Therefore, the processing in the second field is changed from that in the first field. Specifically, the coefficient of one block is shifted. Note that although processing is shifted downward in FIG. 286 (2), processing may be shifted upward.

The processing is the same as that shown in FIG. 286 (1) in that each pixel is changed by 1/16 in the upper and lower pixels. In the second field, as shown in FIGS. 286 (2) (a),
X1 = R1 × 16/16
Y1 = G1 × 16/16
Z1 = R1 × 16/16
(Calculate or process).

  The first coefficient in the calculation of the first to third formulas is 1 because it is 16/16.

In the next block, as shown in FIGS. 286 (2) (b),
X2 = R2 × 15/16 + R3 × 1/16
Y2 = G2 × 15/16 + G3 × 1/16
Z2 = R2 × 15/16 + R3 × 1/16
(Calculate or process).

  The first coefficient in the calculation of the first to third expressions is 15/16, and the second coefficient is 1/16. When these two coefficients are added, it becomes 1.

The next block is as shown in FIGS. 286 (2) (c),
X3 = R3 × 14/16 + R4 × 2/16
Y3 = G3 × 14/16 + G4 × 2/16
Z3 = R3 × 14/16 + R4 × 2/16
(Calculate or process).

  The first coefficient in the calculation of the first to third expressions is 14/16, and the second coefficient is 2/16. When these two coefficients are added, it becomes 1.

Similarly, the next block is shown in FIGS. 286 (2) (d),
X4 = R4 × 13/16 + R5 × 3/16
Y4 = G4 × 13/16 + G5 × 3/16
Z4 = R4 × 13/16 + R5 × 3/16
(Calculate or process).

  The first coefficient in the calculation of the first to third expressions is 13/16, and the second coefficient is 3/16. When these two coefficients are added, it becomes 1.

Hereinafter, similarly, the numerator of the first coefficient is decreased by one and the second coefficient is increased by one. As shown in FIGS. 286 (1) and (e), the fifteenth block after performing the above processing is as follows.
X15 = R15 × 2/16 + R16 × 14/16
Y15 = G15 × 2/16 + G16 × 14/16
Z15 = R15 × 2/16 + R16 × 14/16
(Calculate or process).

The 15 blocks are repeated, and as shown in FIGS. 286 (2) (f), as in FIGS. 286 (2) (b),
X16 = R16 × 1/16 + R17 × 15/16
Y16 = G16 × 1/16 + G17 × 15/16
Z16 = R16 × 1/16 + R17 × 15/16
(Calculate or process).

  By adopting the above method, high-definition image display can be realized.

  In the precharge drive of the present invention, a predetermined voltage is applied to the source signal line 18. The source driver IC outputs a program current. However, in the present invention, the output voltage may be changed in accordance with the gradation in the precharge driving. That is, the precharge voltage output to the source signal line 18 is a program voltage. FIG. 306 shows a circuit configuration in which the precharge voltage program voltage circuit 3061 is introduced in the source driver IC.

  FIG. 306 is a block diagram of one output circuit corresponding to one source signal line 18. A current gradation circuit 654 and a voltage gradation circuit 3061 that outputs gradation output by precharging are configured. Video data is applied to the current gradation circuit 653 and the voltage gradation circuit 3061. The output of the voltage gradation circuit 3061 is applied to a terminal 681 that outputs to the source signal line 18 when the switch 481 is turned on / off. The switch 481 is controlled by a precharge enable (precharge ENBL) signal and a precharge signal (precharge SIG). The switch 481 is controlled to be closed when the precharge enable (precharge ENBL) signal is at the H level and the precharge signal (precharge SIG) is at the H level.

  The voltage gradation circuit 3061 includes a sample hold circuit, a DA circuit, and the like. Based on the digital video data, the voltage is converted by the DA circuit. The converted voltage is sampled and held by a sample and hold circuit and applied to one terminal of the switch 481 through an operational amplifier. The DA circuit does not need to be configured or formed for each voltage gradation circuit 3061. A DA circuit may be externally configured, and the output of the DA circuit may be sampled and held in the voltage gradation circuit 3061.

  The output of the voltage gradation circuit 3061 is applied at the beginning of 1H (indicated by symbol A) as shown in FIG. Thereafter, a program current is supplied to the source signal line by the current output circuit 654 (indicated by symbol B). That is, the voltage is set to the approximate source signal line potential by the voltage. Therefore, the driving transistor is set at a high speed up to a value close to the target current. Thereafter, the current is set up to a target current that compensates for variations in the driving transistor.

  The period A in which the voltage signal is applied is a period of 1/100 to 1/5 of 1H. Alternatively, the period is set to 0.2 μsec or more and 10 μsec or less. Therefore, the period other than the A period is the current application period of the B period. If the A period is short, charge and discharge of the source signal line 18 are not sufficiently performed, and thus insufficient writing occurs. On the other hand, if it is too long, the current application period (B) is shortened, and the program current cannot be sufficiently applied. Therefore, the current correction of the driving transistor 11a is insufficient.

  The voltage application period (A period) is preferably implemented from the beginning of 1H, but is not limited thereto. For example, the blanking period at the end of 1H may be started. Moreover, you may implement A period in the middle of 1H. That is, the voltage application period may be performed in any period of 1H. However, it is preferable that the voltage application period be implemented within a period of 1 / 4H (0.25H) from the beginning of 1H.

  In the embodiment of FIG. 305, the current is applied (B period) after the voltage precharge (A) period, but the present invention is not limited to this. For example, as shown in FIG. 362 (a), all (or most or most) of the 1H periods may be voltage precharge (* A) periods.

  In the period * A in FIG. 362 (a), the voltage program is executed in the period 1H. * A period is a low gradation area. Even if the current program is executed in the low gradation region, the current to be programmed is very small. Therefore, the potential of the source signal line 18 cannot be changed due to the parasitic capacitance of the source signal line 18. That is, the characteristic compensation of the TFT 11a (driving transistor) cannot be performed. In the current programming method, the programming current I and the brightness B are in a linear relationship. Therefore, the luminance change for one gradation is too large in the low gradation area. Therefore, gradation skip is likely to occur in the low gradation region.

  In order to solve this problem, in the present invention, as shown in FIG. 362 (a), a voltage program is executed over a period of 1H in the low gradation region (indicated by * A). The voltage step increment of the voltage program is reduced in the low gradation region. When the voltage applied to the TFT 11a of the pixel 16 is set to a certain step, the output current of the TFT 11a to the EL element 15 has a substantially square characteristic. Therefore, the luminance B with respect to the applied voltage (the luminance B is proportional to the output current to the EL element 15) has a linear human visual sensitivity (the human visual sensitivity changes in a low step when it has a square characteristic. For recognizing

  In the voltage program method, the characteristic compensation of the TFT 11a cannot be performed satisfactorily. However, since the display brightness of the screen 50 is low in the low gradation region, even if display unevenness due to insufficient characteristic compensation occurs, it is not visually recognized. On the other hand, in the voltage program method, the source signal line 18 can be charged and discharged satisfactorily. Therefore, the source signal line 18 can be sufficiently charged / discharged even in the low gradation region, and appropriate gradation display can be realized.

  As can be understood from FIG. 362 (a), when the potential of the source signal line 18 is close to the anode potential (Vdd), the voltage is applied to all (mostly) the period of 1H. When the potential of the source signal line 18 becomes close to 0 (V), the voltage program (A period) and the current program (B) are executed within the period of 1H. Note that in the case where the potential of the source signal line 18 is close to 0 (V) (high gradation region), the current program may be performed over the entire period of 1H.

  In a period other than * A in FIG. 362 (a), a voltage according to a voltage program is applied to the source signal line 18 during a fixed period of 1H (indicated by A), and then a current according to a current program is applied during a period B. Yes. As described above, a predetermined voltage is applied to the gate potential of the TFT 11a of the pixel 16 by applying the voltage during the period A so that the current flowing through the EL element 15 is approximately the desired value. Thereafter, the current flowing through the EL element 15 is set to a predetermined value by the program current during the B period. * In the period A, the voltage program is executed throughout the period of 1H (voltage is applied).

  FIG. 362 (a) shows a signal waveform applied to the source signal line 18 when the TFT 11a (driving transistor) of the pixel 16 is a P channel. However, the present invention is not limited to this. The TFT 11a of the pixel 16 may be an N channel (see, for example, FIG. 1). In this case, as shown in FIG. 362 (b), when the potential of the source signal line 18 is close to 0 (V), the voltage is applied to all (most) of the 1H period. When the potential of the source signal line 18 becomes close to the anode voltage (Vdd), the voltage program (A period) and the current program (B) are executed during the 1H period.

  Note that in the case where the potential of the source signal line 18 is close to Vdd (high gradation region), the current program may be executed over the entire period of 1H.

  In the present invention, the driving transistor 11a is described as a P-channel, but the present invention is not limited to this, and it goes without saying that the driving transistor 11a may be an N-channel. For ease of explanation, the explanation is made only assuming that the driving transistor 11a is a P-channel transistor.

  In the embodiments of the present invention such as FIG. 305 and FIG. 362, the voltage program is mainly written in the low gradation region, and the pixel is written. In the middle / high gradation region, the current program is mainly used for writing. In other words, it is possible to realize a good fusion of both current and voltage driving. This is because the low gradation region is displayed with a predetermined gradation by the voltage. This is because the write current is very small in current drive, and the voltage applied first for 1H (by voltage drive or precharge drive. Precharge drive and voltage drive are conceptually the same. If greatly differentiated, This is because precharge driving has a relatively small number of types of applied voltage, and voltage driving has a large number of types of applied voltage). In the middle gradation area, after writing by voltage, the amount of voltage deviation is compensated by the program current. That is, the program current is dominant (current drive is dominant). The high gradation region is written with a program current. No program voltage application is required. This is because the applied voltage is rewritten by the program current. That is, current driving is overwhelmingly dominant (see FIGS. 363 (b) and 364). Of course, it goes without saying that a voltage may be applied.

  In FIG. 306, the output of the voltage gradation circuit and the output of the current gradation circuit (including the precharge circuit) can be short-circuited at the terminal 681 because the current gradation circuit has high impedance. . In other words, since the current gray scale circuit has high impedance, even if the voltage from the voltage gray scale circuit is applied to the current gray scale circuit, a problem (such as an overcurrent flowing due to a short circuit) does not occur in the circuit. Therefore, although the voltage output and the current output state are switched in the present invention, the present invention is not limited to this. Needless to say, the voltage of the voltage gradation circuit 3061 may be applied to the terminal 681 by turning on the switch 481 (see FIG. 306) in the state where the program current is output from the current gradation circuit 654. Alternatively, the program current may be output from the current gradation circuit 654 with the switch 481 closed and a voltage applied to the terminal 681. Since the current gradation circuit 654 has a high impedance, there is no problem in the circuit. The above state is also an operation category in which the present invention switches between the voltage drive state and the current drive state. The present invention takes advantage of the nature of current and voltage circuits. This is a characteristic configuration not found in other driver circuits.

  Needless to say, as shown in FIG. 363, the program to be applied in the 1H period may be either voltage or current. In FIG. 363, the period * A is a 1H period in which the voltage program is implemented, and the period B is a 1H period in which the current program is implemented. The voltage program is implemented mainly in the low gradation region (indicated by * A), and the current program is implemented in the region of halftone or higher (indicated by B). As described above, switching between voltage driving and current driving may be switched according to the gradation or the magnitude of the program current.

  In the embodiment of the present invention shown in FIG. 306, the same video data is input to the voltage gradation circuit 3061 and the current gradation circuit 654. Therefore, the latch circuit for the video data may be common to the voltage gradation circuit 3061 and the current gradation circuit 654. That is, it is not necessary to provide the latch circuit for the video data in the voltage gradation circuit 3061 and the current gradation circuit 654 independently. Based on the data from the common video data latch circuit, the current gradation circuit 654 or / and the voltage gradation circuit 3061 outputs the data to the terminal 681.

  FIG. 368 is a timing chart of the driving method of the present invention. In FIG. 368, DATA in (a) is image data. CLK in (b) is a circuit clock.

  Pcntl in (c) is a precharge control signal. When the Pcntl signal is at the H level, only the voltage driving mode is set, and when it is at the L level, the current + voltage driving mode is set. Ptc in (d) is a precharge voltage or output switching signal from the voltage gradation circuit 3061. When the Ptc signal is at the H level, a voltage output such as a precharge voltage is applied to the source signal line 18. When the Ptc signal is at the L level, the program current from the current gradation circuit 654 is output to the source signal line.

  For example, in the case of data D (2), D (3), and D (8), the Pcntl signal is at the H level, so that the voltage is output from the voltage gradation circuit 3061 to the source signal line 18 (A period). . When Pcntl is at L level, a voltage is first output to the source signal line 18 and then a program current is output. A period in which the voltage is output is indicated by A, and a period in which the current is output is indicated by B. The period A during which the voltage is output is controlled by the Ptc signal. The Ptc signal is a signal for controlling on / off of the switch 481 in FIG. 306.

  In FIG. 368, the voltage output period A and the current output period B are switched. However, the present invention is not limited to this. Needless to say, the switch 481 (see FIG. 306) may be turned on and the voltage of the voltage gradation circuit 3061 may be applied to the terminal 681 while the program current is output. Alternatively, the program current may be output from the current gradation circuit 654 with the switch 481 closed and a voltage applied to the terminal 681. The switch 481 is opened after the period A. As described above, since the current gradation circuit 654 has a high impedance, there is no problem in the circuit even if it is short-circuited with the voltage circuit.

  In FIG. 370, the period during which the voltage is output to the source signal line 18 is varied by changing the H period of the Ptc signal. The H period is changed depending on the gradation number. For example, in D (7), the Ptc signal is at the L level during the 1H period. Therefore, the switch 481 in FIG. 306 is in an open state for a period of 1H. Therefore, no voltage is applied during the 1H period, and the current programming state is always maintained. In D (5), the Ptc period is longer than the other 1H periods. Therefore, the period A during which the voltage is applied is set to be long.

  In the above embodiment, the current drive state and the voltage drive state are switched. However, the present invention is not limited to this. In the embodiment of FIG. 369, there is no Ptc signal. Therefore, it is controlled by the Pcntl signal. Therefore, voltage driving is performed during the H period, and current driving is performed during the L period.

  The voltage program needs to change the voltage value output to the source signal line 18 depending on the light emission efficiency of the RGB EL elements 15. This is because the voltage (program voltage) applied to the gate terminal of the driving transistor 11a varies depending on the current output from the driving transistor 11a in the pixel configuration of FIG. The output current of the driving transistor 11 a needs to be different depending on the light emission efficiency of the EL element 15. In order to make the source driver IC 14 of the present invention versatile, it is necessary to cope with setting or adjustment even if the pixel size of the EL panel is different or the luminous efficiency of the EL element 15 is different. is there.

  The voltage gradation circuit 3061 outputs a voltage with the anode voltage (Vdd) as the origin. This state is shown in FIG. The anode voltage (Vdd) is the operation origin of the driving transistor 11a. For ease of explanation, it is assumed that the driving transistor 11a as shown in FIG. 1 has a P-channel configuration. Also in the case where the driving transistor 11a is an N-channel, only the origin position changes, so that the description is omitted. Therefore, for ease of explanation, the case where the driving transistor 11a is a P channel will be described as an example.

  In FIG. 311, the horizontal axis is gradation. In the present invention, description will be made assuming that the output gradation of the voltage gradation circuit 3061 is 256 (8 bits) gradation. The vertical axis represents the output voltage to the source signal line 18. In FIG. 311, the potential of the source signal line 18 decreases in proportion to the gradation number.

  The voltage of the source signal line 18 is the gate terminal voltage of the driving transistor 11a. The output current of the driving transistor 11a changes nonlinearly with the gate terminal voltage. In general, when a voltage is applied to the source signal line 18 as shown in FIG. 311, the output current of the driving transistor 11 a changes with a square characteristic with respect to the applied voltage. That is, in FIG. 311, the potential of the source signal line 18 is proportional to the gradation, but the output current of the driving transistor 11 a (current flowing through the EL element 15) has a substantially square characteristic.

  The circuit configuration in FIG. 311 is easy to configure. However, the current flowing through the EL element 15 is not proportional to the gradation number. This is because when a linearly changing voltage is applied to the driving transistor 11a (in the example of FIG. 311), the output current is output in proportion to the square of the applied voltage due to the square characteristics of the transistor 11a. . Therefore, when the gradation number is small, the change in the output current of the transistor 11a is small, and increases rapidly as the gradation number increases. Therefore, the accuracy of the output current with respect to the gradation number changes.

  FIG. 312 shows a configuration for solving this problem. In FIG. 312, when the gradation number is small, the change in the output voltage to the source signal line 18 is large. Further, the smaller the gradation number, the greater the voltage change rate to the source signal line 18. On the other hand, when the gradation number increases (approaching 256th), the change in the output voltage to the source signal line 18 is reduced. Therefore, the relationship between the source signal line output current and the gradation number is non-linear. This non-linear characteristic is made linear by combining with the output current characteristic to the EL element 15 with respect to the gate terminal voltage of the driving transistor 11a. That is, the output current to the EL element 15 of the driving transistor 11a with respect to the change of the gradation number is adjusted to be linear.

  In the current programming method, the current flowing through the EL element 15 with respect to the gradation number has a linear relationship. The configuration (method) in FIG. 312 is a voltage program method. In FIG. 312, the voltage programming method is used, but the current flowing through the EL element 15 with respect to the gradation number has a linear relationship. Therefore, matching is good in the configuration (method) in which the current program method and the voltage program method are combined as shown in FIGS. 306 and 305.

  In FIG. 312, the output current Ie of the driving transistor 11 a with respect to the gradation number changes substantially linearly. Therefore, the relationship of the source signal line output voltage with respect to the gradation number is not small when the gradation number is small, but is finely changed as the gradation number increases. When the gradation number is K and the source signal line is Vs, the change curve equation is such that the source signal line voltage Vs = A / (K · K) as shown in FIG. A is a proportionality constant. Alternatively, the source signal line voltage Vs = A / (B · K · K + C · K + D) or Vs = A / (B · K · K + C). D, B, C, and A are constants.

  As described above, by forming the change curve equation, when the change curve equation is multiplied by the output current Ie of the driving transistor with respect to the source signal line voltage Vs, Ie with respect to Vs can be in a linear relationship.

  In FIG. 312, the change curve equation is a curve. Therefore, it is relatively difficult to create a change curve. For this problem, it is appropriate to construct a change curve equation with a plurality of straight lines as shown in FIG. That is, a change curve is formed by two or more straight lines having an inclination.

  In FIG. 312, the increment of the output voltage of the source signal line 18 is increased (indicated by A) in the range where the gradation number is small, and the increment of the output voltage of the source signal line 18 is decreased in the range where the gradation number is large. (Indicated by B). In the change curve of FIG. 312, the output current Ie of the driving transistor 11a with respect to the gradation number K has a non-linear relationship, and a plurality of non-linear outputs are combined. However, the relationship between the output current Ie and the gradation number K increases in a nearly linear range. Therefore, the combination with current program driving is also easy.

  In the embodiment of FIG. 311, when the gradation number is 0, the potential of the source signal line 18 is not the anode potential (Vdd). The output current of the driving transistor 11a is 0 or almost 0 until the rising voltage. The range up to this rising voltage is the C region. Accordingly, since the area C is blank, the output voltage step of the source signal line can be made relatively fine as compared with FIG. 311 or the like when the number of gradation numbers is constant.

  314 (the relationship where the potential of the source signal line 18 is not the origin (anode potential) when the gradation number is 0), the non-linear relationship of FIG. 312, the relationship combining the plurality of relational expressions of FIG. Needless to say, the relationship of 311 straight lines may be combined with each other.

  The voltage program needs to change the voltage value output to the source signal line 18 depending on the light emission efficiency of the RGB EL elements 15. This is because the voltage (program voltage) applied to the gate terminal of the driving transistor 11a varies depending on the current output from the driving transistor 11a in the pixel configuration of FIG. The output current of the driving transistor 11 a needs to be different depending on the light emission efficiency of the EL element 15. In order to make the source driver IC 14 of the present invention versatile, it is necessary to cope with setting or adjustment even if the pixel size of the EL panel is different or the luminous efficiency of the EL element 15 is different. is there.

  FIG. 364 shows a circuit configuration utilizing the fact that the voltage reference is Vdd in voltage driving. The voltage magnitude Vdd on the vertical axis in FIGS. 311 to 314 is fixed and changed. Therefore, even when the gradation number range (256 gradations = 256 increments) is made constant, the magnitude of the voltage on the vertical axis can be adjusted, and the source driver circuit (IC) 14 can be generalized. it can.

  In FIG. 364, the voltage range of the electronic volume 451 is from Vdd to Vbv. Therefore, the output voltage Vad of the operational amplifier 722a is a value from Vdd to Vbv. Vbv is input from the outside of the source driver IC (circuit) 14. Further, it may be generated inside the IC (circuit) 14. The switch S of the electronic volume 451 decodes 8-bit control data (gradation number) by the decoder circuit 532, the corresponding switch S is closed, and the voltage between the voltage Vdd and Vbv is output from Vad. The voltage Vad is the voltage that is the vertical axis of FIGS. 311 to 314. Therefore, Vad can be easily changed or adjusted by changing Vbv. That is, as shown in FIG. 366, the vertical axis indicates the range of the Vdd voltage to the Vbv voltage. The circuit configuration of FIG. 364 is provided for each of RGB as shown in FIG. If the light emission efficiency of the RGB EL elements 15 is balanced and the white balance can be obtained when the RGB current Ic is Icr: Icg: Icb = 1: 1: 1, one circuit configuration common to RGB (see FIG. Needless to say, 364). Also, a plurality of Ic current generation circuits such as R and G, G and B, and B and R may be shared.

  236, 237, etc. have a two-stage latch circuit 2361 for the current program circuit. The source driver IC (circuit) 14 of the present invention includes both a current program circuit and a voltage program circuit. Therefore, as shown in FIG. 365, a two-stage latch circuit 3651 for voltage programming is provided.

  In FIG. 364 and the like, the anode voltage vdd is the origin. FIG. 371 makes it possible to adjust the voltage corresponding to the anode potential. The voltage from the operational amplifier 722c is applied to the terminal Vdd of the electronic volume 451. The applied voltage is Vbvh. The lower limit voltage of the electronic volume 451 is Vbvl. Therefore, the voltage range applied to the source signal line 18 is Vbvh or less and Vbvl or more as shown in FIG. Since other matters are the same as or similar to those of the other embodiments, description thereof will be omitted.

  As described in FIG. 314, the driving transistor 11a has a rising voltage indicated by C. Below the rising voltage is black display (the driving transistor 11a does not supply current to the EL element 15). FIG. 373 is a circuit for generating the C blank of FIG. The voltage range of C blank is adjusted by Pk data. The Pk data is 8 bits. The Pk data and the gradation number data Data are added by the adding circuit 3731. The added data becomes 9 bits, is input to the decoder circuit 532, is output, and closes the corresponding switch S of the electronic volume 451.

  FIG. 374 shows terminals of the source driver IC (circuit) 14 of the present invention. FIG. 374 is an implementation circuit of FIG. It has 8-bit RGB gradation number data (DataR, DataG, DataB) and RGB reference lower limit voltages (VbvR, VbvG, VbvB).

  FIG. 375 is an implementation circuit of FIG. It has 8-bit RGB gradation number data (DataR, DataG, DataB), RGB reference lower limit voltages (VbvlR, VbvlG, VbvlB), and RGB reference upper limit voltages (VbvhR, VbvhG, VbvhB).

  The above embodiment is line sequential driving. FIG. 307 shows a circuit configuration of dot sequential driving. The program voltage is applied by the dot sequential circuit 3074. The dot sequential drive does not include a sample hold circuit, and the sampled voltage (signal) is sequentially applied to the source signal line 18 without being held in the source driver IC (circuit) 14, and the source signal line 18 Is used as a hold capacitor (circuit configuration).

  In FIG. 307, a controller IC (circuit) 81 has a functional block 3071 and a line memory 3072. The functional block 3071 has a gamma conversion circuit and the like. The line memory 3072 matches the timing with the current program circuit of the source driver IC 14. Therefore, the image data is input to the precharge voltage generation circuit 3041 at the same timing in the line memory 3072. The precharge voltage generation circuit 3041 also has a function of distributing precharge voltages applied to a plurality of ICs (# 1, # 2,... #N). The reason for generating a plurality of precharge voltages simultaneously as described above is to secure a period for applying the precharge voltages by dot sequential driving.

  In the source driver circuit (IC) 14, a latch circuit is configured, and the applied precharge voltage is applied to the source signal line 18 by closing the switch 481 of the preparation point sequential circuit 3074. The unit current transistor group 521c and the like correspond to the current gradation circuit 654 in FIG.

  The above embodiment is a system implemented by the controller IC 81. However, since the generation of the precharge voltage is complicated, it is preferable to separately arrange the precharge controller IC 81b as shown in FIG. The precharge controller IC 81b applies to the DA circuit 551 a plurality of precharge voltages (obtained by dividing the image data of one pixel row in order to ensure the application period of the precharge voltage for each IC). The DA circuit 551 generates a precharge voltage for each source driver IC 14. This precharge voltage is applied to the dot sequential circuit 3074 in FIG.

  Note that the dot sequential circuit 3074 is preferably divided into a plurality of phases such as four phases to ensure a precharge voltage application period, as shown in FIG.

  In the above embodiment, the precharge voltage is applied via the source driver IC 14, but the present invention is not limited to this. For example, as shown in FIG. 310, the precharge transistor 3102 formed on the array 71 substrate is controlled to be turned on / off so that the precharge voltage applied to the precharge voltage line 3101 is applied to the source signal line 18. Needless to say.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments employing an EL display panel, an EL display device, or a driving method of the present invention will be described below with reference to the drawings.

  The EL display panel has a problem that the chromaticity of B is particularly bad, while the chromaticity of R is very good. Therefore, when an image is displayed, the display color may be different from the original image. In the XY coordinates of the chromaticity in FIG. 326, the solid line is the NTSC color range. The dotted line is the color range of the organic EL. Since the color reproduction range of NTSC and the color reproduction range of organic EL are shifted, there is a problem that leaves become a dead leaf color particularly in an image display with many trees.

  A method for solving this problem is color management processing. In this method, image color correction is performed by signal processing. A measure for improving the chromaticity of an image by using a color filter is also exemplified.

  In order to improve the color purity of the EL display panel using the color filter, a color filter 3581 may be arranged, configured, or formed on the light exit side of the display panel 71 as shown in FIG. The color filter may be disposed or formed between the polarizing film 109 and the panel 71 as shown in FIG. 360 (a). The chromaticity of B can be improved by using a color filter that cuts cyan. As the color filter, in addition to a filter made of resin, an interference filter made of an optical interference multilayer film may be used. The color filter may be formed or arranged on the polarizing film 3581 as illustrated in FIG. 360 (b).

  In order to realize color management (color correction processing) in a circuit, it is preferable to change the output ratio of the RGB unit transistors 484 output from each transistor group 521. In order to suppress the phenomenon that the chromaticity of B is poor in organic EL (on the other hand, the chromaticity of R is good) and the leaves of the tree become dead leaves, the current of B should be increased or the current of R should be decreased. .

  In order to adjust the output current of the transistor group 521c, the current Ic in FIG. 208 may be adjusted (in RGB). In addition, it cannot be overemphasized that the matter, structure, method, and apparatus which were demonstrated in this specification in the Example of this invention are applicable.

  A configuration for adjusting the current Ic is illustrated in FIG. FIG. 327 (a) shows a configuration in which 8-bit data is converted into an analog signal by the DA circuit 551 and input to the operational amplifier 722a to change (adjust) the current Ic. The basic current magnitude is externally attached or built-in resistor R1.

  FIG. 327 (b) shows a configuration in which 8-bit data is converted into an analog signal by the DA circuit 551 and the current Ic is changed (adjusted). The basic current magnitude is externally attached or built-in resistor R1. However, in the configuration of FIG. 327 (b), the change in the current Ic with respect to the output voltage of the DA circuit 551 is nonlinear.

  FIG. 327 (c) shows a configuration in which 8-bit data is converted into an analog signal by the DA circuit 551, and the current Ic is changed (adjusted) via the transistor 472b. The basic current magnitude is externally attached or built-in resistor R1. However, in the configuration of FIG. 327 (b), the change in the current Ic with respect to the output voltage of the DA circuit 551 is nonlinear.

  FIG. 328 shows a circuit configuration using an electronic volume circuit 451. The output of the DA circuit 551 is connected to the terminal voltage Vs of the electronic volume circuit 451 in FIG. Other configurations are the same as or similar to those shown in FIGS. That is, the current Ic is switched by the electronic volume 451 and can be adjusted by the output of the DA circuit 551 for color management processing. Needless to say, the configurations of FIGS. 327 and 328 may be combined. Further, it goes without saying that the color management processing may be performed by controlling the electronic volume 451 in FIG.

  FIG. 329 is a modification of FIG. The voltage Vc can be directly input to the input terminal c of the operational amplifier 722a. When Vc is input, the electronic volume 451 is controlled so that none of the switches S is selected and opened. The current Ic can be easily controlled or adjusted by applying the Vc voltage from the outside of the IC 14.

  FIG. 330 changes the input terminal voltage of the operational amplifier 722a by changing the power supply voltage Vda of the DA circuit 551a by the DA circuit 551b. The output current Ic changes linearly with the input terminal voltage.

  In FIG. 330, the output voltage of the DA circuit 551a changes linearly with 8-bit digital data, and the output voltage of the DA circuit 551a changes linearly with the output voltage of the DA circuit 551b. In the circuit configuration shown in FIG. 330, the change width of the current Ic is large and the change is linear, which is preferable as the configuration.

  The color management process is controlled by each RGB current. Note that the RGB current can be expressed by a lighting rate (duty ratio is 1/1). When the duty ratio is 1/1, the lighting rate can be calculated from the sum of image data and the maximum value. When the color management process is performed, the lighting rate is obtained individually for RGB. That is, the lighting rate of R, the lighting rate of G, and the lighting rate of B are obtained (the current consumption of R, the current consumption of G, and the current consumption of B are obtained), and the range and size of a certain ratio Perform color management processing at. This is because, when there are many white displays on the screen, the white balance is achieved and color management processing is unnecessary.

  FIG. 331 is an explanatory diagram of a color management processing method. The duty ratio control is performed in order to average the current consumption of the EL panel as described above. The color management process is performed by adjusting the reference current Ic. In FIG. 331, the reference current Icr of R is decreased and the reference current Icb of B is increased in a range where the lighting rate is high. Further, the B reference current Icb is adjusted by increasing the lighting rate even in the range of the intermediate level (30% to 60%). With the above processing, the color management processing of the EL display device can be satisfactorily realized.

  In FIG. 332, the RGB reference current Ic is increased in the lighting rate region. This is to increase the dynamic range of the image at a low lighting rate (see FIGS. 89 to 93 and its description). The point that the reference current Icb of B is increased in the region where the lighting rate of B is high is color management processing. As described above, the present invention can realize both dynamic image processing and color management processing by reference current control.

  FIG. 333 shows a method of controlling the R reference current Icr to a plurality of levels. As described above, according to the present invention, color management processing can be performed by freely adjusting the reference current.

  FIG. 334 shows a method of controlling the reference current from the RGB lighting rates. However, the color management processing of the EL display panel may be controlled by the ratio of R and B currents (Icr, Icb). FIG. 334 is an explanatory diagram of this embodiment. Instead of the lighting rate on the horizontal axis in FIG. 331, B lighting rate / R lighting rate (B consumption current / R consumption current) is used. The B reference current Icr is changed when the B lighting rate / R lighting rate (B consumption current / R consumption current) exceeds a certain level.

  Similarly, FIG. 335 shows B lighting rate / R lighting rate (B consumption current / R consumption current) instead of the lighting rate on the horizontal axis of FIG. When the B lighting rate / (R lighting rate + G lighting rate) (B consumption current / (R consumption current + G lighting rate)) becomes a certain level or more, the B reference current Icr is changed.

  Note that the above-described configurations of FIGS. 327 to 330 are configurations for adjusting or controlling the current Ic. The output current of the transistor group 521c can be changed by changing the current Ic. Therefore, it goes without saying that this configuration can be used not only for color management processing but also for gradation control, output current control for the transistor 521c, etc., and a white balance adjustment circuit.

  In FIGS. 327 to 335, the color management process is performed by adjusting the reference current Ic. However, the present invention is not limited to this. 41, 125, 130, 131, and 132, the luminance of RGB is individually adjusted by adjusting the duty ratio or changing, controlling, or adjusting the ratio of the non-display area 51 of each RGB. Can be adjusted. Therefore, it goes without saying that the color management processing may be performed using these configurations or methods.

  In this specification, the reference current is described as being changed (for example, FIG. 89, FIG. 90 to FIG. 93, FIG. 331 to FIG. 336, FIG. 383, FIG. 386, etc.). Changing the reference current means changing the program current Iw flowing through the source signal line. Therefore, it goes without saying that changing or controlling or adjusting the reference current can be replaced by changing, controlling or adjusting the program current Iw flowing through the source signal line 18. In the present invention, the current output from the terminal 681 of the source driver circuit 14 can be changed, adjusted, or changed proportionally, at a constant rate, or while maintaining a predetermined relationship by changing the reference current. Or it can be controlled.

  In FIGS. 1, 2, 32, 38, 114, 113, 116, 115, 117, and 387, the program current Iw and the current Ie flowing through the EL element 15 are substantially the same. Accordingly, it goes without saying that changing or controlling or adjusting the reference current can be replaced by changing or controlling or adjusting the current Ie (Iw) flowing through the driving transistor or EL element 15. However, in FIGS. 261, 323, and 317, the currents Ie and Iw flowing through the EL element 15 do not match. However, changing, controlling, or adjusting the reference current can be said to change, control, or adjust the program current Iw that flows through the source signal line 18. The current that flows through the EL element 15 can be varied, controlled, or adjusted approximately proportionally. Needless to say, it can be replaced.

  In addition, as described with reference to FIGS. 305, 362, and 363, changing the reference current means changing the potential of the source signal line 18. For example, when the reference current is increased, the program current Iw is increased proportionally (correlated), and the potential of the source signal line 18 is decreased (when the driving transistor is a P channel). On the contrary, when the reference current is reduced, the program current Iw is reduced proportionally (correlatedly), and the potential of the source signal line 18 is increased (when the driving transistor is a P channel). Therefore, the reference current can be varied, controlled, or adjusted when the potential of the source signal line 18 can be changed, adjusted, varied, or controlled proportionally, at a constant rate, or while maintaining a predetermined relationship. Can be replaced.

  As described above, it is described that the reference current is changed based on the lighting rate. However, the program current Iw flowing through the source signal line is changed based on the lighting rate, and the source signal line 18 is changed. The program current Iw flowing through the circuit is variable, controlled, or adjusted. In addition, the current output from the terminal 681 of the source driver circuit 14 is changed, adjusted, varied, or controlled in proportion, at a constant rate, or in a state where a predetermined relationship is maintained. Also, based on the lighting rate or data sum, the potential of the source signal line 18 or the gate terminal potential of the driving transistor is changed or adjusted proportionally, at a constant rate, or in a state where a predetermined relationship is maintained. Or it can be variable or controlled.

  Needless to say, based on the lighting rate, it can be replaced based on the data sum of video signals. In particular, in the case of current driving, the magnitude of the video signal is proportional to the current flowing through the pixel 16.

  Hereinafter, an EL display panel or an EL display device of the present invention or a device using the driving method thereof will be described. The following apparatus implements the previously described apparatus or method of the present invention.

  FIG. 158 is a cross-sectional view of the viewfinder in the embodiment of the present invention. However, it is schematically drawn for easy explanation. In addition, there are parts that are partially enlarged or reduced, and some parts are omitted. For example, in FIG. 158, the eyepiece cover is omitted. The above also applies to other drawings.

  The back surface of the body 1573 is dark or black. This is because stray light emitted from the EL display panel (display device) 1574 is diffusely reflected on the inner surface of the body 1573 to prevent a decrease in display contrast. Further, a phase plate (λ / 4 plate or the like) 108, a polarizing plate 109, or the like is disposed on the light emission side of the display panel. This is also explained in FIG. 10 and FIG.

  A magnifying lens 1582 is attached to the eyepiece ring 1581. The observer changes the insertion position of the eyepiece ring 1581 in the body 1573 and adjusts so that the display image 50 on the display panel 1574 is in focus.

  Further, if the positive lens 1583 is disposed on the light emission side of the display panel 1574 as necessary, the principal ray incident on the magnifying lens 1582 can be converged. Therefore, the lens diameter of the magnifying lens 1582 can be reduced, and the viewfinder can be downsized.

  FIG. 159 is a perspective view of the video camera. The video camera includes a photographic (imaging) lens unit 1592 and a video or camera body 1573, and the photographic lens unit 1592 and the viewfinder unit 1573 are back to back. An eyepiece cover is attached to the viewfinder (see also FIG. 158) 1573. An observer (user) observes the image 50 on the display panel 1574 from the eyepiece cover portion.

  On the other hand, the EL display panel of the present invention is also used as a display monitor. The display unit 50 can freely adjust the angle at a fulcrum 1591. When the display unit 50 is not used, it is stored in the storage unit 1593.

  The switch 1594 is a changeover or control switch that performs the following functions. A switch 1594 is a display mode switching switch. The switch 1594 is preferably attached to a mobile phone or the like. The display mode changeover switch 1594 will be described.

  As one of the driving methods of the present invention, there is a method in which an N-fold current is supplied to the EL element 15 to light it for a period of 1 / M of 1F. The brightness can be changed digitally by changing the lighting period. For example, assuming that N = 4, a current that is four times as large as the EL element 15 is passed. If the lighting period is set to 1 / M and M = 1, 2, 3, and 4 are switched, the brightness can be switched from 1 to 4 times. In addition, you may comprise so that it can change with M = 1, 1.5, 2, 3, 4, 5, 6, etc.

  The above switching operation is a configuration in which the display screen 50 is displayed very brightly when the power of a mobile phone, a monitor, etc. is turned on, and the display brightness is reduced to save power after a certain period of time. Used for. It can also be used as a function for setting the brightness desired by the user. For example, when outdoors, the screen is very bright. This is because the surroundings are bright outdoors and the screen cannot be seen at all. However, if the display is continued with high luminance, the EL element 15 deteriorates rapidly. For this reason, when it is very bright, it is configured to return to normal luminance in a short time. Further, in the case of displaying with high brightness, the display brightness can be increased by the user pressing the button.

  Therefore, it is preferable that the user can be switched with the button 1594, can be automatically changed in the setting mode, or can be automatically switched by detecting the brightness of external light. Further, it is preferable that the display brightness is set to 50%, 60%, and 80% and can be set by the user.

  The display screen 50 is preferably a Gaussian distribution display. The Gaussian distribution display is a method in which the brightness at the center is bright and the periphery is relatively dark. Visually, if the central part is bright, it is felt bright even if the peripheral part is dark. According to the subjective evaluation, if the peripheral part keeps 70% of brightness compared to the central part, it is visually inferior. Even if the brightness is further reduced to 50% luminance, there is almost no problem. In the self-luminous display panel of the present invention, the above-described N-fold pulse driving (a method in which an N-fold current is supplied to the EL element 15 and the light is lit for 1 / M of 1F) is used from the top to the bottom of the screen. A Gaussian distribution is generated in the direction.

  Specifically, the value of M is increased at the top and bottom of the screen, and the value of M is decreased at the center. This is realized by modulating the operation speed of the shift register of the gate driver 12 or the like. The left and right brightness modulation of the screen is generated by multiplying the table data and the video data. With the above operation, when the peripheral luminance (angle of view 0.9) is 50%, the power consumption can be reduced by about 20% compared to the case of 100% luminance. When the peripheral luminance (angle of view 0.9) is 70%, the power consumption can be reduced by about 15% compared to the case of 100% luminance.

  It is preferable to provide a changeover switch or the like so that the Gaussian distribution display can be turned on and off. This is because, for example, when the Gaussian display is used outdoors, the periphery of the screen cannot be seen at all. Therefore, it is preferable that the user can be switched with a button, can be automatically changed in a setting mode, or can be switched automatically by detecting the brightness of external light. In addition, it is preferable that the peripheral brightness is set to 50%, 60%, and 80% so that the user can set it.

  In a liquid crystal display panel, a fixed Gaussian distribution is generated by a backlight. Therefore, the Gaussian distribution cannot be turned on / off. The fact that the Gaussian distribution can be turned on / off is an effect peculiar to a self-luminous display device.

  Further, when the frame rate is predetermined, flicker may occur due to interference with the lighting state of an indoor fluorescent lamp or the like. That is, when the fluorescent lamp is lit at an alternating current of 60 Hz, if the EL display element 15 operates at a frame rate of 60 Hz, a slight interference occurs and the screen feels slowly blinking. There is. To avoid this, change the frame rate. The present invention adds a frame rate changing function. In addition, the N or M value can be changed in N-fold pulse driving (a method in which an N-fold current is supplied to the EL element 15 and lighted only for a period of 1 / M of 1F).

  The above functions can be realized by the switch 1594. The switch 1594 switches and realizes the above-described functions by holding down a plurality of times according to the menu of the display screen 50.

  Needless to say, the above items are not limited to mobile phones but can be used for televisions, monitors, and the like. In addition, it is preferable to display an icon on the display screen so that the user can immediately recognize the display state. The above matters are the same for the following items.

  The EL display device and the like of this embodiment can be applied not only to a video camera but also to an electronic camera, a still camera, or the like as shown in FIG. The display device is used as a monitor 50 attached to the camera body 1601. In addition to the shutter 1603, a switch 1594 is attached to the camera body 1601.

  The above is the case where the display area of the display panel is relatively small, but the display screen 50 tends to bend when the display area is larger than 30 inches. As a countermeasure, in the present invention, an outer frame 1611 is attached to the display panel as shown in FIG. 161, and the outer frame 1611 is attached by a fixing member 1614 so that it can be suspended. The fixing member 1614 is used to attach to a wall or the like.

  However, as the screen size of the display panel increases, the weight increases. Therefore, a leg mounting portion 1613 is disposed on the lower side of the display panel so that the weight of the display panel can be held by the plurality of legs 1612.

  The leg 1612 can move left and right as shown in A, and the leg 1612 can be contracted as shown in B. Therefore, the display device can be easily installed even in a narrow place.

  In the television of FIG. 161, the screen surface is covered with a protective film (or a protective plate). This is for the purpose of preventing an object from hitting the surface of the display panel and damaging it. An AIR coat is formed on the surface of the protective film, and the surface is embossed to prevent external conditions (external light) from appearing on the display panel.

  A certain space is arranged by spreading beads or the like between the protective film and the display panel. Moreover, a fine convex part is formed in the back surface of a protective film, and space is hold | maintained between a display panel and a protective film with this convex part. By holding the space in this way, the impact from the protective film is suppressed from being transmitted to the display panel.

  It is also effective to place or inject an optical binder such as a liquid such as alcohol or ethylene glycol or a solid resin such as an epoxy resin between the protective film and the display panel. This is because interface reflection can be prevented and the optical binder functions as a buffer material.

  Examples of the protective film include a polycarbonate film (plate), a polypropylene film (plate), an acrylic film (plate), a polyester film (plate), and a PVA film (plate). Needless to say, other engineering resin films (ABS and the like) can be used. Moreover, what consists of inorganic materials, such as tempered glass, may be used. The same effect can be obtained by coating the surface of the display panel with an epoxy resin, a phenol resin, or an acrylic resin with a thickness of 0.5 mm or more and 2.0 mm or less instead of disposing the protective film. It is also effective to emboss the surface of these resins.

  It is also effective to coat the surface of the protective film or coating material with fluorine. This is because the dirt on the surface can be easily wiped off with a detergent or the like. Further, the protective film may be formed thick and may also be used as a front light.

  It goes without saying that the display panel according to the embodiment of the present invention can be effectively combined with a three-side free configuration. In particular, the three-side free configuration is effective when the pixel is manufactured using amorphous silicon technology. Further, in a panel formed by amorphous silicon technology, it is not possible to control the process of variation in characteristics of transistor elements. Therefore, it is preferable to implement the N-fold pulse driving, reset driving, dummy pixel driving, and the like of the present invention. That is, the transistor 11 and the like in the present invention are not limited to those using polysilicon technology, but may be those using amorphous silicon. That is, the transistor 11 constituting the pixel 16 in the display panel of the present invention may be a transistor formed by using amorphous silicon technology. Needless to say, the gate driver circuit 12 and the source driver circuit 14 may also be formed or configured using amorphous silicon technology.

  Note that the N-fold pulse driving of the present invention (FIGS. 13, 16, 19, 20, 22, 24, 30 and the like) or the like is performed more than the display panel by forming the transistor 11 using low-temperature polysilicon technology. This is effective for a display panel in which the transistor 11 is formed by amorphous silicon technology. This is because the characteristics of adjacent transistors in the amorphous silicon transistor 11 are substantially the same. Therefore, even when driving with the added current, the driving current of each transistor is almost the target value (in particular, the N-fold pulse driving in FIGS. 22, 24, and 30 is a pixel configuration of a transistor formed of amorphous silicon). Effective). It goes without saying that the present invention can be applied not only to low-temperature polysilicon display panels but also to amorphous silicon display panels and COS display panels.

  The drive method and drive circuit of the present invention described in this specification such as duty ratio control drive, reference current control, N-fold pulse drive, source driver IC (circuit), gate driver configuration, etc. It is not limited to a drive circuit or the like. Needless to say, the present invention can be applied to other displays such as a field emission display (FED) as shown in FIG.

  In the FED of FIG. 173, electron emission protrusions 1733 (corresponding to the pixel electrode 105 in FIG. 10) that emit electrons in a matrix are formed on the substrate 71. A holding circuit 1734 for holding image data from the video signal circuit 1732 (corresponding to the source driver circuit 14 in FIG. 1) is formed in the pixel (corresponding to a capacitor in FIG. 1). A control electrode 1731 is disposed on the front surface of the electron emission protrusion 1733. A voltage signal is applied to the control electrode 1731 by an on / off control circuit 1735 (which corresponds to the gate driver circuit 12 in FIG. 1).

  If the peripheral circuit is configured as shown in FIG. 174 with the pixel configuration of FIG. 173, duty ratio control driving or N-fold pulse driving can be performed. An image data signal is applied from the video signal circuit 1732 to the source signal line 18. The pixel 16 selection signal is applied from the on / off control circuit 1735a to the selection signal line 2173, the pixels 16 are sequentially selected, and image data is written. Further, an on / off signal is applied from the on / off control circuit 1735b to the on / off signal line 1742, and the FED of the pixel is on / off controlled (duty ratio control).

  The technical idea described in the embodiments of the present invention can be applied to a video camera, a projector, a stereoscopic television, a projection television, and the like. The present invention can also be applied to a viewfinder, a mobile phone monitor, a PHS, a portable information terminal and its monitor, a digital camera and its monitor.

  The present invention can also be applied to an electrophotographic system, a head mounted display, a direct view monitor display, a notebook personal computer, a video camera, and an electronic still camera. The present invention can also be applied to an automatic cash drawer monitor, public telephone, videophone, personal computer, wristwatch, and display device thereof.

  Furthermore, it goes without saying that the present invention can be applied or applied to a display monitor for home appliances, a pocket game device and its monitor, a backlight for a display panel, or a lighting device for home use or business use. The lighting device is preferably configured so that the color temperature can be varied. In this case, the color temperature can be changed by forming RGB pixels in a stripe or dot matrix and adjusting the current flowing through them. It can also be applied to display devices such as advertisements or posters, RGB traffic lights, warning indicator lights, and the like.

  The organic EL display panel is also effective as a light source for the scanner. Using an RGB dot matrix as a light source, the object is irradiated with light to read an image. Of course, it goes without saying that it may be monochromatic. Moreover, it is not limited to an active matrix, A simple matrix may be sufficient. If the color temperature can be adjusted, the image reading accuracy can be improved.

  The organic EL display device is also effective for the backlight of the liquid crystal display device. The RGB pixels of the EL display device (backlight) are formed in a stripe shape or a dot matrix shape, and the color temperature can be changed by adjusting the current passed through them, and the brightness can be easily adjusted. In addition, since it is a surface light source, a Gaussian distribution that brightens the central part of the screen and darkens the peripheral part can be easily configured. It is also effective as a backlight for a field sequential type liquid crystal display panel that alternately scans R, G, and B light. Further, even if the backlight blinks, it can be used as a backlight of a liquid crystal display panel for displaying moving images by inserting black.

  According to the present invention, it is possible to suppress a variation in the gradation output current from each output terminal and perform a good image display, which is useful.

It is a pixel block diagram of the display panel of this invention. It is a pixel block diagram of the display panel of this invention. It is explanatory drawing of operation | movement of the display panel of this invention. It is explanatory drawing of operation | movement of the display panel of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a block diagram of the display apparatus of this invention. It is explanatory drawing of the manufacturing method of the display panel of this invention. It is a block diagram of the display apparatus of this invention. It is a block diagram of the display apparatus of this invention. It is sectional drawing of the display panel of this invention. It is sectional drawing of the display panel of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a block diagram of the display apparatus of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a block diagram of the display apparatus of this invention. It is a pixel block diagram of the display panel of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a block diagram of the display apparatus of this invention. It is a block diagram of the display apparatus of this invention. It is a pixel block diagram of the display panel of this invention. It is a pixel block diagram of the display panel of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. 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It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is explanatory drawing of the drive circuit of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. 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It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is a pixel block diagram of the display panel of this invention. It is a pixel block diagram of the display panel of this invention. It is a pixel block diagram of the display panel of this invention. It is a pixel block diagram of the display panel of this invention. It is a pixel block diagram of the display panel of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. It is explanatory drawing of the drive circuit of the display apparatus of this invention. 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It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the display apparatus of this invention. It is explanatory drawing of the display apparatus of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the power supply circuit of this invention. It is explanatory drawing of the power supply circuit of this invention. It is explanatory drawing of the power supply circuit of this invention. It is explanatory drawing of the power supply circuit of this invention. It is explanatory drawing of the power supply circuit of this invention. It is explanatory drawing of the power supply circuit of this invention. It is explanatory drawing of the power supply circuit of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. 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It is explanatory drawing of the display apparatus of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the drive method of this invention. It is explanatory drawing of the drive method of this invention. It is explanatory drawing of the drive method of this invention. It is explanatory drawing of the drive method of this invention. It is explanatory drawing of the drive method of this invention. It is explanatory drawing of the drive method of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the source driver IC (circuit) of this invention. It is explanatory drawing of the drive circuit of this invention. It is explanatory drawing of the drive circuit of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is an explanatory diagram of a drive circuit of a display panel of the present invention. It is an explanatory diagram of a drive circuit of a display panel of the present invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of driver IC (circuit) of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. It is explanatory drawing of the drive method of the display panel of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 3 is a clear diagram of a display panel driving method of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. It is explanatory drawing of driver IC (circuit) of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention.

Explanation of symbols

11 Transistor (Thin Film Transistor)
12 Gate driver IC (circuit)
14 Source driver IC (circuit)
15 EL (element) (light emitting element)
16 pixel 17 gate signal line 18 source signal line 19 storage capacity (additional capacitor, additional capacity)
50 Display screen 51 Write pixel (row)
52 Non-display pixels (non-display area, non-lighting area)
53 Display pixels (display area, lighting area)
61 Shift register 62 Inverter 63 Output buffer 71 Array substrate (display panel)
72 Laser irradiation range (laser spot)
73 Positioning marker 74 Glass substrate (array substrate)
81 Control IC (circuit)
82 Power IC (circuit)
83 Printed board 84 Flexible board 85 Sealing lid 86 Cathode wiring 87 Anode wiring (Vdd)
88 Data signal line 89 Gate control signal line 101 Bank (rib)
102 Interlayer insulating film 104 Contact connection portion 105 Pixel electrode 106 Cathode electrode 107 Desiccant 108 λ / 4 plate 109 Polarizing plate 111 Thin film sealing film 271 Dummy pixel (row)
341 Output stage circuit 371 OR circuit 401 Lighting control line 471 Reverse bias line 472 Gate potential control line 451 Electronic volume circuit 452 Transistor SD (source-drain) short 471, 472, 473 Current source (transistor)
481 switch (on / off means)
484 Current source (unit transistor)
483 Internal wiring 491 Electronic volume 521 Transistor group 531 Resistor 532 Decoder circuit 533 Level shifter circuit 541 Raising circuit 551 D / A converter 552 Operational amplifier 561 Analog switch 562 Inverter 581 Gate wiring 631 Sleep switch (reference current on / off means)
651 counter 652 NOR
653 AND
654 Current output circuit 655 Switch 671 Matching circuit 681 Input / output pad 691 Reference current circuit 692 Current control circuit 701 Temperature detection means 702 Temperature control circuit 711 Unit gate output circuit 1121 Coil (transformer)
1122 Control circuit 1123 Diode 1124 Capacitor 1125 Resistance 1126 Transistor 1131 Switching circuit (Analog switch)
1251 Output switching circuit 1252 Changeover switch 1501 Analog switch 1502 Switch control line 1503 Connection wiring 1504 Buffer sheet (plate)
1521 Inverter 1522 Connection terminal 1571 Antenna 1572 Key 1573 Case 1574 Display panel 1581 Eyepiece ring 1582 Magnifying lens 1583 Convex lens 1591 Support point (rotating part)
1592 Shooting lens 1593 Storage unit 1594 Switch 1601 Main body 1602 Shooting unit 1603 Shutter switch 1611 Mounting frame 1612 Leg 1613 Mounting base 1614 Fixing part 1731 Video signal circuit 1733 Electron emission protrusion 1734 Holding circuit 1735 On-off control circuit 1741 Selection signal line 1742 ON / OFF signal line 1781 switch 1783 power supply circuit 1821 switch 1831 resistor 1901 reference current circuit 2041 sampling point 2051 SUM circuit 2052 comparison circuit 2061 chassis 2062 operation button 2063 chip component 2171 dummy transistor 2181 subtransistor 2351 precharge control circuit 2361 latch circuit 2362 selector circuit 2363 Precharge circuit 2451 Cut point Separation point)
2561 Switch (connection means)
2571 Selection unit transistor 2681 Anode wiring 2682 Cathode wiring 2683 Cascade terminal 2684 Cascade wiring 2721 Protection diode 2722 Surge reduction resistor 3041 Precharge voltage source 3061 Voltage output circuit 3071 Function block 3072 Line memory 3073 Latch circuit 3074 Point sequential circuit (shift register circuit)
3271 Reference current circuit 3411 Precharge pulse 3441 Wafer 3442 Characteristic distribution 3461 Doping head 3462 Laser head 3581 Color filter (interference filter, interference film)
3731 Adder circuit 3851 Metal thin film (conductive material)
3881 Light absorption film (light absorption material)
3882 Light (trajectory of light)
3891 Ladder resistor (resistor array)
3892 Switch circuit 3893 Voltage input / output terminal 3941 DCDC converter (voltage booster circuit)
3943 Regulator (constant voltage output circuit)
4021 Variable amplifier 4022 Sampling circuit

Claims (1)

EL elements arranged in a matrix,
A driving transistor for driving the EL element;
A power supply circuit for generating an anode voltage and a cathode voltage of the display panel;
A current monitor circuit for calculating or measuring a value corresponding to a current flowing in all EL elements of the display panel;
A voltage control circuit,
The EL display device, wherein the voltage control circuit changes the anode voltage according to the output of the current monitor circuit, and simultaneously changes the cathode voltage in the change direction of the anode voltage.

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