JP2001306018A - Matrix-type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a matrix-type display device which has a low clock signal frequency, a low the operation frequency of a pulse width modulator circuit, a simple configuration, and low power consumption, and which can be realized at a low cost. SOLUTION: A 1st PWM driver part 14 performs outputting by pulse width modulation according to an input brightness data. A 2nd PWM driver part 15 performs outputting by pulse width modulation. according to an outline correction data extracted from the input luminance data by a digital signal processing part 13. A PWM pulse superimposing part 16 superimposes the output pulse of the 1st PWM driver part 14 on that of the 2nd PWM driver part 15 to generate a drive pulse, and supplies it to a matrix panel 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an image having a matrix type display pixel, and is particularly suitable for an FED display device using a field emission type cathode, an organic electroluminescence display device and the like. The present invention relates to a matrix type display device.

[0002]

2. Description of the Related Art In addition to a liquid crystal display, a matrix type display device (matrix display) which displays an image by adjusting the voltage applied to each pixel at the intersection of the electrode groups orthogonal to each other is known as an FED. (Field emission display), PDP (plasma
Display), organic EL (electroluminescence)
Etc. For example, FED is disclosed in Japanese Patent Application Laid-Open No. 4-289644.
As described in Japanese Patent Application Laid-Open Publication No. H10-157, a large number of minute field emission cathodes are arranged in each pixel, and field emission electrons therefrom are accelerated in a vacuum and then irradiated to a phosphor to emit light.

In these matrix type display devices, an appropriate voltage is applied to a certain row to be in a semi-selected state, and at that time, an appropriate signal voltage is applied to each column.
An image is displayed by controlling the light emitting state of each light emitting element at the intersection of a row and a column. At this time, the luminance of each light-emitting element, that is, the gradation, is adjusted by devising a method of applying a signal voltage to each column. As a method of adjusting the gradation, there are pulse width modulation (PWM) for adjusting the light emission time and voltage modulation for adjusting the applied voltage amplitude.

For example, in the gradation display method described in Japanese Patent Laid-Open No. Hei 4-289644, when 256 gradations are to be obtained, the emission luminance is raised to the nth power of 2 (n = 0 to 7). By setting the voltage Vn so as to be proportional and applying the voltage in combination with Vn, display of 256 gradations is realized.
When 256 gradations are to be obtained by pulse width modulation, the element may be driven by setting the pulse width so that the emission luminance is proportional to 2 n (n = 0 to 7).

When an image signal such as a TV signal is displayed on a display panel connected to a matrix wiring electrode, a luminance (PWM) signal corresponding to a display cell row constituting the line is simultaneously output for each line. In some cases, a configuration in which light-emitting lines are sequentially selected by a vertical scanning driver is employed. For example, in Japanese Patent Publication No. 61-38475,
A modification of line sequential / PWM drive in an LED panel or the like is disclosed.

FIG. 5 is a block diagram showing the configuration of a basic matrix type display device. Here, the display element is FED
As will be described later, EL or the like may be used. In FIG. 5, an input video signal input from an input terminal 1 is
Supplied to The decoder 2 decodes the input video signal to obtain video signals (R, G, B) of three primary colors,
In addition to supplying to the / D conversion unit 3, horizontal and vertical synchronization signals are obtained and supplied to the timing generation unit 6.

The timing generator 6 generates various timing signals synchronized with the horizontal and vertical synchronizing signals and supplies them to the clock unit 7. The clock circuit 7 generates a clock of a fixed period at a timing based on the horizontal synchronization signal included in the video signal, supplies the clock to the A / D conversion unit 3 as a sampling clock, and outputs a PWM /
It is supplied to the PWM / driver 8 in the driver unit 9.
The A / D converter 3 converts video signals (R, G, B) of the three primary colors into digital data according to a sampling clock, and supplies the digital data to the P / S converter 4 in the PWM / driver unit 9.

The P / S converter 4 converts the converted R, G, B
The video signal is converted into a serial signal arranged in the corresponding order of each phosphor of the panel, and is supplied to the S / P converter 5. The S / P converter 5 converts the serial signal into a parallel video signal for each row, and supplies the parallel video signal to the PWM / driver 8. The PWM / driver 8 generates a driving pulse having a pulse width corresponding to the luminance of each video signal, and supplies the driving pulse to the matrix panel 11. Matrix panel 1
Reference numeral 1 denotes an image display panel to which a high-voltage power supply 12 is supplied, and display cells are arranged in a simple matrix by row-direction wirings serving as scanning wirings and column-direction wirings serving as data wirings. Only the pixels connected to the row selected by the scanning driver 10 emit electrons for a period corresponding to each supplied pulse width, and the phosphor emits light. The scanning driver 10 forms a two-dimensional image by sequentially scanning selected rows.

FIG. 6 is a schematic waveform diagram of a conventional driving pulse. In FIG. 6, the drive pulse output by the PWM / driver 8 has a wider pulse width as the video data increases, for example, to 05, 7F, and FF. FIG. 7 is a characteristic diagram showing a relationship between video data and luminance in a conventional example. In FIG. 7, the horizontal axis represents the size of video data (drive pulse), and the vertical axis represents luminance. The relationship between the drive pulse width, that is, the period during which the electron beam is turned on, and the luminance of the phosphor screen is
As shown in FIG. 7, it is substantially linear. Therefore, for example, if the pulse width of the drive pulse changes linearly in 256 steps according to the video data, it is possible to reproduce a 256-step linear luminance change. .

[0010]

As described above, one step of the gradation generated when the luminance gradation is generated in the PWM system and driven in line-sequential manner is equivalent to one clock of the PWM / driver clock signal. As the horizontal frequency of the input video signal increases and the number of gradations increases, PWM /
The frequency of the clock signal input to the driver increases,
The operating frequency of the PWM / driver also increases. by the way,
In these display device driving methods, if the contour correction (emphasis) of a video signal is to be performed as in a CRT display, if the number of normal luminance signal gradations is not reduced, the number of gradations required for the contour correction component is as follows. This increases in addition to the number of normal luminance signal gradations, and requires a higher clock frequency. Increasing the clock frequency has the disadvantage that the drive circuit scale and power consumption increase.

In a CRT display, the relationship between the applied voltage and the luminance has a gamma characteristic. By superimposing the contour correction component on the luminance signal, the contour is emphasized by the gamma characteristic (exponential). Further, if a speed modulation circuit or the like is used, it is possible to perform contour emphasis many times more than the contour emphasis performed by the video signal. On the contrary,
When contour enhancement is performed using tone expression by PWM control, there is a disadvantage that the contour correction component can be enhanced only to a linear tone at a tone step level, and the contour enhancement degree is weak. The present invention has been made to solve the above-described problems, and has a low clock signal frequency and a low operating frequency of a pulse width modulation circuit, a simple configuration, low power consumption,
It is an object to provide a matrix display device which can be realized at low cost.

[0012]

In order to attain the above object, an intersection of mutually orthogonal electrode groups of a matrix panel is defined as a pixel, and a voltage applied to each pixel is output by pulse width modulation according to input luminance data. In a matrix type display device which displays an image by controlling with a pulse to be applied, a first output which performs output by pulse width modulation according to the input luminance data is provided.
A PWM driver unit, a second PWM driver unit that outputs by pulse width modulation according to contour correction data extracted from the input luminance data, and an output pulse of the first PWM driver unit and an output pulse of the second PWM driver unit And a PWM pulse superimposing unit for generating a driving pulse and supplying the driving pulse to the matrix panel.

[0013]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1, the same parts as those in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted. Also, the first PWM /
The driver unit 14 and the second PWM / driver unit 15 correspond to the PWM / driver unit 9 in FIG. 5, and have a P / S conversion unit and an S / P conversion unit therein, respectively. Is omitted.

The digital signal processing unit 13 performs gamma processing and the like on the luminance data supplied from the A / D conversion unit 3 and supplies the luminance data to the first PWM / driver unit 14, and creates contour correction data to generate the second PWM / driver. It is supplied to the driver unit 15. The first PWM / driver unit 14 and the second PWM /
The output pulse of the driver unit 15 is controlled by a timing signal from the timing generation unit 6 so as to be generated at the same time, and is supplied to the PWM pulse superimposition unit 16 to generate a superimposed drive pulse. The PWM pulse superimposing unit 16 operates as a vertical driver, and the shift register sequentially supplies a line start signal from the timing generating unit 6 to the row wiring.

In the embodiment, the bias voltage V1 for the data wiring electrode of the first PWM / driver section 14 and the second
The bias voltage V2 for the data wiring electrode for the PWM / driver unit 15 has a relationship of V2> V1, and the pulse width of V2 superimposed on V1 changes according to the increase / decrease of the edge enhancement component. This superimposed drive pulse is applied to the matrix panel 1
1 is supplied.

FIG. 2 is a waveform diagram of driving pulses and the like according to the present invention. FIG. 2A shows a video input signal supplied from the input terminal 1, and FIG. 2B shows a digital signal output from the A / D converter 3. 2 (C) to 2 (G) show waveforms when there is contour correction data such as an edge portion of the video input signal shown in FIG. 2 (A), and FIGS. 2 (H) to 2 (L) Represents a waveform of the video input signal shown in FIG. 2A when there is no edge portion or the like and there is no contour correction data. It should be noted that the waveforms of FIGS. 2A and 2B and the waveforms of FIGS. 2C to 2L are described without regard to timing and pulse width.

FIG. 2C shows the digital signal processor 13 of FIG.
2D is the second PWM.
2 (E) is an output signal of the driver unit 15, FIG. 2 (E) is luminance data supplied from the digital signal processing unit 13 of FIG. 1, and FIG.
2 shows an output signal of the first PWM / driver unit 14, and FIG. 2G shows a drive pulse output from the PWM pulse superimposing unit 16 of FIG. If there is contour correction data, the first PWM /
The second PWM is applied to the bias voltage V1 of the driver unit 14.
The driving pulse is superimposed with the bias voltage V2 of the / driver section 15 and supplied to the matrix panel 11. As shown in FIG. 2 (H), when there is no contour correction data, there is no output signal of the second PWM / driver unit 15 shown in FIG. 2 (I), and the driving pulse output from the PWM pulse superimposing unit 16 is not shown. 2 (L).

FIG. 3 is a characteristic diagram showing the relationship between the device voltage and the light emission luminance. As shown in FIG. 3, a normal FED or EL exhibits a characteristic in which the emission luminance changes almost exponentially with the device voltage. That is, in the electron-emitting device used in the FED, the change in the amount of emission current with respect to the applied voltage follows the Fowler-Nordheim equation, which is a change close to an exponential function. Since the emission luminance of the phosphor screen is almost proportional to the amount of emission current, the luminance also changes in a form close to an exponential function. From this, the bias voltage V of the first PWM
By arbitrarily changing the ratio between the first and second PWM bias voltages V2, it is possible to determine the strength of the edge enhancement. That is, contour enhancement similar to that of a CRT can be performed.

FIG. 4 is a block diagram showing a second embodiment of the present invention. 4, the same parts as those in FIGS. 1 and 5 are denoted by the same reference numerals, and description thereof will be omitted. The main difference from FIG. 1 is that an APL detector 17 and a voltage modulator 18 are provided. The APL detector 17 detects the average luminance level of the input video signal from the digital processing circuit 13 and supplies the average luminance level to the voltage modulator 18. The voltage modulator 18 modulates the bias voltage V2 supplied to the second PWM / driver 15 according to the detected luminance level (APL). Since the panel luminance has a characteristic that changes exponentially with respect to the element voltage, the modulation method may be arbitrary. For example, when the luminance is low, the bias voltage V2 is lowered to weaken the contour correction, and when the luminance is high, the bias voltage is reduced. Settings can be made such that the contour correction is enhanced by increasing the voltage V2.

As described above, the present invention provides the first and second PWs.
M modulation combined and superimposed and output, and one PW
By performing contour enhancement on M, contour enhancement equivalent to that of a CRT can be performed without increasing the clock frequency. In addition, by adaptively moving the voltage at the average luminance level (APL), it becomes possible to perform contour enhancement optimal for an image.

[0021]

The matrix type display device of the present invention has an extremely excellent effect that the frequency of the clock signal and the operating frequency of the pulse width modulation circuit are low, the configuration is simple, the power consumption is small, and the cost can be reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of a driving pulse and the like of the present invention.

FIG. 3 is a characteristic diagram illustrating a relationship between an element voltage and light emission luminance.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a basic matrix type display device.

FIG. 6 is a schematic waveform diagram of a driving pulse in a conventional example.

FIG. 7 is a characteristic diagram showing a relationship between video data and luminance in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 decoder unit 3 A / D conversion unit 4 P / S conversion unit 5 S / P conversion unit 6 timing generation unit 7 clock unit 8 PWM / driver 9 PWM / driver unit 10 scanning driver 11 matrix panel 12 high voltage power supply 13 Digital signal processing unit 14 First PWM / driver unit 15 Second PWM / driver unit 16 PWM pulse superposition unit 17 APL detection unit 18 Voltage modulation unit

Claims (2)

[Claims] 1. A matrix type in which an image is displayed by controlling an applied voltage to each pixel by a pulse output by pulse width modulation according to input luminance data, wherein an intersection of mutually orthogonal electrode groups of a matrix panel is defined as a pixel. In the display device, a first PWM driver unit that outputs by pulse width modulation according to the input luminance data, a second PWM driver unit that outputs by pulse width modulation according to contour correction data extracted from the input luminance data, A matrix-type display device, comprising: a PWM pulse superimposing unit that generates a driving pulse by superimposing an output pulse of the first PWM driver unit and an output pulse of the second PWM driver unit and supplies the driving pulse to the matrix panel. 2. An APL detecting section for detecting an average luminance level from the input luminance data, and a voltage modulating section for modulating a voltage value of an output pulse of the second PWM driver section in accordance with the average luminance level. The matrix type display device according to claim 1, wherein: