JP2004022724A - Semiconductor integrated circuit device and method of constituting semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that can reduce the power consumption. <P>SOLUTION: A CPU 11 judges, during circuit reconstruction processing, whether or not the temperature of an FPGA 12 detected by a temperature sensor 15 is higher than an allowable temperature, and when the temperature is higher than the allowable temperature, the CPU 11 outputs a control signal to set and output a lower operation frequency to a PLL circuit 14 than a present operation frequency; and also lets a ROM 13 to output a circuit data, corresponding with the set operation frequency to an FPGA 12 and outputs a control signal for the FPGA 12 to reconstruct on the basis of the circuit data. When the detected temperature is lower than the critical temperature, the CPU 11 outputs a control signal to set and output a operation frequency higher than the present operation frequency to a PLL circuit 14, and and also lets a ROM 13 to output a circuit data, corresponding with the set operation frequency to a FPGA 12 and outputs a control signal for the FPGA 12, so as to reconstitute on the basis of the circuit data. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated device including a programmable logic device capable of reconfiguring a circuit configuration, and a method of configuring a semiconductor integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the rapid development of IC (integrated circuit) design technology and manufacturing technology, PLDs (Programmable Logic Devices: Programmable Logic Devices) with programmable circuit designs have been developed. In such a programmable logic circuit, by reading circuit information describing the logic circuit, the wiring between the internal logic circuits can be freely configured, and the circuit once created can be reconfigured as many times as necessary. It is possible.
[0003]
A programmable logic circuit called an FPGA (Field Programmable Gate Array) can reconfigure a desired logic circuit by writing a bit stream that controls a switch matrix that connects between logic gates and wirings from outside. As a device, a memory for storing internal circuit configuration data and switch matrix control data between logic gates is provided in the device, and it is possible to provide various operation characteristics with the various data.
[0004]
[Problems to be solved by the invention]
Recently, as the operation speed of the digital circuit has been increased as described above, the power consumption of each IC constituting the digital circuit has been increasing. When the operating speed increases and the power consumption of the IC increases, the IC temperature increases, and the operation of the entire circuit may become unstable and malfunction. As a countermeasure against such a problem, the temperature of the IC has been conventionally reduced by installing a fan cooler near the circuit and air-cooling the air-cooling device. However, it is impossible to suppress a rise in temperature due to an increase in operating speed.
[0005]
In addition, if the temperature of the circuit cannot be reduced by an external action such as a fan cooler, it is necessary to reduce the operating frequency of the circuit to suppress power consumption of the IC and prevent the temperature from rising. However, a decrease in operating speed is inevitable.
[0006]
An object of the present invention is to provide a semiconductor integrated circuit device that reduces power consumption.
[0007]
[Means for Solving the Problems]
The invention according to claim 1 is
In a semiconductor integrated circuit device including a programmable logic device capable of reconfiguring the circuit configuration based on the circuit information describing the circuit configuration,
Storage means for storing a plurality of circuit information according to the power consumption of the programmable logic device,
Detecting means for detecting power consumption of the programmable logic device;
Reconfiguration means for reading circuit information corresponding to the power consumption detected by the detection means from the storage means, and reconfiguring a circuit configuration of the programmable logic device based on the circuit information;
It is characterized by having.
[0008]
According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect,
The detection means detects a temperature of the programmable logic device as power consumption of the programmable logic device.
[0009]
The invention according to claim 7 is
A method of configuring a semiconductor integrated circuit in a semiconductor integrated circuit device including a programmable logic device capable of reconfiguring a circuit configuration based on circuit information describing a circuit configuration,
A step of storing a plurality of circuit information according to the power consumption of the programmable logic device in storage means,
A detecting step of detecting power consumption of the programmable logic device;
Reading circuit information corresponding to the power consumption detected from the detection step from the storage unit, and reconfiguring a circuit configuration of the programmable logic device based on the circuit information;
It is characterized by including.
[0010]
According to the first, second, and seventh aspects of the present invention, the circuit configuration is reconfigured based on the circuit information corresponding to the power consumption of the programmable logic device. Therefore, the circuit configuration is optimally changed according to the power consumption. Power consumption of the semiconductor integrated circuit device can be reduced.
[0011]
According to a third aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect,
A change unit that changes an operating frequency of the programmable logic device based on the power consumption detected by the detection unit,
The storage means stores circuit information in which the number of stages of pipeline processing included in the circuit configuration of the programmable logic device is set according to the operating frequency of the programmable logic device,
The reconfiguration means reads circuit information corresponding to the operating frequency changed by the change means from the storage means, and reconfigures a circuit configuration of the programmable logic device.
[0012]
The invention according to claim 4 is the semiconductor integrated circuit device according to claim 3,
The changing unit, when the power consumption detected by the detecting unit is high, changes the operating frequency of the programmable logic device to low,
The reconfiguring means reads from the storage means circuit information in which the number of stages of pipeline processing included in the circuit configuration of the programmable logic device is reduced according to the low operating frequency changed by the changing means, and reads the programmable logic. It is characterized in that the circuit configuration of the device is reconfigured.
[0013]
The invention according to claim 5 is the semiconductor integrated circuit device according to claim 3 or 4,
When the power consumption detected by the detection unit is low, the change unit changes the operating frequency of the programmable logic device to a high value,
The reconfiguring means reads from the storage means circuit information in which the number of stages of pipeline processing included in the circuit configuration of the programmable logic device is increased according to the high operating frequency changed by the changing means, and reads the programmable logic. It is characterized in that the circuit configuration of the device is reconfigured.
[0014]
According to the third, fourth and fifth aspects of the present invention, when the power consumption of the programmable logic device is high, the operating frequency is lowered and the circuit configuration is reduced to a smaller number of stages of the pipeline processing, so that the power consumption is low. In such a case, since the operating frequency is increased and the circuit configuration is reconfigured to have a large number of stages of pipeline processing, the circuit configuration can be optimally changed according to the operating frequency, and the power consumption of the semiconductor integrated circuit device is reduced. can do.
[0015]
According to a sixth aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect,
Connected via a transmission medium to an external device comprising a storage means for storing a plurality of the circuit information,
The circuit information according to the power consumption is obtained from the external device via a transmission medium.
[0016]
According to the invention of claim 6, since the circuit information is obtained from the external device via the transmission medium, even if the storage capacity of the storage means of the semiconductor integrated device is small and a large amount of circuit information cannot be stored, the circuit information is obtained. By storing a large amount of circuit information in the storage means of the external device, desired circuit information can be easily obtained.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the configuration will be described.
FIG. 1 is a block diagram showing an internal configuration of a semiconductor integrated circuit device 10 according to the present embodiment.
1, a semiconductor integrated circuit device 10 includes a CPU 11, an FPGA 12, a ROM 13, a PLL circuit 14, and a temperature sensor 15.
[0018]
The CPU (Central Processing Unit) 11 reads various control programs stored in the ROM 13 and expands them in a work area (not shown), and controls the operation of each unit according to the programs.
[0019]
Specifically, the CPU 11 reads a circuit reconfiguration processing program stored in the ROM 13 and executes a circuit reconfiguration processing described later.
The CPU 11 detects the temperature of the FPGA 12 by the temperature sensor 15 in the circuit reconfiguration processing, determines whether the detected temperature is higher than the upper limit set allowable temperature, and if it is higher, it is lower than the current operating frequency. A control signal is output to the PLL circuit 14 to set and output the operating frequency, and a control signal is output to the FPGA 12 from the ROM 13 to output the circuit data corresponding to the set operating frequency to the FPGA 12 to reconfigure the FPGA 12 based on the circuit data. Is output. On the other hand, when the detected temperature is lower than the allowable temperature, a control signal is output to the PLL circuit 14 to set and output an operation frequency higher than the current operation frequency, and circuit data corresponding to the set operation frequency is read from the ROM 13 to the FPGA 12. And outputs a control signal to the FPGA 12 to reconfigure based on the circuit data. That is, the CPU 11 has a function as a reconfiguration unit.
[0020]
The FPGA 12, as shown in FIG. 2, is a set of logic circuits including a logic circuit 121, a wiring region 122, and a switch matrix 123. The wiring region 122 is laid in a lattice between the logic circuits 121 arranged in a matrix. The wiring connection is controlled by the switch matrix 123. Further, a plurality of input and output terminals (not shown) are provided in the peripheral portion of the FPGA 12, and logically processes data input from the input terminal based on the operating frequency input from the PLL circuit 14, and outputs the data to the output terminal. I do.
[0021]
Further, the FPGA 12 has a built-in SRAM (Static Random Access Memory) 124 as a rewritable storage element, stores circuit data output from the ROM 13 in the SRAM 124, and performs wiring according to the circuit data in accordance with an instruction from the CPU 11. The wiring connection of the region 122 is performed by the switch matrix 123, and the circuit configuration is reconfigured. Note that any rewritable storage element may be a DRAM (Dynamic Random Access Memory) or the like.
[0022]
The ROM (Read Only Memory) 13 is composed of a semiconductor memory and has a storage area (not shown) in which programs, data, and the like are stored in advance. This storage area stores various control programs and data processed by the various control programs. The program sequentially executes an operation according to a program code that can be read by a computer.
[0023]
The ROM 13 stores circuit data 1 to n indicating the circuit configuration of the FPGA 12 set for each of a plurality of operating frequencies, and outputs the circuit data instructed by the CPU 11 to the FPGA 12. Note that the circuit data includes circuit configuration data of the logic circuit 121 inside the FPGA 12 and switch matrix control data of the switch matrix 123 that controls wiring connections between logic gates. That is, the ROM 13 has a function as storage means for storing circuit information.
[0024]
The PLL (Phase Locked Loop) circuit 14 includes a phase detector, an LPF (Low Pass Filter), a VCO (Voltage Controlled Oscillator), a frequency divider, and the like, and divides an output signal oscillated from the VCO by a frequency divider. The phase difference detector compares the frequency-divided signal and the input signal from the CPU 11 to detect a difference in frequency or phase, and feeds it back to the VCO to generate an output signal of a desired frequency. The signal is output to the FPGA 12 as a frequency signal. That is, the PLL circuit 14 has a function as changing means for changing the operating frequency.
[0025]
The temperature sensor 15 is a sensor that measures the temperature of the FPGA 12, and outputs measured temperature information to the CPU 11. Since the power consumption of the FPGA 12 is proportional to the amount of heat generated, and the amount of heat generated is proportional to the temperature of the FPGA 12, the present embodiment will be described using a temperature sensor as the detecting means for detecting the power consumption.
[0026]
Next, the operation of the present embodiment will be described.
As a premise of the description of the operation, a program for realizing each process described below is stored in the ROM 13 in the form of a computer-readable program code, and the CPU 11 performs an operation according to the program code. Execute sequentially. Further, the CPU 11 can also sequentially execute operations specific to the present embodiment using programs and data supplied from the outside via a transmission medium.
[0027]
Hereinafter, the circuit reconfiguration processing executed by the CPU 11 will be described.
First, the CPU 11 detects the temperature of the FPGA 12 with the temperature sensor 15 and determines whether the detected temperature is higher than the allowable temperature. If the detected temperature is higher than a predetermined temperature, it is determined that the circuit configuration is to be changed, an operating frequency lower than the current operating frequency is set, and a control signal is generated so as to output the set operating frequency, and a PLL circuit is generated. 14 is output. Then, circuit data corresponding to the set operating frequency is output from the ROM 13 to the FPGA 12. Then, the CPU 11 outputs a control signal to the FPGA 12 so as to reconfigure the logic circuit based on the input circuit data.
[0028]
When storing the circuit data input from the ROM 13 in the SRAM 124, the FPGA 12 reconfigures the circuit configuration of the logic circuit 121 and the connection state of the wiring area 122 based on the circuit data stored in the SRAM 124 according to the control signal input from the CPU 11. I do. At the time of this reconfiguration, the FPGA 12 stops inputting data from the input terminal and temporarily stops the logic processing. When the reconfiguration is completed, data input from the input terminal is restarted, and logic processing is performed on the input data in synchronization with the operating frequency input from the PLL circuit 14.
[0029]
On the other hand, when the temperature of the FPGA 12 detected by the temperature sensor 15 is lower than the allowable temperature, an operation frequency higher than the current operation frequency is set based on the detected temperature, and a control signal is output so as to output the set operation frequency. Is generated and output to the PLL circuit 14, and the circuit data corresponding to the set operating frequency is output from the ROM 13 to the FPGA 12. Then, the CPU 11 outputs a control signal to the FPGA 12 so as to reconfigure the logic circuit based on the input circuit data. The FPGA 12 reconfigures the circuit configuration based on the circuit data input from the ROM 13 as described above.
[0030]
The operating frequency set when the CPU 11 changes the circuit configuration can be appropriately set as long as the operating frequency corresponds to the circuit data stored in the ROM 13. For example, the ROM 13 stores circuit data corresponding to each of the operating frequencies 100 MHz, 110 MHz, 120 MHz, 130 MHz, and 140 MHz. Assuming that the current frequency is 130 MHz, when lowering the operating frequency, a lower 100 MHz, Any one of 110 MHz and 120 MHz can be set as the operating frequency. Further, the change width of the operating frequency accompanying the change of the circuit configuration can be set arbitrarily. More specifically, several temperature ranges are set in advance. For example, when the detected temperature is included in 5 to 8 ° C, the operating frequency is reduced by 20 MHz, and when the detected temperature is included in 3 to 5 ° C, the operating frequency is reduced by 10 MHz. For example, a change width of the operating frequency to be changed for each temperature range may be set.
[0031]
Here, the circuit configuration of the above-described FPGA 12 will be specifically described with reference to FIG. 3A and 3B are schematic diagrams of a circuit configuration example for performing pipeline processing on an input signal, and FIG. 3A is an example of a circuit configuration diagram corresponding to a high operating frequency. b) is an example of a circuit configuration diagram corresponding to a low operating frequency. 3 (a) and 3 (b), a plurality of combinational circuits 121a configured by combining circuit elements of a logic circuit 121 for performing logical processing are wired, and each combinational circuit 121a captures and holds an input signal according to a clock. FFs (flip-flops) 121b. Generally, in a digital circuit, as the operating frequency is set higher, the number of elements of the FFs 121b in the circuit is increased to reduce the signal delay between the FFs 121b.
[0032]
Although FIGS. 3A and 3B are different in circuit configuration and operating frequency, the output results by the logical processing are the same. In other words, even if the number of elements constituting the combinational circuit 121a between the FFs 121b changes, the number of elements constituting the combinational circuit 121a in the entire circuit becomes the same as the circuit shown in FIG. 3A and the circuit shown in FIG. Then it does not change.
[0033]
In the above description, when the temperature of the FPGA 12 exceeds the allowable temperature and the operating frequency is lowered, the CPU 11 adjusts the number of stages of the pipeline processing in the circuit to be small, for example, the circuit configuration shown in FIG. To reconfigure the FPGA 12. At this time, the number of elements constituting the combinational circuit 121a does not change in the entire circuit, but the number of elements of the FF 121b decreases due to the decrease in the number of stages of the pipeline processing. Therefore, the circuit scale is reduced, the amount of heat generated along with power consumption is reduced, and the temperature of the FPGA 12 is reduced.
[0034]
On the other hand, when the operating frequency is increased because the temperature of the FPGA 12 has not reached the allowable temperature, the CPU 11 adjusts the number of stages of the pipeline processing in the circuit to a large number. For example, the CPU 11 reconfigures the circuit in the circuit configuration shown in FIG. Configure. At this time, the number of elements constituting the combinational circuit 121a does not change in the entire circuit, but the number of elements of the FF 121b increases due to the increase in the number of stages of the pipeline processing. Therefore, the circuit scale becomes large, and the amount of heat generated together with the power consumption increases. When the temperature of the FPGA 12 rises due to an increase in the amount of heat and reaches the allowable temperature, the FPGA 12 is reconfigured so that the operating frequency is set again low and the circuit scale is reduced.
[0035]
As described above, when the operating frequency is high and the temperature rises, the FPGA 12 is reconfigured into a small circuit configuration in which the operating frequency is lowered and the number of stages of pipeline processing is reduced, and the operating frequency is reduced when the temperature of the FPGA 12 is lowered. By reconfiguring the FPGA 12 into a large-scale circuit configuration in which the number of stages of the pipeline processing is increased by increasing the number of pipeline processes, the FPGA 12 can be operated efficiently and the power consumption can be minimized. Generally, the power consumption of a circuit is proportional to the circuit scale and the operating frequency. For example, if the circuit scale is reduced to 1 / 1.4 and the operating frequency is reduced to 1 / 1.4, the power consumption is reduced to 1/2. Thus, power consumption can be effectively reduced.
[0036]
Note that the description in the present embodiment is an example of a suitable semiconductor integrated circuit device according to the present invention, and the present invention is not limited to this.
For example, in the above description, the PLL circuit 14 is provided to change the operating frequency input to the FPGA 12, but the present invention is not limited to this, and a plurality of clock oscillators may be provided.
[0037]
Further, the semiconductor integrated circuit device is provided with the ROM 13, the circuit data of the FPGA 12 is stored in the ROM 13, and the circuit data corresponding to the operating frequency is output to the FPGA 12. The circuit data is stored in the ROM of the external device of the device 10, the semiconductor integrated circuit 10 is connected to the external device by a transmission medium, desired circuit data is obtained from the external device via the transmission medium, and the FPGA 12 The circuit configuration may be reconfigured.
[0038]
In the above description, the FPGA has been described as a PLD capable of reconfiguring a logic circuit. However, the present invention is not limited to this, and a CPLD (Complex PLD) or another programmable logic circuit may be used. Good.
[0039]
Further, the temperature sensor 15 is provided to measure the temperature of the FPGA 12, and the circuit configuration is changed according to the measured temperature. However, the correlation between the operating frequency and the time during which the temperature rises is measured in advance without the temperature sensor. In advance, the circuit configuration may be changed based on the correlation. For example, when a correlation that the temperature rises by 5 ° C. in 10 minutes at an operating frequency of 120 MHz is obtained, the operating frequency is changed to 120 MHz, the operating frequency is changed to 100 MHz 10 minutes later, and the circuit configuration is changed accordingly. The time required for the temperature rise may be predicted from the correlation, and the circuit configuration may be changed after the predicted time has elapsed.
[0040]
In addition, the detailed configuration and the detailed operation of each unit configuring the semiconductor integrated circuit device 10 according to the present embodiment can be appropriately changed without departing from the gist of the present invention.
[0041]
【The invention's effect】
According to the first, second, and seventh aspects, the circuit configuration is reconfigured based on the circuit information corresponding to the power consumption of the programmable logic device. Therefore, the circuit configuration is optimally changed according to the power consumption. And the power consumption of the semiconductor integrated circuit device can be reduced.
[0042]
According to the third, fourth and fifth aspects of the present invention, when the power consumption of the programmable logic device is high, the operating frequency is lowered and the circuit configuration is reduced to a smaller number of stages of the pipeline processing. In this method, the operating frequency is increased and the circuit configuration is reconfigured to have a large number of stages of pipeline processing. Therefore, the circuit configuration can be optimally changed according to the operating frequency, and the power consumption of the semiconductor integrated circuit device is reduced. be able to.
[0043]
According to the invention of claim 6, since the circuit information is obtained from the external device via the transmission medium, even if the storage capacity of the storage means of the semiconductor integrated circuit device is small and a large amount of circuit information cannot be stored, By storing a large amount of circuit information in the storage means of the external device, desired circuit information can be easily obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an internal configuration of a semiconductor integrated circuit device 10 according to an embodiment of the present invention.
FIG. 2 is a schematic diagram showing an internal configuration of the FPGA 12 of FIG.
3A is a diagram illustrating a circuit configuration of the FPGA 12 set when the operating frequency is high, and FIG. 3B is a diagram illustrating a circuit configuration of the FPGA 12 set when the operating frequency is low. is there.
[Explanation of symbols]
10 semiconductor integrated circuit device 11 CPU
12 FPGA
121 Logic circuit 121a Combination circuit 121b FF (flip-flop)
122 wiring area 123 switch matrix 124 SRAM
13 ROM
14 PLL circuit 15 Temperature sensor

Claims (7)

In a semiconductor integrated circuit device including a programmable logic device capable of reconfiguring the circuit configuration based on the circuit information describing the circuit configuration,
Storage means for storing a plurality of circuit information according to the power consumption of the programmable logic device,
Detecting means for detecting power consumption of the programmable logic device;
Reconfiguration means for reading circuit information corresponding to the power consumption detected by the detection means from the storage means, and reconfiguring a circuit configuration of the programmable logic device based on the circuit information;
A semiconductor integrated circuit device comprising: 2. The semiconductor integrated circuit according to claim 1, wherein said detecting means detects a temperature of said programmable logic device as power consumption of said programmable logic device. A change unit that changes an operating frequency of the programmable logic device based on the power consumption detected by the detection unit,
The storage means stores circuit information in which the number of stages of pipeline processing included in the circuit configuration of the programmable logic device is set according to the operating frequency of the programmable logic device,
2. The semiconductor device according to claim 1, wherein said reconfiguration means reads circuit information corresponding to the operating frequency changed by said change means from said storage means, and reconfigures a circuit configuration of said programmable logic device. Integrated circuit device. The changing unit, when the power consumption detected by the detecting unit is high, changes the operating frequency of the programmable logic device to low,
The reconfiguring means reads from the storage means circuit information in which the number of stages of pipeline processing included in the circuit configuration of the programmable logic device is reduced according to the low operating frequency changed by the changing means, and reads the programmable logic. 4. The semiconductor integrated circuit device according to claim 3, wherein the circuit configuration of the device is reconfigured. When the power consumption detected by the detection unit is low, the change unit changes the operating frequency of the programmable logic device to a high value,
The reconfiguring means reads from the storage means circuit information in which the number of stages of pipeline processing included in the circuit configuration of the programmable logic device is increased according to the high operating frequency changed by the changing means, and reads the programmable logic. 5. The semiconductor integrated circuit device according to claim 3, wherein a circuit configuration of the device is reconfigured. Connected via a transmission medium to an external device comprising a storage means for storing a plurality of the circuit information,
2. The semiconductor integrated circuit device according to claim 1, wherein circuit information corresponding to the power consumption is obtained from the external device via the transmission medium. A method of configuring a semiconductor integrated circuit in a semiconductor integrated circuit device including a programmable logic device capable of reconfiguring a circuit configuration based on circuit information describing a circuit configuration,
A step of storing a plurality of circuit information according to the power consumption of the programmable logic device in storage means,
A detecting step of detecting power consumption of the programmable logic device;
Reading circuit information corresponding to the power consumption detected from the detection step from the storage unit, and reconfiguring a circuit configuration of the programmable logic device based on the circuit information;
A method of configuring a semiconductor integrated circuit, comprising:

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