JP2002369498A - Gate drive circiuit for power semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect the power semiconductor elements of IGBTs, etc., when the elements are parallelly driven by preventing the occurrence of a heat- concentrating phenomenon nor a high-surge voltage impressing the phenomenon to a specific elements. SOLUTION: The detected values D of the currents, flowing to the IGBTs, are inputted to a sample-and-hold circuit (S/H) 13 and a peak hold circuit 14 and the differences between the current values, when the inputting time of power semiconductor element turn-off commands to gate drive circuits for the power semiconductor elements approaches and a maximum current value during the inputting periods of the commands are found by means of a subtractor 15. When the differences are larger than a prescribed value Se, the currents of the elements are made to be balanced with each other by making the time, required until the elements are actually turned off by means of a variable delay circuit 18 to be shorter by setting a flip-flop circuit 17. A circuit such as the one shown in Figure, is provided for each element installed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive circuit for a power semiconductor device such as an IGBT (insulated gate bipolar transistor) constituting a power converter such as an inverter, and more particularly to a gate drive circuit when IGBTs are connected in parallel.

[0002]

2. Description of the Related Art FIG. 6 shows a main circuit diagram of an inverter using an IGBT of this type. In FIG. 1, reference numeral 1 denotes a DC power supply (in the case of AC input, a rectifier + electrolytic capacitor is used); 2 denotes an inverter circuit composed of an IGBT and a diode for converting DC to AC; 3A and 3B denote IGBTs;
Gate drive circuit (provided for each element), 4 is I
A snubber capacitor for protecting the IGBT from a surge voltage when the GBT is turned off, 5 is a wiring inductance between the snubber capacitor and the inverter circuit, and 6 is a load such as a motor.

FIG. 7 shows a specific example of a gate drive circuit. 7
Is a drive circuit power supply, and 8 and 9 are switch elements for turning on and off the IGBT, respectively.
Reference numeral 1 denotes a gate resistor for turn-on and turn-off.
2 is operated by the ON command signal N or the OFF command signal F from FIG. 8 shows a configuration example when the IGBTs are driven in parallel (two parallel). Here, the command signal S from above is input to the gate drive circuits 3A and 3B arranged in parallel,
Each IGBT is driven by each gate drive circuit.

FIGS. 9 and 10 show examples of a collector current detection circuit of an IGBT. FIG. 9 shows a sense IGB having a sensor terminal
The shunt resistor R _S1 is connected to T, and FIG. 10 uses only the shunt resistor R _S2 . In these examples, the current is detected from the voltage between both ends of the shunt resistors R _S1 and R _S2 , and the detection output signals Da and Db are equivalent to the collector current.

[0005]

[0008] As shown in FIG.
When T and the gate drive circuit are connected in parallel and driven, a circuit delay of the control unit (12) in each gate drive circuit, a turn-off gate resistance value (11), and an Due to the variation of the storage time, the actual turn-off waveform of the IGBT becomes an unbalanced current waveform as shown by Ic1 and Ic2 in FIG. When such an unbalance phenomenon occurs, the turn-off loss of a specific element increases, resulting in an abnormal overheating phenomenon, a high di / dt at the time of turn-off of the specific element, and an increase in wiring inductance (reference numeral in FIG. 6). 5) (see waveform Ic1 in FIG. 11).
In the worst case, the IGBT may be destroyed. Therefore, an object of the present invention is to suppress a heat concentration phenomenon and a high surge voltage application phenomenon to a specific element, and prevent the element from being destroyed.

[0006]

In order to solve such a problem, according to the first aspect of the present invention, power semiconductor elements constituting a power converter are connected in parallel, and are commonly used for individually provided gate drive circuits. A current detection means for detecting a current flowing in the power semiconductor element, in a gate drive circuit of the power semiconductor element for driving each of the power semiconductor elements, Calculating means for calculating a difference between a current detection value detected near the input time point of the turn-off command signal and a current maximum value detected during a period in which the turn-off command signal is input, and comparing the calculation result with a predetermined set value A comparison means for performing the operation, when the comparison result is equal to or more than a predetermined value, shorten the time from when the turn-off command signal is input to when the power semiconductor element is actually turned off. It is characterized in.

According to the second aspect of the present invention, the power semiconductor elements constituting the power converter are connected in parallel, and a common drive command signal is given to a separately provided gate drive circuit, so that each of the power semiconductor elements is controlled. In the gate drive circuit of the power semiconductor element to be driven, current differential value detection means for detecting a differential value of a current flowing in the power semiconductor element, and comparison means for comparing the current differential value with a predetermined set value. When the current differential value detected during the period in which the power semiconductor device turn-off command signal is input is equal to or greater than the set value, the time from when the power-off command signal is input until the power semiconductor device is actually turned off. It is characterized by shortening the time.

[0008] That is, these inventions are used when a power semiconductor element such as an IGBT connected in parallel is turned off.
If the turn-off timings of these elements do not match, attention is focused on the phenomenon that a large current flows instantaneously into the element with the later timing, and this phenomenon is detected from the current value or its differential value. After the detection, the drive condition of the element whose timing is later is adjusted so that the switching timing of the element is advanced so that the current imbalance is eliminated and the element is balanced.

[0009]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, reference numeral 13 denotes a sample and hold circuit (S / H), and 14 denotes a peak hold circuit, to which an IGBT collector current detection value D is input. In this detection, a circuit similar to the conventional circuit as shown in FIGS. 9 and 10 is used. The S / H 13 holds the data at the time of the falling of the command signal S during the OFF command period, the peak hold circuit 14 holds the peak value during the OFF command period, and is reset during the ON period. The outputs of the circuits 13 and 14 are input to a subtractor 15, and the result of the subtraction is input to a comparator 16 and compared with a set value Se. Although only one IGBT drive circuit is shown here, it goes without saying that IGBT drive circuits arranged in parallel are similarly configured.

In the above configuration, when the IGBT turns off and a current increasing phenomenon occurs as indicated by Ic1 in FIG. 11, a signal C is output from the comparator 16. This signal C is input to the SR flip-flop circuit 17, which is set. The reset of the circuit 17 is performed by the ON command of the command signal S. 18 is the circuit 1
A variable delay circuit that delays the off command signal F from
Here, when the output H of the circuit 17 is input, the delay time is reduced.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention. This is characterized in that a differential value of the IGBT collector current is detected instead of detecting the IGBT collector current, and the differential value DD of the IGBT collector current is input to the comparator 16. The circuits shown in FIGS. 3 and 4 are used to determine the differential value of the IGBT collector current. This circuit is constructed by adding a differentiating circuit 19 for differentiating the output signal D shown in FIGS. As shown in FIG. 5, by connecting the inductance 20 (the actual inductance may be connected or the wiring inductance may be used), the differential value DD of the collector current is obtained by detecting the voltage between both ends. It may be obtained.

The comparator 16 compares the differential value DD of the collector current obtained as described above with a set value Se1. Then, when the IGBT is turned off, FIG.
The current greatly increases as shown by (di / d at the time of increase).
When t is high), the signal C is output by the comparator 16 and the same operation as in FIG. 1 is performed. Again 1
Although only one IGBT drive circuit is shown,
The configuration of the T drive circuit is the same as in the case of FIG.

In the above, as a method of shortening the time from when the command signal S is input until the IGBT is actually turned off, the delay time of the variable delay circuit is shortened. The turn-off gate resistance may be set to two parallel or two or more series, and when the output signal of the variable delay circuit is active, a method of reducing the combined resistance may be considered. However, if the delay time can be reduced, Any method may be used.

[0014]

According to the present invention, in a system in which an IGBT and a gate drive circuit are connected in parallel, even when the IGBTs and the gate drive circuits provided side by side have a characteristic variation and a difference in internal circuit constants, a substantially balanced current is obtained. It can be turned off with a waveform. As a result, it is possible to prevent the abnormal overheating phenomenon and the destruction of the specific element.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a first example of a detection circuit of a collector current differential value.

FIG. 4 is a circuit diagram showing a second example of a detection circuit of a collector current differential value.

FIG. 5 is a circuit diagram showing a third detection circuit example of a differential collector current value.

FIG. 6 is a configuration diagram showing a conventional example of an inverter.

FIG. 7 is a configuration diagram illustrating a specific example of the gate drive circuit of FIG. 6;

FIG. 8 is a configuration diagram illustrating an example of a system in which an IGBT and a gate drive circuit are arranged side by side.

FIG. 9 is a circuit diagram showing a first example of a collector current detection circuit.

FIG. 10 is a circuit diagram showing a second example of the collector current detection circuit.

FIG. 11 is an explanatory diagram of an example of a current waveform in FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2 ... Inverter circuit, 3A, 3B ... Gate drive circuit, 4 ... Snubber capacitor, 5 ... Wiring inductance, 6 ... Motor (load), 7 ... Power supply for gate drive circuit, 8, 9 ... Switch, 10 , 11 ... gate resistance, 12
... Control unit, 13 ... Sample hold circuit, 14 ... Peak hold circuit, 15 ... Subtractor, 16 ... Comparator, 1
7 ... Set reset flip-flop (SRFF), 1
8: variable delay times, 19: differentiation circuit, 20: reactor.

Claims (2)

[Claims] A power semiconductor for connecting power semiconductor elements constituting a power converter in parallel, applying a common drive command signal to individually provided gate drive circuits, and driving each of the power semiconductor elements. In the gate drive circuit of the element, current detection means for detecting a current flowing in the power semiconductor element, a current detection value detected near an input time point of a turn-off command signal for the power semiconductor element, and the turn-off command signal A calculating means for obtaining a difference from the current maximum value detected during the input period; and a comparing means for comparing the calculation result with a predetermined set value. If the comparison result is equal to or more than a predetermined value, a turn-off command signal is output. A gate drive circuit for a power semiconductor device, wherein the time from when the power semiconductor device is input to when the power semiconductor device is actually turned off is shortened. 2. A power semiconductor for connecting power semiconductor elements constituting a power converter in parallel, applying a common drive command signal to a separately provided gate drive circuit, and driving each of the power semiconductor elements. In the gate drive circuit of the element, a current differential value detecting means for detecting a differential value of a current flowing through the power semiconductor element, and a comparing means for comparing the current differential value with a predetermined set value are provided. If the current differential value detected during the period when the turn-off command signal of the semiconductor element is input is equal to or greater than the set value, shorten the time from when the turn-off command signal is input until the power semiconductor element is actually turned off. A gate drive circuit for a power semiconductor device, comprising: