JP2010259313A - Power conversion system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To protect a freewheel diode against steep reverse recovery in reverse when an output current becomes a leading phase for an output voltage due to an abnormal load or the like with respect to a power converter connecting a resonance capacitor and an induction heating load with the output and operating the output current in a lagging phase for the output voltage. <P>SOLUTION: The power conversion system includes: a voltage detection circuit to detect the voltage between main terminals of a semiconductor element; and a voltage comparison circuit to compare a voltage setting value with a voltage detection value. The power conversion system compares the voltage setting value with the voltage detection value during an off-signal period and does not turn on the semiconductor element when the voltage detection value is large. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a protection circuit for a semiconductor element of a power conversion device in which a resonant capacitor and an induction heating load are connected to an output and an output current is operated in a delayed phase with respect to an output voltage.

FIG. 5 is a circuit diagram for explaining the background art, and FIG. 6 is an operation waveform diagram thereof. First, the circuit diagram shown in FIG. 5 will be described.
A power converter 7 to which a DC voltage source 8 is connected as a DC input is a single-phase rectangular wave composed of a DC capacitor 7e, semiconductor elements 7a, 7b, 7c, and 7d (in this example, IGBTs having diodes connected in antiparallel). This is an output voltage type full bridge inverter.

  The output is connected to an induction heating load 10 composed of a resonance capacitor 9, an inductance component 10a, and a resistance component 10b, and constitutes a resonance circuit as a whole. Here, the frequency command value output from a control circuit (not shown) is input to the pulse generation circuit 11 to generate a control signal. The control signal is input to the gate drive circuit 12, and the output is input to the gates of the semiconductor elements 7a, 7b, 7c, and 7d (IGBT) of the power converter 7.

Next, FIG. 6 will be described.
The output voltage Vo of the power converter 7 is a rectangular wave, but since a resonance circuit is connected to the output, when operating at an output frequency near the resonance point of the resonance curve, the output current Io is The waveform is close to a sine wave. Further, since the operation is performed at an output frequency higher than the resonance point, the output current Io has a delayed phase with respect to the output voltage Vo.

  When the gate signals G7a and G7d are turned off at the point A of the operation period in the delayed phase which is a normal operating state, the voltages V7a and V7d across the IGBTs 7a and 7d rise, and the currents I7a and I7d flowing through the IGBT are 7a and 7d. To 7b, 7c. Since the polarity of I7b and I7c after commutation is negative, the current flows through the freewheeling diode. However, the current decreases gradually due to the resonance circuit connected to the output, and the current becomes positive after the polarity becomes positive. Will increase. Here, by turning on the gate signals G7b and G7c at a point B during a period of time flowing from the point A to the freewheel diode for a certain time, the current smoothly switches from the freewheel diode to the IGBT.

  Next, let us look at point C of the operation period in the leading phase, which is an abnormal operating state. The IGBT currents I7a and I7d are before the gate signals G7a and G7d are turned off when the resonance frequency becomes high due to an abnormality in the induction heating load 10 (inductance component 10a, specifically, a short circuit of the heating coil). In addition, the polarity is negative and flows through the freewheeling diode. That is, the output current Io has a leading phase with respect to the output voltage Vo.

  Therefore, even if the gate signals G7a and G7d are turned off at the point C, the current does not commutate to the IGBTs 7b and 7c but flows directly to the free wheel diodes 7a and 7d. Thereafter, when the gate signals G7b and G7c are turned on at a point D after a certain time from the point C, the free wheel diodes of the IGBTs 7a and 7d are suddenly reversely recovered, and the currents I7a and I7d are commutated to the IGBTs 7b and 7c.

  In this case, for example, in a current region such as a small current, a surge voltage is generated due to a sharp reverse recovery of the free wheel diode, and the semiconductor element may be destroyed. Further, when a MOSFET is used as a semiconductor element of a power converter and a parasitic diode is used as a free wheel diode, the power converter is destroyed only by performing a steep reverse recovery. Patent Document 1 describes the background technology.

However, the background technology is intended for applications in which the output current is gradually controlled by PWM switching, and is not suitable for the case where the semiconductor element is destroyed if the freewheeling diode suddenly reversely recovers even once.

JP 2004-112916 A

  The problem to be solved is related to a power converter that connects a resonant capacitor and an induction heating load to the output and operates the output current in a delayed phase with respect to the output voltage. Is to protect the freewheeling diode from being suddenly reverse-recovered when it reaches the leading phase. Another object of the present invention is to provide a simple control circuit that protects the device from overcurrent due to load abnormality or false firing.

  In order to solve the above-described problem, in the first invention, in the power conversion device in which the resonant capacitor and the induction heating load are connected to the output and the output current is operated in a delayed phase with respect to the output voltage, the main terminal of the semiconductor element A voltage detection circuit that detects an inter-voltage, and a voltage comparison circuit that compares a voltage setting value with the voltage detection value, and compares the voltage setting value with the voltage detection value during an off signal period, A semiconductor element protection circuit that does not turn on the semiconductor element when the detected value is large is provided.

  In the second invention, the voltage detection circuit is constituted by a plurality of voltage dividing resistors connected in parallel with the semiconductor element.

  In a third aspect of the invention, the voltage detection circuit is configured by dividing the control circuit power supply with a plurality of resistors and connecting a diode between the voltage dividing point and the main electrode of the semiconductor element.

  In a fourth aspect of the present invention, the voltage setting value is compared with the detected voltage value during the off signal period in the first to third aspects, and the off signal is turned on when the detected voltage value is large. A failure signal is output after the time when the signal is changed.

  According to a fifth aspect of the present invention, there is provided a power converter for connecting a resonant capacitor and an induction heating load to an output and operating an output current in a delayed phase with respect to the output voltage, and a voltage detection circuit for detecting a voltage between main terminals of a semiconductor element. And a voltage comparison circuit that compares the voltage setting value with the detection value of the voltage detection circuit, and compares the voltage setting value with the voltage detection value during an off signal period, and the voltage detection value is large. When the voltage detection value is large by comparing the voltage setting value and the voltage detection value during the ON signal period with the first protection circuit of the semiconductor element that does not turn on the semiconductor element, And a second protection circuit for the semiconductor element that turns off the semiconductor element more slowly than the normal off operation.

  In a sixth aspect of the invention, a voltage comparison circuit that compares the voltage setting value and the voltage detection value during the off signal period in the fifth aspect of the invention, and the voltage setting value and the voltage detection value during the on signal period The voltage comparison circuit for comparing the two is shared.

  According to a seventh aspect, in the fifth or sixth aspect, the voltage setting value is compared with the voltage detection value during the on-signal period, and a failure is determined when the voltage detection value is large. Or a second failure signal determined as a failure when the detected voltage value is large, by comparing the voltage setting value with the detected voltage value during the off signal period. To do.

  According to the present invention, when a voltage is applied to the semiconductor element, it does not turn on, so that when current flows through the free wheel diode of the opposing arm, it does not suddenly reversely recover. As a result, no surge voltage is generated in a small current region and the semiconductor element is not destroyed. Further, even when a MOSFET parasitic diode is used as a freewheeling diode, it is possible to prevent destruction because it does not perform a sharp reverse recovery. In addition, since the protection circuit for slowly turning off the element when the element is overcurrent can be shared, highly reliable element protection can be realized.

  Furthermore, since the protection judgment is made by comparing the detected value of the main electrode voltage of the semiconductor element with the set value, a current detector or the like is unnecessary, and insulation of the detected voltage is unnecessary, and a simple circuit can be configured. . In addition, highly reliable protection is possible by outputting a failure signal outside the protection circuit.

1 is a circuit diagram showing a first embodiment of the present invention. It is a circuit diagram which shows the 2nd Example of this invention. It is a circuit diagram which shows the 3rd Example of this invention. It is a circuit diagram which shows the 4th Example of this invention. It is a circuit diagram which shows the conventional Example. It is a wave form diagram which shows operation | movement of each part.

  The main points of the present invention are a voltage detection circuit for detecting a voltage between main terminals of a semiconductor element in a power conversion device in which a resonant capacitor and an induction heating load are connected to an output and the output current is operated in a delayed phase with respect to the output voltage. A voltage comparison circuit for comparing the voltage setting value and the voltage detection value, and comparing the voltage setting value and the voltage detection value during an off signal period, and when the voltage detection value is large, The semiconductor device is not turned on, and the semiconductor device is turned off more slowly than usual when the voltage detection value is large in the voltage comparison circuit during the on period.

FIG. 1 is a circuit diagram for explaining an embodiment of the present invention. The waveform diagram is shown in FIG. 6 as in the background art.
First, FIG. 6 will be described.
When the gate signals G7b and G7c are turned on at the point B when the output current Io is in a lag phase with respect to the normal output voltage Vo, the current flows through the free wheel diodes of the IGBTs 7b and 7c that are turned on, and the IGBTs 7b and 7c Is about −V of the forward drop voltage when the diode is conductive.

When the gate signals G7b and G7c are turned on at the point D when the output current Io is in a leading phase with respect to the output voltage Vo due to an abnormality in the induction heating load, current flows in the free wheel diodes of the opposing arms IGBTs 7a and 7d. The voltage Ed of the DC capacitor 7e is applied as the voltage of the IGBTs 7b and 7c, and becomes several hundred volts or more in this power supply.
It is this proposal to protect by utilizing this difference in voltage.

Next, FIG. 1 will be described. It is an Example in the case of using IGBT as a semiconductor element.
A voltage dividing resistor 1 composed of resistors R1 and R2 that divide a value obtained by detecting a voltage between main electrodes of the semiconductor element 7X, a comparator 2 that compares it with a voltage setting value, and a flip-flop that takes a timing when a control signal is turned on 3, a delay circuit 4, an AND circuit 5, and an amplifier circuit 6 for generating a gate signal.

  After dividing the voltage between the main electrodes of the semiconductor element 7X into a voltage of about several volts that can be easily handled by the voltage dividing resistor 1, the comparator 2 compares this value with the voltage setting value, and between the main electrodes of the semiconductor element 7X. Is high (Hi) when the voltage of the diode is about -several V when the diode is conducting, and low (Lo) when the voltage of the DC intermediate capacitor 7e (several hundreds V or more in this power supply) is output. ) Is output.

  Since the comparator 2 outputs high (Hi) at point B when the output current Io is in a lagging phase with respect to the normal output voltage Vo, the control signal is on, that is, low (Lo) → high (Hi). When it becomes, the flip-flop 3 outputs high (Hi). When the output of the delay circuit 4 set to be longer than the delay time of the input → output of the flip-flop 3 changes from low (Lo) → high (Hi), the other input of the AND circuit 5 is also high (Hi). The output also becomes high (Hi), and the semiconductor element 7X (IGBT) is turned on via the amplifier circuit 6.

  At point D when the output current Io is in a leading phase with respect to the output voltage Vo due to an abnormality in the induction heating load, the comparator 2 outputs low (Lo), so the control signal is on, that is, low (Lo ) → High (Hi), flip-flop 3 outputs low (Lo). When the output of the delay circuit 4 changes from low (Lo) to high (Hi), the other input of the AND circuit 5 is low (Lo), so the output remains low (Lo) and the IGBT is not turned on. At the same time, when the control signal changes from low (Lo) to high (Hi), the output of the flip-flop 3 becomes low (Lo), a failure signal is sent to a control circuit (not shown), and the operation is stopped. At this time, the failure factor can be displayed by sending it to the display circuit.

  The effective use of this proposal is that after the control signal is turned off (Lo), after various delays such as the gate drive circuit, the voltage of the semiconductor element rises, the free wheel diode of the opposite arm becomes conductive, and the voltage is Even after falling, the device can afford to output ON to the control signal of the opposite arm.

FIG. 2 shows a second embodiment of the present invention. The difference from the first embodiment is the voltage detection circuit. In this embodiment, the voltage of the power supply Vcc of the control circuit is divided by resistors R1 and R2, and a diode D1 is connected between this voltage dividing point and the main electrode (collector) of the IGBT 7X.
When the IGBT 7X is turned on or when a diode connected in reverse parallel to the IGBT is turned on, the diode D1 conducts, so the voltage at the resistance voltage dividing point is the voltage of the IGBT main electrode (collector) + the diode. This is the forward voltage drop of D1.

Therefore, the comparator 2 outputs high (Hi) at point B when the output current Io is in a lagging phase with respect to the normal output voltage Vo. The operation is the same as that of the first embodiment because the comparator 2 outputs low (Lo) at point D when the output current Io is in the lead phase with respect to the output voltage Vo due to an abnormality in the induction heating load. It is. Since the control power supply is usually about 15 V, the loss of the voltage dividing resistor can be suppressed to a small value compared to the first embodiment.

  FIG. 3 shows a third embodiment of the present invention. The difference from the first and second embodiments is that a protection circuit in the case of an overcurrent such as when a load or IGBT is short-circuited is added. Since the voltage between the main terminals (between collector and emitter) of a semiconductor element such as IGBT during overcurrent rises according to the value of overcurrent, it can be protected by detecting this and turning off the IGBT gently. The circuit has a configuration in which an AND circuit 13, a delay circuit 14, an AND circuit 15, and a time constant changing circuit 16 are added to the first embodiment.

  The operation will be described below. Since the protection when the delayed load is advanced due to an abnormal load is the same as in the first embodiment, the newly added overcurrent protection circuit portion will be described. When the control signal is on (Hi) and the IGBT current becomes an overcurrent, the collector-emitter voltage rises, and the output of the comparator 2 becomes low (Lo). As a result, the output of the AND circuit 13 becomes low (Lo). The delay circuit 14 sets a delay time until the IGBT is turned on and drops to an on voltage of several volts after the control signal is turned on (Hi) in normal operation, and the failure signal is normally operated normally. To prevent output. When the fault signal becomes low (Lo) due to an overcurrent, low (Lo) is input to the AND circuit 15 and the other input is high (Hi), but the output becomes low (Lo) and the amplifier circuit 6 has a gate voltage. Works to lower. At the same time, Low (Lo) is input to the time constant changing circuit 16, and the time constant is lengthened to operate in conjunction with the amplifier circuit 6 so that the gate voltage slowly decreases compared to the normal operation.

  Here, in a normal PWM inverter or the like, the delay circuit 14 is necessary because the time from when the control signal is turned on (Hi) until the IGBT collector-emitter voltage V7X drops to a voltage of several volts is long. However, in a power supply that operates with a delay load, as described above, when the control signal is turned on (Hi), the IGBT voltage V7X is about −several V, and thus the delay circuit 14 can be omitted. . Further, the output of the delay circuit 14 is sent to the control circuit and the display circuit as a failure signal at the time of overcurrent, and the output of the flip-flop 3 is sent to the control circuit and the display circuit as a signal of advance operation due to load abnormality, respectively, and used for stopping the device and displaying the cause of failure. It is done. The circuit of this embodiment is an example using the voltage detection circuit used in the first embodiment, but the same applies to the case of using the voltage detection circuit of the second embodiment. As described above, since the detection of the IGBT collector-emitter voltage for protection when the delay load is abnormal and the lead operation is started and the protection in the case of overcurrent can be shared, a simple control circuit can provide a reliable element. Protection can be realized.

  FIG. 4 shows a circuit diagram of a fourth embodiment of the present invention. The difference from the first to third embodiments is that the protection when the delayed load is advanced and becomes a load due to the abnormality of the load and the protection at the time of overcurrent such as when the IGBT is short-circuited are shared. In any protection case, when it is detected that the voltage between the main terminals (collector-emitter) of the IGBT is higher than a predetermined value, the IGBT is gently turned off to share the protection circuit.

  The circuit outputs the output of a voltage level determination circuit comprising a voltage dividing resistor 1 and a comparator 2 for detecting the collector-emitter voltage level of the IGBT to one input of the AND circuit 13 and a control signal to the other input, Connect each one. The output of the AND circuit 13 is connected to one input of the AND circuit 15 and the input of the time constant changing circuit, and a control signal is connected to the other input of the AND circuit 15. The output of the AND circuit 15 and the output of the time constant changing circuit are each connected to the input of the amplifier circuit 6, and the output of the amplifier circuit 6 is connected to the gate of the IGBT 7X.

  In such a configuration, when the control signal is turned on (Hi) when the output current Io is in a lag phase with respect to the normal output voltage Vo, the output of the comparator 2 is high (Hi), so the failure signal is high. The AND circuit 15 outputs high (Hi), and the amplifier circuit 6 operates to increase the gate voltage. Since the input of the time constant changing circuit 16 is high (Hi), it does not operate, and the amplifier circuit 6 operates to increase the gate voltage with a normal time constant.

  When the output current Io is in a delayed phase with respect to the normal output voltage Vo, when the control signal is turned off (Lo), the output of the comparator 2 is turned low (Lo), but the control signal is turned off (Lo). Therefore, the failure signal remains high (Hi). At this time, the output of the AND circuit 15 is low (Lo) because the control signal is off (Lo) and the failure signal is Hi. As a result, the amplifier circuit 6 operates to lower the gate voltage. Since the input of the time constant changing circuit 16 is high (Hi), the time constant changing circuit 16 does not operate, and the amplifier circuit 6 operates so as to lower the gate voltage with a normal time constant.

  When the output current Io is in the lead phase with respect to the output voltage Vo, even if the control signal is turned on (Hi), the output of the comparator 2 is low (Lo), so the failure signal is low (Lo). As a result, the AND circuit 15 remains low (Lo), and the gate voltage is the off-time voltage (normally −several V), so the IGBT is not turned on.

  Here, in a normal PWM inverter that is not a resonant load, when the control signal is turned on (Hi), the voltage V7X across the IGBT is about several volts from the voltage Ed of the DC capacitor 7e (several hundreds V or more in this power supply). Although a failure signal is output by delaying the time until the voltage drops, this delay circuit can be omitted in a resonant circuit such as this power supply, so both protection circuits must be shared. Can do.

When the control signal is on (Hi) and the current is excessive, such as when the load is short-circuited or the IGBT of the opposite arm is short-circuited, the output of the comparator 2 is low (Lo), so the failure signal is also low (Lo). It becomes. As a result, the AND circuit 15 outputs low (Lo), and the amplifier circuit 6 operates so as to lower the gate voltage. At this time, since the input of the time constant changing circuit 16 is low (Lo), it operates in conjunction with the amplifier circuit 6 so as to lengthen the time constant and slowly lower the gate voltage. The output of the AND circuit 13 is sent as a failure signal to the control circuit and the failure display circuit, and used for stopping the device and displaying the failure factor.
The present embodiment is an example using the voltage detection circuit used in the first embodiment, but the same applies to the case where the voltage detection circuit of the second embodiment is used.
In the above-described embodiment, an example in which an IGBT is applied as a semiconductor element has been described. However, a case in which a MOSFET is applied can be similarly realized.

  Although the induction heating apparatus has been described in the present application, the present invention can be applied to a switching power supply or a DC-DC converter using a resonance circuit.

DESCRIPTION OF SYMBOLS 1 ... Voltage dividing resistor 2 ... Comparator 5 ... AND circuit 3 ... Flip-flop 4 ... Delay circuit 6 ... Amplification circuit 7 ... Power converter 9 ... Resonance capacitor 7X , 7a to 7d ... Semiconductor element (IGBT) 10 ... Induction heating load 7e ... DC capacitor 8 ... DC power supply 10a ... Inductance component 10b ... Resistance component 11 ... Pulse generation circuit DESCRIPTION OF SYMBOLS 12 ... Gate drive circuit 13 ... AND circuit 14 ... Delay circuit 15 ... AND circuit 16 ... Time constant change circuit

Claims (7)

In a power converter that connects a resonant capacitor and an induction heating load to the output and operates the output current in a delayed phase with respect to the output voltage,
A voltage detection circuit for detecting a voltage between main terminals of the semiconductor element, and a voltage comparison circuit for comparing a voltage setting value with a detection value of the voltage detection circuit,
A power conversion comprising a protection circuit for a semiconductor element that does not turn on the semiconductor element when the voltage detection value is large by comparing the voltage setting value and the voltage detection value during an off signal period apparatus.  The power converter according to claim 1, wherein the voltage detection circuit includes a plurality of voltage dividing resistors connected in parallel with a semiconductor element.   2. The power according to claim 1, wherein the voltage detection circuit is configured by dividing a control circuit power supply with a plurality of resistors and connecting a diode between the voltage dividing point and a main electrode of a semiconductor element. Conversion device.   The voltage setting value is compared with the voltage detection value during the off signal period, and when the voltage detection value is large, a failure signal is output after the time when the off signal changes to the on signal. The power converter according to any one of claims 1 to 3. In a power converter that connects a resonant capacitor and an induction heating load to the output and operates the output current in a delayed phase with respect to the output voltage,
A voltage detection circuit for detecting a voltage between main terminals of the semiconductor element, and a voltage comparison circuit for comparing a voltage setting value with a detection value of the voltage detection circuit,
The voltage setting value is compared with the voltage detection value during an off signal period, and when the voltage detection value is large, a first protection circuit of a semiconductor element that does not turn on the semiconductor element, and the voltage detection value during the on signal period A second protection circuit for a semiconductor element that compares the voltage setting value with the voltage detection value and turns off the semiconductor element more slowly than a normal OFF operation when the voltage detection value is large. The power converter characterized by the above-mentioned.   The voltage comparison circuit that compares the voltage setting value and the voltage detection value during the off signal period and the voltage comparison circuit that compares the voltage setting value and the voltage detection value during the on signal period are shared. The power conversion device according to claim 5. The voltage setting value is compared with the voltage detection value during the ON signal period, and the first failure signal determined as a failure when the voltage detection value is large, or the voltage setting value during the OFF signal period The power conversion device according to claim 5 or 6, wherein the voltage detection value is compared, and a second failure signal determined as a failure is output when the voltage detection value is large.

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