JP2002223565A - Dc-to-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC-to-DC converter which enables reduction in switching losses and use of low breakdown voltage MOSFETs of low on-resistance. SOLUTION: In a DC-to-DC converter, having rectifying circuit portions 21, 22 fitted through transformers Tr1-Tr2 on the output sides of conversion circuit portions 11, 12 for converting the source voltage of a DC power source E into Acs, two groups of conversion circuit portions 11, 12 composed by connecting two pairs of switching elements Q1-Q4, Q5-Q8 by full bridge formation are provided for the DC power source E, and series capacitors C1, C2 are inserted and connected between those converting portions 11, 12 and the transformers Tr1, Tr2. Along with shifting the switching phases of switching elements Q4, Q8 on one side by 1/3n period, with respect to switching elements Q1, Q5 on the other side, from among switching elements which form pairs in each connecting circuit 11, 12, the switching phases of the switching elements Q1, Q5 which correspond between individual converting circuits 11, 12 are shifted by 1/2n period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter, and more particularly to a DC-DC converter used in a DC power supply circuit for converting a power supply voltage of a DC power supply into a different DC voltage.
It relates to a C converter.

[0002]

2. Description of the Related Art For example, DC used in a DC power supply circuit is known.
An example of a DC-DC converter is shown in FIG.
FIG. 8 shows a timing chart of the gate signal G for turning on / off each of the switching elements Q _{1 to} Q ₄ of the converter.

The DC-DC converter shown in FIG. 7 has two pairs of switching elements Q ₁ , Q ₄ and Q ₂ , Q ₃ (MOS-FE
T) is connected to the DC power supply E in a full-bridge configuration, a transformer Tr connected to the output side of the converter circuit section 1, and two pairs of transformers connected to the secondary side output of the transformer Tr. It comprises a rectifier circuit 2 composed of diodes D ₁ and D ₄ and D ₂ and D ₃ , and an LC smoothing circuit 3 connected to the output side of the rectifier circuit 2.

In this DC-DC converter, as shown in the timing chart of FIG. 8, the switching elements Q ₁ , Q ₄ and Q ₂ , Q ₃ of the conversion circuit unit 1 are alternately turned on and off to obtain an AC waveform output. The AC waveform output of the conversion circuit unit 1 is transformed by a transformer Tr, and the secondary output of the transformer Tr is rectified by a rectifier circuit 2 and an LC smoothing circuit 3
, A desired DC voltage is generated.

[0005]

By the way, the aforementioned D
Looking at the load side from the transformer input side of the C-DC converter, looks generally inductive load (delay load), in which case the voltage of the switching element Q ₁ to Q _4, i.e., the drain - source voltage V _ds And the drain current _Id has a waveform as shown in FIG. 10 (a) is the drain of the switching element Q ₁ to Q ₄ shown in FIG. 9 - is the respective waveforms of the source voltage V _ds and drain current I _d which schematically illustrates, FIG (b) is turned on Switching loss P ₁
And the switching loss P ₃ at the time of turn-off and the conduction loss P ₂ .

The switching elements Q _{1 to} Q ₄ (MOS-FE
The losses in T) include switching losses P ₁ and P ₃ and conduction losses P ₂ as shown in FIG. 10B, and the switching losses include the turn-on that occurs when the switching elements Q _{1 to} Q ₄ are turned on. the switching loss P _1,
There is a turn-off switching losses P ₃ generated upon turning off of switching elements Q ₁ to Q _4. The switching loss is caused by the drain-source voltage V _ds while the drain current I _d flows in a short transient state in which the switching elements Q _{1 to} Q ₄ change from on to off and from off to on.
Is generated by the application of. On the other hand, the conduction loss P ₂ is
It occurs when the switching element Q ₁ to Q _4, the resistance loss due to the on resistance and the drain current.

As for switching loss, in the case of an inductive load (delayed load), the turn-off switching loss P ₃ is generally larger than the turn-on switching loss P ₁ , and the turn-on switching loss P ₁
May not occur depending on the setting of the circuit constant.

If the DC-DC converter is to be miniaturized, the transformer Tr can be miniaturized if the switching frequency is increased. Therefore, increasing the switching frequency is an effective means. However, as the switching frequency increases, the switching loss proportional to the switching frequency also increases,
To reduce the switching loss, increasing the switching frequency is not a suitable means.

On the other hand, switching elements Q _{1 to} Q ₄ are MOS
-When a MOS-FET is used, the MOS-FET is faster in turn-on and turn-off than a bipolar transistor or an IGBT, and can perform high-speed switching. Compared to IGBT, MOS-FE
The on-resistance of T has the characteristic that it increases in proportion to the element withstand voltage to the power of 2.5. Since the conduction loss of this MOS-FET is a resistance loss determined by the on-resistance and the drain current, the MOS-FE having a high breakdown voltage has a characteristic that the on-resistance increases in proportion to the 2.5th power of the element breakdown voltage.
The use of T causes an exponential increase in conduction loss, causing a decrease in the efficiency of the DC-DC converter.

In view of the above, the present invention has been proposed in view of the above-mentioned problems. An object of the present invention is to reduce the switching loss and to use a MOS-FE for the switching element.
When T is used, a low breakdown voltage MOS-F with low on-resistance
An object of the present invention is to provide a DC-DC converter capable of using ET.

[0011]

According to a first aspect of the present invention, there is provided a rectifier for converting a power supply voltage of a DC power supply into an AC through a transformer on an output side thereof. In a DC-DC converter provided with a circuit portion, n groups of conversion circuit portions in which two pairs of switching elements are connected in a full bridge configuration are provided for the DC power source, and a series capacitor is provided between each of the conversion circuit portions and the transformer. Among the switching elements forming a pair in each conversion circuit unit, the switching phase of the other switching element is shifted by 1 / 3n cycle with respect to one switching element, and the corresponding switching between the conversion circuit units is performed. The switching phase of the element is shifted by 1 / 2n cycle.

According to the first aspect of the present invention, in the conversion circuits of n groups, the switching phase of one of the switching elements forming a pair in each of the conversion circuits is set to the switching phase of the other switching element for 1 / 3n cycle. In addition, by shifting the switching phase of the corresponding switching element between each of the conversion circuit sections by ｎn cycle, the state in which the switching voltage is applied while the switching current flows through the switching element due to commutation is eliminated, so that the switching loss is reduced. It does not occur. In addition, by connecting a series capacitor between the conversion circuit and the transformer, a droop (slope) is applied to the flat part of the output voltage of the conversion circuit, and a voltage waveform with a high rising portion is formed, so that commutation is performed. The commutation operation is reliably performed by increasing the voltage difference before and after the timing. The invention of claim 1 is
As a switching element, a bipolar transistor or an IGBT can be applied in addition to the MOS-FET.

According to a second aspect of the present invention, the switching element is a MOS-FET, and n groups of converter circuits are connected in series to a DC power supply. According to the present invention, the voltage applied to each MOS-FET of the conversion circuit unit can be reduced to 1 / n of the power supply voltage of the DC power supply, whereby the withstand voltage of the MOS-FET used for the switching element is also reduced to 1 / n. This withstand voltage of 2.5
The conduction loss due to the on-resistance that increases in proportion to the power can be suppressed.

According to a third aspect of the present invention, each of the conversion circuits has a half-bridge configuration by replacing one of the switching elements forming a pair in each of the conversion circuits with a capacitor. According to the third aspect of the present invention, the switching phase of the corresponding switching element is shifted by ｎn periods between the conversion circuit sections, so that one of the switching elements forming a pair in each conversion circuit section is switched. Since the commutation is used as a trigger, a half-bridge configuration can be realized with only one of the switching elements forming a pair in each conversion circuit unit.

As described in claim 4, the n
It is also possible to adopt a configuration in which the conversion circuit units of the group are connected in parallel to the DC power supply.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A DC-DC converter according to the present invention
The embodiment of the data is described in detail below. FIG. 1 shows an embodiment of the present invention.
Circuit diagram of the DC-DC converter in the state, FIG.
Each switching element Q of DC-DC converter₁~ Q₈To
Timing chart and diagram of gate signal G to be turned on / off
3 is an output voltage V of the rectifier circuit units 21 and 22₁, V_Two, Tran
Str ₁, Tr_TwoPrimary side voltage, each switching element Q₁
~ Q₈Drain-source voltage V_dsAnd drain current
Style I_dFIG.

The DC-DC converter of this embodiment is
An n group in which two pairs of switching elements Q ₁ , Q ₄ and Q ₂ , Q ₃ and Q ₅ , Q ₈ and Q ₆ , Q ₇ (for example, MOS-FET, bipolar transistor or IGBT) are connected in a full bridge configuration; For example, two groups of conversion circuit units 11 and 12, two transformers Tr ₁ and Tr ₂ connected to the output sides of the conversion circuit units 11 and 12, and connected to the secondary side outputs of the transformers Tr ₁ and Tr ₂ And two groups of rectifier circuits 21 and 22 including two pairs of diodes D ₁ , D ₄ and D ₂ , D ₃ and D ₅ , D ₈ and D ₆ and D ₇ , and the output sides of the rectifier circuits 21 and 22. And an LC smoothing circuit 33 that is commonly connected to the control circuit. In this DC-DC converter, the two groups of conversion circuit units 11 and 12 are connected in series to the DC power supply E. Further, series capacitors C ₁ and C ₂ are inserted and connected between the output sides of the conversion circuit sections 11 and 12 and the primary sides of the transformers Tr ₁ and Tr ₂ .

In this DC-DC converter, as shown in the timing chart of FIG. 2, switching elements Q ₁ , Q ₄ and Q ₂ , Q ₃ and Q ₅ , Q ₈ and Q ₆ , Q ₆ of switching circuits 11 and 12 are provided. ₇ is turned on and off alternately to obtain an AC waveform output.
The AC waveform output of the conversion circuit units 11 and 12 is
The transformers are transformed by r ₁ and Tr ₂ , and the secondary outputs of the transformers Tr ₁ and Tr ₂ are rectified by the rectifier circuits 21 and 22 and smoothed by the LC smoothing circuit 33 to generate a desired DC voltage.

As shown in the timing chart of FIG. 2, one of the two conversion circuit units 11 and 12
Of the switching elements Q ₁ and Q ₄ , one switching element Q ₁ (the switching element Q ₂ is the inverse of the switching element Q ₁ ) and the other switching element Q ₄
(Switching element Q ₃ are inverted switching element Q ₄₎
Is delayed by 1 / 3n cycle, for example, 1/6 cycle. Also, regarding the switching elements Q ₁ and Q ₅ corresponding between the conversion circuit units 11 and 12, the other conversion circuit unit 1
The switching phase of the second switching element Q ₅ (the switching element Q ₆ is the inversion of the switching element Q ₅ ) is delayed by ｎn cycle, for example, １ ／ cycle, with respect to the switching element Q ₁ . Further, of the switching elements Q ₅ and Q ₈ forming a pair in the other conversion circuit section 12, one switching element Q ₅ is switched to the other switching element Q ₈ (the switching element Q ₇ is the inverse of the switching element Q ₈ ). Is delayed by 1/6 cycle.

Switching of the conversion circuit units 11 and 12
Element Q₁~ Q_Four, Q_Five~ Q₈Is the drain as shown in FIG.
−Source voltage V_dsAnd drain current I_dSo
The switching operation is performed (see the table in FIG. 4). Here, FIG.
The table shows each switching element Q ₁~ Q_Four, Q_Five~ Q₈Current value
This shows the change and transition of. Supply constant power to the load,
To supply constant current under voltage output, switch
Element Q₁~ Q_Four, Q_Five~ Q₈The total output current from
The current value is 1 pu even at the timing of the shift. sand
That is, at one of the timings,
Switching element Q₁~ Q_FourOutput current from 0 → 1pu
, The switching of the other conversion circuit unit 12
Element Q_Five~ Q₈Output current changes from 1 → 0pu
I have. Also, at another timing, the conversion circuit 11
Switching element Q₁~ Q_FourOutput current is 1 pu
Then, the switching element Q of the other conversion circuit section 12_Five~
Q₈Is 0 pu.

The interval t₁~ T₈Is 0 <t₁≤ 1/4
・ T, 0 ≦ t_Two<１ ／ T, 0 <t _Three≦ １ ／ · T, 0
≤t_Four<１ ／ T, 0 <t_Five≦ １ ／ · T, 0 ≦ t₆<
1 / 4.T, 0 <t₇≦ １ ／ · T, 0 ≦ t₈<1/4
It can be freely changed within the range of the condition of T. These eight
The condition is the or condition, but t₁+ T_Two+ T_Three+ T_Four+ T_Five+
t₆+ T₇+ T₈= T must be satisfied. The current
Section t to increase or decrease₁, T_Three, T_Five, T₇Is the waveform by the circuit constant
Are practically free from switching losses.
Limited to range.

Each switching element Q₁~ Q_Four, Q_Five~ Q₈of
The switching operation allows the transformer Tr₁, Tr_TwoPrimary
Transformer Tr is connected to the side voltage (second from the top in FIG. 3).₁,
Tr_TwoOf the absolute value of the metamorphic ratio of
In FIG. 3, the primary-side voltage waveform is folded at the zero point.
The top) is the transformer Tr₁, Tr_TwoRectifies the secondary voltage of
Output power obtained as a result of rectification by the circuit units 21 and 22
Pressure V₁, V_TwoBecomes The output power of the rectifier circuits 21 and 22
Pressure V₁, V_TwoCommutation at the highest voltage value.
Load voltage V_outIs generated. this
The commutation is performed at the timing indicated by the arrow in FIG.
Ching element Q₁, Q_Four→ Switching element Q _Five, Q₈→ Sui
Switching element Q_Two, Q_Three→ Switching element Q₆, Q₇→ S
Switching element Q₁, Q_FourIt is repeated in the order of.

In the conversion circuit units 11 and 12, the switching element Q ₁ (Q ₂ ) is
₄ (Q ₃ ) is turned on / off at a timing delayed by １ ／ cycle, and the switching element Q ₅ (Q ₆ ) is turned on / off at a timing delayed by １ ／ cycle with respect to the switching element Q ₁ (Q ₂ ). , And the switching element Q
₈ (Q ₇ ) is 1/6 of the switching element Q ₅ (Q ₆ ).
It is turned on and off at the timing delayed by the period.

Thus, the outputs of the rectifier circuits 21 and 22 are output.
Voltage V₁, V_TwoIs the switching element Q₁~ Q₈
The drain current I_dFlows between the drain and source
Pressure V_{d s}Switching loss because the state where
No loss occurs. Also, determine the commutation timing.
The switching element that triggers commutation is
Child Q_Three, Q_Four, Q₇, Q₈But these switching
Element Q_Three, Q_Four, Q₇, Q₈Is given the gate signal G
Even when turned on, drain current I_dIs a transformer Tr₁, T
r_TwoInstantaneously after commutation due to leakage reactance of
Current rise is suppressed rather than reaching the current
Therefore, turn-on switching loss occurs
There is no.

The conversion circuit units 11 and 12 and the transformer T
By inserting and connecting the series capacitors C ₁ and C ₂ between r ₁ and Tr ₂ , a droop (slope) is applied to the flat portion of the output voltage of the conversion circuit portions 11 and 12, and a voltage waveform having a high rising portion is obtained. By doing so, the voltage difference is increased before and after the commutation timing, and the commutation operation is reliably performed. Further, it is also possible to prevent DC bias excitation of the transformers Tr ₁ and Tr ₂ by cutting DC components included due to variations in ON resistance and switching speed due to individual differences among the switching elements Q _{1 to} Q ₄ and Q _{5 to} Q _8. It is possible.

The switching element Q having the above configuration
₁~ Q_Four, Q_Five~ Q₈In the embodiment in which is a MOS-FET,
In other words, the two groups of conversion circuit units 11 and 12 are connected to the DC power supply E.
And connect them in series.
However, each MOS-FET of the conversion circuit units 11 and 12 may have
Voltage (excluding surge voltage) of DC power supply E
Can be reduced by a factor of two, so that the switch
Element Q₁~ Q_Four, Q _Five~ Q₈MOS-FET used for
The withstand voltage of the conventional DC-DC converter (see FIG. 7)
Can be reduced by half compared to
The conduction loss due to the on-resistance that increases in proportion to the power of 2.5
Can be suppressed.

That is, the switching elements Q _{1 to} Q ₄ and Q ₅
If the breakdown voltage of the to Q ₈ is reduced to 1/2, the on-resistance will be reduced to (1/2) ^2.5%, about 20% (down 80%). Each switching element Q ₁ -Q ₄ , Q _5-
The conduction losses Q ₈ compares seek below.

In a conventional DC-DC converter,
If the on-resistance of the switching elements Q _{1 to} Q ₄ is r ₁ , the drain current is id ₁ , the switching cycle is t _sw, and the conductivity of the switching elements is 50%, the switching element 1
conduction loss P per one cycle (1 pulse) of pc
_loss1 is a _{P loss1 = r 1 × i d1} 2 × t sw / 2.

On the other hand, the DC-DC converter of the embodiment
In the converter, the switching element Q₁~ Q_Four, Q_Five~ Q₈
The on-resistance of_TwoAnd the drain current is i_d2, Switching
The period is set to t_swAnd In this embodiment
One round as shown in the switching pattern (see FIG. 2)
Commutation in the period is the switching element Q₁, Q_Four1 /
Four cycles, the next quarter cycle is the switching element Q_Five, Q₈,
The next 周期 cycle is the switching element Q_Two, Q_Three, The next 1 /
Four cycles are the switching element Q₆, Q₇Will flow to
You. Also, the output voltage of the group of converter circuits is
, So the final output is the same as before
In order to achieve this, the drain current per pc of switching element
i_d2Is the drain current i in the conventional case._d1Twice the switch
Element Q ₁~ Q_Four, Q_Five~ Q₈Is 1 in the conventional case.
/ 2 is 25%.

As a result, the switching element 1pc
The conduction loss P _loss2 per cycle (1 pulse) is P _loss2
= A ^{_{r 2 × i d2 2 × t}} sw / 4. Where i _d2 = 2 × i
_d1, r because r ₂ is about 20% of the r _{1 2} / r ₁ =
Since 0.2, P _loss2 = (0.2 × r ₁ ) × (2 × _{id 1} ) ² × t _sw / 4 = 0.4 × r ₁ × _id ¹² × t _sw / 2 = 0 _0.4 × P _loss1 . This indicates that the conduction loss in the case of the embodiment is reduced to 40% (−60%) in the case of the conventional example. Based on this, considering the total of all the switching elements connected in full bridge by the conversion circuit units 11 and 12, the switching element is 4pc in the conventional example and the switching element 8pc in the embodiment. Therefore, all the switching elements (4p
Assuming that the total conduction loss in c) is 100%, the total conduction loss in all the switching elements (8 pc) in the embodiment is 80% (−20%), and the loss by 20% is reduced.

As another embodiment of the present invention, as shown in FIG. 5, each of the two groups of conversion circuit units 11 'and 12' can have a half-bridge configuration. In the two groups of conversion circuit units 11 'and 12', the switching elements Q ₃ , Q ₄ , Q ₇ and Q ₈ are used as triggers for the commutation in order to determine the commutation timing. The other switching elements Q ₁ , Q ₂ , Q ₅ , and Q ₆ can be replaced with capacitors C ₁₁ , C ₁₂ , C ₂₁ , and C ₂₂ to form a half-bridge configuration. The timing (phase) at which the switching elements Q ₃ , Q ₄ , Q ₇ , Q ₈ are switched in this embodiment is the same as in the case of the full bridge configuration.

As another embodiment, as shown in FIG. 6, two groups of conversion circuit units 11 ″ and 12 ″ are connected to a DC power supply E.
Can be connected in parallel to each other, in which case, the occurrence of switching loss can be suppressed.
Also in this embodiment, the switching elements Q _{1 to} Q ₄ , Q
₅ timing for switching to Q ₈ (phase) is the same as in the full-bridge configuration.

[0033]

According to the present invention, the switching phase of one of the switching elements forming a pair in each of the n conversion circuits is set to 1 / 3n with respect to the switching phase of the other switching element. By shifting the switching phases of the corresponding switching elements by ｎn cycles at the same time as shifting the cycles, the state in which the switching voltage is not applied while the switching current flows through the switching elements due to commutation is eliminated. Does not occur.

Further, the switching element is a MOS-F
In the case of ET, each of the MOS-Fs of the conversion circuit section is connected by connecting the n groups of conversion circuit sections in series with the DC power supply.
The voltage applied to the ET can be reduced to 1 / n of the power supply voltage of the DC power supply, whereby the withstand voltage of the MOS-FET used for the switching element can also be reduced to 1 / n. The conduction loss due to the on-resistance that increases in proportion to the fifth power can be suppressed.

Therefore, a high efficiency DC-DC converter which can reduce the switching loss and use a low withstand voltage MOS-FET having a low on-resistance when a MOS-FET is used as a switching element is provided. be able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a DC-DC converter according to an embodiment of the present invention.

FIG. 2 is a timing chart of a gate signal for turning on / off each switching element of the DC-DC converter of FIG. 1;

3 is a waveform diagram of an output voltage of a rectifier circuit unit in FIG. 1, a primary voltage of a transformer, a drain-source voltage and a drain current of each switching element.

FIG. 4 is a table showing ON / OFF states of respective switching elements in one cycle of a primary side voltage waveform of the transformer in FIG. 3;

FIG. 5 is a circuit diagram showing a DC-DC converter according to another embodiment of the present invention, in which a conversion circuit section has a half-bridge configuration.

FIG. 6 is a circuit diagram showing a DC-DC converter according to another embodiment of the present invention in which two groups of conversion circuit units are connected in parallel to a DC power supply.

FIG. 7 is a circuit diagram showing a conventional example of a DC-DC converter.

8 is a timing chart of a gate signal for turning on / off each switching element of the DC-DC converter of FIG. 7;

9 is a waveform diagram of a drain-source voltage and a drain current of each switching element of FIG.

10A is a schematic diagram showing waveforms of a drain-source voltage and a drain current of the switching element shown in FIG. 9, and FIG. 10B is a schematic diagram showing switching loss and conduction loss at turn-on and turn-off. It is.

[Explanation of symbols]

11,12 converter circuit unit 21, 22 a rectifier circuit portion C _1, C ₂ series capacitor E DC power source Tr _1, Tr ₂ trans _{Q 1 ~Q 4, Q 5 ~Q} 8 switching element

Claims (4)

[Claims] 1. A DC-DC converter having a rectifier circuit section via a transformer on the output side of a conversion circuit section for converting a power supply voltage of a DC power supply into an alternating current, wherein two pairs of switching elements are connected in a full bridge configuration. Conversion circuit sections are provided in n groups for the DC power supply, a series capacitor is inserted and connected between each of the conversion circuit sections and the transformer, and one of the switching elements forming a pair in each of the conversion circuit sections is connected to one of the switching elements. A DC-DC converter characterized in that the switching phase of the other switching element is shifted by 1 / 3n cycle, and the switching phase of the corresponding switching element is shifted by 1 / 2n cycle between the conversion circuit sections. 2. The switching element is a MOS-FET.
The DC-DC converter according to claim 1, wherein n groups of conversion circuit units are connected in series to a DC power supply. 3. The conversion circuit section according to claim 1, wherein one of the switching elements forming a pair in each of the conversion circuit sections is replaced with a capacitor, so that each conversion circuit section has a half-bridge configuration. DC described
-DC converter. 4. The DC-DC converter according to claim 1, wherein the n groups of conversion circuit units are connected in parallel to a DC power supply.