JP2002208638A - Method and system of information processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a system of information processing which enable shortening of the time necessary for reconfiguring a programmable logical circuit and processing effectively. SOLUTION: Circuit information is stored, which contains a first information for constituting a circuit to reconfigure onto a programmable logical circuit 24, having plural logical blocks that are placed in matrix, and a second information for constituting a circuit which is not reconfigured. Based on the circuit information, the circuit corresponding to the first circuit information consists altogether in a column region that is made of more than one logical block columns (a region, depending on the change of the function 51) or in a row region that is made of more than one logical block rows of the programmable logical circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing method and system, and more particularly to an information processing method and system that efficiently uses a programmable logic circuit.

[0002]

2. Description of the Related Art In the field of digital circuit devices, programmable logic circuits such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) are used as prototype devices before producing application-specific integrated circuits (ASICs). Alternatively, it is widely used as an alternative device of the ASIC which requires a long manufacturing period of several weeks to several months.

Recently, programmable logic circuits have been used in order to make it possible to change specifications, correct circuit defects, etc., even after a circuit device is created, taking advantage of the feature of programmable logic circuits that can change the circuit configuration. ing.

[0004] Recently, logic circuits have increased in complexity, and the circuit scale has increased to a level that cannot be realized by a single programmable logic circuit. As one technique for solving this problem, a technique of reconfiguring a programmable logic circuit during processing in order to realize different logic circuits at different times has been proposed. By applying this technology, since the device is small, such as a portable information terminal, various processes can be performed at a relatively high speed even when the size of a circuit that can be incorporated is limited. I have.

However, this technique has a problem that it takes a long time to reconfigure the logic circuit because it is necessary to read the circuit information of the entire circuit again. Furthermore, in order to reconfigure the logic circuit in the middle of the process, the process is temporarily suspended, the data at that time is saved in a storage device outside the programmable logic circuit, new circuit information is read, and the logic circuit is reconfigured. After the configuration, extra processing is required, such as inputting data before reconstruction and new data accompanying the reconstruction.

To solve this problem, a programmable logic circuit described in a data book named “CONFIGURABLE LPGIC” by Atmel Corporation of the United States and a data book named “THE PROGRAMMABLE LOGIC” named by Xilinx Corporation of the United States are disclosed. In the described programmable logic circuit, a data storage device for storing data is provided, and part of the circuit information is read from an external storage device during operation of the circuit to partially reconfigure the logic circuit. Thus, the time required for reconfiguration is kept to a minimum.

[0007] By using such a programmable logic circuit, a large-scale processing circuit is time-divided, and processing is performed while reconfiguring to a small-sized programmable logic circuit, thereby realizing a circuit larger than the circuit scale. As a result, the size and cost of the circuit device can be reduced.

However, even in a programmable logic circuit that can be partially reconfigured during operation, the circuit reconfiguration time in the entire process becomes longer depending on the scale and frequency of write of the circuit information to be written, and the processing performance deteriorates. There was a point.

As an example of a method for solving this problem, there is a circuit design technique called "skeleton circuit technique".
The “skeleton circuit” is a common part of a circuit configured earlier and a circuit configured later when reconfiguring a programmable logic circuit. That is, a skeleton circuit is first configured on a programmable logic circuit, and a difference circuit is configured for this skeleton circuit from a circuit to be configured next, thereby forming a new circuit with minimum circuit information. Thus, the time required for reconfiguring the circuit can be reduced.

One example of skeleton circuit technology is FCC.
M'96's "Assessing Document Relevance with Run-time"
Reconfigurable Machines ".

[0011]

However, in the skeleton circuit technology described above, when the difference circuits are two-dimensionally scattered on the programmable logic circuit, the time required for the reconfiguration of the logic circuit becomes long. There was a point.

In general, a circuit reconfiguration unit in a programmable logic circuit is a column unit or a row unit. When a difference circuit is two-dimensionally scattered on the programmable logic circuit, the circuit reconfiguration unit is not included in the unit. As a result, the ratio of logic cells whose circuits are changed decreases, and the number of reconfiguration units increases. Therefore, the time required for the reconfiguration of the logic circuit increases.

For example, in the Xilinx Virtex series FPGA, logic cells (CLB: Co
In the nfigurable Logic Block), since logic cells are collectively reconfigured in units of columns (columns), if logic cells to be reconfigured in units of columns are concentrated, circuit reconfiguration can be performed in units of less circuit information and reconfiguration Although it is possible to reduce the time, when the difference circuits are two-dimensionally scattered on the programmable logic circuit, the ratio of the logic cells that change the circuit in the circuit reconfiguration unit decreases, and Since the number of reconstruction units increases, the reconstruction time increases.

An object of the present invention is to provide an information processing method and system capable of shortening the time required for reconfiguring a programmable logic circuit and performing efficient processing.

[0015]

In order to achieve the above-mentioned object, a first aspect of the present invention is to provide a circuit for reconfiguring on a programmable logic circuit having a plurality of logic blocks arranged in a matrix. Circuit information including first information and second information for configuring a circuit that is not to be reconfigured, and a circuit corresponding to the first information is programmed based on the stored circuit information. A circuit corresponding to the second information and a circuit corresponding to the second information are collectively formed in a column area formed by one or more logic block columns or a row area formed by one or more logic block rows. Is formed in a region adjacent to a circuit corresponding to

According to a second aspect of the present invention, in the first aspect of the invention, the stored plurality of pieces of circuit information are collectively rearranged in a specific column area or a specific row area in descending order of reuse frequency. It is characterized by the following.

According to a third aspect of the present invention, there is provided a programmable logic circuit having a plurality of logic blocks arranged in a matrix, and first information for configuring a circuit to be reconfigured on the programmable logic circuit. A storage unit that stores circuit information including second information for configuring a circuit that is not reconfigured; and a circuit corresponding to the first information, based on the circuit information stored in the storage unit. The circuit corresponding to the second information is configured to be collectively configured in a column area formed of one or more logic block columns or a row area formed of one or more logic block rows of the programmable logic circuit, and And a configuration unit configured in a region adjacent to a circuit corresponding to information.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the plurality of circuit information stored in the storage means are arranged in a specific column area or a specific row area in descending order of frequency of reuse. The method further comprises a rearrangement method for performing rearrangement.

According to a fifth aspect of the present invention, in the third aspect of the present invention, the constituent means stores a circuit corresponding to the first information of each of the plurality of circuit information stored in the storage means in the column area. When the circuits are collectively configured, the constituent circuits are configured in the same column area, and the circuits corresponding to the first information of each of the plurality of circuit information stored in the storage unit are integrated in the row area. In this case, the constituent circuits are configured in the same row area.

According to a sixth aspect of the present invention, in the third aspect of the present invention, the storage means is connected to the programmable logic circuit and the constituent means via a network.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an information processing method and apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of an information processing system to which the present invention is applied. As shown in FIG. 1, the information processing system 10 includes a CPU (Central Processing Unit) 11 that controls the entire information processing system 10, a chip set 12 having functions such as a memory controller and a bus bridge, an application program, A main memory 13 composed of a DRAM (Dynamic Random Access Memory) used as a work area when executing various control programs and the like, a hard disk drive 22 for storing application programs, circuit module information, and the like, a programmable logic circuit 24 It comprises.

A main memory 13 is connected to a host bus 14 of the CPU 11 via a memory controller included in the chipset 12. The CPU 11 is connected to a PCI bus 15 via a chipset 12.

A hard disk drive 22 and a programmable logic circuit 24 are connected to the PCI bus 15 via a hard disk interface 21 and a programmable logic circuit interface 23, respectively.

The PCI bus 15 is connected to a storage device 31.
a, 31b, 31c, etc., are connected via a communication interface 25 to a network 30 to which they are connected.

Accordingly, the CPU 11
4. Through the chipset 12, the PCI bus 15, and the communication interface 25, various types of information can be exchanged with various devices such as the storage devices 31a, 31b, and 31c connected to the network 30.

FIG. 2 is a diagram showing a plan structure of the programmable logic circuit 24, and FIG. 3 is a block diagram showing an internal structure of the programmable logic circuit 24.

As shown in FIGS. 2 and 3, the programmable logic circuit 24 includes a configuration memory 44 (not shown in FIG. 2) for storing circuit module information, logic cells 40 arranged in a matrix, and wiring areas. It comprises a circuit element 43 composed of 41 and the like and an input / output terminal 42. Note that, in FIGS. 2 and 3, reference numerals are partially omitted.

The configuration memory 44 stores E
EPROM (Electrically Erasable and Progurammabl)
e Read Only Memory), SRAM (Static Random Acce
ss Memory).

On the other hand, the circuit module information is composed of a plurality of circuit information composed of pairs of addresses and data. When the above address is given to the configuration memory 44 of the programmable logic circuit 24 and the data paired with the address is stored in the memory cell corresponding to the address, the circuit configuration in the logic cell 40 is determined according to the data. Or the logic cell 40 and the input / output terminal 42
Are connected to each other, the connection state of the wiring region 41 is reconfigured.

The unit of circuit reconfiguration of the programmable logic circuit 24 is one unit of reconfiguration circuit information in units of logic cells arranged in the column direction among the logic cells 40 arranged two-dimensionally. By writing the circuit module information to the configuration memory for the columns, the entire surface of the programmable logic circuit 24 can be reconfigured, and the circuit module information can be written to the configuration memory 44 for only some of the columns. so,
Even when the programmable logic circuit 24 is operating, the circuit can be partially reconfigured.

Thus, the programmable logic circuit 2
4, the input / output terminals 42
, Data to be processed is input, and the processing result is output via the input / output terminal 42.

On the other hand, the application program stored in the hard disk drive 22 is loaded into the main memory 13 and then executed by the CPU 11. The above-described circuit module information is called in response to a command in the application program being executed, and is loaded into the configuration memory 44 of the programmable logic circuit 24 as necessary, where hardware processing is performed.

FIG. 4 is a diagram showing the structure of the circuit module information. As shown in the figure, the circuit module information is obtained by comparing the circuit information of the preceding base circuit to be configured in advance in the programmable logic circuit 24 with the difference that can realize various different functions by adding the preceding base circuit. Each of the circuits A, B, and C is configured by circuit information.

Next, the operation of the information processing system 10 will be described with reference to FIG. FIG. 5 is a flowchart showing a flow of processing executed by the CPU 11 when executing an application program stored in the hard disk drive 22.

The following description is based on the premise that circuit module information (see also FIG. 4) for each circuit module used in the application program is stored in a predetermined area of the hard disk drive 22 in advance.

First, circuit module information corresponding to all circuit modules used in the application program is read from the hard disk drive 22 (step 101). Subsequently, in the programmable logic circuit 24 of the difference circuit corresponding to any one of the circuit information of the difference circuit and the preceding base circuit corresponding to the circuit information of the preceding base circuit in each read circuit module information. An arrangement position is derived (step 102).

In this embodiment, as shown in FIG. 6, for each circuit module information, a difference circuit corresponding to any one of the circuit information of the difference circuit is one or more of the programmable logic circuits 24. And the preceding base circuit corresponding to the circuit information of the preceding base circuit is placed in the function change non-dependent area 52 which is an area other than the function change dependent area 51. Deriving the arrangement position. At this time, a plurality of the function change dependent areas 51 in which the respective differential circuits of the respective circuit module information are arranged include the programmable logic circuit 2.
The arrangement positions of the respective circuits are derived so as to be arranged in the same column of four.

Next, the circuit information of the preceding base circuit and the circuit information of any of the difference circuits are output to the programmable logic circuit 24 for each circuit module information in accordance with the derived arrangement position. First, a preceding base circuit indicated by each circuit module information and one of the difference circuits are configured (step 103).

As a result, a plurality (four in the figure) of circuit modules 53 (53a, 53b, 53c, 53d) are arranged on the programmable logic circuit 24 as shown in FIG. Each circuit module 53 is divided into a function change dependent area 51 and a function change non-dependent area 52, and among the circuit elements in each circuit module 53, the circuit element related to the function change (when the function is changed). , Ie, the circuit elements included in the difference circuit) are all arranged in the function-change-dependent hub 51. In this example, the shape of the circuit module 53 is a rectangle, and the function change dependent area 51 is defined as a prescribed column on the left end side of the rectangle. The origin coordinates of each circuit module are defined as the lower left corner of the corresponding rectangular area.

Further, in the example shown in the figure, each circuit module group is divided into two circuit module groups, and each circuit module 53 is arranged such that the function change dependent areas 51 included in each circuit module group are located in the same column. Have been.

The processing executed by the CPU 11 is to determine whether the command to be executed next to the application program being executed is a hardware processing command, that is, a command executed by hardware processing using the programmable logic circuit 24. (Step 10
4) If not a hardware processing command (step 10)
No in step 4), the command is regarded as a software processing command, and the command is executed by software (step 105).

On the other hand, if it is determined in step 104 that the command is a hardware processing command (YES in step 104).
S), it is determined whether or not the processing by the hardware processing command is a processing that requires a change in the processing function of the programmable logic circuit 24 (step 106). If the processing requires a change in the processing function (step 106) And YE
S), by outputting the circuit information of the difference circuit of the circuit module information corresponding to the change of the processing function to the programmable logic circuit 24, the circuit of the corresponding function change dependent area 51 is reconfigured (Step 107). Step 1
In step 06, when it is determined that the processing by the hardware processing command does not need to change the processing function of the programmable logic circuit 24 (N in step 106)
O), the processing of step 107 is not executed.

Thereafter, data to be processed is output to the programmable logic circuit 24 via the input / output terminal 42 (step 108). Then, the programmable logic circuit 24
Performs processing by a circuit configured in the programmable logic circuit 24 on input data to be processed,
The data thus obtained is output via the input / output terminal 42.

Therefore, in the processing by the CPU 11, input of data output from the programmable logic circuit 24 is waited for (NO in step 109), and when data is input (YES in step 109), all of the application programs concerned are processed. It is determined whether the processing of the command has been completed (step 110). As a result, if all commands have not been completed (N in step 110)
O), returning to step 104 and repeating the same processing.
Then, when all commands are completed (step 1
10 (YES), this process ends.

Next, with reference to FIG. 7, a description will be given of the process of rearranging circuit modules. FIG. 7 is a flowchart illustrating the flow of the circuit module relocation processing.

A plurality of circuit modules 53 formed on the programmable logic circuit 24 are given unique module names, and the CPU 11 monitors the frequency of use of the used circuit modules. Then, each time the application program uses the circuit module 53 of the programmable logic circuit 24, the frequency is accumulated in a usage frequency table generated by the CPU 11 as shown in FIG. 8 (step 201).

After a predetermined time has elapsed, the circuit module names are sorted in descending order of frequency based on the use frequency table (step 202).

Next, based on the result of the sorting, the addresses of the circuit modules 53 are recalculated in descending order of frequency (step 203). At this time, the function change dependent area 51
Are arranged in the same column, and the address is recalculated so that the address is shifted in the row direction.

Therefore, it is determined whether or not the circuit modules 53 can be arranged in the same column (step 204). If the circuit modules 53 can be arranged (YES in step 204), the calculated address of the circuit module 53 is determined as a new address. (Step 205).

On the other hand, when it is determined that it is not possible to arrange in the same column (NO in step 204), another function change dependent area 51 is newly arranged in another column which does not overlap the circuit module whose new address has already been determined. The new address of the circuit module 53 is determined (step 205).

Then, the circuit module 5 for performing the rearrangement processing
It is determined whether or not there is still 3 (step 207), and if there is any (NO in step 207), step 20 is executed.
4 and the same processing is repeated. If there is no such processing (YES in step 207), all circuit modules 5
The circuit information of No. 3 is updated (step 208), and the rearrangement processing ends.

FIG. 9 shows the rearrangement result when the use frequency table as shown in FIG. 8 is generated for the example shown in FIG.

Next, the configuration procedure of the circuit module 53 for the programmable logic circuit 24 will be described using a specific circuit as an example.

Here, a description will be given of a case where three functions of an adder circuit, a subtractor circuit, and an accumulator, which are conventionally used in various calculations and signal processing, are realized.

FIG. 10 shows an example of the configuration of a circuit having three functions of an addition circuit, a subtraction circuit, and an accumulator.

As shown in the figure, this circuit includes an adder 6
0's and 2's complement generation look-up table (hereinafter, complement LU)
T) 61, 2-input selector 62, latch 6
3, 64, and a selector setting cell 65.

When this circuit is configured as an addition circuit, the complement LUT 61 is set as table data to be output as it is without converting the input signal. The selector setting cell 65 is set so that the input B is output from the selector 62. With this setting, input A and input B
Is input to the adder 60 as it is, and the addition is executed.

When this circuit is configured as a subtraction circuit, the complement LUT 61 is set as table data for always outputting a two's complement for an input signal. The selector setting cell 65 is set so that the input B is output from the selector 62. With this setting, two's complements of the input A and the input B are input to the adder 60, so that the subtraction is executed substantially.

Further, when this circuit is configured as an accumulator, the complement LUT 61 is set as table data to be output as it is without converting the input signal, and the selector 62 is set so that the input from the latch 63 is output from the selector 62. The setting cell 65 is set. With this setting,
When the input A is input, the addition with the past accumulation of the input A is repeated, and the accumulator operation is performed.

FIG. 11 is a diagram showing an example of arrangement when the circuit configuration shown in FIG. 10 is arranged in the programmable logic circuit 24.

In the circuit configuration shown in FIG. 10, two circuit elements to be reconfigured are the complement LUT 61 and the selector setting cell 65. In the example shown in FIG.
Both the UT 61 and the selector setting cell 65 are arranged in one row on the left end, which is the function change dependent area 51 in the circuit area.

In this embodiment, a case has been described where the function change dependent area 51 is an area located at the left end of the rectangular circuit module area. However, the present invention is not limited to this. Alternatively, the circuit module may be configured to have a region located at the right end in the circuit module region, or may be configured to have a region located at the center between the left end and the right end in the circuit module region. In this case, the same effect as in the present embodiment can be obtained.

In this embodiment, a case has been described in which a programmable logic circuit according to the present invention which can change the circuit configuration for each column is applied. However, the present invention is not limited to this. Instead, a mode in which a programmable logic circuit whose circuit configuration can be changed for each row can be applied. In this case,
What is necessary is just to arrange | position so that the circuit corresponding to each of the circuit information of several circuit modules which should be arrange | positioned in a function change dependence area | region may be located in multiple lines in the same row of the said programmable logic circuit. In this case, the same row can be applied to any of the upper and lower ends of the rectangular circuit module and the center row sandwiched between the upper and lower ends. Also in this case, the same effect as that of the present embodiment can be obtained.

In this embodiment, the case where the hard disk drive 22 connected to the PCI bus 15 is applied as the storage means of the present invention has been described.
The present invention is not limited to this. For example, the storage device 31 connected to the network 30 in FIG.
Any of a, 31b, and 31c may be applied as the storage unit of the present invention. In this case, the circuit module information can be obtained from the storage device connected to the network, so that the flexibility of the information processing system 10 is improved.

[0066]

As described above, according to the present invention, the first information and the reconfiguration for configuring a circuit to be reconfigured on a programmable logic circuit having a plurality of logic blocks arranged in a matrix are provided. Circuit information including second information for configuring a circuit not to be stored is stored, and based on this circuit information, a circuit corresponding to the first information is stored in one or more logic block columns of the programmable logic circuit. A column area or a row area composed of one or more logical block rows are collectively configured, and a plurality of pieces of circuit information are reused in a specific column frame area or a specific row area in a descending order of the degree of reuse. Because they are rearranged together, the ratio of logical blocks that change circuits in the circuit reconfiguration unit is improved,
The number of reconfiguration units can be reduced, and the time required to reconfigure a circuit for a programmable logic circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing system to which the present invention has been applied.

FIG. 2 is a diagram showing a planar structure of a programmable logic circuit 24.

FIG. 3 is a block diagram showing an internal structure of the programmable logic circuit 24.

FIG. 4 is a diagram showing a configuration of circuit module information.

FIG. 5 is a block diagram of a CPU 1 when executing an application program stored in a hard disk drive 22;
3 is a flowchart showing a flow of a process executed by Step 1.

FIG. 6 is a conceptual diagram showing an arrangement state of a plurality of circuit modules 53 configured on the programmable logic circuit 24.

FIG. 7 is a flowchart illustrating a flow of a circuit module rearrangement process;

FIG. 8 is a diagram showing a configuration example of a use frequency table.

FIG. 9 shows a result of rearrangement when a use frequency table as shown in FIG. 8 is generated for the example shown in FIG. 6;

FIG. 10 illustrates a configuration example of a circuit having three functions of an addition circuit, a subtraction circuit, and an accumulator.

11 is a diagram showing an arrangement example when the circuit configuration shown in FIG. 10 is arranged in a programmable logic circuit 24;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Information processing system 11 CPU 12 Chipset 13 Main memory 14 Host bus 15 PCI bus 21 Hard disk interface 22 Hard disk drive 23 Programmable logic circuit interface 24 Programmable logic circuit 25 Communication interface 30 Network 31a, 31b, 31c Storage device 40 Logic cell 41 Wiring Area 42 I / O terminal 43 Circuit element 44 Configuration memory 51 Function change dependent area 52 Function change independent area 53, 53a53b, 53c, 53d Circuit module 60 Adder 61 Two's complement generation look-up table (complement LU)
T) 62 Two-input selector 63, 64 Latch 65 Selector setting cell

Claims (6)

[Claims] 1. First information for configuring a circuit to be reconfigured on a programmable logic circuit having a plurality of logic blocks arranged in a matrix, and second information for configuring a circuit not to be reconfigured Based on the stored circuit information, a circuit corresponding to the first information is stored in a column area or at least one column formed by one or more logic block columns of the programmable logic circuit. An information processing method comprising: configuring a circuit corresponding to the second information in an area adjacent to a circuit corresponding to the first information; . 2. The information processing method according to claim 1, wherein the stored plurality of pieces of circuit information are collectively rearranged in a specific column area or a specific row area in descending order of reuse frequency. 3. A programmable logic circuit having a plurality of logic blocks arranged in a matrix, first information for configuring a circuit to be reconfigured on the programmable logic circuit, and a circuit not to be reconfigured. Means for storing circuit information including second information for storing the circuit information corresponding to the first information on the basis of the circuit information stored in the storage means. A circuit corresponding to the second information is arranged adjacent to a circuit corresponding to the first information while being collectively configured in a column area formed of logical block columns or a row area formed of one or more logical block rows. An information processing system comprising: a configuration unit configured in a specified area. 4. The method according to claim 1, further comprising: rearranging the plurality of pieces of circuit information stored in the storage unit in a specific column area or a specific row area in a descending order of reuse frequency. 4. The information processing system according to claim 3, wherein: 5. The information processing apparatus according to claim 1, wherein the configuration unit comprises:
In the case where the circuits corresponding to the above information are collectively configured in the column area, the circuits to be configured are configured in the same column area, and each of the plurality of circuit information stored in the storage unit has a first
4. The information processing system according to claim 3, wherein when a circuit corresponding to the information is configured collectively in the row area, the constituent circuit is configured in the same row area. 6. The storage unit according to claim 3, wherein the storage unit is connected to the programmable logic circuit and the configuration unit via a network.
The information processing system as described.