JP2002026721A - Information processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an information processing unit that can markedly reduce the time until a final processing result is obtained. SOLUTION: Two programmable logic circuits 70A, 70B connected in series are configured, such that one data processing time by the circuit configured in the programmable logic circuit 70A is equal to or greater than a reconfiguration time of a circuit, with respect to the programmable logic circuit 70B connected to the post stage, and the circuit is reconfigured, immediately after the data processing by the configured circuit, with respect to each of the programmable logic circuits 70A, 70B is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus that performs information processing using a plurality of programmable logic circuits.

[0002]

2. Description of the Related Art In the field of digital circuit devices, programmable logic circuits, such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs), are being developed for application specific integrated circuits (AS).
It is widely used as a prototype device for manufacturing an IC (Application Specific Integrated Circuit), or as an alternative to an ASIC that requires a long manufacturing period of several weeks to several months. Recently, programmable logic circuits have been used in order to make it possible to change specifications, correct circuit defects, etc., even after a circuit device is created, taking advantage of the feature of programmable logic circuits that can change the circuit configuration.

Incidentally, there are a skeleton system and a super skeleton system developed from the skeleton system as a technology for forming a functional circuit on a programmable logic circuit. The skeleton method is based on a programmable logic circuit.
This is a method using a skeleton circuit which is a common circuit part of the circuit after the reconfiguration and the circuit before the reconfiguration. As a result, a new circuit can be configured with the small unit of circuit information that is a difference, and the reconfiguration time can be reduced.

[0004] However, the skeleton system does not allow a significant change in function. Therefore, a super skeleton method has been proposed in which the function can be largely changed by changing small circuit information. Super skeleton method
A skeleton circuit to which control lines and circuits are partially added is arranged and wired, and the function can be switched by a slight change such as changing an initial value register used for data input or a signal value of the control line. In addition, as such a super skeleton system, the technology of Japanese Patent Application No. 11-225087 proposed by the present inventors is exemplified.

[0005] However, in such a super skeleton system, a plurality of processes P _i (i =
(1, 2,...)), As shown in FIG. 25, in addition to the processing time tp, function switching (circuit reconfiguration) C _i
Circuit reconfiguration time tc required for (i = 2, 3,...)
, There is a problem that the time until the final processing result is obtained (hereinafter, referred to as “total processing time”) is long.

As a technique that can be applied to solve this problem, there is a technique of performing processing by a programmable logic circuit using a plurality of programmable logic circuits and reconfiguring the circuit of the programmable logic circuit that has completed the processing in parallel. I can analogy.

FIG. 26 shows a configuration example when two programmable logic circuits are used in this technique. As shown in the figure, in this configuration, the first stage (first stage)
Output terminal of the programmable logic circuit 100A is a first-in first-out memory (hereinafter referred to as a “FIFO memory”) 10
2A, the output terminal of the programmable logic circuit 100B is connected to one input terminal of the programmable logic circuit 100B via the FIFO memory 102B.
A, the other input terminal of the two-input multiplexer 104A in which input data to be newly input is input, and the other input terminal of the two-input multiplexer 104B in which one input terminal is connected to the output terminal of the FIFO memory 102A. The output terminal of the multiplexer 104A is connected to the input terminal of the programmable logic circuit 100A. Note that an output terminal of the multiplexer 104B is used as an output terminal from which a final processing result in this configuration is output.

The operation of the configuration shown in FIG. 26 will be described below with reference to FIGS. 27 and 28. FIG. 27 is a schematic diagram showing the flow of operation in the configuration shown in FIG. 26 for each stage, and FIG. 28 shows the change of each stage at this time on a time axis.
Also, C _i (i = 1, 2,...) In each figure indicates function switching (circuit reconfiguration), and P _i (i = 1, 2,...)
·) Is the processing by the circuit constituted by circuit reconfiguration C _i, labeled with the same subscript, respectively show.

First, a skeleton circuit of each of the programmable logic circuit 100A and the programmable logic circuit 100B is formed in stage 0. In the next stage 1, a certain data string is externally input to the programmable logic circuit 100A via the multiplexer 104A, so that the data string is input to the programmable logic circuit 100A.
Executes the processing P ₁ at A, the process P ₁ is completed Stage 2
Move to Incidentally, a result processed by the processing P ₁ is accumulated sequentially FIFO memory 102A, and is output to the programmable logic circuit 100B When the process P ₁ has been completed.

Next, in stage 2, the FIFO memory 1
It executes the processing P ₂ the programmable logic circuit 100B to the input data sequence from 02A, the circuit reconfiguration C ₃ for executing the processes P ₃ at stage 3 perform at the same time the programmable logic circuit 100A. Incidentally, FIFO memory 102 sequentially processing result obtained by the process P ₂
Stored in the B, to be output to the programmable logic circuit 100A via the multiplexer 104A when the process P ₂ has been completed.

Next, in stage 3, the FIFO memory 1
It executes the processing P ₃ in the programmable logic circuit 100A with respect to the input data sequence from 02B, In the programmable logic circuit reconfiguration C ₄ in 100B simultaneously therewith. Hereinafter, similarly, the circuit reconfiguration for the programmable logic circuit 100A and the processing by the reconfigured circuit,
A series of processing is performed by repeating circuit reconfiguration of the programmable logic circuit 100B and processing by the reconfigured circuit, and the final processing result is output to the outside via the multiplexer 104B.

As described above, by performing the processing of the data string and the circuit reconfiguration in parallel, the circuit reconfiguration time tc
(See also FIG. 25), the overall processing time can be reduced.

[0013]

However, in the technique for performing the processing by the programmable logic circuit using a plurality of programmable logic circuits and the reconfiguration of the circuit of the programmable logic circuit after the processing is completed in parallel using the plurality of programmable logic circuits as described above, Although it is possible to avoid the influence of the time required for circuit reconfiguration as described above, since processing is performed on a certain data string and all of the processing results are written to the FIFO memory, the process proceeds to the next stage. There is a problem that the total processing time is equal to or longer than the cumulative time of the processing time tp of all the processing performed in each programmable logic circuit, and the total processing time cannot be sufficiently reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to provide an information processing apparatus capable of greatly shortening the time until a final processing result is obtained. I do.

[0015]

According to another aspect of the present invention, there is provided an information processing apparatus comprising: a plurality of programmable logic circuits connected in series, each of which includes a programmable logic circuit other than the last stage; A plurality of programmable logic circuits configured such that one data processing time by the selected circuit is equal to or longer than a circuit reconfiguration time for a programmable logic circuit connected to a subsequent stage, and output data of a final stage programmable logic circuit. Means for storing at least until the reconfiguration of the circuit for the first-stage programmable logic circuit is completed, and the output data of the last-stage programmable logic circuit and the first-stage programmable logic circuit stored in the storage means. Selecting any of the new input data to be input to the first stage programmable logic circuit And a, a selection input means for inputting.

According to the information processing apparatus of the first aspect,
When a plurality of programmable logic circuits connected in series have one data processing time by a circuit configured in each programmable logic circuit other than the last stage, the data processing time is longer than the circuit reconfiguration time for the programmable logic circuit connected to the subsequent stage. It is configured as follows. Note that an FPGA, a PLD, or the like can be applied as the programmable logic circuit.

Further, in the present invention, the output data of the last-stage programmable logic circuit is stored by the storage means at least until the reconfiguration of the circuit for the first-stage programmable logic circuit is completed. Here, the storage means includes a RAM (Random Access Memory), an EEPROM (E
lectrically Erasable and Programmable Read OnlyMem
ory), Flash EEPROM (Flash EEPROM)
M) and other rewritable storage elements.

Further, in the present invention, one of the output data of the last-stage programmable logic circuit and the new input data newly inputted to the first-stage programmable logic circuit stored in the storage means is selected by the selection input means. Input to the first-stage programmable logic circuit.

As described above, according to the information processing apparatus of the first aspect, a plurality of serially connected programmable logic circuits are processed once by a circuit configured in each programmable logic circuit other than the last stage. Since the time is set to be equal to or longer than the reconfiguration time of the circuit for the programmable logic circuit connected to the subsequent stage, output data after data processing is output from the programmable logic circuit to the subsequent programmable logic circuit. Before the reconfiguration of the circuit in the subsequent programmable logic circuit can be completed, and the output data can be directly output from the programmable logic circuit to the subsequent programmable logic circuit. Immediately after configuration, processing by the reconfigured circuit can be executed, and final processing results can be obtained. It is possible to significantly reduce the Time to be. Further, in this case, it is not necessary to provide a storage means such as a FIFO memory between the programmable logic circuits, which has been conventionally required, so that the device can be reduced in cost and size.

According to the first aspect of the present invention, as in the second aspect of the present invention, a precedent base circuit to be formed first is previously configured for each of the plurality of programmable logic circuits. Further, it is possible to further comprise a circuit configuration means for reconfiguring the circuit immediately after the data processing by the configured circuit is completed.

According to a second aspect of the present invention, the circuit configuration means according to the third aspect of the present invention comprises a plurality of the plurality of programmable logic circuits each configured on the programmable logic circuit in a time division manner. A common circuit portion that can be configured on the programmable logic circuit as a circuit common to all of the circuits, and a non-exclusive independent that does not share a circuit configuration area with the plurality of circuits and does not share a circuit configuration area on the programmable logic circuit It is preferable that a preceding base circuit including a circuit portion is previously configured, and when the programmable logic circuit is reconfigured, a circuit that is a difference between the preceding base circuit and the reconfigured circuit is configured.

Further, as a storage means according to the present invention, a first-in first-out memory, so-called F
It is preferable to apply an IFO memory.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a configuration of an information processing system 10 according to the present embodiment. As shown in FIG. 1, an information processing system 10 according to the present embodiment includes a CPU (Central Processing Unit) 12 that controls the entire operation of the information processing system 10, and a chip set having functions such as a memory controller and a bus bridge. 14
And a DR used as a work area when executing an application program, various control programs, and the like.
A main memory 16 composed of an AM (Dynamic Random Access Memory) and a hard disk drive 22 for storing application programs, circuit information, and the like.
And a programmable logic circuit unit 26 including two programmable logic circuits.

A main memory 16 is connected to a host bus of the CPU 12 via a memory controller included in the chip set 14. The CPU 12 is connected to a PCI bus 18 via a chipset 14.

A hard disk drive 22 and a programmable logic circuit 26 are connected to the PCI bus 18 via a hard disk interface 20 and a programmable logic circuit interface 24, respectively.

The PCI bus 18 is connected to a storage device 32
A, 32B, 32C, etc. are connected via a communication interface 28 to a network 30 to which they are connected. Therefore, the CPU 12 is provided with a host bus,
Via the PCI bus 18 and the communication interface 28,
Storage devices 32A, 32 connected on the network
Various types of information can be exchanged with various devices such as B and 32C.

On the other hand, as described above, the programmable logic circuit unit 26 according to the present embodiment includes two programmable logic circuits. FIG. 2 shows a plan structure of each programmable logic circuit according to the present embodiment, and FIG. 3 shows a block diagram of an internal structure of each programmable logic circuit according to the present embodiment. As shown in FIGS. 2 and 3, the programmable logic circuit according to this embodiment includes a configuration memory 58 (not shown in FIG. 2) for storing circuit information, a logic cell 50 arranged in a matrix, and a wiring. The input / output terminal 54 includes a circuit element 56 including the region 52 and the like.

The configuration memory 58 according to this embodiment includes an EEPROM and an SRAM (Static Ran).
dom Access Memory).

On the other hand, circuit information is composed of pairs of addresses and data. When the above address is given to the configuration memory 58 of the programmable logic circuit, and data corresponding to the address is stored in a memory cell corresponding to the address, a circuit configuration in the logic cell 50 according to the data, The connection state of the wiring region 52 that connects the logic cell 50 and the input / output terminal 54 to each other is reconfigured.

The unit of the circuit reconfiguration information of the programmable logic circuit according to the present embodiment is one unit of the reconfiguration circuit information in the unit of the logic cells arranged in the column direction among the logic cells 50 arranged two-dimensionally. By writing circuit information to the configuration memory 58 for all columns, the entire surface of the programmable logic circuit can be reconfigured, and the circuit information for only some columns is stored in the configuration memory 58. By writing to 58, the circuit can be partially reconfigured even while the programmable logic circuit is operating.

Data to be processed is input to the circuit element 56 thus reconfigured into the programmable logic circuit via the input / output terminal 54, and the processing result is output via the input / output terminal 54. Is done.

On the other hand, the application program stored in the hard disk drive 22 is loaded into the main memory 16 and then executed by the CPU 12. The above-described circuit information is called in response to a command in the application program being executed, and is loaded into the configuration memory 58 of the programmable logic circuit as necessary, where hardware processing is performed.

In the information processing system 10 according to the present embodiment, a super skeleton method is applied as a technique for forming a functional circuit on a programmable logic circuit.

Next, circuit information according to the present embodiment will be described with reference to FIGS. In addition, FIG.
FIG. 3 is a diagram for explaining the concept of the circuit information forming method according to the present embodiment. FIG. 5 is a diagram showing a configuration example of circuit information formed in the present embodiment. In addition,
In the example shown in FIGS. 4 and 5, a case will be described in which three circuits A, B, and C are sequentially formed into a programmable logic circuit by an application program.

In this case, it is assumed that the three circuits A, B, and C conceptually have a relationship as shown in FIG.

That is, in FIG. 4, the common circuit portion (the portion with the diagonal grid in FIG. 4) is the circuit A,
In B and C, the circuit portion configured as a programmable logic circuit can be used in common. This common circuit portion corresponds to a skeleton circuit portion in the above-described skeleton system.

In FIG. 4, the portions shown with halftone dots are the circuits A, A on the programmable logic circuit.
Although the circuit regions overlap each other in B and C, they are exclusive full overlap portions that should constitute different functional circuit portions.

In FIG. 4, the unpainted portions do not overlap with all of the circuits A, B, and C on the programmable logic circuit, but overlap with any other circuit, and have different functions. This is an exclusive partially overlapping portion to constitute a circuit portion.

In FIG. 4, the hatched portions indicate that each of the circuits A, B, and C has a non-exclusive, non-exclusive, non-exclusive structure formed on a programmable logic circuit without overlapping with other circuits. Part.

In the present embodiment, a portion composed of the common circuit portion and the non-exclusive non-common portion of each of the circuits A, B, and C (that is, a portion with an oblique lattice in FIG. 4) And a hatched portion; this circuit portion will be referred to as a predecessor base circuit in this specification) before the plurality of circuits A, B, and C are reconfigured. A preceding base circuit to be formed on a logic circuit is generated, and its circuit information is first generated. That is, as shown in FIG. 5, the circuit information of the preceding base circuit is first generated.

Next, in the case of this example, as described above, three circuits are formed on the programmable logic circuit in the order of the circuit A, the circuit B, and the circuit C. Therefore, as shown in FIG. Generates circuit information for each of the circuits A, B, and C,
Each of the circuit information of these circuits A, B, and C is generated as information of a circuit portion corresponding to a difference between each of the circuits A, B, and C and the preceding base circuit.

In this case, the circuit information of each of the circuits A, B, and C is obtained by partially excluding a circuit portion composed of an exclusive partially overlapping portion that is not painted and an exclusive full overlapping portion in FIG. It will be reconfigured. That is, in the case of this example, each of the circuit information of the circuits A, B, and C includes an exclusive partial overlap portion and an exclusive full overlap portion of the circuits A, B, and C, respectively. Is used as circuit information for partially reconfiguring.

Using the circuit information thus formed,
The procedure for reconfiguring the functional circuits necessary for the processing in the programmable logic circuit and performing the actual processing is as follows.

First, prior to the processing, the CPU 12 reads the circuit information of the preceding base circuit from the hard disk drive 22, and configures the preceding base circuit on a programmable logic circuit.

Then, it waits for a circuit selection instruction from the application program. When the circuit selection instruction is issued, the selected circuit is recognized, and the selected circuit information (the difference from the preceding base circuit is obtained from the preceding base circuit) from the hard disk drive 22. The necessary circuit is generated on the programmable logic circuit by reading the circuit information) and partially reconfiguring the programmable logic circuit based on the circuit information.

In the case of this example, the circuit information of the circuit A is first specified, and the circuit information is used to generate the circuit A in addition to the preceding base circuit already configured on the programmable logic circuit. A partial reconfiguration of a circuit part necessary for the above is performed, and a circuit A is generated on the programmable logic circuit.

When a necessary functional circuit is formed on a programmable logic circuit, processing by the functional circuit is executed. Thereafter, it is determined whether or not all processing by the application program has been completed, and the necessary functional circuits are sequentially determined in the same manner as described above until the processing is completed, based on the preceding circuit information for the generation thereof. In addition to the circuit, it is generated on the programmable logic circuit by partially reconfiguring, and the processing of executing the processing by the generated functional circuit is repeatedly performed, and when it is determined that all the processing by the application program is completed, The above processing ends.

As described above, in the super skeleton system, a plurality of functional circuits can be realized on a programmable logic circuit by merely reconfiguring a small circuit portion without changing the preceding base circuit. High-speed configuration becomes possible.

Next, the configuration of the programmable logic circuit unit 26 according to the present embodiment will be described with reference to FIG. As shown in the figure, the programmable logic circuit unit 26 according to the present embodiment includes a programmable logic circuit 70A.
And a programmable logic circuit 70B. The programmable logic circuit 70A includes a two-input multiplexer 74A and an abacus-type adder / subtractor / multiplier / divider 80A described later as a preceding base circuit. The abacus type adder / subtractor / multiplier / divider 80B, the FIFO memory 72, and the multiplexer 74B are configured as a preceding base circuit.

The output terminal of the abacus-type adder / subtractor / divider 80A is directly connected to the input terminal of the abacus-type adder / subtractor / divider 80B, and the output terminal of the abacus-type adder / subtractor / divider 80B is F
A multiplexer 74A in which input data (Pin here) to be newly input to the abacus-type addition / subtraction / multiplication / divider 80A is input to one input terminal via the IFO memory 72.
Is connected to the other input terminal of a multiplexer 74B in which the output terminal of an abacus-type adder / subtractor / multiplier / divider 80A is connected to one input terminal. The output terminal of the multiplexer 74A is connected to an abacus-type adder / subtractor. It is connected to the input terminal of the multiplier / divider 80A. The output terminal of the multiplexer 74B is connected to the programmable logic circuit 2
6 is used as an output terminal from which the final processing result is output.

On the other hand, FIG. 7 shows a configuration of a preceding base circuit of the abacus-type addition / subtraction / multiplication / divider 80A and the abacus-type addition / subtraction / multiplication / divider 80B. Hereinafter, the configuration of the abacus-type addition / subtraction / multiplication / divider 80A will be described.

As shown in the figure, the preceding base circuit of the abacus-type adder / subtractor / multiplier / divider 80A includes four input units of an X input unit 82, a Y input unit 84, a Cin input unit 86, and a Pin input unit 88; One output unit of the output unit 90, an operation circuit unit 92 composed of operation cells, and a CLA (Carry Look Ah) for processing carry in addition / subtraction multiplication.
(add: carry look-ahead method), a divider final-stage circuit 96 for performing division, a multiplexer 97 for selecting addition / subtraction multiplication or division, and switching control of logic cells of the multiplexer 97 and the arithmetic circuit unit 92. And a control line 98 for performing the operation. FIG. 7 shows a preceding base circuit when the number of operation bits is generalized as n, where n is an even number.

The configuration of each of the four input units 82, 84, 86, 88 in bit units is basically the same. However, in the case of this example, as described later, the Cin input unit 86 is different from the other input units in the inversion process for subtraction.

The configuration of each input unit in bit units includes a register type configured by a flip-flop circuit and a type configured by a switch circuit, and any type is used depending on the application. You can also.

FIG. 8 shows an example of the configuration of a register type input unit in each bit unit. FIG. 8 shows an example of the configuration of the X input unit 82. That is, in the case of this register type, the input unit 40 for each bit comprises a D flip-flop circuit 42, the input bit xi is supplied to the D input terminal, and the input unit bit output xouti is supplied from the Q output terminal. Taken out. Then, the value of the input portion bit output xouti is set by a high-level H or low-level L control signal applied to the preset terminal PR and the clear terminal CL of the D flip-flop circuit 42.

That is, as shown in FIG. 8A, when the control signals applied to the preset terminal PR and the clear terminal CL of the D flip-flop circuit 42 are both at the high level H, the input bit output xouti is the input The bit xi is obtained as it is.

As shown in FIG. 8B, a low level L is applied to the preset terminal PR of the D flip-flop circuit 42.
When the control signal of high level is given to the clear terminal CL, the input part bit output xouti is always "1".

Further, as shown in FIG. 8C, when a high-level H control signal is supplied to the preset terminal PR of the D flip-flop circuit 42 and a low-level L control signal is supplied to the clear terminal CL. , The input part bit output xouti is always “0”. The description of the configuration example of the type configured by the switch circuit is omitted.

When configuring the preceding base circuit, the input unit 40 in bit units of each input unit is connected to each of the input units 40 shown in FIGS.
(C) is set in any one of the states. The state to be set is determined according to the circuit to be configured on the programmable logic circuit next to the preceding base circuit. Since circuit information for configuring the units 82, 84, 86, and 88 is not required, the reconfiguration time can be reduced. In the following description, each input unit 8
2, 84, 86, and 88 will be described as being configured by register types.

As described above, the inversion control circuit is inserted into the Cin input unit 86 for the subtraction operation. The inversion control circuit can be provided either before or after the D flip-flop circuit 45 provided in the input unit 44 in bit units. The example shown in FIG. 9 is an example in the case where it is provided in a stage preceding the D flip-flop circuit 45. That is,
D flip-flop circuit 4 of input unit 44 for each bit unit
5, an inverter 47 and a multiplexer 46
Is provided.

This inversion control circuit includes a multiplexer 46
The switching control is performed by the switching control signal SEL supplied to the input signal Cin, and the switching is performed between the case where the input signal Cin is output with the same polarity and the case where the input signal Cin is output in an inverted state. In FIG. 9, the inverted output is shown by adding an overbar to Cin.

On the other hand, FIG. 10 shows an arithmetic circuit section 92 of the preceding base circuit according to the present embodiment and an adder 94 with a CLA.
FIG. 11 shows the circuit configuration of the S output unit 90, the divider final stage circuit 96, and the multiplexer 97, and FIG. 11 shows the structure of the logic cell 93 in the arithmetic circuit unit 92. FIG. 10 shows the configuration of the arithmetic circuit unit 92 when n = 8. Therefore, the X input unit 82, the Y input unit 84,
Each Cin input unit _{86, x 0 ~x 7, y 0} ~y 7, c
_{Equipped with} a bit unit input unit for 8 bits of _in0 to _cin7.
The in input unit 88 includes a bit unit input unit for 16 bits of _{pin0 to pin15} .

As shown in FIG. 11, each logic cell 93 of the preceding base circuit includes an AND gate 110, a full adder (full adder FA) 111, and a circuit A and a circuit B for a division operation. The multiplexers 112 and 113 output the output of the full adder 111 in the case of addition / subtraction multiplication and the outputs of the circuits A and B in the case of division. The circuit A includes an inverter 114, two AND gates 115 and 116, and an OR gate 117, and the circuit B includes an inverter 118, three AND gates
9, 120, 121 and an OR gate 122.

The multiplexers 112 and 113 are switched by the value of the control line 98, and can perform addition, subtraction, and multiplication when the control line 98 is set to "0". When the value of the control line 98 is set to “1”, division can be performed.

The subscript i assigned to each of the inputs x and y, the carry output c and the partial sum p in FIG.
Represents the digit of the input x to be operated on, and the subscript j is
It indicates the number of calculations performed through the logic cell (corresponding to how many times the logic cell has been input to the logic cell) and the digit of the input y to be operated on.

In the logic cell 93 of FIG. 11, the AND of the input x _i and the input y _i is calculated by the AND gate 110. The AND operation output of the AND gate 110, the carry output c _i ^(j-1) input to the logic cell 93, and the partial sum p _i input to the logic cell 93 are fully added. The adder 111 performs an addition operation. Then, from this full adder 111, a partial sum output p _i ^{(j + 1),} is configured to obtain and carry output c _i ^j.

FIG. 12 shows an equivalent circuit of the logic cell 93 of the arithmetic circuit unit 92 when the abacus-type adder / subtractor / divider 80A is configured as a multiplier, an adder, and a subtractor. FIG. 13 shows an equivalent circuit of the logic cell 93 of the arithmetic circuit unit 92 when the abacus-type addition / subtraction / multiplier / divider 80A is configured as a divider. In the case of a divider, it is necessary to configure a full subtractor to subtract the divisor from the dividend. The full subtractor can be realized by inverting one of the inputs of a portion related to carry (carry) in the full adder. In FIG ^{_{13, b i (j-1}} ) and b _i ^j is meant a borrow.

The carry in the full adder corresponds to a borrow in the full subtractor. The control input of the output multiplexers 112 and 113 (see FIG. 11) is “0”
In this case, a carry is output, and the cell 93 operates as a full adder. In the case of "1", a borrow is output, and the cell 93 operates as a full subtractor.

When the feedback signal cnt from the divider final stage circuit 96 is "0"(dividend> divisor), the result of the subtraction is output. When the feedback signal cnt is "1" (dividend <divisor), the logic cell The input dividend is output as it is without performing the subtraction in 93. 11 and 13, the subscript i of each character represents a digit, and j represents the number of times and digits calculated through the cell.

FIG. 16 shows a divider array when m = 8. In FIG. 16, a portion surrounded by a broken line is the configuration of the divider final stage circuit 96 shown in FIGS.

On the other hand, although not shown, the S output unit 90
Is a configuration of an output buffer register, which is composed of 2n registers, and therefore, in the case of the example of FIG. 10, a register composed of 16 D flip-flop circuits. Then, the S output unit 90 outputs the lower s ₀ to s _{( n-1)} (in the example of FIG. 10,
As s ₀ ~s _7), receives the output bits of each row of the arithmetic circuit 92, also in the example of _{s n ~s (2n-1)} ( FIG. 10 of the upper, as s ₈ ~s _15), the multiplexer 97, and can be output to the outside.

The adder 94 with CLA of the preceding base circuit is configured as shown in FIG. This FIG.
Also corresponds to the case where n = 8. The adder 94 with CLA includes carry outputs c ₇ ′ to c ₁₄ ′ of the last row (row of y ₇ ) of the arithmetic circuit section 92 and a partial sum output s ₈ ′.
Ｓs ₁₄ ′ to calculate the partial sum outputs s _{8 to} s ₁₅ .

As shown in FIG. 14, the adder 9 with CLA 9
4 denotes eight half adders (half adders) 901 to 908
, 12 AND gates 909 to 920, 6 NOR gates 921 to 926, and 6 inverters 927 to 927.
932 and 7 exclusive OR gates 933-
939.

Each of the half adders 901 to 908 is
As shown in FIG. 15, carry output c _(i-1)’And the partial sum
s_iAnd AND gate 941 and EQ
It consists of a exclusive OR gate 942.

In the adder 94 with CLA shown in FIG. 14, a carry signal is propagated using CLA in units of 4 bits as one block, as indicated by a dotted line in FIG. The system carries the carry signal by ripple. Here, half adders 901-908
Input s _i ', c _(i-1)' is when the both "1", the carry signal c _i regardless of the value of the carry signal c from the digit of the lower _(i-1) of each of the two Occurs and the two inputs s _i ′, c
_If either _(i-1) 'is "1", the carry signal c _i is determined by the value of the carry signal c _{(i-1) from} the lower digit. This situation is represented by the following equation.

C _i = g _i + p _i · c _(i−1) (1) where g _i = s _i ′ · c _(i−1) ′ and p _i = s _i ′
[Exor] c _(i-1) . Is a multiplication, and
[Exor] means an exclusive OR operation.

In equation (1), g _i is called a carry generation signal (generator) and p _i is called a carry propagation signal (propagator), but it is functionally exactly equal to the carry and sum of the half adder.

[0078] Using these g _i and p _i, when representing each digit of the carry signal c ₈ to c _{1 4} required in FIG. 14, as the result as shown below, the carry signals of all digits , And the least significant carry signal (here, c ₈ , c ₁₁ ) in the respective adders 94 with CLA.

C ₈ = g ₈ c ₉ = g ₉ + p ₉ · c ₈ = g ₉ + p ₉ · g ₈ c ₁₀ = g ₁₀ + p ₁₀ · c ₉ = g ₁₀ + g ₉ · p ₁₀ + g ₈ · p ₉ · _{p 10 c 11 = g 11 +} p 11 · c 10 = g 11 + g 10 · p 11 + g 9 · p 10 · p 11 + g 8 · p 9
_{· P 10 · p 11 c 12} = g 12 + p 12 · c 11 c 13 = g 13 + p 13 · c 12 = g 13 + g 12 · p 13 + p 12 · p 13 · c 11 c 14 = g 14 + p 14 · _{c 13 = g 14 + g 13} · p 14 + g 12 · p 13 · p 14 + p 12 ·
p ₁₃ · p ₁₄ · c ₁₁ final output s _i as the (in this case s ₈ ~s _15), s ₈
For outputs a p _8. For s ₉ ~s _15, it is output by taking an exclusive OR of the carry propagate signal p _i from the carry signal issued from one lower digit c _(i-1) half adder.

When the abacus-type adder / subtractor / multiplier / divider 80A configured as described above is reconfigured as a multiplication circuit, the X input section 82, the Y input section 84, the Cin input section 86, and the Pin input section of the preceding base circuit are used. 88, the S output unit 90 and the value of each control signal are set as follows based on the circuit information for the multiplication circuit. By the partial reconfiguration based on the circuit information, a multiplication circuit is generated in the programmable logic circuit. Here, the X input unit 82 is the multiplicand, the Y input unit 84 is the multiplier, the S output unit 90 is the product of X and Y, the Pin input unit 88 is the initial value of the partial sum, and the Cin input unit 86 is the carry of the carry. The registers correspond to the initial values. · X input _{unit: x 7 x 6 x 5 x} 4 x 3 x 2 x 1 x 0 · Y _{input: y 7 y 6 y 5 y} 4 y 3 y 2 y 1 y 0 · Cin input: 00000000 · Pin input unit: 00000000 · S output unit _{(product): s 15 s 14 s 13} s 12 s 11 s 10 s 9 s 8 s
_{7 s 6 s 5 s 4 s} 3 s 2 s 1 s 0 · control line 98 values: 0-switching control signal SEL: 0 i.e., X input unit 82 and the Y input unit 84, FIG. 8
As shown in (A), the preset terminal PR and the clear terminal CL are each partially reconfigured to a high level. Also, the Cin input unit 86 and the Pin input unit 88
As shown in (C), the preset terminal PR and the clear terminal CL are partially reconfigured to the high level and the low level, respectively, and are all set to the initial value 0. Furthermore, S output section 90, partially reconfigured to use all s ₀ ~s _{1 5.}

When the abacus-type adder / subtractor / multiplier / divider 80A is reconfigured as an adder circuit, the X input section 82, the Y input section 84, the Cin input section 86, the Pin input section 88, and the S output section 90 and the value of each control signal are set as follows based on the circuit information for the adder circuit. By the partial reconfiguration based on the circuit information, an adder circuit is generated in the programmable logic circuit. · X input _{unit: x 7 x 6 x 5 x} 4 x 3 x 2 x 1 x 0 · Y input: 00000001 · Cin _{input: y 7 y 6 y 5 y} 4 y 3 y 2 y 1 y 0 · Pin input unit: 0000000000000000 · S output section _{(sum): s 8 s 7 s 6} s 5 s 4 s 3 s 2 s 1 s 0 · control line 98 values: 0-switching control signal SEL: 0 Further, abacus type acceleration When the multiplier / divider 80A is reconfigured as a subtraction circuit, the X input unit 82, Y
Input unit 84, Cin input unit 86, Pin input unit 88, S
The output unit 90 and the value of each control signal are set as follows based on the circuit information for the subtraction circuit. Note that “_” (under bar) in the next Cin input unit is y following the “_”.
Means negation. That is, for example, _y ₇ is
It means the negation of y _7. By the partial reconfiguration based on the circuit information, a subtraction circuit is generated in the programmable logic circuit. · X input _{unit: x 7 x 6 x 5 x} 4 x 3 x 2 x 1 x 0 · Y input: 00000001 · Cin _{input: _y 7 _y 6 _y 5 _y} 4 _y 3 _y 2 _y
₁ _y _0-Pin Input unit: 0000000000000001-S output unit _{(difference): s 7 s 6 s 5} s 4 s 3 s 2 s 1 s 0 · control line 98 values: 0-switching control signal SEL: 1 Moreover, When reconfiguring the abacus-type addition / subtraction / multiplier / divider 80A as a division circuit, the X input unit 82, Y
Input unit 84, Cin input unit 86, Pin input unit 88, S
The output unit 90 and the value of each control signal are set as follows based on the circuit information for the division circuit. By the partial reconfiguration based on the circuit information, a division circuit is generated in the programmable logic circuit. X input section: 11111111 Y input section: 0. _{y 1 y 2 y 3 y 4} y 5 y 6 y 7 y 8 · Cin input: 00000000 · Pin Input unit: 0. x ₁ x ₂ x ₃ x ₄ x ₅ x ₆ x ₇ x ₈ x ₉ x
₁₀ x ₁₁ x ₁₂ x ₁₃ x ₁₄ x ₁₅ x ₁₆ S output unit (quotient): 0. s ₁ s ₂ s ₃ s ₄ s ₅ s ₆ s ₇ s ₈ · the value of the control line 98: 1 · the switching control signal SEL: 0 The above is the description of the abacus type addition / subtraction / multiplier / divider 80 A, but the abacus type The addition / subtraction / multiplication / divider 80B is configured similarly to the abacus-type addition / subtraction / multiplication / divider 80A.

The programmable logic circuit 70A and the programmable logic circuit 70B are used as the programmable logic circuit of the present invention, the FIFO memory 72 is used as the storage means of the present invention, the multiplexer 74A is used as the selection input means of the present invention, and the CPU is used.
Reference numerals 12 correspond to the circuit configuration means of the present invention.

Next, the operation of the information processing system 10 according to the present embodiment will be described. First, a general operation flow of the information processing system 10 will be described with reference to FIGS. FIG. 17 shows, for each stage, the configuration of the circuit for the programmable logic circuit unit 26 and the flow of operation when the CPU 12 of the information processing system 10 according to the present embodiment executes processing by the configured circuit. FIG. 18 shows a change of each stage at this time on a time axis. In each figure, C _i (i = 1, 2,...) Indicates function switching (circuit reconfiguration), and P _i (i = 1, 2,...) Indicates circuits with the same subscript. the processing by the circuit formed by the reconstruction C _i, respectively show. Also, here, as described above, the super skeleton method is applied as a technique for configuring a functional circuit on a programmable logic circuit, whereby a single data processing by the circuit configured in the programmable logic circuit 70A is performed. Description will be made on the assumption that the time is longer than the circuit reconfiguration time in the programmable logic circuit 70B.

First, in stage 0, the corresponding preceding base circuit is configured as a skeleton circuit for both the programmable logic circuit 70A and the programmable logic circuit 70B.

In the next stage 1, the processing P ₁ is performed by the abacus-type addition / subtraction / multiplication / division unit 80A of the programmable logic circuit 70A.
Execute Since the circuit reconfiguration C ₂ (the configuration of the preceding base circuit) has been completed in the programmable logic circuit 70B before the first operation result in the process P ₁ is output, the result of the process P ₁ is left as it is. enter the abacus type addition, subtraction, multiplication, and division adder 80B of the programmable logic circuit 70B, it is possible to execute the process P ₂ by abacus type addition, subtraction, multiplication, and division adder 80B. As a result of the process P ₂ are sequentially stored in the FIFO memory 72.

When the process P ₁ is completed in the abacus type addition / subtraction / multiplication / divider 80A of the programmable logic circuit 70A,
In the next stage 2, performed for the programmable logic circuit 70A, the circuit reconfiguration C ₃ for abacus type addition, subtraction, multiplication, and division adder 80A to be able to execute a process P ₃ immediately. By this operation, the abacus-type addition / subtraction / multiplier / divider 80B
By the At the end process P _2, since the circuit reconfiguration C ₃ of the programmable logic circuit 70A is completed, the next stage 3, processing ends at the same time P _2, abacus type addition, subtraction, multiplication, and division adder 80B from the FIFO memory 72 Processing P ₂
The results starts the process P ₃ by abacus type addition, subtraction, multiplication, and division adder 80A by outputting the abacus type addition, subtraction, multiplication, and division adder 80A, performs circuit reconfiguration C ₄ for the programmable logic circuit 70B.

As a result, the circuit reconfiguration C ₄ is completed in the programmable logic circuit 70 B before the first operation result of the process P ₃ is output from the abacus-type adder / subtractor / multiplier / divider 80 A as described above. , enter the result of the process P ₃ directly to the programmable logic circuit 70B, process P ₄
Can be performed.

Hereinafter, similarly, the programmable logic circuit 7
A series of processing is performed by repeating the circuit reconfiguration and the processing by the reconfigured circuit for 0A and the processing by the circuit reconfiguration and the reconfigured circuit for the programmable logic circuit 70B, and the final processing result is output to the multiplexer 74B. Output to the outside through

Thus, the processing P _i (i = 1, 2,...)
・) Can be performed in parallel, so that the total processing time can be greatly reduced.

Next, referring to FIGS. 19 to 22, multiplication processing is performed by an abacus-type addition / subtraction / multiplication / division unit 80A, and then addition processing is performed by an abacus-type addition / subtraction / multiplication / division unit 80B. The operation flow when the subtraction process is performed by the circuit 80A, that is, the flow of the operation when the programmable logic circuit unit 26 performs the calculation process of 'X × Y + AB' will be specifically described. Here, as an example, 8 bits × 8 bits + 16
A case of performing a calculation process of bit-8 bits will be described.

First, a multiplication circuit is used as the abacus-type adder / subtractor / divider 80A of the programmable logic circuit 70A, and the abacus-type adder / subtractor / divider 80 of the programmable logic circuit 70B is used.
In order to configure an adder circuit as B, various registers and control lines of each of the abacus-type add / subtract multiplier / divider 80A and the abacus-type add / subtract multiplier / divider 80B are set as follows based on circuit information. · Pin Input unit: 000000000000000 & abacus type addition, subtraction, multiplication, and division adder input registers 80A; X _{input: x 7 x 6 x 5 x} 4 x 3 x 2 x 1 x 0 Y _{input: y 7 y 6 y 5 y} 4 _{y 3 y 2 y 1 y 0} Cin input: output register 00000000-abacus type addition, subtraction, multiplication, and division adder 80A; S output _{unit: s 15 s 14 s 13 s} 12 s 11 s 10 s 9 s 8 s 7 s 6 s _Five
s input registers _{4 s 3 s 2 s 1 s} 0 · abacus type addition, subtraction, multiplication, and division adder 80B; X input _{unit: a 7 a 6 a 5 a} 4 a 3 a 2 a 1 a 0 Y input: 00000001 Cin input unit : 00000000 & abacus type addition, subtraction, multiplication, and division output register adder 80B; S output _{unit: s 15 s 14 s 13 s} 12 s 11 s 10 s 9 s 8 s 7 s 6 s 5
s ₄ s ₃ s ₂ s ₁ s ₀ control line; input control line for multiplexer 74A set to 1 output control line for multiplexer 74B set to 1 control line 98: 0 for abacus-type adder / subtractor / divider 80A set to abacus Set the control line 98: 0 of the type adder / subtractor / divider 80B to the switching control signal SE of the abacus type adder / subtractor / divider 80A
L: set to 0. Switching control signal SE for abacus-type addition, subtraction, multiplication, and division divider 80B.
FIG. 19 shows the circuit configurations of the multiplication circuit and the addition circuit realized by the above setting, and the data flow of the multiplication processing part.

In the figure, first, a multiplication process of (X × Y) is performed by an abacus-type adder / subtractor / divider 80A, whereby a multiplication result R1 is output to an output terminal of the abacus-type adder / subtractor / divider 80A. The data string of R1 is directly input to the abacus-type addition, subtraction, multiplication, and division divider 80B, and added (R
1 + A) is performed.

The result R2 of the addition processing (R1 + A) is the FIF
Immediately after the data is written into the O memory 72 and immediately after the entire data string of the result R1 is output in the abacus-type adder / subtractor / divider 80A, the registers and control lines of the abacus-type adder / subtractor / divider 80A are changed according to the circuit information as follows. , The subtraction circuit is reconfigured for the abacus-type addition / subtraction / multiplication / divider 80A. · Input register abacus type addition, subtraction, multiplication, and division adder 80A; X input _{section: b 7 b 6 b 5 b} 4 b 3 b 2 b 1 b 0 Y input: 00000001 Cin input: 00000001, control lines; input to the multiplexer 74A Control line: set to 0 Switching control signal SE for abacus-type addition / subtraction / multiplier / divider 80A
FIG. 20 shows the circuit reconfiguration of the subtraction circuit realized by the above setting, and the flow of data written to the FIFO memory 72 after the addition processing.

In FIG. 20, since the subtraction circuit is reconfigured before the first result of the addition processing (R1 + A) is output, the result R2 of the addition processing is directly subtracted by the subtraction circuit (the abacus-type addition / subtraction / division unit 80A). And subtraction processing (R2-
B) can be performed. FIG. 21 shows the flow of data in the subtraction processing portion.

After this subtraction processing, the calculation result R of (X × Y + AB) is output via the multiplexer 74B of the output section.
3 is output. Note that FIG.
3 shows the flow of data output via B.

As described in detail above, in the information processing system according to the present embodiment, a plurality of (two in this embodiment) programmable logic circuits connected in series are replaced with each programmable logic circuit other than the last stage. Is configured so that one data processing time by the circuit configured as described above is equal to or longer than the circuit reconfiguration time for the programmable logic circuit connected to the subsequent stage, so that the output data after data processing from the programmable logic circuit is output from the programmable logic circuit. Before being output to the subsequent programmable logic circuit, the reconfiguration of the circuit in the subsequent programmable logic circuit can be completed, and the output data can be directly output from the programmable logic circuit to the subsequent programmable logic circuit. Since the output can be performed, the processing by the reconfigured circuit is executed immediately after the circuit is reconfigured. It becomes possible, the final processing result is much time to obtain (about one-half as compared to a technique using a plurality of conventional programmable logic circuit
To).

Further, in the information processing system according to the present embodiment, it is not necessary to provide a storage means such as a FIFO memory between each programmable logic circuit, which is conventionally required, so that the apparatus can be reduced in cost and size. can do.

In the information processing system according to the present embodiment, the CPU reconfigures each of the plurality of programmable logic circuits immediately after the data processing by the configured circuit is completed. Therefore, before the output data after the data processing is output from the programmable logic circuit to the downstream programmable logic circuit, the reconfiguration of the circuit in the downstream programmable logic circuit can be surely completed.

Furthermore, in the information processing system according to the present embodiment, as a technique for configuring a functional circuit on a programmable logic circuit, a plurality of functional circuits can be programmed by reconfiguring only a few circuit portions. Since the super skeleton method that can be realized on the circuit is applied, the reconfiguration time of the circuit for the programmable logic circuit can be shortened relatively to the processing time of the configured circuit, and the programmable logic A stable operation of the circuit section becomes possible.

In this embodiment, in order to reduce the circuit scale, in addition to the abacus-type add / subtract multiplier / divider 80A and the abacus-type add / subtract multiplier / divider 80B, a FIFO memory 72,
Although the case where the multiplexers 74A and 74B are also configured by programmable logic circuits has been described, the present invention is not limited to this.
Only the abacus-type adder / subtractor / multiplier / divider 80A and the abacus-type adder / subtractor / multiplier / divider 80B may be configured by respective programmable logic circuits. In this case, it is necessary to provide the FIFO memory 72, the multiplexer 74A, and the multiplexer 74B separately from the programmable logic circuit, but the total processing time can be reduced as in the present embodiment.

Further, in this embodiment, the case where two programmable logic circuits are connected in series to constitute the programmable logic circuit section 26 has been described. However, the present invention is not limited to this. A configuration in which three or more programmable logic circuits are connected in series may be employed.

FIG. 23 shows a configuration example when three programmable logic circuits are connected in series. As shown in the figure, in this configuration, the output terminal of the first-stage (first-stage) programmable logic circuit 130A is connected to the input terminal of the second-stage programmable logic circuit 130B, and the output terminal of the programmable logic circuit 130B is The input data to be newly input to the programmable logic circuit 130A is connected to the input terminal of the programmable logic circuit 130C of the second stage (final stage), and the output terminal of the programmable logic circuit 130C is connected to one input terminal of the programmable logic circuit 130A via the FIFO memory 132. Is input to the other input terminal of the two-input multiplexer 134A and the two input terminals are respectively connected to the programmable logic circuit 130A and the programmable logic circuit 130B.
-Input multiplexer 134 to which the output terminals of
B and the output terminal of the multiplexer 134A is connected to the programmable logic circuit 1
It is connected to the input terminal of 30A. Note that the output terminal of the multiplexer 134B is used as an output terminal from which the final processing result in this configuration is output.

The programmable logic circuits 130A to 130C correspond to the programmable logic circuit of the present invention, the FIFO memory 132 corresponds to the storage means of the present invention, and the multiplexer 134A corresponds to the selection input means of the present invention.

The operation of the configuration shown in FIG. 23 will be described below with reference to FIG. Note that FIG.
Shows the flow of operation in the configuration shown in FIG. 23 on the time axis for each stage. In the same figure, C _i (i = 1, 2,...) Indicates function switching (circuit reconfiguration), and P _i (i = 1, 2,...) Indicates circuits with the same subscript. the processing by the circuit formed by the reconstruction C _i, respectively show.

First, in stage 0, each preceding base circuit of the programmable logic circuit 130A, the programmable logic circuit 130B, and the programmable logic circuit 130C is configured as a skeleton circuit.

[0106] In the next stage 1, it executes the processing P ₁ in the programmable logic circuit 130A. Here, before the first operation result of the process P ₁ comes, because the programmable logic circuit reconfiguration C ₂ in 130B is completed, the process P ₁ results directly programmable logic circuit 130B
Type can execute the process P ₂ by a programmable logic circuit 130B to. Then, before the first operation result of the process P ₂ exits, programmable logic circuits 130
Since the circuit reconfiguration C ₃ in C has been completed, it is possible to execute the process P ₃ by a programmable logic circuit 130C by entering the result of the process P ₂ directly to the programmable logic circuit 130C. It should be noted that, as a result of the process P ₃ is FIFO
The information is sequentially stored in the memory 132.

[0107] When the process P ₁ in a programmable logic circuit 130A is finished, in the next stage 2, the circuit reconfiguration C ₄ to enable the execution processing P ₄ by a programmable logic circuit 130A immediately. At the end of the process P ₃ by a programmable logic circuit 130C by this operation so that circuit reconfiguration C ₄ of the programmable logic circuit 130A is completed.

[0108] The processing when P ₂ is completed in a programmable logic circuit 130B, performs the next stage 3, the circuit reconfiguration C ₅ to be able to run the process P ₅ by a programmable logic circuit 130B immediately.
This operation will be a programmable logic circuit 130B circuit reconfiguration C ₅ of the time output the first result of processing P ₁ by a programmable logic circuit 130A is completed.

The programmable logic circuit 130C
When the processing P ₃ is completed in the next stage 4,
It ends at the same time process P _3, the programmable logic circuit 13
A process P ₄ by 0A, programmable logic circuits 130
A circuit reconfiguration C ₆ for C is performed.

Hereinafter, similarly, the programmable logic circuit 1
30A, the programmable logic circuit 130B, and the programmable logic circuit 130C, a series of processes are performed by repeating circuit reconfiguration and processing by the reconfigured circuit, and the final processing result is output to the multiplexer 134.
It is output to the outside via B.

Therefore, in this case, since the processes can be performed in parallel by the number of programmable logic circuits, the total processing time can be further reduced as compared with the present embodiment.

Further, in this embodiment, the case where the super skeleton system is applied as a technique for forming a functional circuit on a programmable logic circuit has been described, but the present invention is not limited to this. In a plurality of programmable logic circuits connected in series, one data processing time by a circuit constituted by each programmable logic circuit other than the last stage is equal to or longer than a reconfiguration time of a circuit in a programmable logic circuit connected to a subsequent stage of the programmable logic circuit If the condition that
Any technique can be applied. For example, a mode in which a skeleton method that satisfies the above conditions can be applied. In this case, the same effect as in the present embodiment can be obtained.

Further, in this embodiment, the case where the FIFO memory is applied as the storage means of the present invention has been described. However, the present invention is not limited to this, and any memory can be used as long as it is a writable memory. Can be applied.

[0114]

As described above in detail, according to the information processing apparatus according to the present invention, a plurality of programmable logic circuits connected in series can be divided into one by a circuit constituted by each programmable logic circuit other than the last stage. Data processing time is longer than the circuit reconfiguration time for the programmable logic circuit connected to the subsequent stage.
Before the output data after the data processing from the programmable logic circuit is output to the subsequent programmable logic circuit, it is possible to finish the reconfiguration of the circuit in the subsequent programmable logic circuit, and Since output data can be directly output to the programmable logic circuit, processing by the reconfigured circuit can be executed immediately after circuit reconfiguration, and the processing until the final processing result is obtained The advantage is that the time can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing system according to an embodiment.

FIG. 2 is a plan view showing a planar structure of the programmable logic circuit according to the embodiment;

FIG. 3 is a block diagram illustrating an internal structure of the programmable logic circuit according to the embodiment;

FIG. 4 is a schematic diagram for explaining a method for reconfiguring the programmable logic circuit according to the embodiment;

FIG. 5 is a schematic diagram illustrating a configuration example of circuit information according to the embodiment;

FIG. 6 is a block diagram illustrating a configuration of a programmable logic circuit unit according to an embodiment.

FIG. 7 is a block diagram showing a configuration of a preceding base circuit of the programmable logic circuit according to the embodiment;

8 is a circuit diagram showing an example of a circuit configuration of a part of the preceding base circuit shown in FIG. 7;

9 is a circuit diagram illustrating a circuit configuration example of a part of the preceding base circuit of FIG. 7;

10 is a block diagram illustrating a specific configuration example centering on an arithmetic circuit unit of the preceding base circuit of FIG. 7;

11 is a circuit diagram illustrating a configuration example of a logic cell of the preceding base circuit of FIG. 7;

FIG. 12 is a circuit diagram illustrating an equivalent circuit of a logic cell in an arithmetic circuit unit when the programmable logic circuit according to the embodiment is configured as a multiplier, an adder, and a subtractor.

FIG. 13 is a circuit diagram showing an equivalent circuit of a logic cell of an arithmetic circuit unit when the programmable logic circuit according to the embodiment is configured as a divider.

14 is a circuit diagram showing a configuration example of an adder with CLA of the preceding base circuit of FIG. 7;

FIG. 15 is a circuit diagram illustrating a configuration of a half adder used in the preceding base circuit of FIG. 7;

16 is a circuit diagram illustrating a configuration example of an arithmetic circuit unit corresponding to the division processing of the preceding base circuit of FIG. 7;

FIG. 17 shows a CP of the information processing system according to the embodiment.
It is the schematic diagram which showed the flow of operation | movement by U12 for every stage.

FIG. 18 is a schematic diagram when a change of each stage in FIG. 17 is represented on a time axis.

FIG. 19 is a schematic diagram for explaining a data flow in a multiplication process and an addition process of the information processing system according to the embodiment.

20 is a schematic diagram for explaining a flow of data to be written into the FIFO memory after the addition processing in FIG. 19 and a circuit reconfiguration of the subtraction processing.

FIG. 21 is a schematic diagram for explaining a data flow in a subtraction processing portion of the information processing system according to the embodiment.

FIG. 22 is a schematic diagram for explaining a flow of data output via a multiplexer in an output unit of the information processing system according to the embodiment.

FIG. 23 is a block diagram illustrating another configuration example of the programmable logic circuit unit according to the embodiment;

24 is a schematic diagram when a change in each stage in the configuration example shown in FIG. 23 is represented by a time axis.

FIG. 25 is a schematic diagram for explaining a problem of the conventional super skeleton system.

FIG. 26 illustrates the use of a plurality of programmable logic circuits.
FIG. 9 is a block diagram illustrating a configuration example of a technique for performing, in parallel, processing by a programmable logic circuit and reconfiguration of a circuit of the programmable logic circuit that has finished processing;

FIG. 27 is a diagram provided for describing a problem of the related art, and is a schematic diagram illustrating a flow of operation in the configuration shown in FIG. 26 for each stage.

FIG. 28 is a diagram provided for describing a problem of the related art, and is a schematic diagram when a change in each stage in FIG. 27 is represented on a time axis.

[Explanation of symbols]

Reference Signs List 10 information processing system 12 CPU (circuit configuration means) 22 hard disk drive 24 programmable logic circuit section interface 26 programmable logic circuit section 70A, 70B programmable logic circuit 72 FIFO memory (storage means) 74A multiplexer (selection input means) 74B multiplexer 80A, 80B Abacus type adder / subtractor / multiplier / divider 82 X input unit 84 Y input unit 86 Cin input unit 88 Pin input unit 90 S output unit 93 Logic cell 130A, 130B, 130C Programmable logic circuit 132 FIFO memory (storage means) 134A Multiplexer (selection input means) )

Claims (4)

[Claims] 1. A circuit for a plurality of programmable logic circuits connected in series, wherein one data processing time by a circuit configured in each programmable logic circuit other than the last stage is equal to a programmable logic circuit connected to a subsequent stage. A plurality of programmable logic circuits configured so as to be equal to or longer than the reconfiguration time, and storage means for storing output data of the last-stage programmable logic circuit at least until the reconfiguration of the circuit for the first-stage programmable logic circuit is completed Selecting any of the output data of the last-stage programmable logic circuit stored in the storage means and the new input data newly input to the first-stage programmable logic circuit, and inputs the selected data to the first-stage programmable logic circuit. An information processing apparatus comprising: 2. A prior base circuit to be first configured for each of the plurality of programmable logic circuits, and reconfiguration of the circuit immediately after data processing by the configured circuit is completed. 2. The information processing apparatus according to claim 1, further comprising a circuit configuration unit that performs the operation. 3. The circuit configuration means is configured on each of the plurality of programmable logic circuits as a circuit common to all of the plurality of circuits configured on the programmable logic circuit in a time-division manner. A preliminarily configured base circuit including a possible common circuit portion and a non-exclusive independent circuit portion that is not common to the plurality of circuits and does not share a circuit configuration area on the programmable logic circuit, 3. The information processing apparatus according to claim 2, wherein when reconfiguring the programmable logic circuit, a circuit that is a difference between the preceding base circuit and the reconfigured circuit is configured. 4. The information processing apparatus according to claim 1, wherein said storage means is a first-in first-out memory.