JP2002207531A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit processing clock supply control to a peripheral circuit block by a flexible and integrative method, and allowing generation of an efficient low-power-consumption control program by use of an interrupt set in the peripheral circuit block. SOLUTION: The semiconductor integrated circuit has a grouped control circuit 11 holding one or more clock opening/closing control settings wherein arbitrary opening/closing state settings of clock control circuits 4-9 are grouped, and specifying one group among the clock opening/closing control settings, and controls the opening/closing of the clock control circuits 4-9 according to the specified clock opening/closing control setting. The integrated circuit directly controls the opening/closing of the clock control circuits 4-9 by use of interrupt effective control making the interrupt set in the peripheral circuit block effective, or specifies the one group among the clock opening/closing control settings.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to low power consumption control of a one-chip microcomputer (one-chip microcomputer) or the like.

[0002]

2. Description of the Related Art In a conventional one-chip microcomputer, in a low power consumption mode such as a standby state or a clock stop state, a clock supply to a predetermined circuit block group determined by hardware is uniformly stopped. Has low power consumption mode. In these one-chip microcomputers, the conditions for the low power consumption mode are fixed by hardware, which imposes restrictions on the system specifications for set designers, and implements flexible low power consumption control measures on the system. I couldn't do that.

[0003] Further, in an operating state conceivable on a system such as a normal operation mode or a low power consumption mode, some circuit blocks do not need to operate, and supply of a system clock to the circuit blocks is unnecessary. However, since the control for individually stopping the clock supply to an arbitrary circuit block cannot be performed even when the error occurs, the excessive power consumption cannot be suppressed.

FIG. 3 is a block diagram showing the configuration of a system clock supply system in a conventional one-chip microcomputer. The system includes a CPU section 1 of the microcomputer, an interrupt control section 2 for controlling interrupts of the microcomputer peripheral circuits, and a clock signal for the microcomputer peripheral circuits. And a peripheral circuit system clock (PERICLK) from the clock generating unit 3.
10 is a timer a14 which is one of microcomputer peripheral circuits,
The signals are supplied to the timer b15, the timer c16 and the timer d17, and the serial e18 and the serial f19.

The outputs of the timers a14 to d17 are cascaded in order, so that a maximum of four timers can be used as one timer.

In the one-chip microcomputer configured as shown in FIG. 3, when the operation state of the system is set to the low power consumption mode, the clock generator 3 stops the peripheral system clock 10 under the control of the CPU 1, and a14
To control to uniformly stop the clock supply to the microcomputer d17, serial e18, and serial f19 peripheral circuits.

[0007]

As described above, the conventional 1
In the chip microcomputer, the clock supply control to the microcomputer peripheral circuit is uniformly controlled, so that there has been a problem that low power consumption control optimal for a system using the microcomputer cannot be performed.

In order to solve such a problem, for example, a technique for controlling the clock supply to a microcomputer peripheral circuit for each individual circuit block has been known (JP-A-5-303445). According to this technique, the supply of the system clock to each circuit block can be individually stopped by a programmable standby control signal for that circuit block.

However, simply controlling the clock supply individually to the peripheral circuit blocks makes the transition between the clock supply and the stop state complicated as the number of peripheral circuit blocks constituting the one-chip microcomputer increases. As a result, there is a possibility that the program depends on individual processing and becomes inefficient. In addition, it is necessary to deal with the interrupt set in the peripheral circuit block relating to the state transition by an individual program.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. The present invention provides a flexible and integrated method for controlling clock supply to peripheral circuit blocks according to the purpose and state of a system. An object of the present invention is to provide a semiconductor integrated circuit capable of efficiently creating a program by effectively using an interrupt set in a circuit block and performing low power consumption control suitable for the purpose of the system.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a plurality of circuit blocks (timers a14 to d17, serial e and serial f) each having a system clock (peripheral circuit system clock). 10)
A plurality of clock control circuits (clock control circuits 4 to 9) for controlling the supply and opening of the system clock to the plurality of circuit blocks, respectively, and the plurality of clock control circuits. Circuit open / close control states are grouped and set, and clock open / close control signals (clock open / close control 90 to clock open / close control 9) for individually controlling open / close control of the plurality of clock control circuits according to the set open / close control states.
Control circuit for generating 5) (grouping control circuit 11)
And characterized in that:

According to a second aspect of the present invention, in the semiconductor integrated circuit, the clock switching control signal is generated not only in accordance with the switching control state set in the control circuit but also in the plurality of circuit blocks. The interrupt is generated in accordance with the interrupt enable control (interrupt enable control 20 to interrupt enable control 23) for enabling the interrupt.

According to a third aspect of the present invention, in the semiconductor integrated circuit, the control circuit includes a plurality of holding means (opening / closing control setting register 35 to opening / closing control setting register 38) for holding the open / close control state of the clock control circuit in groups. ), Specifying means (group control register 30) for specifying any one of the plurality of holding means, and generating the clock opening / closing control signal in accordance with the opening / closing control state held in the specified holding means. (AND gates 50 to 57: AND gate
(Gates 60 to 67: AND gates 70 to 77: AND gates 80 to 87: OR gates 40 to 47).

The semiconductor integrated circuit according to claim 4, further comprising an interrupt for not only specifying said plurality of holding means by said specifying means but also for enabling an interrupt set in said plurality of circuit blocks. A means (OR gate 31 to OR gate 34) for designating according to the validity control (interrupt validity control 20 to interrupt validity control 23) is provided.

According to the semiconductor integrated circuit of the first aspect, clock open / close states optimally grouped according to the purpose and state of the system are appropriately set in the control circuit, and the open / close control of the clock control circuit is performed according to this setting. This makes it possible to create an efficient program for performing low power consumption control suitable for the purpose of the system.

According to the semiconductor integrated circuit of the present invention, by directly opening and closing the clock control circuit using the interrupt enable control for enabling the interrupt set in the circuit block, a low level directly linked to the interrupt is achieved. Power consumption control can be performed.

According to the semiconductor integrated circuit of the present invention, a plurality of clock open / close states optimally grouped according to the purpose and state of the system are always held, and the clock open / close states are selected and designated by the group designating means. Accordingly, it is possible to more easily perform a state transition according to the state of the system, and it is possible to create a more efficient program for performing low power consumption control.

According to the semiconductor integrated circuit of the present invention, one of a plurality of clock opening / closing control settings grouped by using interrupt enable control for enabling an interrupt set in a circuit block is selected and designated. This makes it possible to always maintain the clock opening / closing control setting linked to the interrupt, further simplify the clock opening / closing control by the program, and more easily perform the low power consumption control directly linked to the interrupt. Becomes possible.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a system clock supply system of a semiconductor integrated circuit according to one embodiment of the present invention.

In FIG. 1, a CPU 1, an interrupt controller 2 for controlling interrupts of peripheral circuits, a clock generator 3, a system clock for a peripheral circuit (PERICLK) 10, a timer a14, a timer b15, a timer c16, a timer d17, The serial e18 and the serial f19 respectively correspond to the respective blocks having the same reference numerals shown in FIG. 3, and the respective functions are the same as those in FIG. Also, the timer a14
The configuration in which the outputs of the timers from to to the timer d17 are sequentially cascaded is the same as the configuration in FIG.

The semiconductor integrated circuit according to the present invention further comprises:
A grouping control circuit 11 under the control of the CPU unit 1 and the interrupt control unit 2; and clock opening / closing control signals 90, 91, 92, 93, 9 from the grouping control circuit 11, respectively.
4 and 95, and individually performs opening / closing control to turn on or off the system clock 10 supplied from the clock generation unit 3, and controls the timer a14, timer b15, timer c16, timer d17, serial e18, and serial f19, respectively. A clock control block 12 including clock control circuits 4, 5, 6, 7, 8, 9 for supplying clocks; Note that this individual clock switching control can be used not only in the low power consumption mode but also in the normal operation mode.

FIG. 2 is a circuit diagram showing a configuration of the grouping control circuit 11. In the figure, 20, 21, 22, and 23 are:
These are timer b interrupt enable control, timer d interrupt enable control, serial e interrupt enable control, and serial f interrupt enable control supplied from the interrupt control unit 2, respectively. The timer b interrupt enable control 20 is a signal that is enabled when the interrupt enable setting is performed so that the CPU unit 1 can recognize the occurrence of the interrupt set in the timer b15. Similarly, timer d interrupt enable control 21
Is an interrupt enable of the timer d17, the serial e interrupt enable control 22 is an enable of the serial e18 interrupt, and the serial f interrupt enable control 23 is a serial f19 enable.
These signals are enabled in response to the interrupts being enabled.

Further, in the figure, 35, 36, 37, 38
Is a group opening / closing control setting register for holding a clock opening / closing control setting of one group, 35 is a group A opening / closing control setting register, 36 is a group B opening / closing control setting register, 37 is a group C opening / closing control setting register, and 38 is a group opening / closing control setting register. Group D opening / closing control setting register, which includes a timer a14, a timer b15, and a timer c1, respectively.
6 and a combination of the timer d17 and the clock opening / closing control settings for the peripheral circuits of the serial e18 and the serial f19 can be grouped and stored. In the illustrated example, these group opening / closing control setting registers have eight registers.
Each of the bits corresponds to a clock opening / closing control signal of the clock control circuits 4 to 9.

Further, there is provided a group control register 30 for designating one of the group opening / closing control setting registers 35, 36, 37, 38 by setting each bit. Each bit output of the group A control bit, the group B control bit, the group C control bit, and the group D control bit of the group control register 30 corresponds to each group designation of the groups A, B, C, and D. Gate 31,
Group 32 of AND gates via 32, 33, 34
0-57, 60-67, 70-77, 80-87. Then, a group A opening / closing control setting register 35, a group B opening / closing control setting register 36, a group C opening / closing control setting register 37, and a group D opening / closing control setting register 38 are selected by each group of the AND gates.

A group control register 30 is provided at one end.
, Two-input OR gates 31, 32,
The other end of each of 33 and 34 is supplied with a timer b interrupt enable control 20, a timer d interrupt enable control 21, a serial e interrupt enable control 22, and a serial f interrupt enable control 23 from the interrupt control unit 2. Group A opening / closing control setting register 3
5, Group B opening / closing control setting register 36, Group C
The opening / closing control setting register 37 and the group D opening / closing control setting register 38 are selected.

The clock open / close control signals 90, 91, 92,
Reference numerals 93, 94, and 95 denote the output of each bit of the group A opening / closing control setting register 35, the group B opening / closing control setting register 36, the group C opening / closing control setting register 37, and the group D opening / closing control setting register 38 as a 4-input OR gate 40.
The control signals output and synthesized at # 47.

The operation of the system clock supply system of the present embodiment configured as described above will be described below. In the following description, a bit value “1” indicates that the control is valid (ON).

"00001111" is set in the group A opening / closing control setting register 35 from the upper bit (bit 7 side),
“00000000” is set in the group B opening / closing control setting register 36 to the group D opening / closing control setting register 38. By enabling the group A control bit of the group control register 30 after this setting, the timer a1
From 4 to the timer d17, the peripheral system clock 10
Is supplied, and the serial e18 and the serial f19 are controlled so that the peripheral system clock 10 is not supplied.

Similarly, after an arbitrary value is set in the register bit of the group B opening / closing control setting register 38 from the group B opening / closing control setting register 36, the control register 30
By turning on the corresponding bit of, the supply control of the peripheral system clock 10 to the peripheral circuit block can be easily performed.

As described above, since it is complicated to perform the clock open / close control setting process for each peripheral circuit every time the clock supply to each peripheral circuit block or the stop state changes, the clock open / close control setting is grouped. Group of opening / closing control setting registers (group A opening / closing control setting register 35 to group D opening / closing control setting register 3
8) is prepared and the setting change by the program is facilitated by operating the group designation bit of the group control register 30.

As an application example of using the interrupt validity control from the interrupt control unit 2, there is a state in which a timer a14 and a timer b15 are cascaded and used, and it is not necessary to operate other than these two timers. It is assumed that it occurs. In this case, if “00000011” is set in advance in the group A opening / closing control setting register 35 and the interrupt enable setting for recognizing the interrupt of the timer b15 to the CPU unit 1 is performed, the group A opening / closing control 20 is performed by the timer b interrupt enable control 20. Control setting register 3
Since 5 is selected, it is not necessary to perform an operation for validating the group A control bit of the group control register 30 again.

As described above, by effectively utilizing the interrupt validity control from the interrupt control unit 2, the setting control by the program can be further simplified. Similarly, when the timer c16 and the timer d17 are cascaded, the timer a14 to the timer d1
7, the serial e18 is used, the serial f19 is used, or a state suitable for each used and unused combination is determined from the group A opening / closing control setting register 35 to the group D opening / closing control setting register 38. , It is possible to reduce the power consumption of the system while minimizing the complexity of software setting.

As described above, since the operation of the control circuit shown in this embodiment does not depend on the operation mode of the one-chip microcomputer or the like,
In the normal operation mode as well as in the low power consumption mode, it is possible to reduce the power consumption of the system by restricting the clock supply to unused peripheral circuits.

Also, there are microcomputers having a standby mode in which the system clock is supplied to the timers and serials of the peripheral circuits even when the CPU unit 1 is stopped, but the control circuit shown in this embodiment is Also in such a standby mode, the present invention can be applied by controlling the supply of the peripheral system clock 10 to the minimum necessary peripheral circuits.

[0035]

As described above, according to the present invention,
One or more clock opening / closing states optimally grouped according to the purpose and state of the system are held, and the clock control circuit is opened / closed in accordance with this setting, thereby performing low power consumption control suitable for the purpose of the system. An efficient program can be created.

Further, according to the present invention, the clock control circuit is directly opened and closed using interrupt enable control for enabling an interrupt set in a circuit block, or one of a plurality of clock open / close states is grouped. By selectively specifying one of them, it is possible to perform low power consumption control directly linked to the interrupt, and it is possible to further simplify the clock switching control by the program.

As described above, according to the present invention, in a system using a one-chip microcomputer or the like, in a normal operation mode or a low power consumption mode, an optimum state for low power consumption control can be obtained by performing simple settings. A semiconductor integrated circuit that can be arbitrarily selected and implemented and can flexibly reduce power consumption can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a system clock supply system of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a grouping control circuit.

FIG. 3 is a block diagram showing a configuration of a system clock supply system in a conventional one-chip microcomputer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU part 2 Interrupt control part 3 Clock generation part 4, 5, 6, 7, 8, 9 Clock control circuit 10 System clock for peripheral circuits (PERICLK) 11 Grouping control circuit 12 Clock control block 14 Timer a 15 Timer b 16 Timer c 17 Timer d 18 Serial e 19 Serial f 20 Timer b interrupt enable control 21 Timer d interrupt enable control 22 Serial e interrupt enable control 23 Serial f interrupt enable control 30 Group control register 31, 32, 33, 34 2-input OR gate 35 Group A opening / closing control setting register 36 Group B opening / closing control setting register 37 Group C opening / closing control setting register 38 Group D opening / closing control setting register 40-474 4-input OR gate 50-57, 60-67, 70-77, 80- 87 A
ND gate 90 Timer a clock switching control signal 91 Timer b clock switching control signal 92 Timer c clock switching control signal 93 Timer d clock switching control signal 94 Serial e clock switching control signal 95 Serial f clock switching control signal

Claims (4)

[Claims] 1. A semiconductor integrated circuit for supplying a system clock to a plurality of circuit blocks, comprising: a plurality of clock control circuits for controlling opening and closing of the supply of the system clock to the plurality of circuit blocks; A control circuit that generates a clock opening / closing control signal that individually controls the opening / closing control of the plurality of clock control circuits according to the set opening / closing control state. A semiconductor integrated circuit, comprising: 2. An interrupt enable control for not only generating the clock open / close control signal according to the open / close control state set in the control circuit but also enabling an interrupt set in the plurality of circuit blocks. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is generated according to the following. 3. The control circuit, comprising: a plurality of holding units for holding an open / close control state of the clock control circuit in a group unit; a designation unit for designating any one of the plurality of holding units; 3. The semiconductor integrated circuit according to claim 1, further comprising: means for generating the clock switching control signal in accordance with the switching control state held by the holding means. 4. A means for designating the plurality of holding means not only by the designating means but also according to interrupt enable control for enabling an interrupt set in the plurality of circuit blocks. 4. The semiconductor integrated circuit according to claim 3, comprising: