GB2210214A - Uninterrupted power supply - Google Patents

Abstract

An off-line power supply includes an inverter for supplying a load from a battery bank when mains are not available. When the mains are available the load is supplied through a gate turn-off static switch and a full wave rectifier provides a supply for maintaining the battery bank charged. The battery voltage is less than that which would normally be necessary to provide the required mains voltage and accordingly the circuit includes a D.C. booster (TR1, L2) and a buck circuit for use when charging the battery from the mains. This enables the A.C. output of the inverter to be taken directly from the inverter output without having to have a heavy and noisy step-up transformer. The supply includes means for reducing switch turn-on and turn-off losses to improve the efficiency of the booster. <IMAGE>

Description

UNINTERRUPTED POWER SUPPLY This invention relates to an uninterrupted power supply (UPS), that is to say, a circuit for supplying a load from an A.C. power supply when it is available, but having a standby battery source which can be charged when the mains are available and within a desired specification, and which can supply the load through an inverter if the mains should fail.

An object of the invention is to provide a compact UPS which is not expensive, and is suitable, for example, for small commercial computers.

The invention may be considered to reside in any of the following features, either taken alone, or in any combination.

The inverter may comprise a full bridge inverter without a transformer. Such a full bridge inverter could comprise four transistor devices in the four arms, each shunted by a freewheel diode.

With such a full bridge inverter, two of the transistors connected in series across the D.C.

terminals of the inverter could be switched alternately on at a low frequency, which will be the desired output frequency of, say 50 or 60 Hertz, and then the other two transistors could be switched on and off at a high carrier frequency, for example, 25.6 kHz, with the duration of each on period being controlled in accordance with a desired sine wave or other output voltage characteristic.

The A.C. side of the bridge could include capacitive and inductive components constituting a filter for the high frequency and the load could be directly coupled across the capacitive component to avoid having an output transformer. A cooling fan need not be necessary.

The inverter can be arranged to charge a battery bank while the mains are available so that the battery bank can be capable of providing the A.C. power supply through the inverter if the mains disappears. In order to keep the cost, size and weight of the power supply down, there may be a buck/boost converter between the battery bank and the inverter so that a battery bank giving a voltage less than the voltage output from the D.C. side of the inverter can be used with the boost converter operative when the power is being supplied from the battery bank and the buck converter operative when the battery bank is being charged through the inverter.

According to one aspect of the invention a power supply comprises a storage battery and an inverter for producing an A.C. supply from the battery and includes a booster for boosting the battery voltage so that the inverter does not need a step up transformer to provide an A.C. supply with a voltage greater than that directly available from the battery. The inverter may also produce a D.C. supply from the mains when it is available for charging the battery.

In an alternative embodiment of the invention, when the mains are available, the battery bank can be charged through a separate secondary winding on a mains transformer through a full wave rectifier and a battery charger and then the buck converter is unnecessary.

The boost converter can include a semiconductor switch which is cyclically turned on and off for periods dependent on the boost ratio required. Avalanched noninductive turn-off prevents the circuit oscillating due to collector current storage time modulation. The base drive desaturates the switching transistor during on periods to prevent excessive current tailing due to hard turn-off.

If a booster is to be a satisfactory replacement of a transformer in the inverter, the booster must be efficient, and according to a second aspect of the invention, turn-off losses in such a boost converter can be reduced by providing a lossless snubber circuit.

At turning on of a thyristor or transistor switch, turn-on current can be restricted by a saturating inductor in series with a non-saturating inductor. The saturating inductor can delay the rise of switch current until the voltage has fallen.

The connection between the mains and the inverter can include a gate turn-off thyristor static switch so that, when failure of the mains is detected, the static switch can be operated very quickly, for example, in less than 10 microseconds (after detection of fault) without having to wait for half-cycle mains commutation.

The equipment can be very compact, and in one embodiment suitable for supplying 2000 VA the external casing is only 350 mm high x 200 mm wide x 600 mm deep.

The battery bank is spread in a horizontal array along the bottom of the casing with a control circuit printed circuit board positioned above it. There are mains inlet and mains outlet sockets in a rear panel and power switching devices for the inverter in the top part of the casing.

The invention may be carried into practice in various ways, and one embodiment will now be described by way of example with reference to the accompanying drawings, in which: FIGURES 1 (LEFT) and (1 RIGHT) together constitute a block diagram showing the general arrangement of an uninterrupted power supply; FIGURE 2 is a circuit diagram of the booster control circuit of Figure 1.

The UPS of Figure 1 is an off-line system, in which a load 13 is normally supplied under standby operation from the mains 10 through a static switch 18 comprising four diodes connected as a full-wave rectifier, but with what would be the D.C. output terminals interconnected by a two-way gate turn-off thyristor 70.

A special RFI filter and spike suppressor 19 removes common mode spikes (up to 6kV, 12J energy) and differential spikes in conjunction with a capacitor 61, and enables the unit to comply with VDE0871 and BS6527 standards regarding limits to RFI.

An inverter 14 for use during mains brownout (low A.C.

peak), blackout (low average content), or more than 2-Hz variation in frequency, comprises four power Darlington transistors 22, 23, 24, 25 in transformerless fullbridge configuration with an L.C. filter comprising a small plastic type capacitor 27 connected in series with a small iron-powder toroid inductor 26 in the cross-arm of the bridge.

Each of the transistors is shunted by a freewheel diode 71, 73, 74, or 75.

When the inverter is in use, the two transistors 22 and 23 connected across the D.C. terminals of the inverter are switched by base drive circuits 44 and 45 at a high carrier frequency of 25.6 kHz, while the other two transistors 24 and 25 are switched alternately at the desired output frequency of 50 Hz. The filter 26, 27 filters out the high carrier frequency from the load.

When the mains supply 10 is within a desired specification monitored as described below, the transistors 22, 23, 24 and 25 are maintained off so that the four freewheel diodes act as a full-wave rectifier providing a fluctuating D.C. supply across a reservoir capacitor 61, for float charging a battery bank 15 by means of a charger 17. The battery negative pole is isolated from earth and floats with respect to the mains supply so that an isolating transformer is not necessary.

When the mains is available, it supplies the load 13 through the-switch 18, and at the same time charges the battery bank through the inverter. The inverter 14 is transparent to the mains and energy flow is bilateral.

If the mains supply is detected as being out of specification, the gate turn-off thyristor 70 is switched off so that the mains is disconnected from the load terminals, which are now supplied from the inverter 14. At the same time, switching of the transistors 22 and 25 is initiated, the charger 17 is inhibited, and the battery bank 15 supplies D.C. to the inverter through a high frequency booster 16 to provide the necessary higher voltage VCC (e.g. 360 V).

Maximum detection time is less than 4 ms with changeover occurring in less than 10 ps. Change-over can occur at any interval during the mains cycle by operation of the static switch 70, whereas a conventional back-to-back thyristor static switch would have to wait for natural line communication before change-over. Because mains and inverter are phaselocked, change-overs are always in phase and smooth operating. When the mains returns within specification, the inverter 14 changes to standby and the switch 18 closes, thus providing a continuous source of power to the load.

Such a 2KVA inverter power supply would conventionally use a large and bulky output transformer so that the necessary mains voltage could be achieved without having too large a battery bank. That has been avoided in the present invention by providing direct coupling from the capacitor 62 to the load 11.

The need for an output transformer has been avoided without increasing the battery bank voltage by providing the booster 16 mentioned above, and a buck regulator 21.

The feature of having no transformer in the output means that the inverter is completely quiet with no mains hum. Also, no fan is needed, and natural cooling is adequate.

The uninterrupted power supply according to the invention would use, in the 2 KVA embodiment, a 10 ampere-hour battery consisting of sixteen 6V cells of the sealed lead acid low maintenance kind, so that the size and weight of the battery bank would be reasonable.

An advantage of having no inverter transformer is that for a given power level the current switched is smaller in that high current wires can be replaced by low current PCB tracks.

Inverter Control The mains supply 11 at the output of the filter 19 is sensed by a differential amplifier 30, converted to digital form by a zero crossing detector (Z.C.D.) 32 and gated to a phase locked loop (P.L.L.) circuit 34 by a multiplexer 33. A digital sinewave reference is generated by a generator 37 and coupled to an error amplifier 38.

The mains output 12 is sensed by a differential amplifier 31 whose output is coupled to the summing junction of the error amplifier 38. A sawtooth carrier signal generated at 40 is phase-locked to the fundamental and is compared to the error signal output from the error amplifier 38 in a pulse width modulator (P.W.M.) stage 41. The sinewave modulated P.W.M.

signal is gated to the base-drive circuits at 42 and 43 after being steered by a Z.C.D. 39 with a half-cycle deadtime provided by a circuit 62.

An enable function gate 54 has inputs from the phase error detector 55 responsive to any phase error between the output of the mains Z.C.D. 32 and Z.C.D. 39; a frequency detector 56; A.C.-low-average and A.C.-lowpeak detectors 50 and 51; and a battery under-voltage lockout 53. The gate provides "enable" or "inhibit" signals C to the buck control 21, battery charger 17, and static switch 18; W to the base drive controls 42 and 43; and Z to the boost control 20; respectively, dependent on whether or not the mains are within specification. Also, when the mains are not within specification the multiplexer 33 is caused to change state by the function gate 54, so that the reference frequency is provided by a crystal oscillator 29.

The detectors 50 and 51 receive as inputs rectified versions of the mains output and the reference sinewave from rectifiers 48 and 49.

The buck control 21 is only enabled if the voltage across the reservoir capacitor 61 is above a certain level.

The base drive circuits 44, 45, 46 and 47 have the following functions; leading edge delay (to prevent shoot-through of transistors 22 and 23); minimum ON time (to allow for turn-off snubber circuit reset); minimum OFF time (to allow turn-on snubber demagnetisation); current limiting to prevent the transistors 22, 23, 24 and 25 from exceeding their F.B.S.O.A.R.; base drive proportional to collector current; negative base-drive voltage monitoring.

Under inverter operation, the battery bank 15 will begin to discharge. A monitor 57 monitors the battery voltage VBB and enables a latch and timer 59 to drive an audible alarm 60. The alarm will "bleep" during moderate discharge and can be muted by a push button 58; however, if the batteries begin to enter the overdischarge region, the monitor 57 overrides 59 and causes the alarm 60 to sound continuously, indicating that shutdown is imminent. Once this point is reached, a comparator 36 shuts down power to the whole system by closing down an auxiliary supply 35.

Following brownouts or blackouts (lasting less than 10 minutes at full load) the alarm is automatically cancelled when the mains returns to within specification. With brownout conditions (e.g. halfcycle) the unit will not switch back to mains supply until the phase error at 55 between 32 and 39 is nulled; this may take several seconds depending on the capture time of the P.L.L. 34.

When changing over to inverter operation, the inverter waveform follows on from the last mains half-cycle so that change-over follows in phase, thus preventing double-pulsing of the sinewave across the load.

Inverter Protection During inverter operation in one mains half-cycle transistor 25 is ON and transistor 22 is latched ON and OFF with H.F. sinewave weighted PWM. Every time transistor 22 turns back on again I must support the reverse recovery current through the freewheel diode 73 of transistor 23 until this diode recovers its blocking state. In order to reduce the turn-on current spike, inductors L4, L5 are inserted in series with the bridge. L4 is a saturable reactor designed to saturate after the inverse diode has recovered its blocking state. L4 supports the entire dc voltage until it saturates, when its impedance collapses abruptly causing a sudden injection of collector current into transistor 22. L5 is therefore included to maintain that transistor within its FBSOAR by limiting the current spike.

The inclusion of L4 and L5 thus reduces turn on energy dissipation.

Inductor L4 is reset by a resistor R15 in series with a diode D10 connected across the two inductors.

This arrangement of a small saturating inductor in series with a non-saturating inductor avoids the need for a large single inductor to restrict transistor current at switching ON. The arrangement could also be used to improve the efficiency of switching the boost transistor TR1. Thus, at turn-on of TR1, the finite reverse recovery time of the diode D8 tends to produce a large current in TR1 momentarily, and to restrict that, inductance can be included in the collector/emitter path of TR1. The present application would involve a large inductor, and to avoid that, a saturating 50uH inductor L3 could be used that saturates during the reverse recovery time of D8 and then resets through resistors R3 and R275 and diode D3 when TR1 turns off.

The saturation of the inductor L3 would cause a sudden collapse of the impedance in the collector/emitter circuit and so merely transfer the power dissipation in the transistor circuit from the turn-on instant to the on-time, so that there would be no improvement in efficiency and possible damage to the transistor.

Accordingly, a small 3uH inductor L17 which does not saturates is included in series with L3 and that presents non-negligible inductive reactance to current growth when L3 saturates.

Booster The booster 16 includes the transistor TR1, which is switched by a control signal alternately off and on.

The ratio of on-time to off-time sets the boost voltage ratio. With an on-time of 80%, the ratio would be 5:1.

(T/(T-t)) where T is the cycle time and t is the ontime). While the transistor is on, current is built up in the inductor L2 from the battery bank 31, but while the transistor is off, the energy stored in the inductor L2 charges the capacitor 61 through a diode D8.

Booster Control The circuit for turning off the transistor TR1 will now be described with reference to Figure 2.

A capacitor C68 is connected in series with a diode D59 so that when the transistor turns off, the collector current is diverted to charge C68. That reduces the rate of change of voltage across the transistor and reduces the losses.

When the voltage across C68 reaches the D.C. output it is clamped by diodes D2 and D60. Diode D8 conducts so that the reservoir capacitance C61 is charged from energy in the inductor L2 and from the battery bank.

Now, at the same instant that C68 is charging up, a capacitor C6 is being discharged through diodes D59 and D2 and a swinging choke L1 so that when TR1 has turned off C68 is fully charged and C6 is discharged.

When TR1 turns back on again its collector voltage falls to Vce (sat) causing C68 to discharge into C6 via D2 and L1. L1 acts in conjunction with C6 and C68 as a non-resistive resonant circuit which causes a resonant "hump" of current to be superimposed onto the collector current of TR1. Because the current path during turnoff and the reset period is through purely reactive elements, then in theory, the snubber circuit is "lossless", thereby giving a highly efficient switching action. L1 is a swinging choke so that, as the loading is increased (i.e. IC increasing) inductance falls.

This means that the resonant "hump" will increase in amplitude, but diminish in pulse duration. This ensures that, during current limit when the on period of TR1 is minimum, the reset time of the snubber is also a minimum; this period may be of the order of 1.5 Js.

Effectively, the energy is recirculated in the reactive circuit C68, D2, L1, C6 rather than being dissipated in resistance.

Claims (13)

1. A power supply comprising a storage battery and an inverter for producing a A.C. supply from the battery, and including a booster for boosting the battery voltage so that the inverter does not need a step-up transformer to provide an A.C. supply with a voltage greater than that directly available from the battery.

2. A power supply as claimed in claim 1, which is capable of producing, through the inverter, a D.C.

supply for charging the battery.

3. A power supply as claimed in either of the preceding claims in which when the mains is available a load is supplied from the mains and not through the inverter but when the mains are not available the load is supplied from the battery through the inverter.

4. A power supply as claimed in any of the preceding claims including a gate turn-off semiconductor switch between the mains and the load upstream of the connection between the inverter and the load.

5. A power supply as claimed in any of the preceding claims including a sensor of the condition of the mains arranged automatically to control operation of the inverter and the booster.

6. A power supply as claimed in any of the preceding claims in which the inverter includes two pairs of semiconductor switches which are arranged during inverter operation so that one pair are alternately switched at mains frequency whereas the other pair are switched at a much higher frequency to provide sinusoidal weighted pulse width modulation.

7. A power supply as claimed in any of the preceding claims in which the inverter is phase locked to the mains.

8. A power supply arranged substantially as herein specifically described with reference to figure 1 of the accompanying drawings.

9. A D.C. booster comprising an inductor and a semiconductor switch to enable, when closed, direct current to build up in the inductor, and, when open, to allow the inductor current to charge a capacitor, and including a snubber circuit for a switch allowing switch current to flow in a substantially resistanceless circuit at turn-off to reduce switching losses.

10. A booster as claimed in claim 9 in which the snubber circuit comprises a non-resistive LC resonant circuit in which switch current can flow at turn-off.

11. An electric circuit including a semiconductor switch, and an impedance for restricting turn-on current in the switch and comprising a saturating inductor and a non-saturating inductor.

12. A circuit as claimed in claim 11 which is arranged for controlling current flow in a circuit including a diode in which the said impedance protects the switch during the recovery time of the diode.

13. An electric circuit arranged substantially as herein specifically described with reference to figure 2 of the accompanying drawings.