GB1571681A - Inverter - Google Patents

Description

(54) D.C. A.C. INVERTER (71) We, ITT CREED LIMITED, a British Company, of Crowhurst Road, Hollingbury, Brighton 6, Sussex, England, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to current inverters.

According to the present invention there is provided a current inverter comprising: a pulse generator producing two antiphase pulse trains of square wave pulses; a reference signal generator said reference signal having a frequency much less than that of the pulses; a zero-crossing detector to detect the zeroes of the reference signal; a pulsewidth modulator connected to the outputs of both the pulse generator and the detector; switching devices connected to the outputs of the modulator; a two-primary-winding transformer having a main secondary winding; a switching and filtering circuit; and a comparator for comparing the output of the filter circuit with the reference signal and producing an output representative of any discrepancy therebetween; in which the outputs of the zero-crossing detector gate the pulse-width-modulator and the switching circuit so that during the positive part-cycle of the reference signal one of the pulse trains is applied to one primary of the transformer and the secondary output is gated to the filter with one polarity relative to ground, and during the negative part-cycle the other pulse train is gated to the other primary and the secondary output is gated to the filter with the opposite polarity whereby, after filtering (smoothing), the resultant output changes polarity whenever the reference signal does; and wherein the output of the comparator is applied to the modulator so that the width of the pulse output from the latter is modified to cause the shape of the output from the filter to be substantially the same as that of the reference signal.

An embodiment of the invention is described below, with reference to the accompanying drawings, of which: Figure 1 is a block schematic diagram of an inverter; Figure 2 is a set of waveforms explaining the operation of the inverter' Figure 3 is another waveform explaining the operation of the inverter; and Figure 4 shows details of some of the blocks of Figure 1.

A clock pulse generator 1 produces two high-frequency, square-wave pulse trains which are in antiphase with each other (Figures 2, A and B).. These two trains are respectively applied to two inputs, 2a, 2b, of a pulse width modulator 2. A reference waveform generator produces a signal (Figure 2, C) which has the waveform desired at the output of the inverter, an alternating waveform and usually sinusodial.

This waveform is applied to a zero-crossing detector 4 which produces two gating square waves in anti-phase whose "walls" are in synchronism with the change-overs of the reference waveform (Figure 2, D and E).

These two square-wave signals are respectively applied to two further inputs, 2c, 2d, of the pulse-width-modulator 2 where they act to gate the input signals on inputs 2a and 2b to the outputs 2e, 2f of the modulator, one gating signal allowing the signals applied to input 2a to reach output 2e while output 2f remains quiescent, the other gating signal allowing the signals applied to input 2b to reach output 2f while output 2e remains quiescent (Figures 2, F and G).

The two output trains from the outputs 2e and 2f are those applied respectively to two amplifier stages 5 at respective inputs Sa and Sb. Each output train is separately amplified in its own amplifier, and applied to one winding of a two-primary trans former 6. This transformer has a main secondary and two auxiliary secondaries.

The main secondary is connected to the inputs 7a and 7b of two gate-controlled semiconductor switches, 7, which alternately feed a filter circuit. The auxiliary secondaries each energize a bias circuit for a respective one of - the gate-controlled rectifiers. Two inputs 7c and 7d of the gate controlled- rectifier circuits are connected respectively to the two gating outputs of the zero-crossing detector 4, and form a further bias control on the gate-controlled rectifiers.

As so far described the circuit would produce on its output a signal somewhat as shown in Figure 2, H. In fact the pulse repetition frequency of the signals A and B would be much higher in relation to the frequency of the reference signal, say 20 kilohertz to a 50 hertz reference signal, but we have drawn it as much less than that (about 250 hertz to 50 hertz) merely for the sake of clarity. Waveform I of Figure 2 gives a closer idea of what the output of the gate-controlled rectifiers would look like, before passing through the filters. After passing through the filters the output would be very like waveform C.

However, the filter output is fed to one input terminal 8a of a comparator 8, to the other input 8b of which the reference signal is applied directly. Within this comparator the actual instantaneous value of the output is compared with the value it should have at that instant, and according to the discrepancy found, if any, the width of the pulses leaving the pulse-width-modulator is adjusted. Thus, if the actual value is higher than the intended value the width of the positive-going pulses is decreased; if it is lower, the width is increased. The effect will be as shown in Figure 3, in full line.

Again we have drawn only a few pulses rather than the some 400 pulses which would normally be there. The dotted line in Figure 3 shows the shape of the output signal from the filter and is fairly faithful copy of the reference signal.

7Figure 4 shows in some detail the circuits and interconnection of the blocks 5, 6 and 7 of Figure 1.

The amplifiers 5 consist of two Darlingtonconnected amplifiers. The inputs Sa and Sb connect to the preceding pulse-widthmodulator 2 as shown in Figure 1 and the outputs are connected each to a respective one of the Drimaries in the transformer 6. At any given time only one of the amplifiers is pulsing its winding. Across each of the output transistors T1 and T2 of the amplifiers is connected a respective diode D1, D2 to limit excessive voltage on -the collectors. This happens because if. say, at turn-off the collector voltage of T1 is rising rapidly, because of back e.m.f., the collector voltage of T2 will be correspondingly going negative, but diode D2 will conduct when the collector of T2 reaches -0.7 volts (say) and, because of tight magnetic coupling between winding L1 and L2 the voltage rise on the collector of T1 will be halted.

Assume that pulse signals are being applied to input Sa. Then winding L2 is activated and the anode of diode D3 is repeatedly driven positive as is, in consequence, the anode of gate-controlled rectifier CR1. Also, from the output of the zero-crossing detector, an enabling signal is applied through the transistor T4 and the optical coupler OC1 to allow positive bias to reach the gate of controlled rectifier CR1. Thus the pulses applied to amplifier 5 are amplified and allowed through the controlled rectifier CR1 onto the line to the filter (L6, C1) as a train of pulse-width-modulated, postive-going pulses. Conversely, when pulsed signals are applied to input 5b of amplifier 5 there appears on the line to the -filter a train of pulse-width-modulated, negative-going pulses. The output of the filter is then a copy of the reference waveform. At 7a are the connection back to the comparator 8.

As was said above, when a transistor T1 or T2 is switched off its collector voltage tends to rise. The voltage at the anode or cathode of its respective diode D4 or D3 tends to go in the opposite direction. The diodes D6 and D5 respectively clamp the voltage at the respective cathode or anode at zero so that the voltage swing on winding L3 is taken up across the diode D4 or D3.

WHAT WE CLAIM IS: 1. A current inverter comprising: a pulse generator producing two antiphase pulse trains of square wave pulses; a reference signal generator said reference signal having a frequency much less than that of the pulses; a zero-crossing detector to detect the zeroes of the reference signal; a pulsewidth modulator connected to the outputs of both the pulse generator and the detector; switching devices connected to the outputs of the modulator; a two-primary-winding transformer having a main secondary winding; a switching and filtering circuit; and a comparator for comparing the output of the filter circuit with the reference signal and producing an output representative of any discrepancy therebetween; in which the outputs of the zero-crossing detector gate the pulse-width-modulator and the switching circuit so that during the positive part-cycle of the reference signal one of the pulse trains is applied to one primary of the transformer and the secondary output is gated to the filter with one polarity relative to

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (2)

**WARNING** start of CLMS field may overlap end of DESC **. former 6. This transformer has a main secondary and two auxiliary secondaries. The main secondary is connected to the inputs 7a and 7b of two gate-controlled semiconductor switches, 7, which alternately feed a filter circuit. The auxiliary secondaries each energize a bias circuit for a respective one of - the gate-controlled rectifiers. Two inputs 7c and 7d of the gate controlled- rectifier circuits are connected respectively to the two gating outputs of the zero-crossing detector 4, and form a further bias control on the gate-controlled rectifiers. As so far described the circuit would produce on its output a signal somewhat as shown in Figure 2, H. In fact the pulse repetition frequency of the signals A and B would be much higher in relation to the frequency of the reference signal, say 20 kilohertz to a 50 hertz reference signal, but we have drawn it as much less than that (about 250 hertz to 50 hertz) merely for the sake of clarity. Waveform I of Figure 2 gives a closer idea of what the output of the gate-controlled rectifiers would look like, before passing through the filters. After passing through the filters the output would be very like waveform C. However, the filter output is fed to one input terminal 8a of a comparator 8, to the other input 8b of which the reference signal is applied directly. Within this comparator the actual instantaneous value of the output is compared with the value it should have at that instant, and according to the discrepancy found, if any, the width of the pulses leaving the pulse-width-modulator is adjusted. Thus, if the actual value is higher than the intended value the width of the positive-going pulses is decreased; if it is lower, the width is increased. The effect will be as shown in Figure 3, in full line. Again we have drawn only a few pulses rather than the some 400 pulses which would normally be there. The dotted line in Figure 3 shows the shape of the output signal from the filter and is fairly faithful copy of the reference signal. 7Figure 4 shows in some detail the circuits and interconnection of the blocks 5, 6 and 7 of Figure 1. The amplifiers 5 consist of two Darlingtonconnected amplifiers. The inputs Sa and Sb connect to the preceding pulse-widthmodulator 2 as shown in Figure 1 and the outputs are connected each to a respective one of the Drimaries in the transformer 6. At any given time only one of the amplifiers is pulsing its winding. Across each of the output transistors T1 and T2 of the amplifiers is connected a respective diode D1, D2 to limit excessive voltage on -the collectors. This happens because if. say, at turn-off the collector voltage of T1 is rising rapidly, because of back e.m.f., the collector voltage of T2 will be correspondingly going negative, but diode D2 will conduct when the collector of T2 reaches -0.7 volts (say) and, because of tight magnetic coupling between winding L1 and L2 the voltage rise on the collector of T1 will be halted. Assume that pulse signals are being applied to input Sa. Then winding L2 is activated and the anode of diode D3 is repeatedly driven positive as is, in consequence, the anode of gate-controlled rectifier CR1. Also, from the output of the zero-crossing detector, an enabling signal is applied through the transistor T4 and the optical coupler OC1 to allow positive bias to reach the gate of controlled rectifier CR1. Thus the pulses applied to amplifier 5 are amplified and allowed through the controlled rectifier CR1 onto the line to the filter (L6, C1) as a train of pulse-width-modulated, postive-going pulses. Conversely, when pulsed signals are applied to input 5b of amplifier 5 there appears on the line to the -filter a train of pulse-width-modulated, negative-going pulses. The output of the filter is then a copy of the reference waveform. At 7a are the connection back to the comparator 8. As was said above, when a transistor T1 or T2 is switched off its collector voltage tends to rise. The voltage at the anode or cathode of its respective diode D4 or D3 tends to go in the opposite direction. The diodes D6 and D5 respectively clamp the voltage at the respective cathode or anode at zero so that the voltage swing on winding L3 is taken up across the diode D4 or D3. WHAT WE CLAIM IS:

1. A current inverter comprising: a pulse generator producing two antiphase pulse trains of square wave pulses; a reference signal generator said reference signal having a frequency much less than that of the pulses; a zero-crossing detector to detect the zeroes of the reference signal; a pulsewidth modulator connected to the outputs of both the pulse generator and the detector; switching devices connected to the outputs of the modulator; a two-primary-winding transformer having a main secondary winding; a switching and filtering circuit; and a comparator for comparing the output of the filter circuit with the reference signal and producing an output representative of any discrepancy therebetween; in which the outputs of the zero-crossing detector gate the pulse-width-modulator and the switching circuit so that during the positive part-cycle of the reference signal one of the pulse trains is applied to one primary of the transformer and the secondary output is gated to the filter with one polarity relative to

ground and during the negative part-cycle the other pulse train is gated to the other primary and the secondary output is gated to the filter with the opposite polarity whereby, after filtering (smoothing), the resultant output changes polarity whenever the reference signal does; and wherein the output of the comparator is applied to the modulator so that the width of the pulse output from the latter is modified to cause the shape of the output from the filter to be substantially the same as that of the reference signal.

2. A current inverter substantially as described with reference to the accompanying drawings.