METHOD AND SYSTEM FOR CONTROLLING RESONANT CONVERTERS USED IN SOLAR INVERTERS
FIELD OF THE INVENTION
The present invention relates, in general, to the field of power generation systems. More specifically, the present invention relates to a method and a system for controlling resonant converters used in solar inverters.
BACKGROUND
Resonant converters are electronic resonant circuits which utilize one or more LC circuits to convert a DC voltage from a DC voltage source to a sinusoidal voltage and a current waveform. Typically, such circuits are widely used in the electronics industry because of huge number of advantages. For example, resonant circuits have low switching losses and have less Electromagnetic Interference (EMI). Further, these circuits are capable to operate at very high switching frequency as they allow zero voltage and current switching conditions for main power devices. High switching frequency operation facilitates the replacement of bulky magnetic components with small size components, thus helping in reducing the overall size of the circuit. In particular, during the circuit operation at zero voltage and current switching conditions, the power devices conduct only when they are turned-on, thereby reducing the switching losses. Moreover, problems which arise due to EMI are considerably reduced. Typically, solar inverters need to generate power from solar energy in an efficient and cost effective manner. To do so, such solar inverters operate such that they are fully functional and independent units or are grid-connected, and they also operate under diverse power levels. To operate under such diverse power levels, typically a DC power source, such as a battery, a fuel cell, or a solar panel, is connected to a solar inverter. The solar inverter generates an AC voltage from the DC power source (solar panel) and delivers power to the AC grid.
In the grid-connected solar inverter, each panel DC voltage is converted into grid compatible AC voltage. Therefore, inverters attached to the panel need to have an
extremely high voltage conversion ratio. Due to high voltage conversion ratio, design of such inverters poses many challenges. For example, a typical panel has an average voltage of 20V and the peak grid voltage is about 340V. It is extremely difficult to achieve such a high conversion ratio in practical scenarios. Additionally, the grid- connected solar inverters need to operate under a wide range of input and output voltages. To achieve this, efforts are continuously being made to design a topology with high efficiency and with a wide range of input operating voltage. One solution to overcome the abovementioned limitations is the use of resonant converters in these solar inverters. A few solutions are available in the market disclosing the use of the resonant converters in the solar inverters. However, the existing solutions suffer from disadvantages such as, less reliability, less efficiency and higher cost. Moreover, the solutions consume a lot of space due to the existing solar inverters configuration.
In light of the foregoing reasons, there is a need for providing an improved topology that includes resonant converters in solar inverter so as to achieve high reliability, high efficiency and low cost. Also, the improved topology should focus on configuring the solar inverter such that less space is consumed. Moreover, the improved topology should have less switching losses and fewer components than the conventional systems. Additionally, the topology should focus on controlling the resonant converters over a wide range of operating conditions efficiently. SUMMARY
An object of the present invention is to provide a method and a system for controlling resonant converters used in solar inverters.
Another object of the invention is to provide an improved topology for use in solar inverters. The topology should preferably have less switching losses and fewer components.
Another object of the invention is to provide a topology for use in solar inverters wherein the topology generates sinusoidal currents and voltages in a transformer.
Yet another objective of the invention is to provide a topology for use in solar inverters wherein the topology controls the circuit over a wide load range and provides high efficiency for a given operating range.
An additional objective of the present invention is to generate power using the controlled resonant converters.
Embodiments of the present invention provide a method for generating power using a controlled resonant converter. The method includes generating a first Direct Current (DC) voltage, the first DC voltage being generated from a DC voltage source. After this, a first Alternating Current (AC) voltage is generated from the first DC voltage using the controlled resonant converter. The controlled resonant converter operates in one or more pre-defined switching modes. Thereafter, the first AC voltage is amplified. The first AC voltage is amplified by a transformer. The amplified AC voltage is then converted to a rectified DC voltage. Lastly, the rectified DC voltage is converted to a second AC voltage, wherein the second AC voltage is synchronized with an AC grid frequency.
Embodiments of the invention provide a system for controlling a resonant converter used in a solar inverter. The resonant converter may be used for generating power. The system includes a Maximum Power Point Tracking (MPPT) calculation module, Phase Locked Loop (PLL) line frequency rectifier, a current regulator and modulator. The MPPT calculation module calculates value of the voltage and current of a DC voltage source corresponding to a maximum power point. The values are calculated to generate a reference current. Further, the PLL line frequency rectifier generates a wave shape of the reference current. Furthermore, the current regulator compares the reference current and a sensed current. The sensed current is collected from an output of the solar inverter. Moreover, the modulator mentioned above generates a plurality of drive signals for controlling the operation of the resonant converter based on the comparison of the reference current and the sensed current. The generated drive signals are then provided to a gate driver. The operation of the resonant converter is controlled by switching the resonant converter in one or more pre-defined switching modes through the drive signals provided by the gate driver.
Embodiments of the present invention provide a method for controlling a resonant converter used in an Alternating Current (AC) module. The method includes generating a reference current based on values of voltage and current of a Direct Current (DC) voltage source and an output of the solar inverter. After this, the reference current is compared with a sensed current. The sensed current is collected from the output of the solar inverter. Once the comparison is performed, a plurality of drive signals is generated for controlling the operation of the resonant converter. Based on the drive signals, the operation of the resonant converter is controlled by switching the resonant converter in one or more pre-defined switching modes. Various examples of the pre- defined switching modes may include, but are not limited to, a full bridge mode, a half bridge mode, a pulse width modulation mode, a pulse skipping mode, and an AC line voltage pulse skipping mode. Finally, the controlled resonant converter may be used for generating power.
BRIEF DESCRIPTION OF THE DRAWINGS
Various embodiments of the present invention will hereinafter be described in conjunction with the appended drawings that are provided to illustrate, and not to limit, the present invention, wherein like designations denote like elements, and in which;
FIG.1 depicts an exemplary inverter circuit of a solar inverter, in which various embodiments of the present invention can be practiced; FIG. 2 is a block diagram illustrating one or more modules of a controller of a resonant circuit, in accordance with an embodiment of the present invention;
FIG. 3 shows variation in the outputs of the modulator with respect to the variation of a control variable at normal load conditions, in accordance with an embodiment of the present invention; FIG. 4 shows another variation in the outputs of the modulator with respect to the control variable at low load conditions, in accordance with an embodiment of the present invention;
FIG. 5a shows a circuit diagram depicting high gain operation of an inverter circuit, in accordance with an embodiment of the present invention;
FIG 5b represents a timing diagram illustrating various signals of the inverter circuit, in accordance with an embodiment of the present invention; FIG. 6a shows a circuit diagram with low gain operation of an inverter, in accordance with an embodiment of the present invention;
FIG. 6b is a timing diagram demonstrating various signals of the inverter circuit, in accordance with an embodiment of the present invention;
FIG. 7a is a timing diagram of the resonant converter operating in a pulse width modulation mode, in accordance with an embodiment of the present invention;
FIG. 7b is a timing diagram of the resonant converter operating in a pulse skipping mode, in accordance with an embodiment of the present invention;
FIG. 7c is a timing diagram of the resonant converter operating in an AC voltage pulse skipping mode, in accordance with an embodiment of the present invention; FIG. 8 is a flow chart for controlling resonant converters used in solar inverters, in accordance with an embodiment of the present invention; and
FIG. 9 depicts a flow chart for generating power using a controlled resonant converter, in accordance with an embodiment of the present invention.
Skilled artisans will appreciate that the elements in the figures are illustrated for simplicity and clarity to help improve the understanding of the embodiments of the present invention and are not intended to limit the scope of the present invention in any manner whatsoever.
DETAILED DESCRIPTION OF THE INVENTION
FIG.1 depicts an exemplary inverter circuit 100 of a solar inverter in which various embodiments of the invention can be practiced. The inverter circuit 100 includes a
bridge inverter 102, a resonant tank circuit 104, a transformer 106, a bridge rectifier 108, an unfolder device 1 10, a controller 112 and a DC/DC resonant converter 114. The inverter circuit 100 is provided with an input DC voltage Vdc. The input voltage Vdc may be generated from various sources such as, but not limited to, a solar panel, one or more solar photovoltaic cells, a fuel cell, a battery, a super capacitor, and other DC power supply. In accordance with an embodiment of the present invention, the input voltage may also be referred to as a first DC voltage. The DC/DC resonant converter 114 may hereinafter be referred to as resonant converter/resonant circuit.
The bridge inverter 102 is formed by one or more power switches S1 , S2, S3, and S4 (collectively referred to as switches i.e. S1-S4). The power switches S1-S4 may be fully controllable semiconductor switches, for example, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). In accordance with one embodiment of the present invention, the semiconductor switches may be chosen so as to have less resistance and less gate charge than the traditional systems for better efficiency. Further, an inductor Ls of the resonant circuit may be selected to have very low losses or very high Q factor. Each power switch of S1-S4 includes one or more anti-parallel diodes D1 , D2, D3, and D4, respectively (collectively referred to as diodes D1-D4). The anti-parallel diodes D1- D4 represent parasitic elements contained within the power switches S1-S4.
As shown in FIG. 1 , the resonant tank circuit 104 is formed by an inductor Ls, a capacitor Cs, and a capacitor Cp. The inductor Ls is connected in series with the capacitor Cs and in parallel with the capacitor Cp In accordance with another
embodiment of the invention, the inductor U may be connected in series with the capacitor Cs , and this configuration is known as a series resonant configuration. In accordance with a further embodiment of the invention, the inductor Ls may be connected in series with the capacitor Cp connected in parallel with the transformer, and this combination may further be connected in series with the capacitor Csas shown in the FIG. 1. In accordance with a further embodiment of the invention, the inductor Ls may be connected in series with the capacitor Cs and an inductor Lp (not shown in the figure). This combination may further be connected in parallel across the primary winding of the transformer (LLC resonant).
In accordance with various embodiments of the present invention, various designs of components of the resonant tank circuit 104 are described herein. In one embodiment, air core or gapped ferrite cores may be used for designing the resonant inductors Ls and inductor Lp. In another embodiment, a custom ferrite core with toroid shape with distributed air gap may be used for designing the resonant inductors Ls and inductor Lp. Herein, the air gap is uniformly distributed so that the core losses are reduced significantly. In further embodiments, the capacitors Cp and Csmay be designed using a combination of one or more ceramic or film capacitors. In yet further
embodiment of the present invention, the capacitors Cp and Cs may be designed using a combination of polypropylene film capacitors. Such capacitors have very low losses and show stable capacitance over a range of temperature and voltage.
Although the resonant tank circuit 104 in the inverter circuit 100 is formed by using LSCSCP passive elements, it will be apparent to a person skilled in the art that the resonant tank circuit 104 may also be formed by using other possible sets of passive elements, for example, LLC, without departing from the scope of the invention in any manner.
As shown in the figure, the transformer 106 is connected to the resonant tank circuit 104 through its primary winding, and transfers power to a load according to the switching of the bridge inverter 102. The secondary winding of the transformer is connected to the diodes D5-D8 (as shown in FIG. 1) of the bridge rectifier 108. In accordance with an embodiment of the present invention, the transformer 106 may be a center tapped transfomier. .
The transformer 106 may have a turns ratio equal to half of the maximum AC output to minimum DC input voltage. In accordance with another embodiment of the present invention, the transformer 106 may have a turns ratio equal to two times the maximum AC output voltage to minimum DC input voltage. The turns ratio of the transformer 106 may vary with the configuration of the inverter circuit 100 as shown in FIG. 1.
As depicted in FIG. 1 , the bridge rectifier 108 is formed by diodes D5, D6, D7, and D8 (collectively referred to as diodes, i.e. D5-D8). The unfolder device 1 10 is formed by one or more switches shown as S5, S6, S7, and S8 (collectively referred to as switches i.e. S5-S8). In accordance with an embodiment of the present invention, the bridge rectifier
108 may be formed with two diodes or four diodes, depending on the transformer configuration. In accordance with an embodiment of the present invention, the unfolder device 110 may be formed using two MOSFETs or four MOSFETs.
In accordance with an embodiment of the present invention, the bridge inverter 102, the resonant tank circuit 104, the transformer 106, and the bridge rectifier 108 together form a DC/DC resonant converter 114. The DC/DC resonant converter 114 converts the first DC voltage (Vdc) into a first AC voltage which is amplified and then converted to a second DC voltage with a rectified sinusoidal wave shape. The rectified sinusoidal DC voltage is also referred to as a pulsating DC voltage. Moreover, FIG. 1 shows a capacitor C connected to the output of the bridge rectifier 108. The function of the capacitor is to filter out the switching frequency harmonics from the second DC voltage. The voltage across the capacitor C is then directed to the unfolder device 110, which converts the second DC voltage with a rectified sinusoidal wave shape into a second AC voltage which is synchronized so as to provide input to an AC grid source. It is thus evident that the unfolder device 110 is operated by switching at the output AC grid voltage frequency. It will be apparent to a person skilled in the art that any suitable controllable switch can be used to unfold the rectified DC voltage waveform on alternate half cycles into the AC source. For example, the switches S5-S8 may be MOSFETs, Bipolar Junction Transistors (BJT), and the like. In accordance with an embodiment of the present invention, the solar inverter may be operated in one or more pre-defined connection modes. The pre-defined connection modes may be, but are not limited to, a stand-alone mode and a grid- connected mode. When the solar inverter is tied in a grid-connected mode, the AC voltage across the AC grid is sensed and the gate signals are derived from alternate zero crossings of the sensed AC voltage. When the solar inverter is operated in the
stand-alone mode, the switches S5-S8 are synchronized with the reference current wave shape generated by the Phase Locked Loop (PLL) as shown in FIG. 2.
Additionally, the controller 112 of FIG. 1 generates plurality of drive signals which are further provided to the DC/DC resonant converter 114. The output of the DC/DC resonant converter 114 varies with the change in the switching frequency of the drive signals and further changes by varying the pulse width at light load conditions or at low output voltages. The detailed working of the controller 12 is explained below in conjunction with FIG. 2.
In accordance with an embodiment of the present invention, the inverter circuit 100 as explained above may be a part of a solar inverter. In the solar inverter, the input is connected to the DC voltage source (Vdc). In accordance with another embodiment of the present invention, the solar inverter may be used independently to generate an AC output from the DC voltage source VdC In accordance with a further embodiment of the present invention, a number of solar inverters may be connected in parallel with each other, and the output of each solar inverter may be provided to a load, for example, to an electrical supply of a building/household.
During the operation, the bridge inverter 102 of the DC/DC resonant converter 1 4 operates in one or more pre-defined switching modes. The one or more pre-defined switching modes may include, but are not limited to, a full bridge mode, a half bridge mode, a pulse width modulation mode, a pulse skipping mode, and an AC line voltage pulse skipping mode. The DC/DC resonant converter 114 may simply be referred to as a resonant converter. The resonant converter may operate in the pre-defined switching modes based on the gain required during the generation of the rectified sinusoidal envelope at the output of the unfolder device 110. When the input DC voltage is low and generated output voltage needs to be high (the gain from output to input voltage requirement is high), then the converter operates in full bridge mode. In the same circuit, when the gain requirement changes due to higher voltage input available to the solar panel and less output voltage required (low voltage gain from output to input), then the converter operates in half bridge mode. During the peak of the sine wave (sinusoidal envelope), the resonant converter operates in the full bridge mode. When the gain falls
below half of its peak value, one of the power switches of the bridge inverter 102 is switched off. For instance, if S4 is switched on and S3 is switched off, the resonant converter/circuit operates in the half bridge mode.
Additionally, the gain of the inverter circuit 100 is controlled by the controller 112 by producing a variable switching frequency that switches the resonant converter to operate in at least one of the above switching modes. In each of the above mentioned switching modes, there are four switching configurations of the bridge inverter 102 that are described in detail in conjunction with circuit diagrams of 5a, 6a, and timing diagrams 5b and 6b. In accordance with an embodiment of the present invention, the methodology of the present invention may be implemented for, but not limited to, micro-inverters and string inverters. Micro-inverters comprise one inverter per solar panel, whereas string inverters comprise one inverter for multiple solar panels.
The present invention as described above facilitates the use of load resonant converters in solar inverters with a control technique that provides a wide range of loads and input voltages. The control technique of the present invention provides precise voltage control under a wide range of load variations. Additionally, high efficiency operation for solar inverters is achieved through a zero-voltage-switching or "soft switching" techniques. During the operation of the circuit using the zero-voltage- switching technique, the power switches S1-S4 are switched on to provide a current flowing path of energy in the transformer. By using an appropriate switching frequency and anti-parallel diodes D1-D4 of the power switches S1-S4, a zero voltage is maintained across the power switches before these switches are switched on. The use of a load resonant circuit facilitates the DC/DC resonant converter of the solar inverter to operate above the resonant frequency of the LC tank circuit. In the resonant operation, an increase in the switching frequency causes a decrease in the voltage across the transformer. The improved topology provided for use in solar inverters has less switching loses and a fewer number of components than used in the traditional systems.
For one ordinary skilled in the art, it is understood that the use of resonant converters is not limited only to solar inverters. There can be many other possible systems where the resonant converter can be used and controlled.
FIG. 2 is a block diagram illustrating one or more modules of the controller 112 of resonant circuit 114, in accordance with an embodiment of the present invention. As mentioned above, the inverter circuit 100 includes the DC/DC resonant converter 114, the unfolder device 110, and the controller 112. To further elaborate, the controller 112 includes a Maximum Power Point Tracking (MPPT) calculation module 202, a Phase Locked Loop (PLL) line frequency rectifier 204, a current regulator 206, a modulator 208, a first gate driver 210, a zero crossing detector 212, and a second gate driver 214.
The controller 112 provides control to the inverter circuit 100 and provides regulation which drives the DC/DC resonant converter 114 to operate in the pre-defined switching modes as discussed above. The control operation begins by sensing the current Isens at the output of the unfolder device 110. The current Isens is provided to the current regulator 206 that compares the sensed current Isens and a reference current lset- The magnitude/value of the reference current lset is calculated by the MPPT calculation module 202. The MPPT calculation module 202 calculates and locks the input voltage and current from the DC voltage source, such as a solar panel, to its maximum power point (or value). Further, the wave shape of the reference current lset is generated from the PLL line frequency rectifier 204. The PLL line frequency rectifier 204 receives an input signal from the AC line voltage from the AC grid. The PLL line frequency rectifier 204 locks the phase of the supplied AC line voltage and generates the wave shape for the reference signal. The magnitude and the wave shape generated by the MPPT calculation module 202 and PLL line frequency rectifier 204, respectively, are multiplied by a multiplier (as shown in FIG.2), generating the reference current t It will be apparent to a person skilled in the art that the reference current is the desired current flowing through a load.
The reference current lset and sensed current Isens are further applied to the current regulator 206 which compares the sensed current Isens with the reference current lset, providing a regulated current at the output. Subsequently, the output generated from
the current regulator 206 is provided to the modulator 208. The modulator 208 generates output signals including a duty 1 cycle signal, a duty 2 cycle signal, a frequency signal and a pulse skip signal. In accordance with an embodiment of the invention, Duty 1 cycle signal is the duty cycle of the first switching leg of the switching source comprising S1 and S2. Duty 2 cycle signal is the duty cycle of the second switching leg of the switching source comprising S3 and S4. Further, the frequency signal represents the switching frequency of the input bridge and the pulse skip signal is utilized for generating pulse skipping at very low output power. A combination of the pre-defined switching modes can be used for operating the resonant converter 114 to generate output with a high efficiency. The output of the modulator 208 is provided to the first gate driver 210 which controls the switches S1-S4 to operate in accordance with one or more of the switching modes as discussed above. Moreover, the pre-defined operation switching modes of the resonant converter are described below in greater detail.
FIG. 3 shows variation in the outputs of the modulator with respect to the variation of a control variable at normal load conditions, in accordance with an embodiment of the present invention. FIG. 3 is shown to depict the duty 1 cycle signal, the duty 2 cycle signal, and the frequency signal. The mentioned signals are plotted against the control variable across the full bridge mode, the half bridge mode, and the pulse width modulation mode. The control variables may be at least one of current and voltage. FIG. 4 shows another variation in the outputs of the modulator with respect to the control variable at low load conditions, in accordance with an embodiment of the present invention. FIG. 4 shows a pulse skip signal, a duty 1 cycle signal, a duty 2 cycle signal, and a frequency signal. These signals are plotted against the control variable in the full bridge mode, half bridge mode, pulse width modulation mode, pulse skipping mode and AC line voltage pulse skipping mode.
In accordance with various embodiments of the present invention, the pre-defined switching modes of the resonant converter 100 will be defined herein. In a full bridge mode, each of the switches S1-S4 is operational and the duty cycle achieved for the top for example, S1 , and the bottom switches, for example S4 are close to 50%. The
operation in the full bridge mode and the gating sequence of switches are illustrated in FIG. 5a and FIG. 5b.
In a half bridge mode, the switch S2 is kept OFF and the switch S3 is kept ON, such that the bridge inverter 102 operates similar to a half bridge converter. The duty cycle achieved for the operation of S1 and S4 in this mode is close to 50%. The operation in the half bridge mode and the gating sequence of switches are illustrated in FIG. 6a and Fig. 6b.
In an AC line voltage pulse skipping mode, the resonant converter is completely switched off for some of the line voltage cycles. This increases the efficiency at light loads.
FIG. 5a shows a circuit diagram depicting high gain operation of an inverter circuit, in accordance with an embodiment of the present invention. Typically, the high gain operation includes four operating switching configurations of the inverter circuit, i.e., 502, 504, 506, and 508 (collectively referred to as 502-508). While operating in the first switching configuration 502, power switches S1 and
S4 are switched on. Accordingly, the current flows through power switch S1, inductor LS) capacitor Cs, power switch S4, and back to the supply. During the operation of the bridge inverter 102 in a second switching configuration 504, all the power switches S1- S4 are turned off and the current freewheels through the diodes D2 and D3. In a third switching configuration 506, power switches S2 and S3 are turned on, and the current flows through power switch S3, capacitor Cs, inductor Ls, and power switch S2. Since the voltage across the power switches S2 and S3 is zero due to conduction of current through diodes D2 and D3 (during the operation in second switching configuration 504), the power switches S2 and S3 have zero turn on losses at the time of turn on in the third switching configuration.
Lastly, during the operation in a fourth switching configuration 508, all four power switches S1-S4 are turned off and the current flows through the diode D4, inductor Ls, and diode D1. It will be apparent to a person skilled in the art that the operation of the
bridge inverter 102 continues as described in four switching configurations 502-508 to provide high gain output for each switching cycle. Additionally, the voltage across the power switches S1 and S4 alternates at the time of each switching cycle. For example, after the above operation is completed in four switching configurations 502-508, during the next switching cycle, the voltage becomes zero across the power switches S1 and S4.
FIG 5b represents a timing diagram illustrating various signals of the inverter circuit, in accordance with an embodiment of the present invention. The timing diagram includes representations of a first signal 510, a second signal 512, and a third signal 514.
The gate voltages across each power switch S1 and S4 are collectively referred to as Vgi-Vg4. The first signal 510 shows gate voltage Vg and Vg4 across power switches S1 and S4 during the operation of the inverter circuit 100 in the first switching configuration 502, for which the power switches S1 and S4 are turned on. Similarly, the second signal 512 shows gate voltage Vg2 and Vg3 across power switches S2 and S3, respectively, during the operation of the inverter circuit 100 in the third switching configuration 506, for which the power switches S2 and S3 are turned on. The third signal 514 shows a current waveform l| and a pulse stream that represents voltage VAB provided to the primary winding of the transformer 106. The voltage VAB is the difference between the voltages of the first signal 510 and the second signal 512. Additionally, the current waveform is the AC waveform that is generated corresponding to the four operating switching configurations 502-508 of the inverter circuit 100. Current waveform li is a time-varying current across the transformer 106.
The voltage pulse stream and current waveform li as illustrated in the third signal 514 is based on the four operating switching configurations 502-508. For example, during the first switching configuration 502, when the power switches S1 and S4 are conducting, the voltage across the transformer 106 rises to VP. The current across the power switches rises and flows in a positive cycle. Further, during the third switching configuration 506, when the power switches S2 and S3 are conducting, the voltage and current across the transformer 106 alternate in phases; but with the same magnitude.
While the circuit operates in the second switching configuration 504 and the fourth switching configuration 508, the parasitic current flows through the anti-parallel diodes D2-D3 and D1-D4 respectively. Therefore, at the time of turn-on (during the first switching configuration 502 and third switching configuration 506), the power switch has zero turn-on losses.
FIG. 6a shows a circuit diagram with low gain operation of an inverter. Typically, the low gain operation includes four operating switching configurations of the inverter circuit, i.e., 602, 604, 606, and 608 (collectively referred to as 602-608).
During the operation in first switching configuration 602, power switches S1 and S4 are switched on. Accordingly, the current flows through power switch S1 , inductor Ls, capacitor Cs, power switch S4, and back to the supply. Further, during the operation of the bridge inverter 102 in the second switching configuration 604, the power switches S1 , S2, and S3 are turned off and the power switch S4 is kept switched on. The current freewheels through the diode D2, inductor Ls, capacitor Cs, and the power switch S4. In the third switching configuration 606, power switches S2 and S4 are switched on, while power switches S1 and S3 are switched off. The current flows through power switch S2, S4, capacitor Cs, and inductor Ls. Since the voltage across the power switch S2 is zero due to conduction of current through diode D2, during the operation in second switching configuration 604, the power switch S2 has zero turn on losses at the time of turn on during the operation in switching configuration 606.
Lastly, during the operation in the fourth switching configuration 608, power switches S1, S2, and S3 are switched off and the power switch S4 is kept switched on. The current flows through the power switch S4 and diode D1. It will be apparent to a person skilled in the art that the operation of the bridge inverter 102 continues as described in four switching configurations 602-608 to provide low gain output for each switching cycle. Additionally, the voltage across the power switch S1 alternates at the time of each switching cycle. For example, after the above operation is completed in four switching configurations 602-608, during the next switching cycle the voltage becomes zero across the power switch S1.
FIG. 6b is a timing diagram demonstrating various signals of the inverter circuit, in accordance with an embodiment of the present invention. The timing diagram includes representations of a first signal 610, a second signal 612, and a third signal 614.
The gate voltages across each power switch S1 , S2, S3 and S4 are referred to as Vg1, Vg2, Vg3 and Vg4 respectively. The first signal 610 shows gate voltage Vgi across power switches S1 during the operation of the inverter circuit of the solar inverter 100 in the first switching configuration 602, for which the power switches S1 and S4 are turned on. Similarly, the second signal 612 shows gate voltage Vg2 across power switch S2 during the operation of the inverter circuit 100 in the third switching configuration 606, for which the power switches S2 and S4 are switched on. The third signal 614 shows a current waveform l| and a pulse stream that represents voltage VAB provided to the primary winding of the transformer 106. The voltage VAB is the difference between the voltages of the first signal 610 and the second signal 612. Additionally, the current waveform \\ is the AC waveform that is generated corresponding to the four operating switching configurations 602-608 of the inverter circuit 100. Current waveform l| is a time-varying current across the transformer 106.
The voltage pulse stream and current waveform as illustrated in the third signal 6 4 are based on the four operating switching configurations 602-608. For example, during the first switching configuration 602, when the power switches S1 and S4 are conducting, the voltage across the transformer 106 rises to Vp. The current across the power switches rises and flows in a positive cycle. During the third switching
configuration 606, when the power switches S2 and S4 are conducting, the voltage and current across the transformer 106 alternate inphase, but with the same magnitude. Additionally, while the circuit operates in the second switching configuration 604 and the fourth switching configuration 608; the parasitic current flows through the anti-parallel diodes D2 and D1 respectively. Therefore, at the time of turn-on (during the first switching configuration 602 and third switching configuration 606), the power switch has zero turn-on losses.
FIG. 7a is a timing diagram of the resonant converter operating in a pulse width modulation mode, in accordance with an embodiment of the present invention. The
timing diagram is shown to represent a first signal 702, a second signal 704, a third signal 706, and a fourth signal 708.
The gate voltages across each power switch S1 , S2, S3 and S4 are referred to as Vgi, Vg2, Vg3, and Vg4 corresponding to the signals 702, 704, 706 and 708 in the FIG. 7a. FIG. 7b is a timing diagram of the resonant converter operating in a pulse skipping mode and half bridge mode in accordance with an embodiment of the present invention. The timing diagram illustrates a first signal 710, a second signal 712, a third signal 714, a fourth signal 716 and a pulse skipping signal 718.
The gate voltages across each power switch S1 , S2, S3 and S4 are referred to as Vg1 i Vg2, Vg3, and Vg4 corresponding to the signals 710, 712, 714 and 716 in the FIG. 7b. Further, the pulse skipping signal 718 is applied in the half bridge mode.
FIG. 7c is a timing diagram of the resonant converter operating in an AC voltage pulse skipping mode and full bridge mode in accordance with an embodiment of the present invention. The timing diagram shows a first signal 720, a second signal 722, and a pulse skipping signal 724.
The gate voltages across each power switch S1-S4 are collectively referred to as gi-Vg4 and correspond to the signal 720. Further, the gate voltages across each power switch S2-S3 are collectively referred to as Vg2-Vg3 and correspond to the signal 722. The circuit operates in pulse width modulation mode as explained in Fig. 7a. The pulse width of the gate signals changes in response to the control variable. If lower current output is required, then the circuit operates in half bridge mode. The gates are either frequency controlled and / or pulse width controlled.
In accordance with an embodiment of the present invention, the circuit operates in pulse skipping mode when it is required to operate the circuit at very low power. When the pulse skipping signal is high, the bridge switches S1 , S2, S3 and S4 continue their . normal operation, for example, the switches operate either in a half bridge mode or a full bridge mode. When the pulse skipping signal is low, then the switches S1 , S2, S3 and
S4 are turned off. This saves power in low power output mode. Further, the pulse skipping signal 724 is applied in the full bridge mode referred to by signals 720 and 722.
FIG. 8 is a flow chart illustrating a method for controlling resonant converters used in solar inverters, in accordance with an embodiment of the present invention. The resonant converter may include one or more inductors, one or more capacitors, and a combination of the inductors and the capacitors.
Initially, at 802, a reference current is generated based on values of voltage and current of a Direct Current (DC) voltage source and an output of the solar inverter. The value of the reference current corresponds to a maximum power point. The maximum power point is the value at which the DC voltage source is operated to ensure maximum power output from the DC voltage source. Further, the wave shape of the reference current is generated by the PLL line frequency rectifier 204. The PLL line frequency rectifier 204 is synchronized with an AC grid. Then, at 804, the reference current is compared with a sensed current. The sensed current is collected from the output of the solar inverter. After performing the comparison, at 806, drive signals are generated by the modulator 208, for controlling the operation of the resonant converter. The operation of the resonant converter is controlled by switching the resonant converter from one predefined switching mode, such as a full bridge switching mode, to another pre-defined switching mode, for example, a half bridge switching mode. Moreover, the resonant converter is controlled to produce a first AC voltage. The method includes controlling the voltage from the DC voltage source by changing the pre-defined switching modes of the resonant converter. Additionally, the method includes determining zero crossing of the output of the solar inverter.
FIG. 9 depicts a flowchart for generating power using a controlled resonant circuit, in accordance with an embodiment of the invention.
To start with, at 902, a first DC voltage is generated by a DC voltage source Vdc of FIG. 1. After this, at 904, a first AC voltage is generated from the first DC voltage. The first AC voltage is generated using the controlled resonant converter. The resonant converter operates in the pre-defined switching modes as described above. Then, at
906, the first AC voltage is amplified, wherein the first AC voltage is amplified by the transformer 106. After amplification, at 908, the amplified first AC voltage is converted to a rectified DC voltage, the conversion being performed by the bridge rectifier 108. The rectified DC voltage is a rectified DC sine wave. Lastly, at step 910, the rectified DC voltage is converted to a second AC voltage to be supplied to the main grid, by unfolding the rectified DC voltage. This is performed by the unfolder device 110. The method includes generating gating signals for the unfolder device 1 0 of the solar inverter.
Moreover, the unfolder device operates in at least one of grid-connected mode and stand-alone mode. The unfolder device 110 operates in the grid-connected mode to determine gate signals at alternate zero crossings. Alternatively, the unfolder device 110 operates in the stand alone mode to synchronize the unfolder current with the reference current.
The present invention described above have numerous advantages. In particular, the present invention provides an improved topology for controlling resonant converters in solar inverters. The improved topology facilitates high efficiency and reliability, reduces cost, and requires less number of components. Since the topology requires less number of components, the solar inverters consume less space. The present invention further focuses on using only one switching stage, which helps in reducing the switching or frequency losses to a great extent. Moreover, the topology focuses on controlling the resonant converters over a wide range of operating conditions efficiently.
The method and the system for controlling resonant converters, or any of its components, as described in the present invention, may be embodied in the form of an embedded controller. Typical examples of embedded controllers include a general- purpose computer, a programmable microprocessor, a micro controller, a peripheral integrated circuit element, ASIC's (Application Specific Integrated Circuit), PLC's
(Programmable Logic Controller), and other devices or arrangements of devices that are capable of implementing the steps that constitute the method for the present invention.
The embedded controller executes a set of instructions (or program instructions) that are stored in one or more storage elements to process the input data. These storage elements can also hold data or other information, as desired, and may be in the
form of an information source or a physical memory element present in the processing machine. The set of instructions may include various commands that instruct the processing machine to perform specific tasks such as the steps that constitute the method for the present invention. The set of instructions may be in the form of a software or firmware program. Further, the software or firmware may be in the form of a collection of separate programs, a program module with a large program, or a portion of a program module.
While various embodiments of the invention have been illustrated and described, it will be clear that the invention is not limited only to these embodiments. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention.