CN2872734Y - Multiple-level converter mixed-pliers position topology - Google Patents
Multiple-level converter mixed-pliers position topology Download PDFInfo
- Publication number
- CN2872734Y CN2872734Y CN 200520015475 CN200520015475U CN2872734Y CN 2872734 Y CN2872734 Y CN 2872734Y CN 200520015475 CN200520015475 CN 200520015475 CN 200520015475 U CN200520015475 U CN 200520015475U CN 2872734 Y CN2872734 Y CN 2872734Y
- Authority
- CN
- China
- Prior art keywords
- tie point
- branch road
- auxiliary capacitor
- parallel
- clamp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The utility model discloses a mixed-clamp multiple-level converter topology for achieving multiple-level topology in combination of active and passive devices. The topology has n levels (n is an integral larger than 2). Each bridge arm includes (n-1) equivalent capacitors, (2n-2) main switch tubes, (2n-4) clamp switch tubes with anti-parallel diodes, (n-2)is multiplied by (n-3) clamp diodes and (n-2) auxiliary capacitors, wherein each main switch tube is an active switch with anti-parallel diode. The utility model can achieve neutral-point voltage balance without the need of additional voltage balancing circuit and independent voltage source under the condition of any load characteristics. The utility model solves the shortcomings of conventional multiple-level topology such as imbalance of capacitor voltage in case of large level number.
Description
Technical field
The utility model relates to many level DCs-ac converter circuit topological structure, is a kind of hybrid clamped multilevel inverter top specifically.
Background technology
Three kinds of traditional multi-level converter topologys all are to utilize a kind of clamping device to realize clamp function, and they all exist certain shortcoming in actual applications.Particularly high level is counted the imbalance problem of capacitance voltage under the situation, becomes the principal element that the restriction multi-level converter is used in practice.In order to address this problem from topology, in the last few years, some novel topology was suggested and studied.Wherein a kind of topology is by realizing clamp jointly with diode and striding capacitance.From the principle of synthesising output voltage, this topology has very big similitude with striding capacitance type topology, and it is synthetic that striding capacitance wherein all participates in voltage.Aspect the capacitance voltage balance, this topology also is that the Redundanter schalter state of output level is realized in the middle of utilizing.So under pure idle situation, can not guarantee the balance of voltage of striding capacitance, can not be used for occasions such as reactive power compensation.Another kind of topology is to realize clamping action jointly by active device and passive diode and electric capacity, and it can both guarantee the self-balancing of capacitance voltage at each on off state, and is not subjected to the influence of load characteristic, can be applied to meritorious and idle conversion occasion.But should topology need a large amount of passive and active devices, this drawbacks limit its application in practice.
Summary of the invention
The purpose of this utility model provides a kind of hybrid clamped multilevel inverter top that number of devices is less, have the capacitance voltage self-balancing ability that uses.
Hybrid clamped multilevel inverter top of the present utility model adopts active device and passive device to realize clamp jointly.
If hybrid clamped multilevel inverter top has the n level, n is the positive integer greater than 2, it is characterized in that each brachium pontis comprises n-1 equivalent capacitance, the individual main switch of 2 (n-1), each main switch is the anti-also active switch of diode of band, the clamp switch pipe of the anti-and diode of the individual band of 2 (n-2), (n-2) * (n-3) individual clamping diode and (n-2) individual auxiliary capacitor
Shunt capacitance branch road and main switch branch road between the positive and negative busbar of each brachium pontis, capacitive branch is made of n-1 equivalent capacitance series connection, main switch props up the active switch series connection anti-and diode of the individual band of route 2 (n-1) and constitutes, this main switch branch road has 2 (n-1)-1 tie point, n-2 in parallel auxiliary capacitor branch road that is connected in series between first tie point and the 2nd (n-1)-1 tie point in the main switch branch road; The anti-also clamp switch that is connected in series of diode of the two ends of each auxiliary capacitor two bands in parallel respectively, wherein the tie point of two the clamp switch pipes in parallel with first auxiliary capacitor is received the tie point of first and second electric capacity in the described capacitive branch; The tie point of two the clamp switch pipes in parallel with second auxiliary capacitor is received the tie point of second and the 3rd electric capacity in the described capacitive branch; The rest may be inferred, and the tie point of two the clamp switch pipes in parallel with n-2 auxiliary capacitor is received the tie point of n-2 and n-1 electric capacity in the described capacitive branch;
The individual clamping diode that is connected in series of 2 (n-3) in parallel between second tie point in the described series connection main switch branch road and the individual tie point of the 2nd (n-2), wherein the tie point of first and second Su position diodes is received the tie point of first and second auxiliary capacitors in the described auxiliary capacitor branch road; The tie point of third and fourth clamping diode is received the tie point of second and the 3rd auxiliary capacitor in the described auxiliary capacitor branch road; The rest may be inferred, and the tie point of the 2nd (n-3)-1 and the individual Su of the 2nd (n-3) position diode is received the tie point of n-3 and n-2 electric capacity in the described auxiliary capacitor branch road;
If i is certain tie point in the 3rd to n-2 the tie point in the described series connection main switch branch road, the individual clamping diode branch road that is connected in series of 2 (n-i-1) in parallel between i tie point and the 2nd (the n-1)-i tie point, 2 (n-i-1)-1 tie point are then arranged in this branch road, if p is the odd number tie point in 2 (n-i-1)-1 tie point, q is the even number tie point in 2 (n-i-1)-1 tie point; P tie point receive in the described series connection main switch branch road between i-1 tie point and the 2nd (the n-1)-i+1 tie point p+1 tie point in the clamping diode branch road in parallel; Q tie point receive in the described series connection main switch branch road between i+1 tie point and the 2nd (the n-1)-i-1 tie point q-1 tie point in the clamping diode branch road in parallel.
N level of hybrid clamped multilevel inverter top output of the present utility model made up by the corresponding on off state of power switch pipe and produces.The self-balancing function of dc-link capacitance voltage is to realize by being connected in parallel of two groups of different dc-link capacitance branch roads and auxiliary capacitor branch road.This balance of voltage method be auxiliary capacitor as intermediary, realize the balance of voltage of dc-link capacitance by it and the parallel connection between different dc-link capacitances.This method does not need complicated control method, is not subjected to the influence of load characteristic, can under variable loads guarantee the balance of voltage of electric capacity.Each active device and passive device in the topology can both directly and indirectly be clamped to the voltage of a level.
Novel combination clamping multi-level converter topology of the present utility model can all guarantee the balance of voltage of electric capacity under any loading condition, can be applied to meritorious and idle conversion occasion.
Description of drawings
Fig. 1 is a hybrid clamped multilevel inverter top circuit diagram of the present utility model, (only having drawn the single armed topological circuit);
Fig. 2 is the circuit diagram of combination clamping type five level single armed topologys;
Embodiment
With reference to Fig. 1, if hybrid clamped multilevel inverter top has the n level, n is the positive integer greater than 2, each brachium pontis comprises n-1 equivalent capacitance, the individual main switch of 2 (n-1), each main switch is the active switch of the anti-and diode of band, the clamp switch pipe of the anti-and diode of the individual band of 2 (n-2), (n-2) * (n-3) individual clamping diode and (n-2) individual auxiliary capacitor.Shunt capacitance branch road and main switch branch road between the positive and negative busbar of each brachium pontis, capacitive branch is made of n-1 equivalent capacitance C1～C (n-1) series connection, main switch props up active switch S1～S2 (n-1) series connection anti-and diode of the individual band of route 2 (n-1) and constitutes, this main switch branch road has 2 (n-1)-1 tie point, n-2 in parallel auxiliary capacitor branch road Cc1～Cc (n-2) that is connected in series between first tie point and the 2nd (n-1)-1 tie point in the main switch branch road; The anti-also clamp switch that is connected in series of diode of the two ends of each auxiliary capacitor two bands in parallel respectively, two clamp switch pipe Sc1 wherein in parallel with first auxiliary capacitor Cc1, the tie point of Sc2 is received first and second capacitor C 1 in the described capacitive branch, the tie point of C2; With second two clamp switch pipe Sc3 that auxiliary capacitor Cc2 is in parallel, the tie point of Sc4 is received second and the 3rd capacitor C 2 in the described capacitive branch, the tie point of C3; The rest may be inferred, and two the clamp switch pipe Sc2s (n-2)-1 in parallel with n-2 auxiliary capacitor Cc (n-2), the tie point of Sc2 (n-2) receive the tie point of n-2 and n-1 electric capacity in the described capacitive branch;
The individual clamping diode Dc1～Dc2 (n-3) that is connected in series of 2 (n-3) in parallel between second tie point in the described series connection main switch branch road and the individual tie point of the 2nd (n-2), first and second Su position diode Dc1 wherein, the tie point of Dc2 is received the tie point of first and second auxiliary capacitors in the described auxiliary capacitor branch road; Third and fourth clamping diode Dc3, the tie point of Dc4 receive the tie point of second and the 3rd auxiliary capacitor in the described auxiliary capacitor branch road; The rest may be inferred, and the tie point of the 2nd (n-3)-1 and the individual Su of the 2nd (n-3) position diode is received the tie point of n-3 and n-2 electric capacity in the described auxiliary capacitor branch road;
If i is certain tie point in the 3rd to n-2 the tie point in the described series connection main switch branch road, the individual clamping diode branch road that is connected in series of 2 (n-i-1) in parallel between i tie point and the 2nd (the n-1)-i tie point, 2 (n-i-1)-1 tie point are then arranged in this branch road, if p is the odd number tie point in 2 (n-i-1)-1 tie point, q is the even number tie point in 2 (n-i-1)-1 tie point; P tie point receive in the described series connection main switch branch road between i-1 tie point and the 2nd (the n-1)-i+1 tie point p+1 tie point in the clamping diode branch road in parallel; Q tie point receive in the described series connection main switch branch road between i+1 tie point and the 2nd (the n-1)-i-1 tie point q-1 tie point in the clamping diode branch road in parallel.
Figure 2 shows that combination clamping type five level single armed topological circuit examples, each brachium pontis comprises 4 equivalent capacitance C1～C4,8 main switch S1～S8, each main switch is the anti-also active switch of diode of band, 6 anti-also clamp switch pipe Sc1～Sc6 of diode of band, 3 * 2 clamping diode Dc1～Dc6 and 3 auxiliary capacitor Cc1～Cc3.
Shunt capacitance branch road and main switch branch road between the positive and negative busbar of each brachium pontis, capacitive branch is made of 4 equivalent capacitance C1～C4 series connection, main switch props up 8 of routes band active switch S1～S8 anti-and diode formation of connecting, this main switch branch road has 7 tie points, 3 auxiliary capacitor branch road Cc1～Cc3 that are connected in series in parallel between first tie point in the main switch branch road and the 7th tie point; The anti-also clamp switch that is connected in series of diode of the two ends of each auxiliary capacitor two bands in parallel respectively, two clamp switch pipe Sc1 wherein in parallel with first auxiliary capacitor Cc1, the tie point of Sc2 is received first and second capacitor C 1 in the described capacitive branch, the tie point of C2; With second two clamp switch pipe Sc3 that auxiliary capacitor Cc2 is in parallel, the tie point of Sc4 is received second and the 3rd capacitor C 2 in the described capacitive branch, the tie point of C3; With the 3rd two clamp switch pipe Sc5 that auxiliary capacitor Cc3 is in parallel, the tie point of Sc6 is received third and fourth capacitor C 3 in the described capacitive branch, the tie point of C4;
4 clamping diode Dc1～Dc4 that are connected in series in parallel between second tie point in the described series connection main switch branch road and the 6th tie point, first and second Su position diode Dc1 wherein, the tie point of Dc2 is received first and second auxiliary capacitor Cc1 in the described auxiliary capacitor branch road, the tie point of Cc2; Third and fourth clamping diode Dc3, the tie point of Dc4 receive second and the 3rd auxiliary capacitor Cc2 in the described auxiliary capacitor branch road, the tie point of Cc3;
2 clamping diode Dc5～Dc6 that are connected in series in parallel between the 3rd tie point in the described series connection main switch branch road and the 5th tie point, the tie point of these 2 series connection clamping diode Dc5～Dc6 is received second tie point in above-mentioned four series connection clamping diode Dc1～Dc4 branch roads.
Master power switch pipe S1～S8 is used for realizing the output voltage expected; Clamp switch pipe Sc1～Sc6 and clamping diode Dc1～Dc6 realize clamp function jointly; Clamp switch pipe Sc1～Sc6 and auxiliary capacitor Cc1～Cc3 can guarantee the balance of voltage of each capacitor C 1～C4 of dc terminal simultaneously.
1. the principle of synthesizing many level
A plurality of level of topology output are that the combination by on off state realizes.The output that obtains expecting, on off state must be observed following rule:
1), four main switches and three clamp switch pipe conductings are simultaneously arranged corresponding to each on off state;
2) first main switch S1 and the 8th the complementary conducting of main switch S8, in these six main switches of seven main switch S2～S7 of second main switch to the, three adjacent continuous conductings of switch, be S1 and S8, S2 and S5, S3 and S6, it is right that S4 and S7 are respectively the switch of complementary work, if a conducting of switch centering, another necessarily turn-offs, and vice versa;
3) the complementary conducting of first main switch S1 and first clamp switch pipe Sc1;
4) among clamp switch Sc1～Sc6, two adjacent switch complementary conductings.
2. the realization of dc-link capacitance voltage self-balancing function
The capacitance voltage self-balancing function of hybrid clamped multilevel inverter top of the present utility model realizes by auxiliary capacitor Cc1～Cc3 and clamp switch Sc1～Sc6.If converter is another on off state by a switch state, two groups of different electric capacity are connected in parallel by clamp switch so.For example, on off state for some S1 conductings, according to above-mentioned switch rule, clamp switch Sc2, Sc4 and Sc6 answer conducting, and this moment, C1 was with Cc1, and C2 is with Cc2, C3 is connected in parallel respectively with Cc3, and two electric capacity that are connected in parallel so can equate by discharging and recharging the voltage trend that makes them: Vc1=Vc
c1, Vc2=Vc
c2, Vc3=Vc
c3; For next on off state, S1 turn-offs, according to above-mentioned switch rule, clamp switch Sc1, Sc3 and Sc5 answer conducting, and this moment, C2 was with Cc1, C3 is with Cc2, C4 is connected in parallel respectively with Cc3, and is same, and two electric capacity of parallel connection can equate by discharging and recharging the voltage trend that makes them: Vc2=Vc
c1, Vc3=Vc
c2, Vc4=Vc
c3.In other words, clamping capacitance can discharge and recharge the balance that guarantees voltage according to the voltage difference with their shunt capacitances.Like this, all dc-link capacitance C1～C4 can by with the balance of voltage of keeping them in parallel of clamping capacitance Cc1～Cc3.
3. the clamp mechanism of switching device and diode
When the main switching device in the hybrid clamped multilevel inverter top turn-offs, all be clamped to corresponding dc-link capacitance jointly, be the voltage swing of an output level by active-clamp switch and passive-clamp diode.Wherein, the first main switch S1, the 8th main switch S8 and six clamp switch pipe Sc1～Sc6 directly are clamped to dc-link capacitance; Second to the 7th main switch S2～S7 and clamping diode Dc1～Dc6 are clamped to dc-link capacitance indirectly by above-mentioned direct clamping device, thereby realize that each device in the topology all is clamped to the size of an output level.
Claims (2)
1. hybrid clamped multilevel inverter top, be provided with the n level, n is the positive integer greater than 2, it is characterized in that each brachium pontis comprises n-1 equivalent capacitance, 2n-2 main switch, each main switch is the anti-also active switch of diode of band, 2n-4 the anti-also clamp switch pipe of diode of band, (n-2) * (n-3) individual clamping diode and n-2 auxiliary capacitor, shunt capacitance branch road and main switch branch road between the positive and negative busbar of each brachium pontis, capacitive branch is made of n-1 equivalent capacitance (C1～C (n-1)) series connection, main switch props up route 2n-2 band active switch (S1～S2 (n-1)) series connection anti-and diode and constitutes, this main switch branch road has 2n-3 tie point, n-2 in parallel auxiliary capacitor branch road (Cc1～Cc (n-2)) that is connected in series between first tie point in the main switch branch road and 2n-3 the tie point; The anti-also clamp switch that is connected in series of diode of the two ends of each auxiliary capacitor two bands in parallel respectively, two clamp switch pipe (Sc1 wherein in parallel with first auxiliary capacitor (Cc1), Sc2) tie point is received first and second electric capacity (C1, tie points C2) in the described capacitive branch; Two the clamp switch pipe (Sc3s in parallel with second auxiliary capacitor (Cc2), Sc4) tie point is received second and the 3rd electric capacity (C2 in the described capacitive branch, C3) tie point, the rest may be inferred, the tie point of two the clamp switch pipes in parallel with n-2 auxiliary capacitor (Cc (n-2)) (Sc (2 (n-2)-1), Sc2 (n-2)) is received the tie point of n-2 and n-1 electric capacity in the described capacitive branch;
2n-6 in parallel clamping diode (Dc1～Dc2 (n-3)) that is connected in series between second tie point in the described series connection main switch branch road and 2n-4 the tie point, wherein (Dc1, tie point Dc2) receive the tie point of first and second auxiliary capacitors in the described auxiliary capacitor branch road to the first and second Ge Clamp-on position diodes; (Dc3, tie point Dc4) receive the tie point of second and the 3rd auxiliary capacitor in the described auxiliary capacitor branch road to third and fourth clamping diode; The rest may be inferred, and the tie point of 2n-7 and 2n-6 Clamp-on position diode is received the tie point of n-3 and n-2 electric capacity in the described auxiliary capacitor branch road;
If i is certain tie point in the 3rd to n-2 the tie point in the described series connection main switch branch road, 2n-2i-2 in parallel clamping diode branch road that is connected in series between i tie point and 2n-2-i the tie point, 2n-2i-3 tie point then arranged in this branch road, if p is 2n-2i-3 the odd number tie point in the tie point, q is 2n-2i-3 the even number tie point in the tie point; P tie point receive in the described series connection main switch branch road between i-1 tie point and 2n-i-1 the tie point p+1 tie point in the clamping diode branch road in parallel; Q tie point receive in the described series connection main switch branch road between i+1 tie point and 2n-i-3 the tie point q-1 tie point in the clamping diode branch road in parallel.
2. many level of combination clamping type topology according to claim 1, it is characterized in that level n is 5, each brachium pontis comprises 4 equivalent capacitances (C1～C4), the main switch of the anti-and diode of 8 bands (S1～S8), anti-and the diode clamp switching tube of 6 bands (Sc1～Sc6), 6 clamping diodes (Dc1～Dc6) and 3 auxiliary capacitors (Cc1～Cc3), shunt capacitance branch road and main switch branch road between the positive and negative busbar of each brachium pontis, (C1～C4) series connection constitutes capacitive branch, and main switch props up the anti-also active switch of diode of 8 bands of route, and (S1～S8) series connection constitutes by 4 equivalent capacitances; 3 auxiliary capacitor branch roads that are connected in series in parallel between first tie point in the described series connection main switch branch road and the 7th tie point (Cc1～Cc3); The clamp switch that is connected in series of the two ends of each auxiliary capacitor two band anti-Bing Clamp-on position diodes in parallel respectively, Liang Clamp-on bit switch (Sc1 wherein in parallel with first auxiliary capacitor (Cc1), Sc2) tie point is received first and second electric capacity (C1, tie points C2) in the described capacitive branch; (Sc3, tie point Sc4) receive second and the 3rd electric capacity (C2, tie point C3) in the described capacitive branch to the Liang Clamp-on bit switch in parallel with second auxiliary capacitor (Cc2); (Sc5, tie point Sc6) receive third and fourth electric capacity (C3, tie point C4) in the described capacitive branch to the Liang Clamp-on bit switch in parallel with the 3rd auxiliary capacitor (Cc3);
4 clamping diodes that are connected in series in parallel between second tie point in the described series connection main switch branch road and the 6th tie point (Dc1～Dc4), the first and second Ge Clamp-on position diode (Dc1 wherein, Dc2) tie point is received first and second auxiliary capacitors (Cc1, tie points Cc2) in the described auxiliary capacitor branch road; (Dc3, tie point Dc4) receive second and the 3rd auxiliary capacitor (Cc2, tie point Cc3) in the described auxiliary capacitor branch road to third and fourth clamping diode;
(Dc5～Dc6), (tie point of Dc5～Dc6) is received above-mentioned four series connection clamping diodes (second tie point in the branch road of Dc1～Dc4) to 2 clamping diodes that are connected in series in parallel between the 3rd tie point in the described series connection main switch branch road and the 5th tie point for these 2 series connection clamping diodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520015475 CN2872734Y (en) | 2005-10-11 | 2005-10-11 | Multiple-level converter mixed-pliers position topology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520015475 CN2872734Y (en) | 2005-10-11 | 2005-10-11 | Multiple-level converter mixed-pliers position topology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2872734Y true CN2872734Y (en) | 2007-02-21 |
Family
ID=37741074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200520015475 Expired - Fee Related CN2872734Y (en) | 2005-10-11 | 2005-10-11 | Multiple-level converter mixed-pliers position topology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2872734Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710162A (en) * | 2012-06-12 | 2012-10-03 | 阳光电源股份有限公司 | Seven-level circuit, grid-connected inverter and modulation method and device for grid-connected inverter |
| CN102710133A (en) * | 2012-06-12 | 2012-10-03 | 阳光电源股份有限公司 | Seven-level circuit, a grid-connected inverter and modulation method and device of seven-level circuit |
| CN109474197A (en) * | 2018-11-12 | 2019-03-15 | 沈阳工业大学 | A kind of more level combination clamping type topological structures of novel large capacity and topological method |
-
2005
- 2005-10-11 CN CN 200520015475 patent/CN2872734Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710162A (en) * | 2012-06-12 | 2012-10-03 | 阳光电源股份有限公司 | Seven-level circuit, grid-connected inverter and modulation method and device for grid-connected inverter |
| CN102710133A (en) * | 2012-06-12 | 2012-10-03 | 阳光电源股份有限公司 | Seven-level circuit, a grid-connected inverter and modulation method and device of seven-level circuit |
| CN102710162B (en) * | 2012-06-12 | 2014-08-06 | 阳光电源股份有限公司 | Seven-level circuit, grid-connected inverter and modulation method and device for grid-connected inverter |
| CN102710133B (en) * | 2012-06-12 | 2014-09-17 | 阳光电源股份有限公司 | Seven-level circuit, a grid-connected inverter and modulation method and device of seven-level circuit |
| CN109474197A (en) * | 2018-11-12 | 2019-03-15 | 沈阳工业大学 | A kind of more level combination clamping type topological structures of novel large capacity and topological method |
| CN109474197B (en) * | 2018-11-12 | 2021-03-26 | 沈阳工业大学 | Novel high-capacity multi-level hybrid clamping type topological structure and topological method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101572503A (en) | Multi-level circuit of universal switch capacitor diode clamping assembly | |
| CN102427304B (en) | Single-phase half-bridge five-level inverter and application circuit thereof | |
| CN101584109B (en) | Drive for a phase module branch of a multilevel converter | |
| CN101262180B (en) | Single-phase circuit topology structure for clamp multi-level converter | |
| CN1060601C (en) | Multi-level inverter | |
| CN104218832B (en) | A kind of single-phase five level topology and inverters | |
| JP5593660B2 (en) | 5 level inverter | |
| CN104410260B (en) | Fault-tolerance-capability-equipped MMC sub-module structure capable of realizing DC fault self-protection, and MMC modulation method thereof | |
| CN102594182A (en) | Multilevel inversion topological unit and multilevel inverter | |
| CN104081649B (en) | The AC/DC multi-unit power transducer that two-terminal HVDC is connected | |
| CN1860673A (en) | Converter circuit for connecting a plurality of switching voltage levels | |
| CN103633872A (en) | Capacitor voltage self-balancing circuit of modularized multi-level converter | |
| CN103250338A (en) | Multi-level voltage converter | |
| CN102097967B (en) | Cascaded multi-level converter | |
| CN1767345A (en) | Hybrid clamped multilevel inverter top | |
| JP2012253981A (en) | Five-level conversion circuit | |
| CN106602912A (en) | Capacitance and voltage self-ordering modular multilevel converter | |
| CN2872734Y (en) | Multiple-level converter mixed-pliers position topology | |
| CN1909346A (en) | Integrated converting means with three-phase activity coefficient adjustment | |
| JP5780907B2 (en) | Power converter | |
| CN201430543Y (en) | Universal switched-capacitor diode-clamping combined multi-level circuit | |
| CN1826722A (en) | Rectifier circuit | |
| CN102427305B (en) | Single-phase half-bridge five-level inverter and application circuit thereof | |
| CN102437769B (en) | Single-phase semi-bridge five-electrical level inverter and its application circuit | |
| CN102664514A (en) | Switch tube unit, five-level inverters and power generation system with same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070221 Termination date: 20141011 |
|
| EXPY | Termination of patent right or utility model |