CN218499004U - Low-inductance DC isolation bus - Google Patents
Low-inductance DC isolation bus Download PDFInfo
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- CN218499004U CN218499004U CN202122667027.4U CN202122667027U CN218499004U CN 218499004 U CN218499004 U CN 218499004U CN 202122667027 U CN202122667027 U CN 202122667027U CN 218499004 U CN218499004 U CN 218499004U
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Abstract
The utility model discloses a low inductance dc busbar that separates, adopt the multilayer conducting layer, two-layer insulating layer that sets up in adjacent conducting layer, with the disconnection of outermost conducting layer or two conducting layers, connect at least one at the disconnection department and separate direct current bus, constitute by multilayer conducting layer and separate direct current bus, adopt this kind to separate direct current bus connection between parallel connection's adjacent power positive input end or between the positive output end, reduce the return circuit inductance between the parallelly connected DCDC, reduce difference frequency oscillation amplitude between the DCDC, improve its resonant frequency, reduce return circuit inductance and resonance Q value.
Description
Technical Field
The utility model belongs to the technical field of bus structure technique and specifically relates to a low sense separates direct current generating line.
Background
At present, in the parallel connection process of high-frequency high-density isolation DCDC, non-isolation DCDC, DCAC and the like, because different converters have different frequencies, or have the same frequency but are asynchronous, when and only when the switching frequency of the converters is close to the resonant frequency of parallel port filter capacitors and loop inductors, because port loops are all low-impedance devices, the Q value of a resonant network is high, the ripple voltage of the ports can be amplified in the phase-staggered process along with the difference frequency after being connected in parallel, according to the difference of the Q values of the loops, the ripple voltage of the difference mode which meets the requirements originally can be amplified to 10-20 times, and extra alternating current loss is increased.
For a high-power density hydrogen power engine DCDC converter, in order to improve power density, power expansion is realized by a multiphase interleaved variable frequency topological scheme design and parallel connection of multiple module units, small loop inductance is realized in a common module through a PCB interlayer, the multiple module units are interleaved for filtering, ripple current is well counteracted, but along with the improvement of module power level, multiple modules are required to be connected in parallel to realize power expansion, extra requirements of a parallel module port and physical dimensions of a parallel bus are not limited to reduce loop inductance, extra requirements comprise a series fuse or a switch device, extra requirements comprise a series fuse and a switch device, physical dimensions comprise a large current-carrying sectional area, an insulating layer and an insulating distance reserved for high voltage, mounting screws preset for assembling and the like, so that the inductance of a parallel port is not small, and because different module working frequencies are asynchronous, a port capacitor connected in parallel with the multiple modules and the inductance of a parallel circuit generate resonance, the resonance frequency is close to the module working frequency, and the port ripple voltage is amplified.
In order to reduce the loop inductance, a blocking capacitor is disposed between positive input ports or positive output ports of adjacent power supplies, but how to dispose the blocking capacitor is an urgent problem to be solved at present.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a low sense separates direct current generating line, adopt the multilayer conducting layer, set up the insulating layer between adjacent conducting layer, with the disconnection of outermost conducting layer or two conducting layers, connect at least one at disconnection place, constitute at a distance from direct current generating line by multilayer conducting layer and at a distance from direct current generating line, adopt this kind to separate direct current generating line to connect between parallel connection's adjacent power positive input end or between the positive output end, reduce the return circuit inductance between the parallelly connected DCDC, reduce difference frequency oscillation amplitude between the DCDC, improve its resonant frequency, reduce return circuit inductance and resonance Q value.
In a first aspect, the above mentioned utility model aims at realizing through following technical scheme:
the utility model provides a low sense dc blocking bus, includes the three-layer insulating layer, between adjacent insulating layer, is provided with the conducting layer, and every conducting layer sets up the end of drawing forth at the both ends of generating line, breaks off in the middle of the first conducting layer, and the both ends of disconnection department are connected the both ends of blocking electric capacity, form the series structure of first conducting layer anterior segment, blocking electric capacity, first conducting layer back end.
In a second aspect, the above object of the present invention can be achieved by the following technical solutions:
the utility model provides a low sense dc blocking bus, including five layers of insulating layers, between adjacent insulating layer, be provided with the conducting layer, every conducting layer sets up the end of drawing forth at the both ends of generating line, break off in the middle of the first conducting layer, form first disconnection department, connect the both ends of first blocking electric capacity respectively at first disconnection department both ends, form the series structure of first conducting layer anterior segment, electric capacity, first conducting layer back end, break off in the middle of the fourth conducting layer, form second disconnection department, connect the both ends of second blocking electric capacity respectively at second disconnection department both ends, form the series structure of fourth conducting layer anterior segment, electric capacity, fourth conducting layer back end.
The utility model discloses further set up to: connecting a leading-out terminal of the first end of the first conductive layer and a leading-out terminal of the first end of the fourth conductive layer together; connecting a leading-out terminal of the first end of the second conducting layer with a leading-out terminal of the first end of the third conducting layer; connecting a leading-out end of the second end of the first conductive layer with a leading-out end of the second end of the fourth conductive layer; and connecting the leading-out terminal of the second end of the second conductive layer and the leading-out terminal of the second end of the third conductive layer together.
The utility model discloses further set up to: the insulating layer adopts flexible insulating material, and the conducting layer adopts the copper layer.
The utility model discloses further set up to: the width of the insulating layer is greater than the width of the conductive layer.
The utility model discloses further set up to: the DC blocking capacitor comprises at least one capacitor, and all capacitors are connected in parallel at the disconnected part of the conductive layer.
The utility model discloses further set up to: the DC blocking capacitor is a ceramic capacitor.
Compared with the prior art, the beneficial technical effects of this application do:
1. the method comprises the steps that a plurality of conductive layers are arranged, a disconnection part is arranged in one or two outermost conductive layers, a blocking capacitor is connected to the disconnection part, the other conductive layers are not disconnected, and the blocking effect is achieved through the blocking capacitor;
2. furthermore, the direct current blocking capacitors are arranged at the disconnection positions of the outermost two layers of the four conductive layers, the ports of the outermost conductive layers are connected together, the ports of the middle conductive layers are connected together, the overcurrent of the bus is increased, and the current is guaranteed to meet the power requirement;
3. furthermore, the blocking capacitor is added on the conducting layer, so that when multiple DCDC power supplies are connected in parallel, if the power supplies are short-circuited, the work of other power supplies cannot be influenced.
Drawings
FIG. 1 is a schematic diagram of a DC blocking bus bar structure with double copper layers according to an embodiment of the present application;
FIG. 2 is a front view of the dual copper layer DC blocking bus bar of the present application;
FIG. 3 is a side view of a dual copper layer DC blocking bus bar of the present application;
FIG. 4 is a cross-sectional view of a dual copper layer DC blocking bus bar of the present application;
FIG. 5 is a schematic diagram of a DC blocking bus bar structure with four copper layers according to an embodiment of the present application;
FIG. 6 is a front view of a four copper layer DC blocking bus bar of the present application;
FIG. 7 is a side view of a four copper layer DC blocking bus bar of the present application;
fig. 8 is a cross-sectional view of a four copper layer dc blocking busbar of the present application.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Detailed description of the preferred embodiment
The low-inductance DC blocking bus comprises three insulating layers and two copper layers, wherein a copper layer is arranged between every two adjacent insulating layers, a leading-out end 11 and a leading-out end 12 are respectively arranged at two ends of the first copper layer, and a leading-out end 111 and a leading-out end 112 are respectively arranged at two ends of the second copper layer, as shown in figures 1 and 2.
The two leading-out ends of the first copper layer and the two leading-out ends of the second copper layer are arranged in a staggered mode so as to be connected with the circuit board and an external connecting wire conveniently.
As shown in fig. 3 and 4, a first copper layer is disposed between the first insulating layer and the second insulating layer 18, and a second copper layer 19 is disposed between the second insulating layer 18 and the third insulating layer 110.
A break is provided in the first insulating layer at the same location as the first copper layer, dividing the first insulating layer into two parts, a first front insulating layer section 13 and a first rear insulating layer section 15, respectively, and correspondingly dividing the first copper layer into two parts, a first front copper layer section 16 and a first rear copper layer section 17, respectively.
A blocking capacitor 14 is arranged at the disconnected position of the first copper layer, two ends of the blocking capacitor 14 are respectively connected with a first copper layer front section 16 and a first copper layer rear section 17 to form a series structure of the first copper layer front section, the blocking capacitor and the first copper layer rear section, and the blocking capacitor 14 adopts a chip capacitor.
The widths of the two copper layers are the same or different, the widths of the three insulating layers are larger than those of the copper layers, and the insulating layers are made of flexible insulating materials. The flexible insulating material comprises polyimide.
The number of the blocking capacitors is set according to the overcurrent requirement of the bus.
The blocking capacitor is a ceramic capacitor.
When the blocking direct current bus is applied to the bypass capacitor bus in the state that a plurality of DCDC power supplies are connected in parallel, the loop inductance between the parallel DCDCDCDCDCDCDCs can be reduced, the difference frequency oscillation amplitude between the DCDCDCs is reduced, the resonance frequency of the DCDCDCs is improved, the loop inductance and the resonance Q value are reduced, the blocking effect is realized by increasing the blocking capacitor, when one path of the DCDC power supplies is short-circuited, the work of the other DCDC power supplies is not influenced, the short-circuit DC-DC power supplies are connected in parallel, the open-circuit protection is realized from a power level port fuse wire, and the low-inductance blocking direct current bus realizes the open circuit through the blocking capacitor.
Detailed description of the preferred embodiment
The low-inductance DC blocking bus comprises five insulating layers and four copper layers, wherein each copper layer is arranged between adjacent insulating layers, a leading-out end 21 and a leading-out end 22 are respectively arranged at two ends of a first copper layer, a leading-out end 221 and a leading-out end 222 are respectively arranged at two ends of a second copper layer, a leading-out end 231 and a leading-out end 232 are respectively arranged at two ends of a third copper layer, and a leading-out end 241 and a leading-out end 242 are respectively arranged at two ends of a fourth copper layer, as shown in FIGS. 5 and 6.
The leading-out end 21, the leading-out end 221, the leading-out end 231 and the leading-out end 241 are positioned at the first end of the isolated direct current bus and are arranged in a staggered manner; the leading-out terminal 22, the leading-out terminal 222, the leading-out terminal 232 and the leading-out terminal 242 are positioned at the second end of the DC blocking bus and are arranged in a staggered mode.
As shown in fig. 7 and 8, a first copper layer is disposed between the first insulating layer and the second insulating layer 26, a second copper layer 27 is disposed between the second insulating layer 26 and the third insulating layer 28, a third copper layer 29 is disposed between the third insulating layer 28 and the fourth insulating layer 210, and a fourth copper layer is disposed between the fourth insulating layer 210 and the fifth insulating layer.
At the same position of the first insulating layer and the first copper layer, a first break is provided, which divides the first insulating layer into two parts, namely a first insulating layer front section 23 and a first insulating layer rear section 25, respectively, and correspondingly, divides the first copper layer into two parts, namely a first copper layer front section 216 and a first copper layer rear section 217, respectively.
And arranging a blocking capacitor 24 at a first disconnected position of the first copper layer, wherein two ends of the blocking capacitor 24 are respectively connected with the first copper layer front section 216 and the first copper layer rear section 217 to form a series structure of the first copper layer front section, the blocking capacitor and the first copper layer rear section.
Similarly, a second break is provided at the same position of the fifth insulating layer and the fourth copper layer 211, and the second break divides the fifth insulating layer into two parts, namely, a front fifth insulating layer 213 and a rear first insulating layer 215, and correspondingly, divides the fourth copper layer into two parts, namely, a front fourth copper layer and a rear fourth copper layer.
And a blocking capacitor 214 is arranged at a second disconnected position of the fourth copper layer, and two ends of the blocking capacitor 214 are respectively connected with the front section of the fourth copper layer and the rear section of the fourth copper layer to form a series structure of the front section of the fourth copper layer, the blocking capacitor and the rear section of the fourth copper layer.
The first copper layer leading-out terminal 21 and the fourth copper layer leading-out terminal 241 at the first end of the DC blocking bus bar are connected together, and the second copper layer leading-out terminal 221 and the third copper layer leading-out terminal 231 are connected together and respectively used as two leading-out terminals at the first end of the DC blocking bus bar.
The first copper layer terminal 22 and the fourth copper layer terminal 242 at the second end of the dc blocking bus bar are connected together, and the second copper layer terminal 222 and the third copper layer terminal 232 are connected together as two terminals of the second end of the dc blocking bus bar.
In the present embodiment, the copper layer is used as the conductive layer, and the like are repeated for conductive layers made of other conductive materials.
The embodiment of this specific implementation mode is the preferred embodiment of the present invention, not limit according to this the utility model discloses a protection scope, so: all equivalent changes made according to the structure, shape and principle of the utility model are covered within the protection scope of the utility model.
Claims (7)
1. The utility model provides a low sense separates direct current generating line which characterized in that: the insulating layer comprises three insulating layers, conducting layers are arranged between the adjacent insulating layers, leading-out ends are arranged at two ends of a bus of each conducting layer, the middle of the first conducting layer is disconnected, two ends of the disconnected part are connected with two ends of a blocking capacitor, and a series structure of a front section of the first conducting layer, the blocking capacitor and a rear section of the first conducting layer is formed.
2. The utility model provides a low inductance separates direct current generating line which characterized in that: the insulating layer structure comprises five insulating layers, wherein conducting layers are arranged between adjacent insulating layers, leading-out ends are arranged at two ends of a bus of each conducting layer, the middle of the first conducting layer is disconnected to form a first disconnection part, two ends of the first disconnection part are respectively connected with two ends of a first blocking capacitor to form a series structure of a front section of the first conducting layer, a capacitor and a rear section of the first conducting layer, the middle of the fourth conducting layer is disconnected to form a second disconnection part, two ends of the second disconnection part are respectively connected with two ends of a second blocking capacitor to form a series structure of a front section of the fourth conducting layer, a capacitor and a rear section of the fourth conducting layer.
3. The low-inductance DC blocking bus bar of claim 2, wherein: connecting a leading-out terminal of the first end of the first conductive layer and a leading-out terminal of the first end of the fourth conductive layer together; connecting the leading-out end of the first end of the second conducting layer with the leading-out end of the first end of the third conducting layer; connecting a leading-out terminal of the second end of the first conductive layer with a leading-out terminal of the second end of the fourth conductive layer; and connecting the leading-out terminal of the second end of the second conductive layer and the leading-out terminal of the second end of the third conductive layer together.
4. The low-inductance DC blocking bus bar according to claim 1 or 2, characterized in that: the insulating layer is made of flexible insulating materials, and the conducting layer is made of copper layers.
5. The low-inductance DC blocking bus bar according to claim 1 or 2, characterized in that: the width of the insulating layer is greater than the width of the conductive layer.
6. The low inductance dc blocking dc bus according to claim 1 or 2, wherein: the blocking capacitor comprises at least one capacitor, and all capacitors are connected in parallel at the disconnection of the conductive layer.
7. The low inductance dc blocking dc bus according to claim 1 or 2, wherein: the blocking capacitor is a ceramic capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122667027.4U CN218499004U (en) | 2021-11-02 | 2021-11-02 | Low-inductance DC isolation bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122667027.4U CN218499004U (en) | 2021-11-02 | 2021-11-02 | Low-inductance DC isolation bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218499004U true CN218499004U (en) | 2023-02-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122667027.4U Active CN218499004U (en) | 2021-11-02 | 2021-11-02 | Low-inductance DC isolation bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218499004U (en) |
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2021
- 2021-11-02 CN CN202122667027.4U patent/CN218499004U/en active Active
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