CN203761293U - Single-phase three-level-inverter neutral point potential balance controller - Google Patents
Single-phase three-level-inverter neutral point potential balance controller Download PDFInfo
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- CN203761293U CN203761293U CN201420100302.1U CN201420100302U CN203761293U CN 203761293 U CN203761293 U CN 203761293U CN 201420100302 U CN201420100302 U CN 201420100302U CN 203761293 U CN203761293 U CN 203761293U
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Abstract
The utility model relates to a single-phase three-level-inverter neutral point potential balance controller. A single-phase three-level-inverter comprises an inverter control loop and an inverter main loop with a switch device control port. The inverter main loop comprises a left bridge arm possessing a first left switch device to a fourth left switch device and a right bridge arm possessing a first right switch device to a fourth right switch device. The controller comprises a voltage/current detection unit, a neutral point potential balance control unit and a pulse control unit, wherein the voltage/current detection unit is connected to the inverter main loop; the neutral point potential balance control unit is connected to the voltage/current detection unit; the pulse control unit is connected to the neutral point potential balance control unit. The controller works when the inverter carries out motion. A large power device is not increased, a product cost and a size are not increased and a purpose of restraining a neutral point potential offset in real time is reached.
Description
Technical field
The utility model relates to electric and electronic technical field, relates in particular to a kind of single-phase three-level inverter midpoint potential balance controller.
Background technology
As everyone knows, three level structures have and reduce harmonic wave of output voltage content, improve output voltage grade, reduce output filter size and reduce the advantages such as voltage stress that switching tube bears, therefore, more and more be used in recent years the fields such as AC voltage adjusting, speed governing and UPS, and become gradually the hot subject of research.
Yet, capacitor voltage equalizing problem is the significant obstacle of restriction three level structural circuit application always, wherein, DC bus-bar voltage mid-point potential offset can affect the symmetry of output voltage, the requirement of withstand voltage that improves main switch, increase harmonic wave of output voltage content, the every advantage of three level is degenerated to two level.Therefore the balance that, an important topic in three-level inverter research is exactly midpoint potential is controlled.
Aspect the three-level inverter midpoint potential balance control of prior art, Chinese patent < < inhibition three-level inverter mid-point potential offset device > > (patent No. ZL201220448570.3), a kind of device that suppresses three-level inverter mid-point potential offset is disclosed, this device needs to add more high performance components on hardware, comprise IGBT, diode and inductance etc., thereby increased the volume of whole inverter, and the hardware cost of this device can increase along with the raising of inverter power grade.
In addition, the control method > > (application number 201310312771.X) of DC side midpoint potential balance in Chinese patent application < < NPC tri-level structures, a kind of control method of NPC tri-level structure DC side midpoint potential balances is disclosed, it is regulating measure that the method be take each sector redundancy small vector in space vector pulse width modulation (SVPWM), calculate the interior redundancy small vector of the switch periods allocation proportion of action time, with this alignment current potential, control, the control algolithm of this patent application is complicated, increased software overhead.
Therefore, three-level inverter midpoint potential balance control field is needed a kind of mid-point potential offset that can effectively suppress badly can too much not increase again the control device of product cost and volume.
Utility model content
The problem existing in order to solve above-mentioned prior art, the utility model aims to provide a kind of single-phase three-level inverter midpoint potential balance controller, to realize, can effectively suppress mid-point potential offset and can too much not increase again the object of product cost and volume.
A kind of single-phase three-level inverter midpoint potential balance controller described in the utility model, described single-phase three-level inverter comprises inverter control loop and with the inverter major loop of switching device control port, wherein, described inverter major loop comprises: the left brachium pontis with the first left-handed opening device to the four left-handed opening devices, and the right brachium pontis with the first right switching device to the four right switching devices, it is characterized in that, described controller comprises:
With the voltage/current detection unit that described inverter major loop is connected, it gathers DC bus-bar voltage signal, mid-point voltage signal, the load current signal that flows through load and the zero current signal of described inverter major loop, and is exported;
The midpoint potential balance control unit being connected with described voltage/current detection unit, it receives described DC bus-bar voltage signal, mid-point voltage signal, load current signal and zero current signal, and exports corresponding balance enable signal; And
The pulse control unit being connected with described midpoint potential balance control unit, it receives first left modulation signal to the four left modulation signal and first right modulation signal to the four right modulation signal corresponding with described the first left-handed opening device to the four left-handed opening devices and the right switching device of the first right switching device to the four respectively of described balance enable signal and described inverter control loop output, and the left correction modulation signal of the first left correction modulation signal to the four and the right correction modulation signal of the first right correction modulation signal to the four that to described switching device control port output, for alignment current potential, carry out balance control.
In above-mentioned single-phase three-level inverter midpoint potential balance controller,
Described midpoint potential balance control unit comprises:
Signal comparator circuit, it receives described DC bus-bar voltage signal, mid-point voltage signal, load current signal and zero current signal, and export the too high signal of midpoint potential, midpoint potential is crossed low signal and load current direction signal;
Circuit is selected in the correction being connected with described signal comparator circuit, and it receives the too high signal of described midpoint potential, midpoint potential is crossed low signal and load current direction signal, and exports described balance enable signal;
Described pulse control unit comprises:
Logic judging circuit, it receives first left modulation signal to the four left modulation signal and first right modulation signal to the four right modulation signal corresponding with described the first left-handed opening device to the four left-handed opening devices and the right switching device of the first right switching device to the four respectively of described balance enable signal and described inverter control loop output, and output multi-channel is selected signal;
The modulation signal correction circuit being connected with described logic judging circuit, it receives described multichannel and selects signal, described the first left modulation signal of left modulation signal to the four and the right modulation signal of the first right modulation signal to the four, and exports the left correction modulation signal of described the first left correction modulation signal to the four and the right correction modulation signal of the first right correction modulation signal to the four.
In above-mentioned single-phase three-level inverter midpoint potential balance controller, described signal comparator circuit comprises:
The first comparator, its positive input terminal receives described mid-point voltage signal, and its negative input end receives described DC bus-bar voltage signal by the first resistance on the one hand, and by the second adjustable resistance ground connection, its output is exported the too high signal of described midpoint potential on the other hand;
The second comparator, its negative input end receives described mid-point voltage signal, and its positive input terminal receives described DC bus-bar voltage signal by the 3rd resistance on the one hand, and by the 4th adjustable resistance ground connection, its output is exported described midpoint potential and is crossed low signal on the other hand; And
The 3rd comparator, its positive input terminal receives described load current signal, and its negative input end receives described zero current signal, and its output is exported described load current direction signal.
In above-mentioned single-phase three-level inverter midpoint potential balance controller, described correction selects circuit to comprise:
The first not gate, its input is connected with the output of described the first comparator;
The second not gate, its input is connected with the output of described the second comparator;
The 3rd not gate, its input is connected with the output of described the 3rd comparator;
First with door, its first input end is connected with the output of described the first not gate, its second input is connected with the output of described the second comparator, and its 3rd input is connected with the output of described the 3rd comparator, and its output is exported described balance enable signal;
Second with door, its first input end is connected with the output of described the first comparator, its second input is connected with the output of described the second not gate, and its 3rd input is connected with the output of described the 3rd comparator, and its output is exported described balance enable signal;
The 3rd with door, its first input end is connected with the output of described the first not gate, its second input is connected with the output of described the second comparator, its 3rd input is connected with the output of described the 3rd not gate, its output is exported described balance enable signal; And
The 4th with door, its first input end is connected with the output of described the first not gate, its second input is connected with the output of described the second comparator, and its 3rd input is connected with the output of described the 3rd comparator, and its output is exported described balance enable signal.
In above-mentioned single-phase three-level inverter midpoint potential balance controller, described logic judging circuit comprises:
First or door, an one input with described first with output be connected, its another input with the described the 4th with output be connected;
Second or door, an one input with described second with output be connected, its another input with the described the 3rd with output be connected;
The 5th with door, its first input end receives described the first left modulation signal by a not gate, its second to the 3rd input receives respectively the described second to the 3rd left modulation signal, its the 4th to the 6th input receives described the 4th left modulation signal and the first to second right modulation signal by a not gate respectively, its the 7th to the 8th input receives respectively described the 3rd to the 4th right modulation signal, its 9th input with described first or door output be connected;
The 6th with door, its first input end receives described the first left modulation signal by a not gate, its second to the 3rd input receives respectively the described second to the 3rd left modulation signal, its four-input terminal receives described the 4th left modulation signal by a not gate, its the 5th to the 6th input receives respectively described the first to second right modulation signal, its the 7th to the 8th input receives described the 3rd to the 4th right modulation signal by a not gate respectively, its 9th input with described first or door output be connected;
The 7th with door, its first to second input receives respectively the first to second left modulation signal, its the 3rd to the 5th input receives described the 3rd to the 4th left modulation signal and the first right modulation signal by a not gate respectively, its the 6th to the 7th input receives respectively the described second to the 3rd right modulation signal, its the 8th input receives described the 4th right modulation signal by a not gate, its 9th input with described second or door output be connected;
The 8th with door, its first to second input receives described the first to second left modulation signal by a not gate respectively, it the 3rd receives respectively described the 3rd to the 4th left modulation signal to four-input terminal, its the 5th input receives described the first right modulation signal by a not gate, its the 6th to the 7th input receives respectively the described second to the 3rd right modulation signal, its the 8th input receives described the 4th right modulation signal by a not gate, its 9th input with described second or door output be connected; And
8-3 encoder, its first to fourth input is connected with the output of door with the 5th to the 8th respectively, its 5th to the 8th input end grounding, its output is exported described multichannel and is selected signal.
In above-mentioned single-phase three-level inverter midpoint potential balance controller, described modulation signal correction circuit comprises: the first to the 8th 8-1 data selector being connected with the output of described 8-3 encoder respectively, wherein,
The first to second input of a described 8-1 data selector receives respectively described the first left modulation signal, its the 3rd to the 5th input receives described the first left modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the first left correction modulation signal;
The first to second input of described the 2nd 8-1 data selector and the 4th to the 5th input receive respectively described the second left modulation signal, its the 3rd input receives described the second left modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the second left correction modulation signal;
The first input end of described the 3rd 8-1 data selector and the 3rd to the 5th input receive respectively described the 3rd left modulation signal, its second input receives described the 3rd left modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the 3rd left correction modulation signal;
The first input end of described the 4th 8-1 data selector and the 3rd input receive respectively described the 4th left modulation signal, its second input and the 4th to the 5th input receive described the 4th left modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the 4th left correction modulation signal;
The first input end of described the 5th 8-1 data selector and the 5th input receive respectively described the first right modulation signal, it second receives described the first right modulation signal by a not gate to four-input terminal, its the 6th to the 8th input end grounding, its output is exported described the first right correction modulation signal;
The first to the 3rd input and the 5th input of described the 6th 8-1 data selector receive respectively described the second right modulation signal, its four-input terminal receives described the second right modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the second right correction modulation signal;
First to fourth input of described the 7th 8-1 data selector receives respectively described the 3rd right modulation signal, its the 5th input receives described the 3rd right modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the 3rd right correction modulation signal;
The first input end of described the 8th 8-1 data selector and four-input terminal receive respectively described the 4th right modulation signal, its second to the 3rd input and the 5th input receive described the 4th right modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the 4th right correction modulation signal.
Owing to having adopted above-mentioned technical solution, the utility model is embedded between the control loop and major loop of common single-phase three level structure inverters, modulation signal to former inverter is revised, specifically, by midpoint potential balance control unit according to the corresponding balance enable signal of the positive negative output of the size of the DC bus-bar voltage of inverter and mid-point voltage and load current, and coordinate pulse control unit according to this balance enable signal, the former modulation signal of inverter to be revised, thereby alignment current potential carries out balance control in inverter output normal working voltage.Because the utility model is realized by hardware, need not programme, can not increase software overhead, and not adopt and there is no power device, therefore can too much not increase inverter volume and hardware cost, be not subject to inverter power level affects yet; This controller is practical, applicable to various single-phase three-level inverter products and cascade high voltage transformer product, can effectively the drift of DC bus midpoint potential be controlled in suitable scope.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of a kind of single-phase three-level inverter midpoint potential of the utility model balance controller;
Fig. 2 is the hardware structure diagram of midpoint potential balance control unit in the utility model;
Fig. 3 is the two carrier wave SPWM modulation system schematic diagrames of single-phase three-level inverter;
Fig. 4 is the hardware structure diagram of pulse control unit in the utility model;
Fig. 5 is the structure chart of logic judging circuit in pulse control unit of the present utility model;
Fig. 6 is the structure chart of modulation signal correction circuit in pulse control unit of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, provide preferred embodiment of the present utility model, and be described in detail.
Refer to Fig. 1-6, the utility model, it is a kind of single-phase three-level inverter midpoint potential balance controller, single-phase three-level inverter comprises inverter control loop 10 and with the inverter major loop 20 of switching device control port (not shown), wherein, inverter major loop 20 comprises: there is the left brachium pontis of the first left-handed opening device L1 to the four left-handed opening device L4, and the right brachium pontis with the right switching device R4 of the first right switching device R1 to the four, controller of the present utility model comprises:
The voltage/current detection unit 1 being connected with inverter major loop 20, it gathers DC bus-bar voltage signal UPN, mid-point voltage signal UON, the load current signal Iout that flows through load 30 and the zero current signal I0 of inverter major loop 20, and is exported;
The midpoint potential balance control unit 2 being connected with voltage/current detection unit 1, it specifically comprises:
Signal comparator circuit 21, it receives DC bus-bar voltage signal UPN, mid-point voltage signal UON, load current signal Iout and zero current signal I0, and export the too high signal A of midpoint potential, midpoint potential is crossed low signal B and load current direction signal C;
Circuit 22 is selected in the correction being connected with signal comparator circuit 21, and it receives the too high signal A of midpoint potential, midpoint potential is crossed low signal B and load current direction signal C, and exported corresponding balance enable signal;
With the pulse control unit 3 that midpoint potential balance control unit 2 is connected, it specifically comprises:
Logic judging circuit 31, first left modulation signal OL1 to the four left modulation signal OL4 and first right modulation signal OR1 to the four right modulation signal OR4(corresponding with the first left-handed opening device L1 to the four left-handed opening device L4 and the right switching device R4 of the first right switching device R1 to the four respectively of its receiving balance enable signal and inverter control loop 10 outputs is former modulation signal), and output multi-channel is selected signal D, E, F;
The modulation signal correction circuit 32 being connected with logic judging circuit 31, it receives multichannel and selects signal D, E, F, the left modulation signal OL4 of the first left modulation signal OL1 to the four and the right modulation signal OR4 of the first right modulation signal OR1 to the four, and the first left correction modulation signal NL4 of left correction modulation signal NL1 to the four and the right correction modulation signal NR4(of the first right correction modulation signal NR1 to the four that to the output of switching device control port, for alignment current potential, carry out balance control are new modulation signal).
As shown in Figure 2, in the present embodiment, signal comparator circuit 21 specifically comprises:
The first comparator 211, its positive input terminal receives mid-point voltage signal UON, its negative input end receives DC bus-bar voltage signal UPN by the first resistance r1 on the one hand, on the other hand by the second adjustable resistance r2 ground connection, and the too high signal A of its output output midpoint potential;
The second comparator 212, its negative input end receives mid-point voltage signal UON, its positive input terminal receives DC bus-bar voltage signal UPN by the 3rd resistance r3 on the one hand, and on the other hand by the 4th adjustable resistance r4 ground connection, its output output midpoint potential is crossed low signal B; And
The 3rd comparator 213, its positive input terminal receives load current signal Iout, and its negative input end receives zero current signal I0, its output output load current direction signal C.
In the present embodiment, revise and select circuit 22 specifically to comprise:
The first not gate 221, its input is connected with the output of the first comparator 211;
The second not gate 222, its input is connected with the output of the second comparator 212;
The 3rd not gate 223, its input is connected with the output of the 3rd comparator 213;
First with door 224, its first input end is connected with the output of the first not gate 221, its second input is connected with the output of the second comparator 212, its 3rd input is connected with the output of the 3rd comparator 213, its output is exported balance enable signal;
Second with door 225, its first input end is connected with the output of the first comparator 211, its second input is connected with the output of the second not gate 222, its 3rd input is connected with the output of the 3rd comparator 213, its output is exported balance enable signal;
The 3rd with door 226, its first input end is connected with the output of the first not gate 221, its second input is connected with the output of the second comparator 212, its 3rd input is connected with the output of the 3rd not gate 223, its output is exported balance enable signal; And
The 4th with door 227, its first input end is connected with the output of the first not gate 221, its second input is connected with the output of the second comparator 212, its 3rd input is connected with the output of the 3rd comparator 213, its output is exported balance enable signal.
As shown in Figure 5, in the present embodiment, logic judging circuit 31 specifically comprises:
First or door 311, an one input is connected with 224 output with first, and its another input is connected with 227 output with the 4th;
Second or door 312, an one input is connected with 225 output with second, and its another input is connected with 226 output with the 3rd;
The 5th with door 313, its first input end receives the first left modulation signal OL1 by a not gate, its second to the 3rd input receives respectively the second to the 3rd left modulation signal OL2-OL3, its the 4th to the 6th input receives the 4th left modulation signal OL4 and the first to second right modulation signal OR1-OR2 by a not gate respectively, its the 7th to the 8th input receives respectively the 3rd to the 4th right modulation signal OR3-OR4, and its 9th input is connected with first or door 311 output;
The 6th with door 314, its first input end receives the first left modulation signal OL1 by a not gate, its second to the 3rd input receives respectively the second to the 3rd left modulation signal OL2-OL3, its four-input terminal receives the 4th left modulation signal OL4 by a not gate, its the 5th to the 6th input receives respectively the first to second right modulation signal OR1-OR2, its the 7th to the 8th input receives the 3rd to the 4th right modulation signal OR3-OR4 by a not gate respectively, and its 9th input is connected with first or 311 output;
The 7th with door 315, its first to second input receives respectively the first to second left modulation signal OL1-OL2, its the 3rd to the 5th input receives the 3rd to the 4th left modulation signal OL3-OL4 and the first right modulation signal OR1 by a not gate respectively, its the 6th to the 7th input receives respectively the second to the 3rd right modulation signal OR2-OR3, its the 8th input receives the 4th right modulation signal OR4 by a not gate, and its 9th input is connected with second or 312 output;
The 8th with door 316, its first to second input receives the first to second left modulation signal OL1-OL2 by a not gate respectively, it the 3rd receives respectively the 3rd to the 4th left modulation signal OL3-OL4 to four-input terminal, its the 5th input receives the first right modulation signal OR1 by a not gate, its the 6th to the 7th input receives respectively the second to the 3rd right modulation signal OR2-OR3, its the 8th input receives the 4th right modulation signal OR4 by a not gate, and its 9th input is connected with second or 312 output; And
8-3 encoder 317, its first to fourth input is connected with the output of door 314-316 with the 5th to the 8th respectively, its 5th to the 8th input end grounding, its output output multi-channel is selected signal D, E, F.
As shown in Figure 6, in the present embodiment, modulation signal correction circuit 32 specifically comprises: the first to the 8th 8-1 data selector 321-328 being connected with the output of 8-3 encoder 317 respectively, wherein,
The first to second input of the one 8-1 data selector 321 receives respectively the first left modulation signal OL1, its the 3rd to the 5th input receives the first left modulation signal OL1 by a not gate, its the 6th to the 8th input end grounding, its output is exported the first left correction modulation signal NL1;
The first to second input of the 2nd 8-1 data selector 322 and the 4th to the 5th input receive respectively the second left modulation signal OL2, its the 3rd input receives the second left modulation signal OL2 by a not gate, its the 6th to the 8th input end grounding, its output is exported the second left correction modulation signal NL2;
The first input end of the 3rd 8-1 data selector 323 and the 3rd to the 5th input receive respectively the 3rd left modulation signal OL3, its second input receives the 3rd left modulation signal OL3 by a not gate, its the 6th to the 8th input end grounding, its output output the 3rd left correction modulation signal NL3;
The first input end of the 4th 8-1 data selector 324 and the 3rd input receive respectively the 4th left modulation signal OL4, its second input and the 4th to the 5th input receive the 4th left modulation signal OL4 by a not gate, its the 6th to the 8th input end grounding, its output output the 4th left correction modulation signal NL4;
The first input end of the 5th 8-1 data selector 325 and the 5th input receive respectively the first right modulation signal OR1, it second receives the first right modulation signal OR1 by a not gate to four-input terminal, its the 6th to the 8th input end grounding, its output is exported the first right correction modulation signal NR1;
The first to the 3rd input and the 5th input of the 6th 8-1 data selector 326 receive respectively the second right modulation signal OR2, its four-input terminal receives the second right modulation signal OR2 by a not gate, its the 6th to the 8th input end grounding, its output is exported the second right correction modulation signal NR2;
First to fourth input of the 7th 8-1 data selector 327 receives respectively the 3rd right modulation signal OR3, its the 5th input receives the 3rd right modulation signal OR3 by a not gate, its the 6th to the 8th input end grounding, its output output the 3rd right correction modulation signal NR3;
The first input end of the 8th 8-1 data selector 328 and four-input terminal receive respectively the 4th right modulation signal OR4, its second to the 3rd input and the 5th input receive the 4th right modulation signal OR4 by a not gate, its the 6th to the 8th input end grounding, its output output the 4th right correction modulation signal NR4.
Below operation principle of the present utility model is elaborated.
The utility model is embedded between the control loop and major loop of common single-phase three level structure inverters, is mainly used in the modulation signal of former inverter to revise.
Voltage/current detection unit 1 in the utility model adopts the hardware composition proposal of conventional electric resistance partial pressure and electric current CT, is mainly used in obtaining DC bus-bar voltage signal UPN, mid-point voltage signal UON, the load current signal Iout that flows through load and zero current signal I0.The input of this voltage/current detection unit 1 is connected in single-phase three-level inverter DC bus two ends, bus mid point and load outlet line, and output is connected to midpoint potential balance control unit 2.Especially, electric current CT should be noted that load current positive direction during wiring, and the direction of Iout shown in Fig. 1 is electric current positive direction.
Midpoint potential balance control unit 2 in the utility model is mainly used in DC bus-bar voltage signal UPN, mid-point voltage signal UON and load current signal Iout to judge, thereby obtains the balance enable signal to SPWM modulation signal, specifically:
Signal comparator circuit 21 is for providing DC bus mid-point potential offset signal (being that the too high signal A of midpoint potential and midpoint potential are crossed low signal B) and load current direction signal C, and its principle is,
Utilize integrated amplifier that the mid-point voltage signal UON detecting and DC bus-bar voltage signal UPN are compared, if mid-point voltage upwards exceeds the fluctuation range (UON >=[r2/ (r1+r2)] * UPN) that inverter allows, provide the too high signal A=1 of midpoint potential; If mid-point voltage exceeds the fluctuation range (UON≤[r3/ (r3+r4)] * UPN) that inverter allows downwards, provide midpoint potential and cross low signal B=1; If mid-point voltage is at stability range ([r3/ (r3+r4)] * UPN < UON < [r2/ (r1+r2)] * UPN), the too high signal A of midpoint potential and midpoint potential are crossed low signal B and are 0(and represent that midpoint potential is without abnormal).The fluctuation range that the second adjustable resistance r2 in Fig. 2 and the 4th adjustable resistance R4 can need to regulate frequency converter to allow according to user: [r2/ (r1+r2)] * UPN is the inverter allowable fluctuation range upper limit, and [r3/ (r3+r4)] * UPN is inverter allowable fluctuation range lower limit.Signal comparator circuit 21 also utilizes integrated amplifier that the load current Iout detecting and zero current signal I0 are compared, if load current Iout is more than or equal to 0(, is Iout >=I0), provide load current direction signal C=1; If it is Iout < I0 that load current Iout is less than 0(), provide load current direction signal C=0.
Revise and select circuit 22 according to DC bus mid-point potential offset signal (being that the too high signal A of midpoint potential and midpoint potential are crossed low signal B) and load current direction signal C, generate corresponding balance enable signal (selecting suitable modulation signal amendment scheme), it is mainly to utilize logic gates to realize that circuit 22 is selected in this correction, its principle is
If load current is being for just and need to improve midpoint potential (being A=0, B=1, C=1), first with balance enable signals for door 224 outputs be that 1(represents to select amendment scheme 1), all the other 3 balance enable signals of exporting with door are 0;
If load current is being for just and need to reduce midpoint potential (being A=1, B=0, C=1), second with balance enable signals for door 225 outputs be that 1(represents to select amendment scheme 2), all the other 3 balance enable signals of exporting with door are 0;
If load current is for negative and need to improve midpoint potential (be A=0,, B=1, C=0), the 3rd with balance enable signals for door 226 outputs be that 1(represents to select amendment scheme 3), all the other 3 balance enable signals of exporting with door are 0;
If load current is for negative and need to reduce midpoint potential (being A=1, B=0, C=0), the 4th with balance enable signals for door 227 outputs be that 1(represents to select amendment scheme 4), all the other 3 balance enable signals of exporting with door are 0;
Below the correction principle of amendment scheme 1～4 is elaborated:
Single-phase three-level inverter major loop as shown in Figure 1, its each brachium pontis has three kinds of effective statuses, with tri-state switch Sx(x=L, R) represent, Sx=P represents that switching device 1,2 is open-minded, switching device 3,4 turn-offs; Sx=O represents that switching device 2,3 is open-minded, and switching device 1,4 turn-offs; Sx=N represents that switching device 3,4 is open-minded, and switching device 1,2 turn-offs; For example SL=P represents that the first to second left-handed opening device L1, L2 are open-minded, and the 3rd to the 4th left-handed opening device L3, L4 turn-off.Three-level inverter has nine kinds of effective left and right brachium pontis unit switch states, and wherein PO(is SL=P, SR=O), ON, OP, NO one of four states can affect midpoint potential (it being called to intermediate switch state temporarily herein).The impact of these four kinds of intermediate switch state alignment current potentials is relevant with load current direction: load current Iout is timing, PO and NO state can be to bus mid point Injection Currents, improve midpoint potential, OP and ON state can flow out electric current from bus mid point, reduce midpoint potential; Load current Iout is contrary while being negative, and PO and NO state can reduce midpoint potential, and OP and ON state can improve midpoint potential.Therefore, amendment scheme 1～4 is exactly according to current midpoint potential state and load current direction, selects suitable intermediate switch state to replace mutually.Because single-phase three-level inverter has multiple SPWM modulator approach, concrete amendment scheme need to be determined according to concrete modulator approach.
Two carrier wave SPWM modulation systems of take below in the present embodiment describe as example
The two carrier wave SPWM modulation systems of single-phase three-level inverter as shown in Figure 3.According to the operation principle of SPWM modulation system, in the front half period of a modulation period, only have OO, ON, PO, tetra-kinds of on off states of PN, wherein ON and PO are the intermediate switch states of adjustable midpoint potential, and can alternately occur in the front half period; In like manner, four on off states in later half cycle of modulating wave are OO, OP, NO and NP, and wherein OP and NO are the intermediate switch states of adjustable midpoint potential, and can alternately occur in the later half cycle.To sum up can obtain following amendment scheme:
Amendment scheme 1---with PO state, substitute ON state, with NO state, substitute OP state, in order to improve midpoint potential;
Amendment scheme 2---with ON state, substitute PO state, with OP state, substitute NO state, in order to reduce midpoint potential;
Amendment scheme 3---with ON state, substitute PO state, with OP state, substitute NO state, in order to improve midpoint potential;
Amendment scheme 4---with PO state, substitute ON state, with NO state, substitute OP state, in order to reduce midpoint potential.
Therefore, when first to fourth when one in 224-227 is output as 1 balance enable signal (other three balance enable signals of exporting with door are 0) with door, represent that this controller understands the abnormality of the midpoint potential of inverter, and selected the amendment scheme for this situation, then just can to the former modulation signal of inverter, carry out concrete correction by the following logic gates for each amendment scheme and operate; And when first to fourth is 0 with a balance enable signal for 224-227 output, represent that the midpoint potential of inverter is normal.
Pulse control unit 3 in the utility model is according to the balance enable signal (being selected amendment scheme) of midpoint potential balance control unit 2 outputs, three-level inverter SPWM modulation signal is revised, and in inverter output normal working voltage, alignment current potential carries out balance control.Specifically:
Logic judging circuit 31, according to the modulation signal of balance enable signal and former three-level inverter (i.e. the left modulation signal OL4 of the first left modulation signal OL1 to the four and the right modulation signal OR4 of the first right modulation signal OR1 to the four), generate multichannel and select signal D, E, F, it is mainly to utilize logic gates and 8-3 encoder 317 to carry out logic judgement: as from the foregoing, in four amendment schemes, when there is intermediate switch state in former modulation signal, need to mutually replace, and while there are other states, still need to keep former modulation signal, need that (1 signal is 1 by four balance enable signals for this reason, all the other 3 signals are 0) and 8 former three-level inverter modulation signals carry out integrated logic judgement:
When balance enable signal is 0(, do not have amendment scheme to enable) or former modulation signal while there is not intermediate switch state, it is that 000(is D=0, E=0, F=0 that the multichannel of 8-3 encoder 317 outputs is selected signal);
When first with door the 224 or the 4th be that 1(is that amendment scheme 1 or 4 enables with balance enable signals for door 227 outputs) and former modulation signal while being ON state, it is that 001(is D=0, E=0, F=1 that the multichannel of 8-3 encoder 317 outputs is selected signal);
When first with door the 224 or the 4th be that 1(is that amendment scheme 1 or 4 enables with balance enable signals for door 227 outputs) and former modulation signal while being OP state, it is that 010(is D=0, E=1, F=0 that the multichannel of 8-3 encoder 317 outputs is selected signal);
When second with door the 225 or the 3rd be that 1(is that amendment scheme 2 or 3 enables with balance enable signals for door 226 outputs) and former modulation signal while being PO state, it is that 011(is D=0, E=1, F=1 that the multichannel of 8-3 encoder 317 outputs is selected signal);
When second with door the 225 or the 3rd be that 1(is that amendment scheme 2 or 3 enables with balance enable signals for door 226 outputs) and former modulation signal while being NO state, it is that 100(is D=1, E=0, F=0 that the multichannel of 8-3 encoder 317 outputs is selected signal).
Modulation signal correction circuit 32 is mainly selected signal D, E, F according to above-mentioned multichannel, select new modulation signal (i.e. the first left correction modulation signal NL4 of left correction modulation signal NL1 to the four and the right correction modulation signal NR4 of the first right correction modulation signal NR1 to the four) and export to major loop switching device control port, it is mainly to utilize logic gates and the first to the 8th 8-1 data selector 321-328 to carry out data selection:
If it is 000 that multichannel is selected signal D, E, F, keep former modulation signal constant;
If it is 001 that multichannel is selected signal D, E, F, exporting new modulation signal is PO state;
If it is 010 that multichannel is selected signal D, E, F, exporting new modulation signal is NO state;
If it is 011 that multichannel is selected signal D, E, F, exporting new modulation signal is ON state;
If it is 100 that multichannel is selected signal D, E, F, exporting new modulation signal is OP state.
Because the above-mentioned technology by 8-1 data selector change modulation signal state is routine techniques well known in the art, therefore, repeat no more herein.
So far, the new modulation signal of the output of pulse control unit 3 can be used for alignment current potential and carries out balance control.
In sum, controller of the present utility model works in inverter action, neither increases high power device, can too much not increase product cost and volume, has reached again the object of real-time inhibition mid-point potential offset.
Above-described, be only preferred embodiment of the present utility model, not in order to limit scope of the present utility model, above-described embodiment of the present utility model can also make a variety of changes.Be that simple, the equivalence that every claims according to the utility model application and description are done changes and modify, all fall into the claim protection range of the utility model patent.The utility model not detailed description be routine techniques content.
Claims (6)
1. a single-phase three-level inverter midpoint potential balance controller, described single-phase three-level inverter comprises inverter control loop and with the inverter major loop of switching device control port, wherein, described inverter major loop comprises: the left brachium pontis with the first left-handed opening device to the four left-handed opening devices, and the right brachium pontis with the first right switching device to the four right switching devices, it is characterized in that, described controller comprises:
With the voltage/current detection unit that described inverter major loop is connected, it gathers DC bus-bar voltage signal, mid-point voltage signal, the load current signal that flows through load and the zero current signal of described inverter major loop, and is exported;
The midpoint potential balance control unit being connected with described voltage/current detection unit, it receives described DC bus-bar voltage signal, mid-point voltage signal, load current signal and zero current signal, and exports corresponding balance enable signal; And
The pulse control unit being connected with described midpoint potential balance control unit, it receives first left modulation signal to the four left modulation signal and first right modulation signal to the four right modulation signal corresponding with described the first left-handed opening device to the four left-handed opening devices and the right switching device of the first right switching device to the four respectively of described balance enable signal and described inverter control loop output, and the left correction modulation signal of the first left correction modulation signal to the four and the right correction modulation signal of the first right correction modulation signal to the four that to described switching device control port output, for alignment current potential, carry out balance control.
2. single-phase three-level inverter midpoint potential balance controller according to claim 1, is characterized in that,
Described midpoint potential balance control unit comprises:
Signal comparator circuit, it receives described DC bus-bar voltage signal, mid-point voltage signal, load current signal and zero current signal, and export the too high signal of midpoint potential, midpoint potential is crossed low signal and load current direction signal;
Circuit is selected in the correction being connected with described signal comparator circuit, and it receives the too high signal of described midpoint potential, midpoint potential is crossed low signal and load current direction signal, and exports described balance enable signal;
Described pulse control unit comprises:
Logic judging circuit, it receives first left modulation signal to the four left modulation signal and first right modulation signal to the four right modulation signal corresponding with described the first left-handed opening device to the four left-handed opening devices and the right switching device of the first right switching device to the four respectively of described balance enable signal and described inverter control loop output, and output multi-channel is selected signal;
The modulation signal correction circuit being connected with described logic judging circuit, it receives described multichannel and selects signal, described the first left modulation signal of left modulation signal to the four and the right modulation signal of the first right modulation signal to the four, and exports the left correction modulation signal of described the first left correction modulation signal to the four and the right correction modulation signal of the first right correction modulation signal to the four.
3. single-phase three-level inverter midpoint potential balance controller according to claim 2, is characterized in that, described signal comparator circuit comprises:
The first comparator, its positive input terminal receives described mid-point voltage signal, and its negative input end receives described DC bus-bar voltage signal by the first resistance on the one hand, and by the second adjustable resistance ground connection, its output is exported the too high signal of described midpoint potential on the other hand;
The second comparator, its negative input end receives described mid-point voltage signal, and its positive input terminal receives described DC bus-bar voltage signal by the 3rd resistance on the one hand, and by the 4th adjustable resistance ground connection, its output is exported described midpoint potential and is crossed low signal on the other hand; And
The 3rd comparator, its positive input terminal receives described load current signal, and its negative input end receives described zero current signal, and its output is exported described load current direction signal.
4. single-phase three-level inverter midpoint potential balance controller according to claim 3, is characterized in that, described correction selects circuit to comprise:
The first not gate, its input is connected with the output of described the first comparator;
The second not gate, its input is connected with the output of described the second comparator;
The 3rd not gate, its input is connected with the output of described the 3rd comparator;
First with door, its first input end is connected with the output of described the first not gate, its second input is connected with the output of described the second comparator, and its 3rd input is connected with the output of described the 3rd comparator, and its output is exported described balance enable signal;
Second with door, its first input end is connected with the output of described the first comparator, its second input is connected with the output of described the second not gate, and its 3rd input is connected with the output of described the 3rd comparator, and its output is exported described balance enable signal;
The 3rd with door, its first input end is connected with the output of described the first not gate, its second input is connected with the output of described the second comparator, its 3rd input is connected with the output of described the 3rd not gate, its output is exported described balance enable signal; And
The 4th with door, its first input end is connected with the output of described the first not gate, its second input is connected with the output of described the second comparator, and its 3rd input is connected with the output of described the 3rd comparator, and its output is exported described balance enable signal.
5. single-phase three-level inverter midpoint potential balance controller according to claim 4, is characterized in that, described logic judging circuit comprises:
First or door, an one input with described first with output be connected, its another input with the described the 4th with output be connected;
Second or door, an one input with described second with output be connected, its another input with the described the 3rd with output be connected;
The 5th with door, its first input end receives described the first left modulation signal by a not gate, its second to the 3rd input receives respectively the described second to the 3rd left modulation signal, its the 4th to the 6th input receives described the 4th left modulation signal and the first to second right modulation signal by a not gate respectively, its the 7th to the 8th input receives respectively described the 3rd to the 4th right modulation signal, its 9th input with described first or door output be connected;
The 6th with door, its first input end receives described the first left modulation signal by a not gate, its second to the 3rd input receives respectively the described second to the 3rd left modulation signal, its four-input terminal receives described the 4th left modulation signal by a not gate, its the 5th to the 6th input receives respectively described the first to second right modulation signal, its the 7th to the 8th input receives described the 3rd to the 4th right modulation signal by a not gate respectively, its 9th input with described first or door output be connected;
The 7th with door, its first to second input receives respectively the first to second left modulation signal, its the 3rd to the 5th input receives described the 3rd to the 4th left modulation signal and the first right modulation signal by a not gate respectively, its the 6th to the 7th input receives respectively the described second to the 3rd right modulation signal, its the 8th input receives described the 4th right modulation signal by a not gate, its 9th input with described second or door output be connected;
The 8th with door, its first to second input receives described the first to second left modulation signal by a not gate respectively, it the 3rd receives respectively described the 3rd to the 4th left modulation signal to four-input terminal, its the 5th input receives described the first right modulation signal by a not gate, its the 6th to the 7th input receives respectively the described second to the 3rd right modulation signal, its the 8th input receives described the 4th right modulation signal by a not gate, its 9th input with described second or door output be connected; And
8-3 encoder, its first to fourth input is connected with the output of door with the 5th to the 8th respectively, its 5th to the 8th input end grounding, its output is exported described multichannel and is selected signal.
6. single-phase three-level inverter midpoint potential balance controller according to claim 5, is characterized in that, described modulation signal correction circuit comprises: the first to the 8th 8-1 data selector being connected with the output of described 8-3 encoder respectively, wherein,
The first to second input of a described 8-1 data selector receives respectively described the first left modulation signal, its the 3rd to the 5th input receives described the first left modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the first left correction modulation signal;
The first to second input of described the 2nd 8-1 data selector and the 4th to the 5th input receive respectively described the second left modulation signal, its the 3rd input receives described the second left modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the second left correction modulation signal;
The first input end of described the 3rd 8-1 data selector and the 3rd to the 5th input receive respectively described the 3rd left modulation signal, its second input receives described the 3rd left modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the 3rd left correction modulation signal;
The first input end of described the 4th 8-1 data selector and the 3rd input receive respectively described the 4th left modulation signal, its second input and the 4th to the 5th input receive described the 4th left modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the 4th left correction modulation signal;
The first input end of described the 5th 8-1 data selector and the 5th input receive respectively described the first right modulation signal, it second receives described the first right modulation signal by a not gate to four-input terminal, its the 6th to the 8th input end grounding, its output is exported described the first right correction modulation signal;
The first to the 3rd input and the 5th input of described the 6th 8-1 data selector receive respectively described the second right modulation signal, its four-input terminal receives described the second right modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the second right correction modulation signal;
First to fourth input of described the 7th 8-1 data selector receives respectively described the 3rd right modulation signal, its the 5th input receives described the 3rd right modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the 3rd right correction modulation signal;
The first input end of described the 8th 8-1 data selector and four-input terminal receive respectively described the 4th right modulation signal, its second to the 3rd input and the 5th input receive described the 4th right modulation signal by a not gate, its the 6th to the 8th input end grounding, its output is exported described the 4th right correction modulation signal.
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| CN105406746A (en) * | 2014-09-16 | 2016-03-16 | 上海三菱电梯有限公司 | Three-level power converter midpoint potential balance control method |
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| CN108540005A (en) * | 2018-04-27 | 2018-09-14 | 上能电气股份有限公司 | A kind of DC bus-bar voltage balance control method of three-level inverter |
| CN108540005B (en) * | 2018-04-27 | 2020-11-27 | 上能电气股份有限公司 | Direct-current bus voltage balance control method of three-level inverter |
| CN109085765A (en) * | 2018-08-06 | 2018-12-25 | 江苏师范大学 | Three level active power filter rapid model prediction control method of neutral-point-clamped formula |
| CN113328647A (en) * | 2020-02-28 | 2021-08-31 | 北京金风科创风电设备有限公司 | Control circuit of NPC type three-level converter and NPC type three-level converter |
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