CN117850563A - Protection circuit, electronic equipment and protection method of multi-chip system - Google Patents

Abstract

The application discloses a protection circuit, electronic equipment and protection method of multi-chip system, protection circuit includes the power that is used for providing stable voltage, is used for providing the protection module of protection voltage, is used for providing first high level input signal and first low level input signal's first input module, is used for providing second high level input signal and second low level input signal's second input module, with first high level input signal, first low level input signal, second high level input signal and second low level input signal connection's signal processing module for confirm the drive locking module of the PWM drive's of multi-chip system control strategy. The output signals corresponding to the input signals are obtained through the first input module, the second input module and the signal processing module, whether the multi-chip system is abnormal or not can be judged according to the output signals and the driving locking module, PWM driving can be timely closed when the multi-chip system is abnormal, and reliability of the multi-chip system is improved.

Description

Protection circuit, electronic equipment and protection method of multi-chip system

Technical Field

The present disclosure relates to the field of chip protection, and in particular, to a protection circuit, an electronic device, and a protection method for a multi-chip system.

Background

Program "run-out" means that after the chip is subject to some disturbance, the value of the program counter PC deviates from a given unique variation history, resulting in the program running deviating from the normal running path. In a switching power supply system, if PWM driving cannot be turned off in time when the system is abnormal, a switching device is damaged if light, and an external connection device is damaged if heavy.

At present, when an electronic chip is operated, the situation of system abnormality, such as program 'run-away', is unavoidable. When a system abnormality occurs, a common solution is to reset and restart the system. However, the logic operation of a pure hardware implementation reset method is complex, resulting in lower reliability of the multi-chip system.

Disclosure of Invention

The embodiment of the application provides a protection circuit, electronic equipment and a protection method of a multi-chip system, so that PWM (pulse-Width modulation) driving is turned off in time when the multi-chip system operates abnormally, and the reliability of the multi-chip system is improved.

In a first aspect, an embodiment of the present application provides a protection circuit of a multi-chip system, which is applied to the multi-chip system, where the protection circuit of the multi-chip system includes a power supply, a protection module, a first input module, a second input module, a signal processing module, and a protection module, where:

A power supply for providing a regulated voltage; the protection module is used for being connected with a power supply, limiting the current of the power supply and providing protection voltage; a first input module for providing a first high level input signal and a first low level input signal; a second input module for providing a second high level input signal and a second low level input signal; a signal processing module configured with a first high-level input signal processing port for connection with a first high-level input signal, a first low-level input signal processing port for connection with a first low-level input signal, a second high-level input signal processing port for connection with a second high-level input signal, and a second low-level input signal processing port for connection with a second low-level input signal at a protection voltage; wherein, the signal processing module includes: the first signal processing unit is connected with the first high-level input signal processing port and the second high-level input signal processing port, and is used for carrying out logic judgment on the first high-level input signal and the first low-level input signal under the protection voltage and outputting a first logic judgment signal through the first signal output port; the second signal processing unit is connected with the first low-level input signal processing port and the second low-level input signal processing port, and is used for carrying out logic judgment on the second high-level input signal and the second low-level input signal under the protection voltage and outputting a second logic judgment signal through the second signal output port; the third signal processing unit is connected with the first signal output port and the second signal output port, and is used for carrying out logic judgment on the first logic judgment signal and the second logic judgment signal under the protection voltage and outputting a third logic judgment signal through the third signal output port; the drive locking module is connected with the third signal output port and used for determining a control strategy of PWM driving of the multi-chip system according to the third logic judgment signal under the protection voltage, and the control strategy is used for closing the PWM driving when the multi-chip system is abnormal in operation.

In a second aspect, embodiments of the present application provide an electronic device comprising part or all of the protection circuit as described in any of the circuits of the first aspect.

In a third aspect, an embodiment of the present application provides a protection method for a multi-chip system, where the protection method is applied to the multi-chip system, and the protection method includes:

setting a plurality of mutually exclusive input signals, wherein the input signals comprise a first high-level input signal and a first low-level input signal which are input by a first input module, and a second high-level input signal and a second low-level input signal which are input by a second input module; determining an output signal corresponding to the input signal through the input signal and the signal processing module; and determining a PWM driving control strategy of the multi-chip system according to the output signal, wherein the control strategy is used for closing PWM driving when the multi-chip system is abnormal in operation.

In a fourth aspect, embodiments of the present application provide a protection device for a multi-chip system, where the protection device includes:

the signal input module is used for setting a plurality of mutually exclusive input signals, wherein the input signals comprise a first high-level input signal and a first low-level input signal which are input by the first input module, and a second high-level input signal and a second low-level input signal which are input by the second input module; the reading output module is used for determining an output signal corresponding to the input signal through the input signal and the signal processing module; and the driving control module is used for determining a control strategy of PWM driving of the multi-chip system according to the output signal, and the control strategy is used for closing the PWM driving when the multi-chip system is abnormal in operation.

In a fifth aspect, embodiments of the present application provide a protection device for a multi-chip system, the device including: a memory, a processor and a protection program of a multichip system stored on the memory and executable on the processor, the protection program of the multichip system being configured to implement part or all of the steps of the protection method of the multichip system according to any of the third aspects.

By implementing the embodiment of the application, the protection circuit of the multi-chip system comprises a power supply, a protection module, a first input module, a second input module, a signal processing module and a protection module, wherein the power supply is used for providing stable voltage; the protection module is used for being connected with a power supply, limiting the current of the power supply and providing protection voltage; the first input module is used for providing a first high-level input signal and a first low-level input signal; the second input module is used for providing a second high-level input signal and a second low-level input signal; the signal processing module is configured with a first high-level input signal processing port for connection with a first high-level input signal, a first low-level input signal processing port for connection with a first low-level input signal, a second high-level input signal processing port for connection with a second high-level input signal, and a second low-level input signal processing port for connection with a second low-level input signal under a protection voltage; wherein, the signal processing module includes: the first signal processing unit is connected with the first high-level input signal processing port and the second high-level input signal processing port, and is used for carrying out logic judgment on the first high-level input signal and the first low-level input signal under the protection voltage and outputting a first logic judgment signal through the first signal output port; the second signal processing unit is connected with the first low-level input signal processing port and the second low-level input signal processing port, and is used for carrying out logic judgment on the second high-level input signal and the second low-level input signal under the protection voltage and outputting a second logic judgment signal through the second signal output port; the third signal processing unit is connected with the first signal output port and the second signal output port, and is used for carrying out logic judgment on the first logic judgment signal and the second logic judgment signal under the protection voltage, and outputting a third logic judgment signal through the third signal output port; the driving locking module is connected with the third signal output port and is used for determining a control strategy of PWM driving of the multi-chip system according to the third logic judgment signal under the protection voltage, and the control strategy is used for closing the PWM driving when the multi-chip system operates abnormally. The output signals corresponding to the input signals can be obtained through the first input module, the second input module and the signal processing module, whether the multi-chip system is abnormal or not can be judged according to the output signals and the driving locking module, PWM driving is turned off in time when the multi-chip system is abnormal, and reliability of the multi-chip system is improved.

Drawings

In order to more clearly describe the technical solutions in the embodiments or the background of the present application, the following description will describe the drawings that are required to be used in the embodiments or the background of the present application.

FIG. 1 is a schematic diagram of a protection circuit of a multi-chip system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a protection circuit of a multi-chip system according to an embodiment of the present application;

FIG. 3 is a flow chart of a method for protecting a multi-chip system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an input signal and a corresponding output signal of a multi-chip system according to an embodiment of the present disclosure;

FIG. 5 is a block diagram of a protection device for a multichip system according to an embodiment of the application;

fig. 6 is a block diagram of a protection device of a multi-chip system according to an embodiment of the present application.

Detailed Description

In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.

The terms first, second, third and the like in the description and in the claims and drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The following is a description of key concepts and features related to the embodiments of the present application.

(1) MOS: is an abbreviation for MOSFET. MOSFET metal-oxide semiconductor field effect transistor, G: gate; s: source; d: drain, source and drain of the MOS transistor are interchangeable, and they are all N-type regions formed in P-type back gate. In most cases, the two regions are identical, and even the two ends are reversed, so that the performance of the device is not affected.

(2) PWM: the pulse width modulation is an analog control mode, and the bias of the base electrode or the grid electrode of the transistor is modulated according to the change of corresponding load so as to change the on time of the transistor or the MOS transistor, thereby changing the output of the switching regulated power supply.

At present, when an electronic chip is operated, the situation that a system is abnormal inevitably occurs, including the initialization of chip power-on, the process of program update, program run-off and the like. When a system abnormality occurs, a common solution is to reset and restart the system. However, the logic operation of the reset method realized by pure hardware is complex, an external circuit and a plurality of modules are required to be designed, the cost of the external hardware is increased, and the anti-interference capability and the reliability are lower.

To the above-mentioned problem, the embodiment of the application provides a protection circuit of multichip system, and protection circuit of multichip system includes power, protection module, first input module, second input module, signal processing module and drive locking module, wherein: the power supply is used for providing stable voltage; the protection module is used for being connected with a power supply, limiting the current of the power supply and providing protection voltage; the first input module is used for providing a first high-level input signal and a first low-level input signal; the second input module is used for providing a second high-level input signal and a second low-level input signal; the signal processing module is configured with a first high-level input signal processing port for connection with a first high-level input signal, a first low-level input signal processing port for connection with a first low-level input signal, a second high-level input signal processing port for connection with a second high-level input signal, and a second low-level input signal processing port for connection with a second low-level input signal under a protection voltage; wherein, the signal processing module includes: the first signal processing unit is connected with the first high-level input signal processing port and the second high-level input signal processing port, and is used for carrying out logic judgment on the first high-level input signal and the first low-level input signal under the protection voltage and outputting a first logic judgment signal through the first signal output port; the second signal processing unit is connected with the first low-level input signal processing port and the second low-level input signal processing port, and is used for carrying out logic judgment on the second high-level input signal and the second low-level input signal under the protection voltage and outputting a second logic judgment signal through the second signal output port; the third signal processing unit is connected with the first signal output port and the second signal output port, and is used for carrying out logic judgment on the first logic judgment signal and the second logic judgment signal under the protection voltage and outputting a third logic judgment signal through the third signal output port; the driving locking module is connected with the third signal output port and is used for determining a control strategy of PWM driving of the multi-chip system according to the third logic judgment signal under the protection voltage, and the control strategy is used for closing the PWM driving when the multi-chip system operates abnormally. The output signals corresponding to the input signals can be obtained through the first input module, the second input module and the signal processing module, whether the multi-chip system is abnormal or not can be judged according to the output signals and the driving locking module, PWM driving is turned off in time when the multi-chip system is abnormal, and reliability of the multi-chip system is improved.

In one possible implementation, referring to fig. 1, fig. 1 is a schematic diagram of a protection circuit of a multi-chip system according to an embodiment of the present application, and as shown in fig. 1, a protection circuit 100 of the multi-chip system includes a power supply 101, a protection module 102, a first input module 103, a second input module 104, a signal processing module 105, and a driving locking module 106, where the multi-chip system includes a first chip, a second chip, and a PWM driving.

Wherein the power supply 101 is configured to provide a stable voltage; the protection module 102 is configured to connect to the power supply 101, limit current of the power supply 101, and provide a protection voltage; the first input module 103 is configured to provide a first high-level input signal and a first low-level input signal; the second input module 104 is configured to provide a second high level input signal and a second low level input signal; the signal processing module 105 is configured with a first high-level input signal processing port for connection with a first high-level input signal, a first low-level input signal processing port for connection with a first low-level input signal, a second high-level input signal processing port for connection with a second high-level input signal, and a second low-level input signal processing port for connection with a second low-level input signal at the protection voltage; wherein the signal processing module 105 comprises: a first signal processing unit 1051, connected to the first high-level input signal processing port and the second high-level input signal processing port, configured to perform logic determination on the first high-level input signal and the first low-level input signal under the protection voltage, and output a first logic determination signal through a first signal output port; a second signal processing unit 1052, connected to the first low-level input signal processing port and the second low-level input signal processing port, configured to perform logic determination on the second high-level input signal and the second low-level input signal under the protection voltage, and output a second logic determination signal through a second signal output port; a third signal processing unit 1053, connected to the first signal output port and the second signal output port, configured to perform logic determination on the first logic determination signal and the second logic determination signal under the protection voltage, and output a third logic determination signal through the third signal output port; and the driving locking module 106 is connected with the third signal output port and is used for determining a control strategy of PWM driving of the multi-chip system according to the third logic judgment signal under the protection voltage, and the control strategy is used for closing the PWM driving when the multi-chip system operates abnormally.

Wherein, the power supply is a stable voltage source with the amplitude of 3.3V.

Wherein the input signals may be in a high-level state, a low-level state, and a high-resistance state, the plurality of input signals including a first high-level signal and a first low-level signal set by the first chip, and a second high-level signal and a second low-level signal set by the second chip.

The protection module comprises a plurality of protection resistors and protection capacitors, and is used for current limiting and filtering.

The protection resistor is arranged between the stable voltage source and other components of the circuit, and plays a role in current limiting.

The PWM drive defaults to normally open operation, pulse signals are generated at a certain frequency by the PWM drive through the control circuit, and the width of the pulse is adjusted according to a set modulation proportion. When the pulse width is narrower, the equipment is in a discontinuous working state; as the pulse width increases, the device on time increases and the average power or voltage output increases. By varying the pulse width and period, fine control of the device can be achieved.

In this example, the first input module, the second input module and the signal processing module may obtain an output signal corresponding to the input signal, and according to the output signal and the driving locking module, may determine whether the multi-chip system is abnormal and determine a PWM driving control policy, thereby improving reliability of the multi-chip system and efficiency of chip protection.

In one possible implementation, the signal processing module further includes:

the positive end of the first diode is connected with the protection voltage, and the negative end of the first diode is connected with the first signal output port; the positive end of the second diode is connected with the protection voltage and the first low-level input signal, and the negative end of the second diode is connected with the first low-level input signal processing port; and the positive end of the third diode is connected with the protection voltage and the second low-level input signal, and the negative end of the third diode is connected with the second low-level input signal processing port.

The second signal processing unit is a MOS tube, a grid electrode of the second signal processing unit is connected with the first low-level input signal processing port and the second low-level input signal processing port, a source electrode of the second signal processing unit is grounded, and a drain electrode of the second signal processing unit is connected with the second signal output port; the first signal processing unit and the third signal processing unit are different units in the same AND gate chip; the protection module comprises a plurality of identical protection resistors; the first diode, the second diode, and the third diode are identical.

The MOS tube is used as a switch to control whether the current is conducted or not, and the second signal processing unit can be any triode or circuit structure capable of realizing the same switching function.

Specifically, referring to fig. 2, fig. 2 is a schematic diagram of a protection circuit of a multi-chip system provided in the embodiment of the present application, as shown in fig. 2, the first diode is D1, the second diode is D2, the third diode is D3, the first signal processing unit is U16-C, the third signal processing unit is U16-D, R1, R2, R3, R4, R5, R6, R7, R8, R9 are protection resistors, C1, C2 are protection capacitors, wherein U16-C, U-D is a different module in the same chip, and pins 8,9,10 of U16-C in fig. 2 correspond to pins 8,9,10 of U16 chip; pins 11,12,13 of U16-D in FIG. 2 correspond to pins 11,12,13 of the U16 chip.

The chip model of U16-C, U16-D can be S74AHC08PW-Q100, or one or more chips which can realize the same function.

Therefore, in this example, through the cooperation of the plurality of diodes, the first signal processing unit, the second signal processing unit and the third signal processing unit, whether the multi-chip system is in an abnormal state or not can be judged through the output signals corresponding to the plurality of input signals, normal operation of the protection circuit is ensured, reliability of the multi-chip system is improved, and meanwhile, the protection circuit cost is reduced and meanwhile, efficiency of the protection circuit can be ensured by adopting a plurality of identical devices and different modules under the same chip.

An electronic device is provided that includes some or all of the protection circuitry of any of the multi-chip systems as in the protection circuitry examples described above.

In one possible implementation manner, referring to fig. 3, fig. 3 is a flowchart of a protection method of a multi-chip system according to an embodiment of the present application, and as shown in fig. 3, the protection method of the multi-chip system includes the following steps:

s301, setting a plurality of mutually exclusive input signals;

s302, determining an output signal corresponding to the input signal through the input signal and a signal processing module;

s303, determining a control strategy of PWM driving of the multi-chip system according to the output signal.

The plurality of mutually exclusive input signals comprise a first high-level input signal, a first low-level input signal, a second high-level input signal and a second low-level input signal.

The first high-level input signal and the first low-level input signal are a group of mutually exclusive input signals set by a first chip in the multi-chip system, and the second high-level input signal and the second low-level input signal are a group of mutually exclusive input signals set by a second chip in the multi-chip system.

Wherein the control strategy is used for turning off the PWM drive when the multi-chip system is abnormal in operation.

In this example, the control strategy of the multi-chip system is determined according to the output signal, so that the protection circuit can be ensured to close the PWM drive in time after the abnormality of the output signal is identified, the operation of the multi-chip system is stopped, the multi-chip system is protected, and the reliability of the multi-chip system and the efficiency of the protection circuit are improved.

In one possible implementation manner, the determining, by the input signal and the signal processing module, an output signal corresponding to the input signal includes: determining the first logic judgment signal by the first high-level input signal, the second high-level input signal and the first signal processing unit; determining a second logic judgment signal by the first low-level input signal, the second low-level input signal, a second diode, a third diode and a second signal processing unit; and determining a third logic judgment signal through the first logic judgment signal, the second logic judgment signal, the first diode and the third signal processing unit.

Wherein the third logic judgment signal is an output signal corresponding to the input signal.

It can be seen that, in this example, after the input signal, the plurality of diodes, and the plurality of signal processing units obtain the first logic determination signal and the second logic determination signal, the third logic determination signal is determined according to the first logic determination signal, the second logic determination signal, and the second signal processing unit, and the third logic determination signal is used as the output signal of the protection circuit, so that the efficiency of the protection circuit can be improved while the reliability of the protection circuit is ensured.

In one possible implementation manner, the determining, by the first logic determination signal, the second logic determination signal, the first diode, and the third signal processing unit, the third logic determination signal includes:

when the multi-chip system normally operates, the first diode, the second diode, the third diode and the second signal processing unit are not conducted, the first logic judgment signal and the second logic judgment signal are both high-level signals, and two input signals of the third signal processing unit are both high-level signals, and at the moment, the third logic judgment signal is a high-level signal; when the multi-chip system operates abnormally, the level of one or more signals of the input signals is inverted or in a high-resistance state, one or more signals of the first logic judgment signal and the second logic judgment signal are low-level signals, one or more signals of two input signals of the third signal processing unit are low-level signals, and at the moment, the third logic judgment signal is a low-level signal.

Wherein said determining a control strategy for said multi-chip system based on said output signal comprises: judging whether the output signal is a low level signal or not; and detecting that the output signal is a low-level signal, wherein the multi-chip system runs abnormally at the moment, and controlling the PWM drive to be closed.

Wherein the output signal is the third logic determination signal.

Specifically, referring to fig. 2 and fig. 4, fig. 4 is a block diagram of a protection device of a multi-chip system provided in an embodiment of the present application, as shown in fig. 2 and fig. 4, the first signal processing unit is an and logic gate U16-C, the second signal processing unit is a MOS transistor Q1, and the third signal processing unit is an and logic gate U16-D;

when the multi-chip system normally operates, a plurality of mutually exclusive input signals of the multi-chip system are in a normal state, PH and PH1 are both in a high level (H) at the moment, 9 pins of U16-C are input into PH,9 pins are in a high level (H), 10 pins of U16-C are input into PH1, 10 pins are in a high level (H), because logic of U16-C is an AND gate, 8 pins of U16-C are output into a high level (H), both the positive end and the negative end of D1 are in a high level (H), D1 is not conducted, a stable voltage source P3V3 flows to 12 pins of U16-D through a protection resistor R1, and at the moment, 12 pins of U16-D are input into a high level (H); the multiple mutually exclusive input signals set by the multi-chip system are in a normal state, PL and PL1 are low level (L) at the moment, a stable voltage source P3V3 flows to PL, PL1, D2 and D3 through a protection resistor R5 and a protection resistor R6, positive and negative ends of the stable voltage source P3V3 are low level (L), D2 and D3 are non-conductive, a grid electrode and a source electrode of a MOS tube Q1 are low level (L), Q1 is non-conductive, the stable voltage source P3V3 flows to a pin 13 of U16-D through a protection resistor R7, at the moment, the pin 13 of U16-D is input into high level (H), the inputs 12 and 13 of U16-D are simultaneously high level (H), the output SD of U16-D, namely the pin 11 is high level (H), and the PWM driving of the system is unlocked;

When the multi-chip system is abnormal in operation, the mutually exclusive input signals of multiple levels arranged in the multi-chip system are in an abnormal state, one or more levels in the input signals are inverted or in a high-resistance state, and when one or more of PH/PH1 is in a low level (L) or a high-resistance state (Z), one or more of the inputs of U16-C is in a low level (L), the output 8 pin of U16-C is in a low level (L), the positive end of D1 is in a high level (H), the negative end is in a low level (L), D1 is conducted, a stable voltage source P3V3 flows to the output 8 pin of U16-D through a protection resistor R1, the stable voltage source P3V3 is in a low level (L) after passing through U16-C, at the moment, the input 12 pin of U16-D is in a low level (L), the output 11 pin of U16-D is in a low level (L), namely SD is in a low level (SD), and the CPU detects SD signals to be L, and the system PWM is locked;

for example, when one or more of PL/PL1 is in the high level (H) or the high-resistance state (Z), the stable voltage source P3V3 passes through the protection resistor R5 and the protection resistors R6, D2, D3, the MOS transistor Q1 is turned on, the stable voltage source P3V3 flows to gnd_s through R7 and Q1, the input 13 pin of U16-D is the output 11 pin of U16-D with low level (L), i.e., SD is low level (L), the CPU detects the SD signal as L, and the PWM driving of the system is locked.

The protection method and the protection circuit not only can protect a double-chip system, but also can extend and protect a three-chip and more multi-chip system.

It can be seen that, in this example, by the protection method, whether the multi-chip system is abnormal or not may be determined by detecting the output signal of the protection circuit, so as to determine the control strategy for PWM driving, and by adopting the protection method, protection may be provided in the chip initialization process and the program update process, so that the reliability of the multi-chip system is improved.

Referring to fig. 5, fig. 5 is a block diagram of a protection device for a multi-chip system according to an embodiment of the present application, and as shown in fig. 5, a protection device 500 for a multi-chip system includes:

a signal input module 501, configured to set a plurality of mutually exclusive input signals, where the input signals include a first high-level input signal and a first low-level input signal input by a first input module, and a second high-level input signal and a second low-level input signal input by a second input module;

the reading output module 502 is configured to determine an output signal corresponding to the input signal through the input signal and the signal processing module;

A driving control module 503, configured to determine a control strategy of PWM driving of the multi-chip system according to the output signal, where the control strategy is used to turn off the PWM driving when the multi-chip system is abnormal.

Referring to fig. 6, fig. 6 is a block diagram of a protection device of a multi-chip system according to an embodiment of the present application, and as shown in fig. 6, a protection device 600 of a multi-chip system includes a processor 601, a memory 602, and a communication interface 603, where the processor 601, the memory 602, and the communication interface 603 are connected to each other, and perform communication work therebetween;

the memory 602 has executable program codes stored thereon, and the communication interface 603 is used for wireless communication;

the processor 601, when executing executable program code, performs some or all of the steps of any of the methods of protecting a multi-chip system as described in the method examples above.

Processor 601 may include one or more processing cores. The processor 601 connects various portions of the overall electronic device using various interfaces and lines to perform various functions of the electronic device and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 602, and invoking data stored in the memory 602. Alternatively, the processor 601 may be implemented in hardware in at least one of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (ProgrammableLogic Array, PLA). The processor 601 may integrate one or a combination of several of a central processing unit (CentralProcessing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. It will be appreciated that the modem may not be integrated into the processor 601 and may be implemented solely by a single communication chip.

The Memory 602 may include random access Memory (Random Access Memory, RAM) or Read-Only Memory (ROM). Memory 602 may be used to store instructions, programs, code, a set of codes, or a set of instructions. The memory 602 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing examples of the respective methods described above, and the like. The storage data area may also store data created by the electronic device in use, etc.

It will be appreciated that the electronic device may include more or fewer structural elements than those described in the above structural block diagrams, including, for example, a power module, physical key, wiFi (Wireless Fidelity ) module, speaker, bluetooth module, sensor, etc., without limitation.

The present application provides a computer readable storage medium storing a computer program for electronic data exchange, the computer program comprising execution instructions for performing part or all of the steps of a method of protecting any one of the multichip systems as described in the method examples above.

The present application also provides a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform part or all of the steps of a method of protecting any one of the multichip systems as described in the method examples above. The computer program product may be a software installation package.

It should be noted that, for simplicity of description, the protection method examples of any multi-chip system are all described as a series of combinations of actions, but those skilled in the art should appreciate that the present application is not limited by the order of actions described, as some steps may take place in other order or simultaneously in accordance with the present application. Further, those skilled in the art will also appreciate that the examples described in the specification are preferred examples and that the acts referred to are not necessarily required in the present application.

Although the present application has been described herein in connection with various examples, other variations to the disclosed examples can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various exemplary methods of the protection method of any of the multi-chip systems described above may be accomplished by a program that instructs associated hardware, the program may be stored in a computer readable memory, the memory may comprise: flash disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.

The foregoing has described the present application in detail, and specific examples have been provided herein to illustrate the principles and embodiments of a method and apparatus for protecting a multi-chip system of the present application, the above examples being provided only to assist in understanding the method and core ideas of the present application; meanwhile, as for those skilled in the art, according to the idea of the protection method and apparatus for a multi-chip system of the present application, there are various changes in the specific embodiments and application scope, and in summary, the present disclosure should not be construed as limiting the present application.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, hardware products, and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be appreciated that any product, such as the terminals of the flowcharts described above and computer program products, which are controlled or otherwise configured to perform the processing methods of the flowcharts described herein for one of the examples of protection methods for a multi-chip system, falls within the scope of the relevant product described herein.

It will be apparent to those skilled in the art that various modifications and variations can be made in the method and apparatus for protecting a multichip system provided herein without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (10)

1. The utility model provides a protection circuit of multichip system, is applied to multichip system, its characterized in that, protection circuit of multichip system includes power, protection module, first input module, second input module, signal processing module and drive locking module, wherein:

the power supply is used for providing stable voltage;

the protection module is used for being connected with the power supply, limiting the current of the power supply and providing protection voltage;

the first input module is used for providing a first high-level input signal and a first low-level input signal;

the second input module is used for providing a second high-level input signal and a second low-level input signal;

the signal processing module is configured with a first high-level input signal processing port for connecting with a first high-level input signal, a first low-level input signal processing port for connecting with a first low-level input signal, a second high-level input signal processing port for connecting with a second high-level input signal, and a second low-level input signal processing port for connecting with a second low-level input signal under the protection voltage; wherein the signal processing module comprises:

The first signal processing unit is connected with the first high-level input signal processing port and the second high-level input signal processing port, and is used for carrying out logic judgment on the first high-level input signal and the first low-level input signal under the protection voltage and outputting a first logic judgment signal through a first signal output port;

the second signal processing unit is connected with the first low-level input signal processing port and the second low-level input signal processing port, and is used for carrying out logic judgment on the second high-level input signal and the second low-level input signal under the protection voltage and outputting a second logic judgment signal through a second signal output port;

the third signal processing unit is connected with the first signal output port and the second signal output port, and is used for carrying out logic judgment on the first logic judgment signal and the second logic judgment signal under the protection voltage and outputting a third logic judgment signal through the third signal output port;

the driving locking module is connected with the third signal output port and used for determining a control strategy of PWM driving of the multi-chip system according to the third logic judgment signal under the protection voltage, and the control strategy is used for closing the PWM driving when the multi-chip system operates abnormally.

2. The protection circuit of claim 1, wherein the signal processing module further comprises:

the positive end of the first diode is connected with the protection voltage, and the negative end of the first diode is connected with the first signal output port;

the positive end of the second diode is connected with the protection voltage and the first low-level input signal, and the negative end of the second diode is connected with the first low-level input signal processing port;

and the positive end of the third diode is connected with the protection voltage and the second low-level input signal, and the negative end of the third diode is connected with the second low-level input signal processing port.

3. The protection circuit of claim 2, wherein the second signal processing unit is a MOS transistor, a gate of the second signal processing unit is connected to the first low-level input signal processing port and the second low-level input signal processing port, a source of the second signal processing unit is grounded, and a drain of the second signal processing unit is connected to the second signal output port;

the first signal processing unit and the third signal processing unit are different units in the same AND gate chip;

the protection module comprises a plurality of identical protection resistors;

The first diode, the second diode, and the third diode are identical.

4. An electronic device comprising the protection circuit according to any one of claims 1-3.

5. A protection method for a multichip system, applied to a multichip system, the protection method comprising:

setting a plurality of mutually exclusive input signals, wherein the input signals comprise a first high-level input signal and a first low-level input signal which are input by a first input module, and a second high-level input signal and a second low-level input signal which are input by a second input module;

determining an output signal corresponding to the input signal through the input signal and a signal processing module;

and determining a control strategy of PWM driving of the multi-chip system according to the output signal, wherein the control strategy is used for turning off the PWM driving when the multi-chip system is abnormal in operation.

6. The method of claim 5, wherein the signal processing module includes a first signal processing unit, a second signal processing unit, and a third signal processing unit, and wherein determining, by the input signal and the signal processing module, an output signal corresponding to the input signal includes:

Determining a first logic judgment signal through the first high-level input signal, the second high-level input signal and a first signal processing unit;

determining a second logic judgment signal by the first low-level input signal, the second low-level input signal, a second diode, a third diode and a second signal processing unit;

and determining a third logic judgment signal through the first logic judgment signal, the second logic judgment signal, the first diode and a third signal processing unit, wherein the third logic judgment signal is an output signal corresponding to the input signal.

7. The method of claim 6, wherein the determining a third logic determination signal by the first logic determination signal, the second logic determination signal, the first diode, and a third signal processing unit comprises:

when the multi-chip system normally operates, the first diode, the second diode, the third diode and the second signal processing unit are all not conducted, the first logic judgment signal and the second logic judgment signal are both high-level signals, and two input signals of the third signal processing unit are both high-level signals, and at the moment, the third logic judgment signal is a high-level signal;

When the multi-chip system operates abnormally, the level of one or more signals of the input signals is inverted or in a high-resistance state, one or more signals of the first logic judgment signal and the second logic judgment signal are low-level signals, one or more signals of two input signals of the third signal processing unit are low-level signals, and at the moment, the third logic judgment signal is a low-level signal.

8. The method of claim 6 or 7, wherein determining a control strategy for PWM driving of the multi-chip system based on the output signal comprises:

judging whether the output signal is a low level signal or not, wherein the output signal is the third logic judgment signal;

and detecting that the output signal is a low-level signal, wherein the multi-chip system runs abnormally at the moment, and controlling the PWM drive to be closed.

9. A protection device for a multichip system, the protection device comprising:

the signal input module is used for setting a plurality of mutually exclusive input signals, wherein the input signals comprise a first high-level input signal and a first low-level input signal which are input by the first input module, and a second high-level input signal and a second low-level input signal which are input by the second input module;

The reading output module is used for determining an output signal corresponding to the input signal through the input signal and the signal processing module;

and the driving control module is used for determining a control strategy of PWM driving of the multi-chip system according to the output signal, and the control strategy is used for closing the PWM driving when the multi-chip system is abnormal in operation.

10. A protection device for a multichip system, the device comprising: memory, a processor and a protection program of a multichip system stored on the memory and executable on the processor, the protection program of the multichip system being configured to implement the steps of the protection method of the multichip system according to any of claims 5-8.