CN117595262A - Reactive harmonic suppression method for photovoltaic grid-connected inverter - Google Patents
Reactive harmonic suppression method for photovoltaic grid-connected inverter Download PDFInfo
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- CN117595262A CN117595262A CN202311436303.3A CN202311436303A CN117595262A CN 117595262 A CN117595262 A CN 117595262A CN 202311436303 A CN202311436303 A CN 202311436303A CN 117595262 A CN117595262 A CN 117595262A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/01—Arrangements for reducing harmonics or ripples
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/24—Arrangements for preventing or reducing oscillations of power in networks
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2300/00—Systems for supplying or distributing electric power characterised by decentralized, dispersed, or local generation
- H02J2300/20—The dispersed energy generation being of renewable origin
- H02J2300/22—The renewable source being solar energy
- H02J2300/24—The renewable source being solar energy of photovoltaic origin
Abstract
The application provides a reactive harmonic suppression method for a photovoltaic grid-connected inverter, which comprises the following steps: acquiring voltage signals of upper and lower direct current bus capacitors of the three-level inverter to serve as reference voltage amplitude signals of SPWM (sinusoidal pulse width modulation) modulation waves; selecting a corresponding reference voltage amplitude signal by judging the polarity of the power grid voltage; calculating to obtain a DC bus voltage ripple according to the obtained upper DC bus capacitance voltage signal and the lower DC bus capacitance voltage signal; injecting the zero sequence component into the SPWM modulation wave to equivalently generate an SVPWM modulation wave, and adding the DC bus voltage ripple into the SVPWM modulation wave so as to balance the neutral point potential of the bus and further inhibit the harmonic wave of the output current. According to the reactive harmonic suppression method for the photovoltaic grid-connected inverter, the midpoint voltage offset caused by the reduction of the capacitance value and reactive components of the direct current bus can be adjusted in real time, the stability and balance of modulation output are ensured, the fluctuation of the voltage of the direct current bus is controlled within an allowable threshold, and the voltage balance of the bus is maintained.
Description
Technical Field
The application belongs to the technical field of photovoltaic grid connection, and particularly relates to a reactive harmonic suppression method for a photovoltaic grid-connected inverter.
Background
In recent years, as the heat of photovoltaic inverters continues to rise, the demand for efficient solar inverters is increasing, and solutions with low cost and high efficiency are permanently pursued by all manufacturers, so that improvement and optimization of circuit topology are indispensable measures for achieving the goal.
The T-shaped three-level inverter has the advantages that the output voltage and current harmonic wave is small, the voltage and the switching loss born by a switching device are reduced by half, and the like, and the T-shaped three-level inverter is widely applied to the photovoltaic system industry, the size of the DC bus capacitance value of the inverter is related to potential balance, and the smaller the capacitance value is, the more serious the potential fluctuation is, so that the partial pressure of two capacitance voltages is uneven. The unbalanced neutral point potential can cause the increase of the low harmonic content of the alternating current output side, so that the output waveform is distorted, the electric energy quality is reduced, and the output efficiency of the inverter is lowered.
In addition, in practical application, the power factor output of the photovoltaic inverter is 1, and can be adjusted between 0.8 lead and 0.8 lag. When the power factor of the photovoltaic inverter is 0.8 or-0.8, grid-connected current can be distorted, current harmonic waves become large, and system stability is affected.
Disclosure of Invention
In view of the above, the application aims to provide a reactive harmonic suppression method for a photovoltaic grid-connected inverter, so as to solve the problems that the output waveform is distorted and the power quality is reduced due to the fact that the low harmonic content of an alternating current output side is increased caused by unbalanced midpoint potential.
In order to achieve the above purpose, the technical scheme of the application is realized as follows:
the application provides a reactive harmonic suppression method for a photovoltaic grid-connected inverter, which comprises the following steps:
acquiring voltage signals of upper and lower direct current bus capacitors of the three-level inverter to serve as reference voltage amplitude signals of SPWM (sinusoidal pulse width modulation) modulation waves;
selecting a corresponding reference voltage amplitude signal by judging the polarity of the power grid voltage;
calculating to obtain a DC bus voltage ripple according to the obtained upper DC bus capacitance voltage signal and the lower DC bus capacitance voltage signal;
injecting the zero sequence component into the SPWM modulation wave to equivalently generate an SVPWM modulation wave, and adding the DC bus voltage ripple into the SVPWM modulation wave so as to balance the neutral point potential of the bus and further inhibit the harmonic wave of the output current.
Further, obtaining the upper and lower dc bus capacitor voltage signals of the three-level inverter as the reference voltage amplitude signal of the SPWM modulated wave, including:
the method comprises the steps of obtaining instantaneous values of upper and lower direct current bus capacitor voltage signals of a three-level inverter, and taking the instantaneous values as reference voltage amplitude values of SPWM (sinusoidal pulse width modulation) waves, wherein the reference voltage of the SPWM waves is as follows:
wherein u is A_ref 、u B_ref 、u C_ref The reference voltages are three phases respectively, m is the modulation ratio, and A is the reference voltage amplitude.
Further, selecting the corresponding reference voltage amplitude signal by judging the polarity of the power grid voltage comprises the following steps:
selecting a corresponding reference voltage amplitude by judging the polarity of the power grid voltage;
in response to the grid voltage being in the positive half cycle, the reference voltage amplitude of the SPWM modulation wave is the instantaneous value of the upper DC bus capacitance voltage, namely when u gn When not less than 0 (n=a, b, c),
in response to the power grid voltage being in the negative half cycle, the reference voltage amplitude of the SPWM modulation wave is the instantaneous value of the voltage of the lower direct-current bus capacitor, when u gn <0 (n=a, b, c),
wherein V is c1 Representing the instantaneous value of the voltage of the upper DC bus capacitor, V c2 Representing the instantaneous value of the voltage of the lower dc bus capacitor.
Further, the calculation of the dc bus voltage ripple according to the obtained upper and lower dc bus capacitance voltage signals includes:
the DC bus voltage ripple is calculated by using the upper DC bus capacitance voltage instantaneous value and the lower DC bus capacitance voltage instantaneous value, and the calculation formula is as follows:
further, the injecting the zero sequence component into the SPWM modulated wave to equivalently generate the SVPWM modulated wave, and adding the dc bus voltage ripple into the SVPWM modulated wave to balance the neutral point potential of the bus, thereby suppressing the harmonic of the output current, including:
injecting the zero sequence component into the SPWM modulation wave to obtain an SVPWM modulation wave in an equivalent way;
responding to the fact that the voltage instantaneous value of the upper direct current bus capacitor is larger than that of the lower direct current bus capacitor, the voltage ripple is positive, the positive half cycle amplitude of saddle wave output by SVPWM modulation is smaller than the negative half cycle amplitude, and the positive voltage ripple is superimposed into the saddle wave to reduce the offset of the negative half cycle;
and in response to the instantaneous value of the upper DC bus capacitor voltage being less than the instantaneous value of the lower DC bus capacitor voltage, the voltage ripple is negative, the positive half cycle amplitude of the saddle wave output by SVPWM modulation is greater than the negative half cycle amplitude, and the negative voltage ripple is superimposed into the saddle wave to reduce the offset of the positive half cycle.
Further, the neutral potential offset is adjusted, and the voltage ripple of the direct current bus is controlled within a preset threshold range so as to maintain the neutral potential balance of the bus.
Compared with the prior art, the reactive harmonic suppression method for the photovoltaic grid-connected inverter has the following beneficial effects:
the reactive harmonic suppression method for the photovoltaic grid-connected inverter can reduce waveform distortion of output current of the inverter under a non-unit power factor, so that the output current harmonic meets the requirement; the neutral point potential offset caused by the reduction of the bus capacitance and the reactive component can be adjusted in real time, the bus voltage balance is maintained, the fluctuation amplitude of the DC bus voltage is controlled within an allowable threshold range, and the inverter is ensured not to stop due to faults.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application, illustrate and explain the application and are not to be construed as limiting the application. In the drawings:
fig. 1 is a flowchart of a method for suppressing reactive harmonics of a photovoltaic grid-connected inverter according to an embodiment of the present application;
fig. 2 is a circuit topology diagram of a T-type three-level inverter according to an embodiment of the present application;
FIG. 3 is a graph showing voltage and current waveforms without adding an algorithm at non-unity power factor according to an embodiment of the present application;
fig. 4 is a graph showing voltage and current waveforms of the addition algorithm at non-unity power factor according to the embodiments of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
As described in the background art, there are a great deal of literature currently carrying out detailed study and cause analysis on the problems of harmonic suppression and neutral-point potential imbalance of a three-level inverter, but the solutions in the literature have the following limitations: the existing harmonic suppression method is used for optimizing a control loop under a unit power factor, and does not consider how to reduce the harmonic wave of output current under a non-unit power factor; the midpoint potential unbalance software solution method is midpoint potential control based on SVPWM modulation and midpoint potential control based on carrier PWM modulation, essentially changes the action time of a redundancy small vector to realize midpoint potential balance control, and is not suitable for SVPWM modulation with zero sequence component injection SPWM equivalent; if the situation that the capacitance value of the direct current bus is reduced and the reactive component is large in proportion and simultaneously exists is considered, the existing control algorithm cannot ensure that the inverter meets the harmonic requirement and stability.
In order to solve the above problems, referring to fig. 1, the present embodiment provides a method for suppressing reactive harmonics of a photovoltaic grid-connected inverter, the method including:
step S101, upper and lower direct current bus capacitor voltage signals of a three-level inverter are obtained to serve as reference voltage amplitude signals of SPWM modulation waves.
Specifically, under the condition that the DC bus capacitance value is reduced, the traditional bus voltage is replaced by the upper DC bus capacitance voltage instantaneous value and the lower DC bus capacitance voltage instantaneous value, and the values are used as the reference voltage amplitude of the SPWM modulation wave to be used for calculating the reference voltage of the SPWM modulation wave.
In some embodiments, instantaneous values of the upper and lower dc bus capacitor voltage signals of the three-level inverter are obtained as reference voltage amplitudes of the SPWM modulated wave, where the reference voltages of the SPWM modulated wave are:
wherein u is A_ref 、u B_ref 、u C_ref The reference voltages are three phases respectively, m is the modulation ratio, and A is the reference voltage amplitude.
Step S102, selecting a corresponding reference voltage amplitude signal by judging the polarity of the power grid voltage.
Specifically, selecting a reference voltage amplitude by judging the polarity of the power grid voltage, and if the power grid voltage is in a positive half cycle, taking the reference voltage amplitude of the SPWM modulation wave as an upper direct current bus capacitor voltage instantaneous value; and if the power grid voltage is in the negative half cycle, the reference voltage amplitude of the SPWM modulation wave is the instantaneous value of the voltage of the lower direct current bus capacitor.
In some embodiments, the SPWM modulated reference voltage amplitude is the upper DC bus capacitance voltage instantaneous value in response to the grid voltage being in the positive half cycle, i.e., when u gn When not less than 0 (n=a, b, c),
in response to the grid voltage being in the negative half cycle, the reference voltage amplitude of the SPWM modulation is the instantaneous value of the voltage of the lower direct current bus capacitor, namely when u gn <0 (n=a, b, c),
wherein V is c1 Representing the instantaneous value of the voltage of the upper DC bus capacitor, V c2 Representing the instantaneous value of the voltage of the lower dc bus capacitor.
And step S103, calculating to obtain DC bus voltage ripple according to the obtained upper DC bus capacitance voltage signal and lower DC bus capacitance voltage signal.
Specifically, the dc bus voltage ripple is calculated by using the upper dc bus capacitance voltage and the lower dc bus capacitance voltage, where the dc bus voltage ripple is
When V is c1 ＞V c2 At the time DeltaU dc > 0; when V is c1 ＜V c2 At the time DeltaU dc ＜0。
Further, the dc bus voltage ripple is obtained by calculating an upper dc bus capacitor voltage instantaneous value and a lower dc bus capacitor voltage instantaneous value, so as to adjust the midpoint potential offset in real time, and control the dc bus voltage ripple within a preset threshold range (0-150V), and it is to be noted that the threshold range is calibrated according to actual experience by a person skilled in the art, so as to maintain the midpoint voltage balance of the bus, further reduce distortion of the output current waveform and harmonics of the output current, and ensure stable operation of the inverter.
And S104, injecting a zero sequence component into the SPWM modulation wave to equivalently generate an SVPWM modulation wave, and superposing the DC bus voltage ripple into the SVPWM modulation wave so as to balance the neutral point potential of the bus and further inhibit the harmonic wave of the output current.
Specifically, in this embodiment, the zero sequence component is injected into the SPWM modulated wave to obtain the SVPWM modulated wave equivalently;
responding to the fact that the voltage instantaneous value of the upper direct current bus capacitor is larger than that of the lower direct current bus capacitor, the voltage ripple is positive, the positive half cycle amplitude of saddle wave output by SVPWM modulation is smaller than the negative half cycle amplitude, and the positive voltage ripple is superimposed into the saddle wave to reduce the offset of the negative half cycle;
and in response to the instantaneous value of the upper DC bus capacitor voltage being less than the instantaneous value of the lower DC bus capacitor voltage, the voltage ripple is negative, the positive half cycle amplitude of the saddle wave output by SVPWM modulation is greater than the negative half cycle amplitude, and the negative voltage ripple is superimposed into the saddle wave to reduce the offset of the positive half cycle.
Therefore, voltage ripple is superimposed into SVPWM modulation output, and the purpose is to adjust midpoint voltage offset caused by direct current bus capacitance value reduction and reactive component in real time, ensure stability and balance of modulation output, control fluctuation of direct current bus voltage within an allowable threshold, and maintain bus voltage balance.
The reactive harmonic suppression method for the photovoltaic grid-connected inverter can reduce waveform distortion of output current of the inverter under a non-unit power factor, so that the output current harmonic meets the requirement; the neutral point potential offset caused by the reduction of the bus capacitance and the reactive component can be adjusted in real time, the bus voltage balance is maintained, the fluctuation amplitude of the DC bus voltage is controlled within an allowable threshold range, and the inverter is ensured not to stop due to faults.
In this embodiment, for a T-type three-level inverter, the three-level inverter circuit topology structure is shown in fig. 2, and the method can be applied to a working condition that a non-unit power factor and a dc bus capacitance value of the inverter are reduced at the same time; in the SVPWM modulated wave with equivalent SPWM modulated wave injected with zero sequence component, the instantaneous value of the upper bus capacitor voltage and the instantaneous value of the lower bus capacitor voltage are selected to replace the traditional bus voltage to serve as the reference voltage of the SPWM modulated wave, so that the SPWM modulated wave has real-time performance and accuracy, the DC bus voltage modulated wave is injected into the saddle wave of the SVPWM modulated output, the output offset and fluctuation are further reduced, and the output stability is maintained.
As can be seen from fig. 3 and fig. 4, when the power factor of the inverter is ±0.8, compared with the method described in this embodiment, the waveform distortion of the output current after adding the method is reduced, the voltage fluctuation amplitude of the upper and lower bus capacitors is almost unchanged, and the harmonic wave of the output current is ensured to meet the requirement.
Table 1 shows the output current harmonic data of the method and the method without adding the method under the condition of constant capacitance value of the direct current bus and different power non-unit power factors. As can be seen from the comparison of the data in table 1, when the power factor of the inverter is ±0.8, that is, the capacity and the inductive reactive power of the inverter, the THD of the three-phase output current is obviously reduced after the method is added, the maximum THD is not more than 3%, and table 1 is as follows:
table 2 is harmonic data when the method was added at different power non-unity power factors by varying the dc bus capacitance. As can be seen from the comparison of the data in Table 2, under the condition of non-unit power factor, the harmonic wave of the current when the DC bus capacitance is 75uF is slightly larger than that when the DC bus capacitance is 140uF, and the maximum THD value is not more than 3%. Therefore, the method can reduce the neutral point potential offset caused by the reduction of the bus capacitance value, and maintain the bus voltage balance, so that the stable operation of the inverter can be ensured, and the aims of reducing the cost and enhancing the efficiency are fulfilled. Table 2 shows the following:
it should be noted that some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Those of ordinary skill in the art will appreciate that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements and/or the like which are within the spirit and principles of the embodiments are intended to be included within the scope of the present application.
Claims (6)
1. A method for suppressing reactive harmonics of a photovoltaic grid-connected inverter, the method comprising:
acquiring voltage signals of upper and lower direct current bus capacitors of the three-level inverter to serve as reference voltage amplitude signals of SPWM (sinusoidal pulse width modulation) modulation waves;
selecting a corresponding reference voltage amplitude signal by judging the polarity of the power grid voltage;
calculating to obtain a DC bus voltage ripple according to the obtained upper DC bus capacitance voltage signal and the lower DC bus capacitance voltage signal;
injecting the zero sequence component into the SPWM modulation wave to equivalently generate an SVPWM modulation wave, and adding the DC bus voltage ripple into the SVPWM modulation wave so as to balance the neutral point potential of the bus and further inhibit the harmonic wave of the output current.
2. The method for suppressing reactive harmonics of a photovoltaic grid-connected inverter according to claim 1, wherein the step of obtaining the upper and lower dc bus capacitor voltage signals of the three-level inverter as the reference voltage amplitude signal of the SPWM modulated wave comprises:
the method comprises the steps of obtaining instantaneous values of upper and lower direct current bus capacitor voltage signals of a three-level inverter, and taking the instantaneous values as reference voltage amplitude values of SPWM (sinusoidal pulse width modulation) waves, wherein the reference voltage of the SPWM waves is as follows:
wherein u is A_ref 、u B_ref 、u C_ref The reference voltages are three phases respectively, m is the modulation ratio, and A is the reference voltage amplitude.
3. The method for suppressing reactive harmonics of a photovoltaic grid-connected inverter according to claim 2, wherein the selecting the corresponding reference voltage amplitude signal by determining the polarity of the grid voltage comprises:
selecting a corresponding reference voltage amplitude by judging the polarity of the power grid voltage;
in response to the grid voltage being in the positive half cycle, the reference voltage amplitude of the SPWM modulation wave is the instantaneous value of the upper DC bus capacitance voltage, namely when u gn When not less than 0 (n=a, b, c),
in response to the power grid voltage being in the negative half cycle, the reference voltage amplitude of the SPWM modulation wave is the instantaneous value of the voltage of the lower direct-current bus capacitor, when u gn <0 (n=a, b, c),
wherein V is c1 Representing the instantaneous value of the voltage of the upper DC bus capacitor, V c2 Representing the instantaneous value of the voltage of the lower dc bus capacitor.
4. The method for suppressing reactive harmonics of a photovoltaic grid-connected inverter according to claim 3, wherein the calculating the dc bus voltage ripple according to the obtained upper and lower dc bus capacitance voltage signals comprises:
the DC bus voltage ripple is calculated by using the upper DC bus capacitance voltage instantaneous value and the lower DC bus capacitance voltage instantaneous value, and the calculation formula is as follows:
5. the method for suppressing reactive harmonics of a photovoltaic grid-connected inverter according to claim 4, wherein the step of injecting zero sequence components into SPWM modulated waves to equivalently generate SVPWM modulated waves and adding the dc bus voltage waves to the SVPWM modulated waves to balance neutral point potentials of buses and thereby suppress harmonics of output currents comprises:
injecting the zero sequence component into the SPWM modulation wave to obtain an SVPWM modulation wave in an equivalent way;
responding to the fact that the voltage instantaneous value of the upper direct current bus capacitor is larger than that of the lower direct current bus capacitor, the voltage ripple is positive, the positive half cycle amplitude of saddle wave output by SVPWM modulation is smaller than the negative half cycle amplitude, and the positive voltage ripple is superimposed into the saddle wave to reduce the offset of the negative half cycle;
and in response to the instantaneous value of the upper DC bus capacitor voltage being less than the instantaneous value of the lower DC bus capacitor voltage, the voltage ripple is negative, the positive half cycle amplitude of the saddle wave output by SVPWM modulation is greater than the negative half cycle amplitude, and the negative voltage ripple is superimposed into the saddle wave to reduce the offset of the positive half cycle.
6. The method for suppressing reactive harmonics of a photovoltaic grid-connected inverter according to claim 1, wherein the method comprises the steps of:
and adjusting the neutral point potential offset, and controlling the voltage ripple of the direct current bus within a preset threshold range so as to maintain the neutral point potential balance of the bus.
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