CN114900036A - Switched capacitor voltage-stabilizing chip circuit with double control modes - Google Patents
Switched capacitor voltage-stabilizing chip circuit with double control modes Download PDFInfo
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- CN114900036A CN114900036A CN202210569345.3A CN202210569345A CN114900036A CN 114900036 A CN114900036 A CN 114900036A CN 202210569345 A CN202210569345 A CN 202210569345A CN 114900036 A CN114900036 A CN 114900036A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 60
- 238000001514 detection method Methods 0.000 claims abstract description 16
- 230000006641 stabilisation Effects 0.000 claims abstract description 7
- 238000011105 stabilization Methods 0.000 claims abstract description 7
- 230000033228 biological regulation Effects 0.000 claims description 18
- 238000001914 filtration Methods 0.000 claims description 3
- 239000003381 stabilizer Substances 0.000 abstract description 5
- 230000009977 dual effect Effects 0.000 description 11
- 230000008859 change Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000001939 inductive effect Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000004146 energy storage Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
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- 230000006872 improvement Effects 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A switched capacitor voltage stabilization chip circuit with double control modes relates to a switched capacitor voltage stabilization chip circuit. The invention aims to solve the problem that the traditional linear voltage stabilizer is low in efficiency. The invention comprises a gain jump module, a clock generation module, a switched capacitor array module, a feedback control module and a current detection module; the output end of the gain jump module is connected with the input end of the clock generation module, the output end of the clock generation module is connected with the input end of the switched capacitor array module, the output end of the current detection module is connected with the input end of the feedback control module, and the feedback control module controls the clock generation module. The invention belongs to the field of power management chips.
Description
Technical Field
The invention relates to a switched capacitor voltage stabilization chip circuit, and belongs to the field of power management chips.
Background
In the modern times, we are in an information-based world, particularly in the 21 st century, portable devices such as mobile phones and other products are developed at a high speed and become an indispensable part in production and life of people, the portable devices such as mobile phones and other portable devices are usually powered by batteries, but the voltage directly provided by the batteries is generally called coarse voltage, and with the continuous improvement of the performance of electronic products, the coarse voltage is no longer suitable for directly powering each module of the mobile phone, and at this time, the mobile phone can be used after being rectified by a power supply, and the process is called power supply management.
The power management chip is an important type in analog chip products, the main power management is divided into the following forms of direct current to direct current (DC-DC), alternating current to direct current (AC-DC) and direct current to alternating current (DC-AC), while the power supply of the portable equipment is generally direct current to direct current and then supplies power to other modules, generally, different modules in the chip have respective performance requirements on power supply, and therefore different power management schemes are generated to correspondingly optimize various modules.
The current dc-dc converter is mainly divided into two categories, namely a linear regulator and a nonlinear regulator, the linear regulator is also called LDO, the linear regulator can provide a stable output voltage under a varying input voltage, has the characteristics of low noise, strong load carrying capacity and the like, and is very suitable for being used in noise-sensitive scene applications such as mobile phones and radio frequency communication, but the linear regulator has the following defects, the first point is that the structure of the linear regulator determines that the linear regulator can only realize a voltage drop function and cannot simultaneously realize the functions of boosting or reversing and the like under the same circuit structure, the second point is that when the difference between the input voltage and the output voltage is large, the efficiency of the system is very low, and the defect of low efficiency under the current scene applications such as long-time standby and the like can be amplified.
The second power management chip is a nonlinear voltage stabilizer, namely a switching power converter, the design of the switching power converter correspondingly makes up the defects of some aspects of the LDO, at present, the characteristics of the switching power converter are light weight, high efficiency and integration of voltage reduction and reduction, so that the switching power converter is widely applied to terminal communication equipment which mainly comprises a computer, becomes an indispensable power management mode in the development of wave tide in the information era, and has the specific principle that the system utilizes an inductor or a capacitor as energy storage software through the conduction and the turn-off of a mos switch tube, and charges and discharges an output end to maintain a stable output voltage in two quadrants of a clock switching period by absorbing and releasing energy. The inductive voltage drop converter has the characteristics of high efficiency, low ripple and the like, and the efficiency can easily exceed 90%, but the chip has the defects of sensitivity to noise, large area, low price and inconvenience for small-size integration, so the inductive voltage drop converter is usually used in the scenes of low sensitivity to noise and large load.
Therefore, a need exists for a switched capacitor dc converter, which operates on the principle of using a capacitor as an energy storage element and controlling the turn-on and turn-off of a switch mos transistor by a clock so that a transmission capacitor absorbs energy from a power supply and then releases the energy to a load, thereby transferring the energy, and outputting a stable voltage through a negative feedback loop. Therefore, the advantages and disadvantages of the capacitive dc converter are relatively compromised, and are a choice between the LDO and the inductive dc converter.
Disclosure of Invention
The invention provides a switched capacitor voltage stabilizing chip circuit in a dual control mode to solve the problem of low efficiency of the traditional linear voltage stabilizer.
The technical scheme adopted by the invention for solving the problems is as follows: the invention comprises a gain jump module, a clock generation module, a switched capacitor array module, a feedback control module and a current detection module; the output end of the gain jump module is connected with the input end of the clock generation module, the output end of the clock generation module is connected with the input end of the switched capacitor array module, the output end of the current detection module is connected with the input end of the feedback control module, and the feedback control module controls the clock generation module.
Furthermore, the circuit of the gain jump module consists of three divider resistors and two comparators; the negative end of the comparator is connected with the reference signal, and the output end of the comparator is connected with the input end of the clock generation module.
Further, the comparator is a hysteresis comparator.
Furthermore, the clock generation module consists of two comparators, a trigger and a capacitor; and the output end of the comparator is respectively connected with the R end and the S end of the trigger.
Further, the capacitance switch array module consists of nine transistors and two flying capacitors; and the grid signal of the transistor is connected with the output end of the clock generation module.
Further, the transistor is a mos transistor.
Furthermore, the circuit of the feedback control module consists of a comparator, a trigger and an AND gate; the output end of the comparator is connected with the input end of the trigger, the output end of the trigger is connected with the input end of the AND gate, the other end of the AND gate is connected with a clock signal clk, and the output end of the AND gate controls an output signal of the clock generation module.
Further, the flip-flop is a dff flip-flop.
Furthermore, the current detection module consists of six transistors and an operational amplifier; and the capacitance resistor in the current detection module has a filtering function.
Further, the transistor is a mos transistor.
The invention has the beneficial effects that:
1. compared with the inductor as an energy storage element, the switched capacitor converter can realize the miniaturization of the structure and the full integration of a power management chip. The charge pump is selected as the main body of the buck converter, and the clock generating circuit is used for controlling the switching power tube to stabilize the voltage, so that the voltage stabilization precision and the conversion efficiency are improved, and the loss is reduced;
2. aiming at the problems that the existing system cannot simultaneously meet the requirements of low ripple wave, high efficiency and the like due to the defect of a single control mode, the switched capacitor voltage stabilizer designs a mode of switching the system modulation mode according to load change through analyzing the system modulation mode under different conditions, adjusts the system stability and provides a scheme of frequency compensation;
3. the switched capacitor voltage stabilizing chip adopts a multi-gain mode switched capacitor array structure to realize the switching of three gain ratios, and compared with a linear voltage stabilizer, the mode can expand the range of input voltage, solve the problem of unmatched gain ratios under large input voltage and further improve the system efficiency.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of a gain hopping module;
FIG. 3 is a schematic diagram of a clock generation module;
FIG. 4 is a schematic diagram of a switched capacitor array module;
FIG. 5 is a schematic diagram of the structure of a feedback control module;
fig. 6 is a schematic structural diagram of a current detection module.
Detailed Description
The first embodiment is as follows: referring to fig. 1, the present embodiment is described, and a switched capacitor voltage regulation chip circuit in dual control mode according to the present embodiment includes a gain jump module 101, a clock generation module 102, a switched capacitor array module 103, a feedback control module 104, and a current detection module 105; the output end of the gain jump module 101 is connected to the input end of the clock generation module 102, the output end of the clock generation module 102 is connected to the input end of the switched capacitor array module 103, the output end of the current detection module 105 is connected to the input end of the feedback control module 104, and the feedback control module 104 controls the clock generation module 102.
The second embodiment is as follows: the present embodiment is described with reference to fig. 1 and fig. 2, and the circuit of the gain jump module 101 of the switched capacitor voltage regulation chip circuit in dual control mode according to the present embodiment is composed of three voltage-dividing resistors and two comparators; the negative terminal of the comparator is connected to the reference signal, and the output terminal of the comparator is connected to the input terminal of the clock generation module 102.
In this embodiment, the negative terminal of the comparator is connected to the reference signal for dividing the input voltage, and the output of the hysteresis comparator is connected to the input terminal of the clock generation module for controlling the selection of the clock level.
When the input voltage swings left and right near the interval jump point, the selection of the gain mode is not continuously switched between the two modes, so that the system is more stable, and it should be noted that, for the normal operation of the module, the hysteresis window of the hysteresis comparator should not be set too large, the output of the hysteresis comparator is a two-bit control signal, and the control signal controls the following digital coding circuit to generate a group of clock signals which can control the switch mos tube.
The third concrete implementation mode: in the present embodiment, the comparator of the switched capacitor voltage regulation chip circuit in dual control mode according to the present embodiment is a hysteresis comparator, which is described with reference to fig. 1 and 2.
The fourth concrete implementation mode: the present embodiment is described with reference to fig. 1 and fig. 3, and the clock generation module 102 of the switched capacitor voltage stabilization chip circuit in dual control mode of the present embodiment is composed of two comparators, a flip-flop and a capacitor; and the output end of the comparator is respectively connected with the R end and the S end of the trigger.
The bias current in this embodiment is provided by an operational amplifier and a resistor.
This embodiment utilizes two comparators, when V r Voltage of less than V L When the lower comparator outputs a low level, the following trigger is reset, and the current flows through the capacitor C S Charging when V r Is gradually pulled up to a potential higher than V L At the potential of V, the upper comparator outputs a low level to reset the flip-flop, and the capacitor C0 discharges rapidly, so that V r The potential on is again reduced, so that the reciprocating cycle generates a periodic change, therebyBut will make V r A periodically varying ramp signal is generated, which is processed to provide a clock for the subsequent operation, and the frequency of the ramp signal is the reference frequency of the system, and the formula is as follows:
the required clock frequency is finally obtained by changing the value of the capacitance resistor and the value of the reference voltage accessed by the comparator; in the above formula, f represents the clock frequency, m represents the proportional relation of the two branch currents, V H Represents the voltage, R, connected to the positive terminal of the comparator s Representing the magnitude of the resistance, V ref Which represents the reference voltage to which the positive terminal of the op-amp is connected.
The fifth concrete implementation mode: the present embodiment is described with reference to fig. 1 and fig. 4, and the capacitor switch array module 103 of the switched capacitor voltage regulation chip circuit in dual control mode according to the present embodiment is composed of nine transistors and two flying capacitors; the gate signal of the transistor is connected to the output of the clock generation block 102.
In this embodiment, the output terminal of the capacitor switch array module 103 is connected to vout.
The circuit structure of the switched capacitor array module 103 is shown in fig. 4, and is composed of two capacitors and nine switched mos transistors, the gate terminal of each switched transistor is connected to a group of control signals generated from the clock encoding circuit, and the switched capacitor array module can form the switching of three gain modes, namely, 1X, 1/2X and 2/3X gain modes, according to the combination of the on and off of the switched transistors, so as to improve the system efficiency.
The sixth specific implementation mode: the present embodiment is described with reference to fig. 1 and 4, and the transistor of the switched capacitor regulator chip circuit in dual control mode according to the present embodiment is a mos transistor.
The seventh embodiment: the present embodiment is described with reference to fig. 1 and fig. 5, and the circuit of the feedback control module 104 of the switched capacitor voltage regulation chip circuit in dual control mode of the present embodiment is composed of a comparator, a flip-flop, and an and gate; the output end of the comparator is connected with the input end of the trigger, the output end of the trigger is connected with the input end of the and gate, the other end of the and gate is connected with the clock signal clk, and the output end of the and gate controls the output signal of the clock generation module 102.
The PFM pulse frequency modulation mode circuit of the feedback control module 104 in this embodiment is shown in fig. 5; the principle of adjusting the change of the clock frequency can be fed back by the change of the output voltage, namely, the output voltage is compared with the reference voltage to generate a comparator output voltage control signal Vcmpout, the signal and the clock signal cooperate to generate a clock signal clk _ pfm with variable frequency, namely, when the output voltage is lower than the reference voltage, the comparator generates a high level, the circuit continues to increase the output voltage by clk, namely, the fundamental frequency clock, until the output voltage is higher than the reference voltage, the comparator generates a low level, so that the output end of the AND gate generates a low level and keeps the low level, the switch capacitor array module is discharged until the output voltage is lower than the reference voltage again, and the cycle is repeated, so that the signal clk _ pfm can be a clock signal which changes according to the output voltage.
The specific implementation mode is eight: the present embodiment is described with reference to fig. 1 and 5, and the flip-flop of the switched capacitor voltage regulation chip circuit in the dual control mode according to the present embodiment is a dff flip-flop.
The specific implementation method nine: the present embodiment is described with reference to fig. 1 and fig. 6, in which the current detection module 105 of the switched capacitor voltage regulation chip circuit in dual control mode of the present embodiment is composed of six transistors and one operational amplifier; the capacitance and resistance in the current detection module 105 have a filtering function.
The detailed implementation mode is ten: in the present embodiment, the transistor of the switched capacitor voltage regulation chip circuit in dual control mode according to the present embodiment is a mos transistor, which is described with reference to fig. 1 and fig. 6.
Principle of operation
The switched capacitor voltage regulator chip 100 combines two classical modulation modes, so that switching can be performed according to the change of current load, a PFM frequency modulation mode is used in low load, and an input current limiting control loop is used in high load. The gain jump module 101 generates a control signal according to the input voltage, thereby controlling the clock generated by the clock generation circuit module 102, and further controlling the conduction and the closure of the switch power tube, thereby enabling the switched capacitor array module 103 to work in an expected mode, selecting a proper charge pump structure, thereby improving the overall efficiency of the system, the feedback control module 104 provides two control modes, when working under the control of the PFM loop, the magnitude of the charging current is limited, thereby avoiding the generation of a large ripple wave on the output voltage, when working in the input current-limiting loop, the magnitude of the charging current is controlled by the gate voltage of the control signal generated by the negative feedback loop error amplifier. And in the latter stage, a PFM modulation mode is adopted when light load is judged according to the load current judged by the current detection module 105, and an input current-limiting modulation mode is adopted when high load is judged, so that the system can work in the best state, and the high-efficiency voltage stabilization effect is further met.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. The utility model provides a switched capacitor voltage regulation chip circuit of two accuse modes which characterized in that: the switched capacitor voltage stabilization chip circuit in the dual-control mode comprises a gain jump module (101), a clock generation module (102), a switched capacitor array module (103), a feedback control module (104) and a current detection module (105); the output end of the gain jump module (101) is connected with the input end of the clock generation module (102), the output end of the clock generation module (102) is connected with the input end of the switched capacitor array module (103), the output end of the current detection module (105) is connected with the input end of the feedback control module (104), and the feedback control module (104) controls the clock generation module (102).
2. The switched capacitor voltage regulation chip circuit of claim 1, wherein: the circuit of the gain jump module (101) consists of three divider resistors and two comparators; the negative end of the comparator is connected with the reference signal, and the output end of the comparator is connected with the input end of the clock generation module (102).
3. The switched capacitor voltage regulation chip circuit of claim 2, wherein: the comparator is a hysteresis comparator.
4. The switched capacitor voltage regulation chip circuit of claim 1, wherein: the clock generation module (102) consists of two comparators, a trigger and a capacitor; and the output end of the comparator is respectively connected with the R end and the S end of the trigger.
5. The switched capacitor voltage regulation chip circuit of claim 1, wherein: the capacitance switch array module (103) consists of nine transistors and two flying capacitors; the gate signal of the transistor is connected with the output end of the clock generation module (102).
6. The switched capacitor voltage regulation chip circuit of claim 5, wherein: the transistor is a mos transistor.
7. The switched capacitor voltage regulation chip circuit of claim 1, wherein: the circuit of the feedback control module (104) consists of a comparator, a trigger and an AND gate; the output end of the comparator is connected with the input end of the trigger, the output end of the trigger is connected with the input end of the AND gate, the other end of the AND gate is connected with a clock signal clk, and the output end of the AND gate controls an output signal of the clock generation module (102).
8. The switched capacitor voltage regulation chip circuit of claim 7, wherein: the flip-flop is a dff flip-flop.
9. The switched capacitor voltage regulation chip circuit of claim 1, wherein: the current detection module (105) consists of six transistors and an operational amplifier; and the capacitance resistor in the current detection module (105) has a filtering function.
10. The dual-control-mode switched-capacitor voltage regulation chip circuit of claim 9, wherein: the transistor is a mos transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210569345.3A CN114900036A (en) | 2022-05-24 | 2022-05-24 | Switched capacitor voltage-stabilizing chip circuit with double control modes |
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| CN202210569345.3A CN114900036A (en) | 2022-05-24 | 2022-05-24 | Switched capacitor voltage-stabilizing chip circuit with double control modes |
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2022
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Application publication date: 20220812 |