CN113098309B - Digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control - Google Patents

Digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control Download PDF

Info

Publication number
CN113098309B
CN113098309B CN202110267299.7A CN202110267299A CN113098309B CN 113098309 B CN113098309 B CN 113098309B CN 202110267299 A CN202110267299 A CN 202110267299A CN 113098309 B CN113098309 B CN 113098309B
Authority
CN
China
Prior art keywords
bridge arm
current side
neutral point
point potential
digital delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110267299.7A
Other languages
Chinese (zh)
Other versions
CN113098309A (en
Inventor
周兴达
郭明珠
尹立坤
唐博进
张若愚
郝峰杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Three Gorges Corp
Original Assignee
China Three Gorges Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China Three Gorges Corp filed Critical China Three Gorges Corp
Priority to CN202110267299.7A priority Critical patent/CN113098309B/en
Publication of CN113098309A publication Critical patent/CN113098309A/en
Application granted granted Critical
Publication of CN113098309B publication Critical patent/CN113098309B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]

Abstract

The invention discloses a digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control, which mainly aims to eliminate the adverse effect of digital delay on the three-level topology direct-current side neutral point potential balance control. In practical engineering applications, the three-level converter generally adopts digital control, and the digital control has inherent digital delay, and the digital delay causes additional fluctuation of the neutral point potential on the direct current side of the three-level topology. The invention adds a digital delay compensation link on the basis of the general neutral point potential balance control of the three-level topology direct current side, thereby eliminating the neutral point potential fluctuation of the three-level topology direct current side caused by digital delay. In addition, the digital delay compensation method provided by the invention is not only suitable for three-bridge arm three-level topology, but also suitable for neutral point potential balance control of any bridge arm number on the direct current side of the three-level topology.

Description

Digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control
Technical Field
The invention relates to the technical field of three-level power electronic converters, in particular to a digital delay compensation method for neutral point potential balance control of a multi-bridge arm three-level topology direct-current side.
Background
Since the first proposal in 1981, the neutral point diode clamp type three-level topology has been widely used in the fields of motor drivers, grid-connected inverters, active power filters and the like. The three-level topology has significant advantages over the conventional two-level topology, such as lower switching voltage stress and smaller passive filter volume. However, the three-level topology also has its drawbacks, the most prominent one being: an additional control method is required to keep the neutral point potential balance of the direct current side. Without proper balancing control, the difference between the two capacitor voltages on the dc side can become large in some extreme cases, leading to distortion of the output current waveform and even overvoltage damage to the switching device.
Various carrier pulse width modulation (CBPWM) based three-level direct current side neutral point potential balancing methods are most widely applied. The balance method based on CBPWM essentially comprises the steps of calculating a proper common mode voltage, and superposing the calculated common mode voltage on an original modulation signal to realize balance control of the neutral point potential of a three-level direct current side. According to the relation between the neutral point potential and the neutral point average current on the dc side, the document [1] q.song, w.liu, q.yu, et al.a. neutral-point potential balancing algorithm for the same-level NPC inverting and using the same with respect to the estimated zero-sequence voltage [ C ]. IEEE applied Power Electronics Conference,2003. The document [2] C.Wang, Y.Li.analysis and calculation of zero-sequence voltage regulating in three-level NPC converters [ J ]. IEEE Transactions on Industrial Electronics,2010,57(7): 2262-2271 ] proposes a precise calculation method of common-mode voltage, which is a more general neutral point potential balancing method on the three-level topology DC side. The above balancing method ignores the effect of digitally controlled delays in practical engineering applications.
Digital Signal Processors (DSPs) have been widely used in industrial control, and have the advantages of convenient programming and less susceptibility to external interference. However, the digital control method cannot avoid a digital delay of one control period, which results in a decrease in the control performance of the balancing method, as compared with the analog control. Document [3] X.Zhou and S.Lu, "information of Digital Delay on the Zero-Sequence Voltage Injection Neutral-Point Potential Balance for Three-Level NPC Inverters and Its Compensation Method," in IEEE Access, vol.7, pp.71593-71606,2019, doi:10.1109/ACCESS.2019.2920275.
Disclosure of Invention
Aiming at the problems, the invention provides a digital delay compensation method for multi-bridge arm three-level topology direct current side neutral point potential balance control, and the method mainly aims to eliminate the adverse effect of digital delay on the three-level topology direct current side neutral point potential balance control. The invention adds a digital delay compensation link on the basis of the general neutral point potential balance control of the three-level topology direct current side, thereby eliminating the neutral point potential fluctuation of the three-level topology direct current side caused by digital delay. In addition, the digital delay compensation method provided by the invention is not only suitable for three-bridge arm three-level topology, but also suitable for neutral point potential balance control of a three-level topology direct-current side with any bridge arm number.
The technical scheme adopted by the invention is as follows:
the digital delay compensation method for neutral point potential balance control of the multi-bridge arm three-level topology direct-current side comprises the following steps of:
s1, firstly, defining a common mode voltage calculation method of the neutral point potential balance control of the general multi-bridge arm three-level direct current side without digital delay compensation to be expressed by a function F, wherein the form is shown as formula (1):
vcom(kTs)＝F(△vdc(kTs),ia,b,c,...,n(kTs),vA,B,C,...,N(kTs)) (1)；
wherein: t issA digital control period representing a common mode voltage calculation method;
k represents the k-th digital control period of the common-mode voltage calculation method;
Δvdc(kTs) Expressed in kTsDigitally controlling the voltage difference value of upper and lower capacitors on the direct current side of the multi-bridge arm three-level converter at periodic time;
ia,b,c,...,n(kTs) Expressed in kTsThe alternating current side of the multi-bridge arm three-level converter outputs current at a digital control period moment;
vA(kTs)、vB(kTs)、vC(kTs)、…、vN(kTs) Is expressed in kTsAnd normalizing modulation signals of each bridge arm of the multi-bridge arm three-level converter without adding common-mode components in the digital control period.
S2, normalizing the modulated wave signal v of each bridge arm in each control periodA(kTs)、vB(kTs)、vC(kTs)、…、vN(kTs) The definitions are as follows from big to small: v. of1(kTs)、v2(kTs)、v3(kTs)、…、vn(kTs) And define i1(kTs)、i2(kTs)、 i3(kTs)、…、in(kTs) Is v is1(kTs)、v2(kTs)、v3(kTs)、…、vn(kTs) The corresponding alternating current side outputs current;
s3 definition of Δ vdc((k+1)Ts) Is (k +1) TsThe invention is characterized in that delta v is provided for controlling the difference value of the upper and lower capacitance voltages at the direct current side of the multi-bridge arm three-level converter at the periodic time by digital controldc((k+1)Ts) The calculation expression of (2) is shown as formula (2):
Figure BDA0002972652420000031
s4, converting the delta v in the formula (1)dc(kTs) By Δ vdc((k+1)Ts) Instead of calculating the common-mode voltage vcom(kTs) Is calculated to obtain a final common mode voltage vcom(kTs) The expression of (b) is shown in formula (3).
vcom(kTs)＝F(△vdc((k+1)Ts),ia,b,c,...,n(kTs),vA,B,C,...,N(kTs)) (3)；
S5 calculating the final common mode voltage v obtained in the formula (3)com(kTs) Adding to each bridge arm normalized modulated wave vA(kTs)、vB(kTs)、vC(kTs)、…、vN(kTs) In the middle, digital delay compensation of multi-bridge arm three-level direct-current side neutral point potential balance control can be realized.
Due to the adoption of the technical scheme, the invention has the following advantages:
the invention discloses a digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control, which mainly aims to eliminate the adverse effect of digital delay on the three-level topology direct-current side neutral point potential balance control. In practical engineering applications, the three-level converter generally adopts digital control, and the digital control has inherent digital delay, and the digital delay causes additional fluctuation of the neutral point potential on the direct current side of the three-level topology. The invention adds a digital delay compensation link on the basis of the general neutral point potential balance control of the three-level topology direct current side, thereby eliminating the neutral point potential fluctuation of the three-level topology direct current side caused by digital delay. In addition, the digital delay compensation method provided by the invention is not only suitable for three-bridge arm three-level topology, but also suitable for neutral point potential balance control of a three-level topology direct-current side with any bridge arm number.
Drawings
Fig. 1 is a multi-bridge arm three-level converter topology diagram.
Fig. 2 is a block diagram of neutral point potential balance control on the direct current side of a multi-bridge arm three-level converter with digital delay compensation.
Fig. 3 is a simulated waveform diagram of dc side voltage using a general three-level dc side neutral point potential balance control without digital delay compensation.
Fig. 4 is a waveform diagram of a dc side voltage simulation using the three-level dc side neutral point potential balance control digital delay compensation method proposed herein.
Detailed Description
A digital delay compensation method for neutral point potential balance control of a multi-bridge arm three-level topology direct-current side is disclosed. The method mainly aims to eliminate the adverse effect of digital delay on the neutral point potential balance control of the three-level topological direct-current side. In practical engineering applications, the three-level converter generally adopts digital control, and the digital control has inherent digital delay, and the digital delay can cause additional fluctuation of the neutral point potential on the direct current side of the three-level topology. The invention adds a digital delay compensation link on the basis of the general neutral point potential balance control of the three-level topology direct current side, thereby eliminating the neutral point potential fluctuation of the three-level topology direct current side caused by digital delay. In addition, the digital delay compensation method provided by the invention is not only suitable for three-bridge arm three-level topology, but also suitable for neutral point potential balance control of a three-level topology direct-current side with any bridge arm number.
The following describes the specific implementation steps of the present invention by taking a four-leg three-level converter as an example.
First, at kTsThe difference value delta v of the upper and lower capacitor voltages at the direct current side of the four-bridge arm three-level converter is obtained by sampling at a momentdc(kTs) The output current of the alternating current side of the four-leg converter is ia(kTs)、ib(kTs)、ic(kTs)、id(kTs) And the normalized modulation signal of each bridge arm without adding the common-mode component is vA(kTs)、vB(kTs)、vC(kTs)、vD(kTs). In addition, the capacitance values of two direct current sides of the three-level converter are defined to be C, and the control period of the digital control algorithm of the three-level converter is defined to be Ts. Defining a general common mode voltage calculation method for neutral point potential balance control on a three-level direct current side, the common mode voltage calculation method is expressed by a function F, as shown in formula (1).
vcom(kTs)＝F(△vdc(kTs),ia,b,c,d(kTs),vA,B,C,D(kTs)) (1)；
The detailed derivation process of formula (1) is not given here, and is only replaced by the function symbol F, because the common mode voltage calculation method of the general three-level dc-side neutral point potential balance control without digital delay compensation is mature, and many documents have been studied, and the specific derivation process can be found in documents [4] x.zhou, s.lu, a single zero-sequence voltage information method to basic the neutral-point potential for the same three-level NPC inverters,2018IEEE Applied Power Electronics Conference and exposure (APEC), San Antonio, TX, USA,2018, pp.2471-2475.
As can be seen from equation (1), the existing common-mode voltage vcom(kTs) The calculation process is based on kTsVariables sampled at one time, e.g. Δ vdc(kTs)、vA,B,C,D(kTs)、ia,b,c,d(kTs) But due to the presence of the digital delay control a common mode voltage vcom(kTs) The output and the effect are generated after a digital delay control, and the direct current side neutral point potential of the three-level converter is fluctuated due to the digital delay.
To solve this problem, if the time (k +1) T is predicted by some methodsΔ v of timedc((k+1)Ts) And Δ v in the formula (1)dc(kTs) By Δ vdc((k+1)Ts) Instead of calculating the common-mode voltage vcom(kTs) The fluctuation of the digital delay generated to the neutral point potential of the three-level DC side can be eliminated.
To obtain Δ vdc((k+1)Ts) Firstly, normalizing the modulation wave signal v of each bridge arm in each control period obtained by samplingA(kTs)、vB(kTs)、vC(kTs)、vD(kTs) V is defined as the order from big to small1(kTs)、v2(kTs)、v3(kTs)、 v4(kTs) And will ia(kTs)、ib(kTs)、ic(kTs)、id(kTs) Is defined as i1(kTs)、i2(kTs)、i3(kTs)、i4(kTs) Wherein i1(kTs)、i2(kTs)、i3(kTs)、i4(kTs) Is v is1(kTs)、v2(kTs)、v3(kTs)、v4(kTs) The corresponding ac side outputs current.
The most important invention point of the invention is to provide the delta v in the neutral point potential balance algorithm of the direct current side of the multi-bridge arm three-level converterdc((k+1)Ts) The expression (2) shows that, here, a four-leg three-level converter is taken as an example:
Figure BDA0002972652420000051
wherein v isi(kTs) Represents kTsNormalizing modulation signals of all bridge arms without adding common-mode components into the four-bridge arm three-level converter at the moment; v. ofcom((k-1) represents (k-1) TsCommon mode voltage v obtained by time calculationcomA value of (d); i.e. ii(kTs) Represents kTsAnd outputting current at the alternating current side of the four-leg converter at the moment.
Further, Δ v in the formula (1)dc(kTs) By Δ v in equation (2)dc((k+1)Ts) Alternatively, an expression of the final common mode voltage may be calculated as shown in equation (3).
vcom(kTs)＝F(△vdc((k+1)Ts),ia,b,c,d(kTs),vA,B,C,D(kTs)) (3)；
Finally, adding the calculated final common-mode voltage to the normalized modulation wave v of each bridge armA(kTs)、vB(kTs)、vC(kTs)、 vD(kTs) In the method, the balance control of the neutral point potential on the multi-bridge arm three-level direct current side with the digital delay function can be realized. As shown in fig. 2. The dotted line frame in fig. 2 represents a digital delay compensation method for multi-bridge arm three-level dc-side neutral point potential balance control proposed by the present invention, and the portion outside the dotted line frame in fig. 2 represents a general three-level dc-side neutral point potential balance control block diagram without digital delay compensation.
In order to illustrate the effectiveness of the invention, a four-leg three-level converter simulation model is built based on MATLAB/SIMULINK software, and the converter topology part of the simulation model is shown in FIG. 1. DC side total voltage v of simulation modeldc150V, a direct current side capacitance value C is 0.7mF, each phase of load resistance R at the alternating current side of the simulation model is 2 ohms, the turn-to ratio of each phase of bridge arm modulation signal of the simulation model is 0.9, each phase of output current peak value at the alternating current side of the simulation model is 33A, and a control algorithm control period T in the simulation models0.0001 second.
Fig. 3 and 4 show simulation waveforms of upper and lower capacitor voltages on the dc side of the four-leg three-level converter obtained based on the simulation model, where fig. 3 shows a simulation result without digital delay compensation, fig. 4 shows a simulation result after the digital delay compensation method provided by the present invention is adopted, and it can be seen from the simulation result that after the digital delay compensation method provided by the present invention is adopted, the difference value of the upper and lower capacitor voltages on the dc side of the four-leg three-level converter is reduced from 6V to 2V, the neutral point potential on the dc side of the four-leg three-level converter is more stable, and the above results demonstrate the correctness and effectiveness of the present invention.

Claims (1)

1. The digital delay compensation method for neutral point potential balance control of the multi-bridge arm three-level topology direct-current side is characterized by comprising the following steps of:
s1, firstly, defining a common-mode voltage calculation method of the multi-bridge arm three-level direct-current side neutral point potential balance control without digital delay compensation to be expressed by a function F, wherein the form is shown as formula (1):
vcom(kTs)＝F(△vdc(kTs),ia,b,c,...,n(kTs),vA,B,C,...,N(kTs)) (1)；
wherein: t is a unit ofsA digital control period representing a common mode voltage calculation method;
k represents the k-th digital control period of the common-mode voltage calculation method;
Δvdc(kTs) Expressed in kTsDigitally controlling the voltage difference value of upper and lower capacitors on the direct current side of the multi-bridge arm three-level converter at periodic time;
ia,b,c,...,n(kTs) Expressed in kTsThe alternating current side of the multi-bridge arm three-level converter outputs current at a digital control period moment; v. ofA(kTs)、vB(kTs)、vC(kTs)、…、vN(kTs) Expressed in kTsNormalizing modulation signals of each bridge arm of the multi-bridge arm three-level converter without adding common-mode components in a digital control period;
s2, normalizing the modulated wave signal v of each bridge arm in each control periodA(kTs)、vB(kTs)、vC(kTs)、…、vN(kTs) The definitions are as follows from big to small: v. of1(kTs)、v2(kTs)、v3(kTs)、…、vn(kTs) And define i1(kTs)、i2(kTs)、i3(kTs)、…、in(kTs) Is v1(kTs)、v2(kTs)、v3(kTs)、…、vn(kTs) The corresponding alternating current side outputs current;
s3 definition of Δ vdc((k+1)Ts) Is (k +1) TsNumerical control periodic time multi-bridge arm three-level converter DC side upper and lower capacitance voltage difference value delta vdc((k+1)Ts) The calculation expression of (2) is shown as formula (2):
Figure FDA0002972652410000011
s4, converting the delta v in the formula (1)dc(kTs) By Δ vdc((k+1)Ts) Instead of calculating the common-mode voltage vcom(kTs) To calculate the final common-mode voltage vcom(kTs) The expression of (b) is shown in formula (3);
vcom(kTs)＝F(△vdc((k+1)Ts),ia,b,c,...,n(kTs),vA,B,C,...,N(kTs)) (3)；
s5 calculating the final common mode voltage v obtained in the formula (3)com(kTs) Adding to each bridge arm normalized modulated wave vA(kTs)、vB(kTs)、vC(kTs)、…、vN(kTs) In the middle, digital delay compensation of multi-bridge arm three-level direct-current side neutral point potential balance control can be realized.
CN202110267299.7A 2021-03-11 2021-03-11 Digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control Active CN113098309B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110267299.7A CN113098309B (en) 2021-03-11 2021-03-11 Digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110267299.7A CN113098309B (en) 2021-03-11 2021-03-11 Digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control

Publications (2)

Publication Number Publication Date
CN113098309A CN113098309A (en) 2021-07-09
CN113098309B true CN113098309B (en) 2022-07-12

Family

ID=76667411

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110267299.7A Active CN113098309B (en) 2021-03-11 2021-03-11 Digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control

Country Status (1)

Country Link
CN (1) CN113098309B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103490655A (en) * 2012-06-07 2014-01-01 Abb研究有限公司 Method and apparatus for zero-sequence damping and voltage balancing
CN107404239A (en) * 2016-05-18 2017-11-28 整流器技术太平洋有限公司 There is no the three-phase activity coefficient adjustment AC DC self-balancing rectifiers that neutral point connects
CN111509732A (en) * 2020-04-26 2020-08-07 哈尔滨理工大学 Multi-level topological reactive power compensation device with fault-tolerant function and compensation method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8570776B2 (en) * 2011-05-27 2013-10-29 Alstom Technology Ltd Method and device for determining a control scheme for an active power filter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103490655A (en) * 2012-06-07 2014-01-01 Abb研究有限公司 Method and apparatus for zero-sequence damping and voltage balancing
CN107404239A (en) * 2016-05-18 2017-11-28 整流器技术太平洋有限公司 There is no the three-phase activity coefficient adjustment AC DC self-balancing rectifiers that neutral point connects
CN111509732A (en) * 2020-04-26 2020-08-07 哈尔滨理工大学 Multi-level topological reactive power compensation device with fault-tolerant function and compensation method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
NPC三电平容错逆变器异步电机驱动系统FCS-MPTC;张磊等;《铁道科学与工程学报》;20200115(第01期);全文 *
农业装备中三电平二极管箝位式逆变器拓扑结构的改进;刘国海等;《农业工程学报》;20131115(第22期);全文 *

Also Published As

Publication number Publication date
CN113098309A (en) 2021-07-09

Similar Documents

Publication Publication Date Title
Zhang et al. Study of multisampled multilevel inverters to improve control performance
US8471514B2 (en) Adaptive harmonic reduction apparatus and methods
CN107681915A (en) Based on the multi-electrical level inverter combination method and device for determining frequency finite aggregate model prediction
Celikovic et al. Modeling of capacitor voltage imbalance in flying capacitor multilevel dc-dc converters
Dalessandro et al. A novel hysteresis current control for three-phase three-level PWM rectifiers
CN103701355A (en) Control system of NPC (Neutral Point Clamped) tri-level half-bridge inverter and voltage sharing control method
CN113098309B (en) Digital delay compensation method for multi-bridge arm three-level topology direct-current side neutral point potential balance control
CN108964119A (en) A kind of three level grid-connected inverter common-mode voltage predictor method of T-type
WO2022188629A1 (en) Direct-current side neutral-point potential balancing method suitable for three-level converter having any number of bridge arms
CN116979535A (en) Dual harmonic current detection method for active power filter
CN109687748B (en) Modulation and capacitance voltage balance control method of neutral point clamped five-level converter
He et al. A universal multicarrier multisampling method for digitally controlled inverters
CN107994796B (en) Control method and device of single-phase converter
CN111064380A (en) Grid-connected inverter system
CN110912435A (en) Neutral point voltage balance control method of three-level inverter
Mouton et al. Trajectory-based LQR control of a grid-connected converter with an LCL filter
Komurcugil et al. Sliding-mode and proportional-resonant based control strategy for three-phase grid-connected LCL-filtered VSI
CN111628643B (en) Method for predicting current sampling in PFC control
CN110995044B (en) Nonlinear correction device for power switch device
CN107359804B (en) Dead-beat control method for LCL type three-level grid-connected inverter
Sharma et al. Neural network-based three-phase NPC rectifier for DC bus capacitor voltage balancing under perturbed mains supply conditions
CN109217691B (en) MMC submodule capacitor voltage balance control method based on state observer
Tan et al. Deadbeat plus fractional-order repetitive control for grid-tied inverter
Wang et al. Selection Design of Low Frequency Voltage Ripple Suppression for MMC Sub-Module based on Split Capacitor
CN111446873B (en) Nonlinear passive current control method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant