CN111562481A - Compound semiconductor chip on-chip test circuit based on power-on probe - Google Patents
Compound semiconductor chip on-chip test circuit based on power-on probe Download PDFInfo
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- CN111562481A CN111562481A CN202010449991.7A CN202010449991A CN111562481A CN 111562481 A CN111562481 A CN 111562481A CN 202010449991 A CN202010449991 A CN 202010449991A CN 111562481 A CN111562481 A CN 111562481A
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- probe
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/36—Overload-protection arrangements or circuits for electric measuring instruments
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention is suitable for the technical field of on-chip test of chips, and provides a compound semiconductor chip on-chip test circuit based on a power-up probe, which comprises a grid power-up probe and a drain power-up probe, and also comprises: a switch unit and a voltage limiting unit; the first end of the switch unit is connected with the grid power-on probe, the second end of the switch unit is grounded, and the third end of the switch unit is connected with one end of the voltage limiting unit; the other end of the voltage limiting unit is connected with the drain electrode power-up probe. The voltage and the current of the drain electrode power-on probe applied to the compound semiconductor chip are limited within a safe range through the switch unit and the voltage limiting unit, so that the problems that when the drain electrode power-on probe is powered on firstly, the drain electrode of the compound semiconductor chip is easy to form very high current, the performance of the chip is degraded, and even the chip is burnt are solved.
Description
Technical Field
The invention belongs to the technical field of on-chip testing of chips, and particularly relates to a compound semiconductor chip on-chip testing circuit based on a power-up probe.
Background
The compound semiconductor chip mainly refers to chips such as a low noise amplifier, a power amplifier, a switch, a frequency multiplier, a mixer, and the like, of which active devices are High Electron Mobility Transistors (HEMTs) of gallium arsenide, indium phosphide, or gallium nitride. The chip requires dc power to the chip with power-up probes during chip testing. When the grid and the drain of the circuit need to be powered respectively, the grid is powered firstly, and then the drain is powered, if the grid power-on probe is not powered for some reason, and the drain power-on probe is powered, the drain of the chip is easy to generate very high current, so that the performance of the chip is degraded, and the chip is even burnt.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a circuit for testing a compound semiconductor chip on a chip based on a power-up probe, so as to solve the problem in the prior art that when a gate power-up probe is not powered up and a drain power-up probe is powered up, a very high current is easily formed at a drain of the compound semiconductor chip, which causes degradation of chip performance and even burns out the chip.
A first aspect of embodiments of the present invention provides a power-on probe-based compound semiconductor chip on-chip test circuit, including a gate power-on probe and a drain power-on probe, wherein, during a chip test, the gate power-on probe is connected to a compound semiconductor chip through a gate power-on pad, the drain power-on probe is connected to the compound semiconductor chip through a drain power-on pad, and the power-on probe-based compound semiconductor chip on-chip test circuit further includes: a switch unit and a voltage limiting unit;
the first end of the switch unit is connected with the grid electrode power-on probe, the second end of the switch unit is grounded, the third end of the switch unit is connected with one end of the voltage limiting unit, and the other end of the voltage limiting unit is connected with the drain electrode power-on probe;
the switch unit and the voltage limiting unit are used for limiting the voltage applied to the compound semiconductor chip by the drain energizing probe when the grid energizing probe is not energized and the drain energizing probe is energized.
Optionally, the switch unit is a switch tube;
the grid electrode of the switch tube is connected with the grid electrode power-on probe, the source electrode of the switch tube is grounded, the drain electrode of the switch tube is connected with one end of the voltage limiting unit, and the other end of the voltage limiting unit is connected with the drain electrode power-on probe.
Optionally, the voltage limiting unit is a diode;
the negative pole of the diode is connected with the drain electrode of the switching tube, and the positive pole of the diode is connected with the drain electrode electrification probe.
Optionally, the switch tube is a depletion type insulated gate field effect tube.
Optionally, the depletion type insulated gate field effect transistor is an N-channel depletion type insulated gate field effect transistor or a P-channel depletion type insulated gate field effect transistor.
Optionally, a position where the first end of the switch unit is connected with the grid energizing probe is 1cm to 50cm away from a needle point of the grid energizing probe;
the distance between the part of the voltage limiting unit connected with the drain electrode electrification probe and the tip of the drain electrode electrification probe is 1 cm-50 cm.
Optionally, the first end of the switch unit and the gate energizing probe, and the voltage limiting unit and the drain energizing probe are connected by welding via wires.
Optionally, the gate energizing probe and the drain energizing probe are in a line type structure or a broken line type structure.
Optionally, the diode is a silicon diode or a germanium diode.
Optionally, the compound semiconductor chip on-chip test circuit based on the power-on probe further includes a probe pin base for fixing the gate power-on probe and the drain power-on probe respectively.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: through the switch unit and the voltage limiting unit, when the compound semiconductor chip is tested on a chip, the voltage applied to the compound semiconductor chip by the drain electrode power-on probe is limited when the grid electrode power-on probe is not powered, and the current of the drain electrode of the compound semiconductor chip is limited by grounding the second end of the switch unit; the current and the voltage applied to the compound semiconductor chip by the drain electrode energizing probe are limited within a safe range, and the problems that the grid electrode energizing probe is not energized, and when the drain electrode energizing probe is energized, the drain electrode of the compound semiconductor chip is easy to form very high current, so that the performance of the chip is degraded, and even the chip is burnt are solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a prior art compound semiconductor chip-on-chip test circuit based on a powered probe;
FIG. 2 is a schematic diagram of a compound semiconductor chip on-chip test circuit based on a power-on probe according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating the current flow when the drain power-up probe is powered up according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the flow of current when the gate power-up probe is powered up first and then the drain power-up probe is powered up according to an embodiment of the present invention;
FIG. 5(1) is a schematic diagram of a gate probe/drain probe configuration according to an embodiment of the present invention;
FIG. 5(2) is a schematic diagram of a structure of a gate probe/drain probe according to another embodiment of the present invention;
FIG. 6(1) is a front view of a compound semiconductor chip on-chip test circuit based on a power-on probe according to an embodiment of the present invention;
fig. 6(2) is a top view of a compound semiconductor chip on-chip test circuit based on a power-on probe according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 2, a power-up probe-based compound semiconductor chip on-chip test circuit including a gate power-up probe connected to a compound semiconductor chip through a gate power-up pad and a drain power-up probe connected to the compound semiconductor chip through a drain power-up pad at the time of chip test, further includes: a switch unit and a voltage limiting unit.
The first end of the switch unit is connected with the grid electrode power-on probe, the second end of the switch unit is grounded, the third end of the switch unit is connected with one end of the voltage limiting unit, and the other end of the voltage limiting unit is connected with the drain electrode power-on probe; and the switch unit and the voltage limiting unit are used for limiting the voltage applied to the compound semiconductor chip by the drain electrode power-on probe when the grid electrode power-on probe is not powered on and the drain electrode power-on probe is powered on.
The compound semiconductor chip may be a conventional GaAs, InP or GaN field effect transistor chip, or a multifunctional circuit chip such as a low noise amplifier, a power amplifier, a switch, a frequency multiplier, a mixer, a phase shifter or a switch including a GaAs, InP or GaN field effect transistor, and when performing a chip test on such a chip, a gate or a drain of the chip needs to be dc-powered by a power-up probe, as shown in fig. 1, a conventional gate power-up probe and a conventional drain power-up probe are independent from each other, and after the gate power-up probe or the drain power-up probe is respectively powered up, the gate power-up probe or the drain power-up probe is connected to the chip through a gate power-up PAD (PAD) or a drain power-up PAD (PAD) on the chip to. In this case, however, if no voltage is applied to the gate energizing probe, when the dc power supply energizes the drain energizing probe, the drain of the compound semiconductor chip is liable to generate a very high current, which may cause deterioration of the chip performance or even burn-out of the chip.
According to the embodiment of the invention, the switch unit and the voltage limiting unit are arranged between the grid energizing probe and the drain energizing probe, through the switch unit and the voltage limiting unit, when the compound semiconductor chip is tested on a chip, the grid energizing probe can be not energized, when the drain energizing probe is energized, the voltage applied to the compound semiconductor chip by the drain energizing probe is limited, and the current of the drain of the compound semiconductor chip is limited through the grounding of the second end of the switch unit; the current and the voltage applied to the compound semiconductor chip by the drain electrode energizing probe are limited within a safe range, and the problems that the grid electrode energizing probe is not energized, and when the drain electrode energizing probe is energized, the drain electrode of the compound semiconductor chip is easy to form very high current, so that the performance of the chip is degraded, and even the chip is burnt are solved.
Optionally, the switch unit may be a switch tube, and the voltage limiting unit may be a diode.
At the moment, the grid electrode of the switch tube is connected with the grid electrode energizing probe, the source electrode of the switch tube is grounded, the drain electrode of the switch tube is connected with the cathode of the diode, and the anode of the diode is connected with the drain electrode energizing probe. When the grid electrode energizing probe is not energized and the drain electrode energizing probe is energized, the voltage applied to the compound semiconductor chip by the drain electrode energizing probe is limited through the diode, and meanwhile, the current of the drain electrode of the compound semiconductor chip is limited through the grounding of the source electrode of the switching tube, so that the current and the voltage applied to the compound semiconductor chip by the drain electrode energizing probe are both limited within a safe range.
The switching tube and the diode can adopt discrete devices, the diode can be a silicon diode or a germanium diode, the voltage applied to the compound semiconductor chip by the drain electrode electrification probe can be limited within the threshold voltage range of the diode, and further the voltage applied to the compound semiconductor chip by the drain electrode electrification probe is limited within the safety range. The present invention does not limit the diode as long as the voltage across the compound semiconductor chip connected in parallel therewith can be limited within a safe range.
Referring to fig. 3, when the gate energizing probe is not energized and the drain energizing probe is energized, the diode can limit the voltage applied to the compound semiconductor chip by the drain energizing probe within the threshold voltage range of the diode, and simultaneously, a drain current is generated through the switching tube, and the drain current is grounded through the source to limit the current of the drain of the compound semiconductor chip within the safe current range.
Referring to fig. 4, when the grid power-on probe is powered up first and then the drain power-on probe is powered up, the | U of the switching tubeGSIf the switch tube is exhausted, the grid energizing probe and the drain energizing probe can respectively energize the grid and the drain of the compound semiconductor chip through the grid energizing PAD and the drain energizing PAD.
Optionally, the switching tube may be a depletion mode insulated gate field effect transistor.
Wherein, for depletion type insulated gate field effect transistor, the voltage at gate source is UGSWhen equal to 0, a conducting channel is established in the field effect tube, and a drain-source voltage U is addedDSThen, a drain current I can be generatedDAdding appropriate UGSAfter, drain current IDWill gradually decrease to none. That is, the probe is not energized at the gate, i.e., UGS0, the drain energizing probe is energized, i.e. UDSWhen the power-on probe of the grid electrode is not electrified, the drain electrode of the compound semiconductor chip forms very high current when the power-on probe of the drain electrode is electrified, so that the performance of the chip is prevented from being degraded and even burntThe problem of chip destruction.
Optionally, when the dc voltage applied to the gate energizing probe is a negative voltage, the depletion type insulated gate field effect transistor is an N-channel depletion type insulated gate field effect transistor; when the direct current voltage applied to the grid electrode electrifying probe is positive voltage, the depletion type insulated gate field effect transistor is a P-channel depletion type insulated gate field effect transistor.
Optionally, the first end of the switch unit and the gate energizing probe, and the voltage limiting unit and the drain energizing probe are connected by welding via wires.
As an embodiment of the invention, the position of the first end of the switch unit, which is connected with the grid energizing probe, is 1 cm-50 cm away from the needle point of the grid energizing probe; the part of the voltage limiting unit connected with the drain electrode electrification probe is 1 cm-50 cm away from the tip of the drain electrode electrification probe. The problem of test consistency caused by deformation of a needle point easily caused by the fact that the connected position is too close to the needle point of the grid energizing probe or the needle point of the drain energizing probe is solved.
Alternatively, the gate energizing probe and the drain energizing probe in the embodiment of the present invention may be line-type structures shown in fig. 5(1), or zigzag-type structures shown in fig. 5 (2).
As an embodiment of the present invention, the compound semiconductor chip on-chip test circuit based on a power-up probe may further include a probe pin holder for respectively fixing the gate power-up probe and the drain power-up probe.
Referring to fig. 6(1) and 6(2), the power-on probe-based compound semiconductor chip on-chip test circuit may be located on a probe stage, the probe stage may have probe sockets for fixedly mounting the gate power-on probe and the drain power-on probe, respectively, and a stage for carrying the compound semiconductor chip, and the first end of the switch unit is connected to the gate power-on probe and the voltage limiting unit is connected to the drain power-on probe by soldering via wires, so as to facilitate fixing.
According to the embodiment of the invention, a grid electrode power-on probe and a drain electrode power-on probe are fixedly arranged on a probe needle seat, a switch unit and a voltage limiting unit are arranged between the grid electrode power-on probe and the drain electrode power-on probe, when a compound semiconductor chip is tested on a wafer, the grid electrode power-on probe is not powered, when the drain electrode power-on probe is powered, the voltage applied to the compound semiconductor chip by the drain electrode power-on probe is limited, and meanwhile, the current of the drain electrode of the compound semiconductor chip is limited by grounding the second end of the switch unit; the current and the voltage applied to the compound semiconductor chip by the drain electrode energizing probe are limited within a safe range, and the problems that the grid electrode energizing probe is not energized, and when the drain electrode energizing probe is energized, the drain electrode of the compound semiconductor chip is easy to form very high current, so that the performance of the chip is degraded, and even the chip is burnt are solved.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A power-probe-based compound semiconductor chip-on-chip test circuit comprising a gate power-up probe connected to a compound semiconductor chip through a gate power-up pad and a drain power-up probe connected to the compound semiconductor chip through a drain power-up pad during chip testing, further comprising: a switch unit and a voltage limiting unit;
the first end of the switch unit is connected with the grid electrode power-on probe, the second end of the switch unit is grounded, the third end of the switch unit is connected with one end of the voltage limiting unit, and the other end of the voltage limiting unit is connected with the drain electrode power-on probe;
the switch unit and the voltage limiting unit are used for limiting the voltage applied to the compound semiconductor chip by the drain energizing probe when the grid energizing probe is not energized and the drain energizing probe is energized.
2. The power-on probe-based compound semiconductor chip on-chip test circuit of claim 1, wherein the switching unit is a switching tube;
the grid electrode of the switch tube is connected with the grid electrode power-on probe, the source electrode of the switch tube is grounded, the drain electrode of the switch tube is connected with one end of the voltage limiting unit, and the other end of the voltage limiting unit is connected with the drain electrode power-on probe.
3. The power-up probe-based compound semiconductor chip on-chip test circuit of claim 2, wherein the voltage limiting unit is a diode;
the negative pole of the diode is connected with the drain electrode of the switching tube, and the positive pole of the diode is connected with the drain electrode electrification probe.
4. The power-on probe-based compound semiconductor chip on-chip test circuit of claim 2, wherein the switching transistor is a depletion mode insulated gate field effect transistor.
5. The power-on probe-based compound semiconductor chip on-chip test circuit of claim 4, wherein the depletion mode insulated gate field effect transistor is an N-channel depletion mode insulated gate field effect transistor or a P-channel depletion mode insulated gate field effect transistor.
6. The power-on probe-based compound semiconductor chip on-chip test circuit according to any one of claims 1 to 5,
the distance between the first end of the switch unit and the connection part of the grid energizing probe is 1 cm-50 cm from the needle point of the grid energizing probe;
the distance between the part of the voltage limiting unit connected with the drain electrode electrification probe and the tip of the drain electrode electrification probe is 1 cm-50 cm.
7. The power-on probe-based compound semiconductor chip on-chip test circuit according to any one of claims 1 to 5,
the first end of the switch unit is connected with the grid electrode power-on probe, and the voltage limiting unit is connected with the drain electrode power-on probe through wires in a welding mode.
8. The power-on probe-based compound semiconductor chip on-chip test circuit of any one of claims 1 to 5, wherein the gate power-on probe and the drain power-on probe are of a linear structure or a zigzag structure.
9. The power-on probe-based compound semiconductor chip on-chip test circuit of claim 3, wherein the diode is a silicon diode or a germanium diode.
10. The power-on-probe-based compound semiconductor chip on-chip test circuit of claim 1, further comprising probe pins for respectively holding said gate power-on probe and said drain power-on probe.
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| CN202010449991.7A CN111562481B (en) | 2020-05-25 | 2020-05-25 | Compound semiconductor chip on-chip test circuit based on power-on probe |
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007137284A2 (en) * | 2006-05-23 | 2007-11-29 | Integrated Technology Corporation | Probe needle protection method for high current probe testing of power devices |
| CN101216528A (en) * | 2008-01-15 | 2008-07-09 | 中国科学院上海微系统与信息技术研究所 | On-chip test method for microwave power amplifier chip and its test system |
| US20080290882A1 (en) * | 2006-05-23 | 2008-11-27 | Integrated Technology Corporation | Probe needle protection method for high current probe testing of power devices |
| CN102157415A (en) * | 2011-03-15 | 2011-08-17 | 上海宏力半导体制造有限公司 | Method for testing wafer parameters of bare chips |
| CN102339814A (en) * | 2010-07-16 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for testing metal-oxide-semiconductor field-effect transistor (MOSFET) |
| CN102830337A (en) * | 2012-08-29 | 2012-12-19 | 中国电子科技集团公司第十三研究所 | System for testing direct current performance of wide bandgap semiconductor chip |
| CN103837809A (en) * | 2012-11-23 | 2014-06-04 | 北大方正集团有限公司 | IC layout for testing MOSFET matching and test method |
| US20150067429A1 (en) * | 2013-09-03 | 2015-03-05 | Freescale Semiconductor, Inc. | Wafer-level gate stress testing |
| CN106601645A (en) * | 2016-12-13 | 2017-04-26 | 武汉新芯集成电路制造有限公司 | Test structure and layout method thereof |
| CN108107241A (en) * | 2017-12-01 | 2018-06-01 | 浙江大学 | A kind of novel probe structure of stable drain voltage |
| US20180180661A1 (en) * | 2016-12-22 | 2018-06-28 | Texas Instruments Incorporated | High-side gate over-voltage stress testing |
| CN108766900A (en) * | 2018-04-12 | 2018-11-06 | 中国电子科技集团公司第五十五研究所 | A kind of On-wafer measurement DC probe card |
-
2020
- 2020-05-25 CN CN202010449991.7A patent/CN111562481B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007137284A2 (en) * | 2006-05-23 | 2007-11-29 | Integrated Technology Corporation | Probe needle protection method for high current probe testing of power devices |
| US20080290882A1 (en) * | 2006-05-23 | 2008-11-27 | Integrated Technology Corporation | Probe needle protection method for high current probe testing of power devices |
| CN101216528A (en) * | 2008-01-15 | 2008-07-09 | 中国科学院上海微系统与信息技术研究所 | On-chip test method for microwave power amplifier chip and its test system |
| CN102339814A (en) * | 2010-07-16 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for testing metal-oxide-semiconductor field-effect transistor (MOSFET) |
| CN102157415A (en) * | 2011-03-15 | 2011-08-17 | 上海宏力半导体制造有限公司 | Method for testing wafer parameters of bare chips |
| CN102830337A (en) * | 2012-08-29 | 2012-12-19 | 中国电子科技集团公司第十三研究所 | System for testing direct current performance of wide bandgap semiconductor chip |
| CN103837809A (en) * | 2012-11-23 | 2014-06-04 | 北大方正集团有限公司 | IC layout for testing MOSFET matching and test method |
| US20150067429A1 (en) * | 2013-09-03 | 2015-03-05 | Freescale Semiconductor, Inc. | Wafer-level gate stress testing |
| CN106601645A (en) * | 2016-12-13 | 2017-04-26 | 武汉新芯集成电路制造有限公司 | Test structure and layout method thereof |
| US20180180661A1 (en) * | 2016-12-22 | 2018-06-28 | Texas Instruments Incorporated | High-side gate over-voltage stress testing |
| CN108107241A (en) * | 2017-12-01 | 2018-06-01 | 浙江大学 | A kind of novel probe structure of stable drain voltage |
| CN108766900A (en) * | 2018-04-12 | 2018-11-06 | 中国电子科技集团公司第五十五研究所 | A kind of On-wafer measurement DC probe card |
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